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19-2595; Rev 0; 10/02
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
General Description
The MAX9173 quad low-voltage differential signaling (LVDS) line receiver is ideal for applications requiring high data rates, low power, and low noise. The MAX9173 is guaranteed to receive data at speeds up to 500Mbps (250MHz) over controlled-impedance media of approximately 100. The transmission media can be printed circuit (PC) board traces or cables. The MAX9173 accepts four LVDS differential inputs and translates them to LVCMOS/LVTTL outputs. The MAX9173 inputs are high impedance and require an external termination resistor when used in a point-topoint connection. The device supports a wide common-mode input range of 0.05V to VCC - 0.05V, allowing for ground potential differences and common-mode noise between the driver and the receiver. A fail-safe feature sets the output high when the inputs are open, or when the inputs are undriven and shorted or undriven and parallel terminated. The EN and EN inputs control the high-impedance outputs. The enables are common to all four receivers. Inputs conform to the ANSI TIA/EIA-644 LVDS standard. The flow-through pinout simplifies board layout and reduces crosstalk by separating the LVDS inputs and LVCMOS/LVTTL outputs. The MAX9173 operates from a single 3.3V supply, and is specified for operation from -40C to +85C. Refer to the MAX9121/ MAX9122 data sheet for lower jitter quad LVDS receivers with parallel fail-safe. Refer to the MAX9123 data sheet for a quad LVDS line driver with flowthrough pinout. The device is available in 16-pin TSSOP, SO, and space-saving thin QFN packages.
Features
o Accepts LVDS and LVPECL Inputs o Fully Compatible with DS90LV048A o Low 1.0mA (max) Disable Supply Current o In-Path Fail-Safe Circuitry o Flow-Through Pinout Simplifies PC Board Layout Reduces Crosstalk o Guaranteed 500Mbps Data Rate o 400ps Pulse Skew (max) o Conforms to ANSI TIA/EIA-644 LVDS Standard o High-Impedance LVDS Inputs when Powered-Off o Available in Tiny 3mm x 3mm QFN Package
MAX9173
Ordering Information
PART MAX9173EUE MAX9173ESE MAX9173ETE* TEMP RANGE -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 16 TSSOP 16 SO 16 Thin QFN-EP**
*Future product. Contact factory for availability. **EP = Exposed pad.
Typical Operating Circuit
LVDS SIGNALS MAX9173 MAX9123
Tx
100
Rx
Applications
Digital Copiers Laser Printers Cellular Phone Base Stations Network Switches/Routers Backplane Interconnect Clock Distribution LCD Displays Telecom Switching Equipment
Tx 100 Rx LVTTL/LVCMOS DATA INPUTS Tx 100 Rx
LVTTL/LVCMOS DATA OUTPUTS
Tx
100
Rx
Pin Configurations and Functional Diagram appear at end of data sheet.
100 SHIELDED TWISTED CABLE OR MICROSTRIP BOARD TRACES
________________________________________________________________ Maxim Integrated Products
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..........................................................-0.3V to +4.0V IN_+, IN_- to GND .................................................-0.3V to +4.0V OUT_, EN, EN to GND................................-0.3V to (VCC + 0.3V) Continuous Power Dissipation (TA = +70C) 16-Pin TSSOP (derate 9.4mW/C above TA = +70C) ..755mW 16-Pin SO (derate 8.7mW/C above TA = +70C) ........696mW 16-Pin QFN (derate 14.7mW/C above TA = +70C) ..1177mW Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C ESD Protection (Human Body Model, IN_+, IN_-) ............7.0kV Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 1.2V, common-mode input voltage VCM = |VID/2| to VCC - |VID/2|, outputs enabled, and TA = -40C to +85C. Typical values are at VCC = 3.3V, VCM = 1.2V, |VID| = 0.2V, and TA = +25C, unless otherwise noted.) (Notes 1, 2)
PARAMETER LVDS INPUTS (IN_+, IN_-) Differential Input High Threshold Differential Input Low Threshold Input Current (Noninverting Input) Power-Off Input Current (Noninverting Input) Input Current (Inverting Input) Power-Off Input Current (Inverting Input) LVCMOS/LVTTL OUTPUTS (OUT_) Output High Voltage (Table 1) Output Low Voltage Output Short-Circuit Current Output High-Impedance Current LOGIC INPUTS (EN, EN) Input High Voltage Input Low Voltage Input Current Input Clamp Voltage POWER SUPPLY Supply Current Disabled Supply Current ICC ICCZ Inputs open Disabled, inputs open 12 0.56 15 1.0 mA mA VIH VIL IIN VCL VIN = high or low ICL = -18mA 2.0 0 -15 -0.88 VCC 0.8 +15 -1.5 V V A V VOH VOL IOS IOZ Open, undriven short, or IOH = -4.0mA undriven parallel termination VID = 0 IOL = +4.0mA, VID = -100mV VOUT_ = 0 (Note 3) Disabled, VOUT_ = 0 or VCC -45 -1 2.7 2.7 3.2 3.2 0.1 -77 0.25 -120 +1 V mA A V VTH VTL IIN_+ IIN_+OFF IIN_IIN_-OFF Figure 1 VIN_+ = 0 to 3.6V, VIN_- = 0 to 3.6V, VCC = 0 or open (Figure 1) Figure 1 VIN_+ = 0 to 3.6V, VIN_- = 0 to 3.6V, VCC = 0 or open, Figure 1 -100 +0.5 -0.5 -0.5 -0.5 -45 -45 -2.5 0 +5.0 0 -5 +0.5 +10 +0.5 0 mV mV A A A A SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
AC ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, CL = 15pF, |VID| = 0.2V, VCM = 1.2V, and TA = -40C to +85C. Typical values are at VCC = 3.3V and TA = +25C, unless otherwise noted.) (Notes 4-7)
PARAMETER Differential Propagation Delay High to Low Differential Propagation Delay Low to High Differential Pulse Skew |tPHLD - tPLHD| Differential Channel-to-Channel Skew Differential Part-to-Part Skew Rise Time Fall Time Disable Time High to Z Disable Time Low to Z Enable Time Z to High Enable Time Z to Low Maximum Operating Frequency SYMBOL tPHLD tPLHD tSKD1 tSKD2 tSKD3 tSKD4 tTLH tTHL tPHZ tPLZ tPZH tPZL fMAX CONDITIONS Figures 2 and 3 Figures 2 and 3 Figures 2 and 3 (Note 8) Figures 2 and 3 (Note 9) Figures 2 and 3 (Note 10) Figures 2 and 3 (Note 11) Figures 2 and 3 Figures 2 and 3 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 RL = 2k, Figures 4 and 5 All channels switching (Note 12) 250 0.66 0.62 9.5 9.5 3 3 MIN 1.2 1.2 TYP 2.01 2.07 60 100 MAX 2.7 2.7 400 500 1 1.5 1.0 1.0 14 14 14 14 UNITS ns ns ps ps ns ns ns ns ns ns ns MHz
MAX9173
Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, and VID. Note 2: Devices are 100% production tested at TA = +25C and are guaranteed by design for TA = -40C to +85C as specified. Note 3: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification. Note 4: AC parameters are guaranteed by design and characterization. Note 5: CL includes scope probe and test jig capacitance. Note 6: Pulse generator output conditions: tR = tF < 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, VOH = 1.3V, VOL = 1.1V. High-impedance delay pulse generator output conditions: tR = tF < 3ns (0% to 100%), frequency = 1MHz, 50% duty cycle, VOH = 3V and VOL = 0. Note 7: Propagation delay and differential pulse skew decrease when |VID| is increased from 200mV to 400mV. Skew specifications apply for 200mV |VID| 1.2V over the common-mode range VCM = |VID|/2 to VCC - |VID|/2. Note 8: tSKD1 is the magnitude of the difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|. Note 9: tSKD2 is the magnitude of the difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of any other channel on the same part. Note 10: tSKD3 is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions at the same VCC and within 5C of each other. Note 11: tSKD4 is the magnitude of the difference of any differential propagation delays between parts operating over rated conditions. Note 12: 60% to 40% duty cycle, VOL = 0.4V (max), VOH = 2.7V (min), load = 15pF. Note 1:
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
Typical Operating Characteristics
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.2V, f = 100MHz, input rise and fall time = 1ns (0% to 100%), CL = 15pF, and TA = +25C, unless otherwise noted.) (Figures 2 and 3)
DIFFERENTIAL THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
DIFFERENTIAL INPUT THRESHOLD VOLTAGE (mV)
MAX9173 toc02 MAX9173 toc03
SUPPLY CURRENT vs. FREQUENCY
90 80 SUPPLY CURRENT (mA) 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 1000 FREQUENCY (MHz) ONE CHANNEL SWITCHING CL = 15pF ALL CHANNELS SWITCHING
MAX9173 toc01
SUPPLY CURRENT vs. TEMPERATURE
16 ALL INPUTS OPEN 15 SUPPLY CURRENT (mA) 14 13 12 11 10 9 8 -40 -15 10 35 60 85 TEMPERATURE (C) -35
100
-39 VTH -43
-47 VTL -51
-55 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
OUTPUT SHORT-CIRCUIT CURRENT vs. SUPPLY VOLTAGE
MAX9173 toc04
OUTPUT HIGH-IMPEDANCE CURRENT vs. SUPPLY VOLTAGE
MAX9173 toc05
OUTPUT HIGH VOLTAGE vs. SUPPLY VOLTAGE
3.6 OUTPUT HIGH VOLTAGE (V) 3.5 3.4 3.3 3.2 3.1 3.0 2.9 2.8 IOH = -4mA
MAX9173 toc06
-60 OUTPUT SHORT-CIRCUIT CURRENT (mA) ALL INPUTS OPEN -65 -70 -75 -80 -85 -90 -95 -100 3.0 3.1 3.2 3.3 3.4 3.5
-0.010 OUTPUT HIGH-IMPEDANCE CURRENT (nA) EN = LOW, EN = HIGH, VOUT = 0 -0.015
3.7
-0.020
-0.025
-0.030 3.6 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V)
2.7 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
OUTPUT LOW VOLTAGE vs. SUPPLY VOLTAGE
MAX9173 toc07
DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE
MAX9173 toc08
DIFFERENTIAL PROPAGATION DELAY vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY (ns) 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 1.85 1.80 -40 -15 10 35 60 85 tPHLD tPLHD
MAX9173 toc09
98 97 OUTPUT LOW VOLTAGE (mV) 96 95 94 93 92 91 90 89 88 3.0 3.1 3.2 3.3 3.4 3.5 IOL = 4mA
2.20 DIFFERENTIAL PROPAGATION DELAY (ns) 2.15 tPLHD 2.10 2.05 2.00 1.95 1.90
2.30
tPHLD
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
4
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.2V, f = 100MHz, input rise and fall time = 1ns (0% to 100%), CL = 15pF, and TA = +25C, unless otherwise noted.) (Figures 2 and 3)
DIFFERENTIAL PROPAGATION DELAY vs. COMMON-MODE VOLTAGE
MAX9173 toc10
DIFFERENTIAL PROPAGATION DELAY vs. DIFFERENTIAL INPUT VOLTAGE
MAX9173 toc11
DIFFERENTIAL PROPAGATION DELAY vs. LOAD
3.0 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 1.7 10 20 DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9173 toc12
2.7 DIFFERENTIAL PROPAGATION DELAY (ns) 2.6 2.5 2.4 2.3 2.2 2.1 2.0 1.9 1.8 0.1 0.6 1.1 1.6 2.1 2.6 tPHLD tPLHD
2.40 DIFFERENTIAL PROPAGATION DELAY (ns) 2.35 2.30 2.25 2.20 2.15 2.10 2.05 2.00 1.95 1.90 0.1 0.3 0.5 0.7 0.9 1.1 tPHLD tPLHD
tPLHD
tPHLD
3.1
30 LOAD (pF)
40
50
COMMON-MODE VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (V)
TRANSITION TIME vs. SUPPLY VOLTAGE
MAX9173 toc13
TRANSITION TIME vs. TEMPERATURE
MAX9173 toc14
TRANSITION TIME vs. LOAD
1800 TRANSITION TIME (ps) 1600 1400 1200 1000 800 600 400 tTHL
MAX9173 toc15
720
800 750 TRANSITION TIME (ps) 700 650 tTHL 600 550 500 450 tTLH
2000 tTLH
TRANSITION TIME (ps)
680
tTLH
640 tTHL 600
560 3.0 3.1 3.2 3.3 3.4 3.5 3.6 SUPPLY VOLTAGE (V)
400 -40 -15 10 35 60 85 TEMPERATURE (C)
10
20
30 LOAD (pF)
40
50
DIFFERENTIAL PULSE SKEW vs. SUPPLY VOLTAGE
MAX9173 toc16
DIFFERENTIAL PULSE SKEW vs. INPUT TRANSITION TIME
f = 50MHz DIFFERENTIAL PULSE SKEW (ps) 350 300 250 200 150 100 50 0 1.0 1.5 2.0 2.5 3.0
MAX9173 toc17
DIFFERENTIAL PULSE SKEW (ps)
120 110 100 90 80 70 60 50 40 30 20 10 0 3.0 3.1 3.2 3.3 3.4 3.5
400
3.6
SUPPLY VOLTAGE (V)
INPUT TRANSITION TIME (ns)
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
Pin Description
PIN TSSOP/SO 1 2 3 4 5 6 7 8 9, 16 10 11 12 13 14 15 -- QFN 15 16 1 2 3 4 5 6 7, 14 8 9 10 11 12 13 Exposed Pad NAME IN1IN1+ IN2+ IN2IN3IN3+ IN4+ IN4EN, EN OUT4 OUT3 GND VCC OUT2 OUT1 EP FUNCTION Inverting Differential Receiver Input for Receiver 1 Noninverting Differential Receiver Input for Receiver 1 Noninverting Differential Receiver Input for Receiver 2 Inverting Differential Receiver Input for Receiver 2 Inverting Differential Receiver Input for Receiver 3 Noninverting Differential Receiver Input for Receiver 3 Noninverting Differential Receiver Input for Receiver 4 Inverting Differential Receiver Input for Receiver 4 Receiver Enable Inputs. When EN = high and EN = low or open, the outputs are active. For other combinations of EN and EN, the outputs are disabled and in high impedance. LVCMOS/LVTTL Receiver Output for Receiver 4 LVCMOS/LVTTL Receiver Output for Receiver 3 Ground Power-Supply Input. Bypass VCC to GND with 0.1F and 0.001F ceramic capacitors. Place the smaller value cap as close to the pin as possible. LVCMOS/LVTTL Receiver Output for Receiver 2 LVCMOS/LVTTL Receiver Output for Receiver 1 Exposed Pad. Solder to ground plane for proper heat dissipation.
Table 1. Input/Output Function Table
ENABLES EN H EN L or open INPUTS (IN_+) - (IN_-) VID 0 VID -100mV Open, undriven short, or undriven parallel termination All other combinations of ENABLE pins Don't care OUTPUT OUT_ H L H Z
Detailed Description
LVDS is a signaling method intended for point-to-point communication over a controlled-impedance medium as defined by the ANSI TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption while reducing EMI and system susceptibility to noise. The MAX9173 is a 500Mbps, four-channel LVDS receiver intended for high-speed, point-to-point, low-power applications. Each channel accepts an LVDS input and
6
translates it to an LVTTL/LVCMOS output. The receiver is specified to detect differential signals as low as 100mV and as high as 1.2V within an input voltage range of 0 to VCC. The 250mV to 400mV differential output of an LVDS driver is nominally centered around a 1.2V offset. This offset, coupled with the receiver's 0 to VCC input voltage range, allows more than 1V shift in the signal (as seen by the receiver). This allows for a difference in ground references of the transmitter and the receiver, the common-mode effects of coupled noise, or both.
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
Fail-Safe
The MAX9173 fail-safe drives the receiver output high when the differential input is: * Open * * Undriven and shorted Undriven and terminated
OUT_ 45mV IN_IN_+
MAX9173
VCC
2.5A
Without fail-safe, differential noise at the input may switch the receiver and appear as data to the receiving system. An open input occurs when a cable and termination are disconnected. An undriven, terminated input occurs when a cable is disconnected with the termination still connected across the receiver inputs or when the driver of a receiver is in high impedance. An undriven, shorted input can occur due to a shorted cable.
5A
"In-Path" vs. "Parallel" Fail-Safe
The MAX9173 has in-path fail-safe that is compatible with in-path fail-safe receivers, such as the DS90LV048A. Refer to the MAX9121/MAX9122 data sheet for pin-compatible receivers with parallel fail-safe and lower jitter. Refer to the MAX9130 data sheet for a single LVDS receiver with parallel fail-safe in an SC70 package. The MAX9173 with in-path fail-safe is designed with a +45mV input offset voltage, a 2.5A current source between VCC and the noninverting input, and a 5A current sink between the inverting input and ground (Figure 1). If the differential input is open, the 2.5A current source pulls the input to approximately VCC 0.8V and the 5A current sink pulls the inverting input to ground, which drives the receiver output high. If the differential input is shorted or terminated with a typical value termination resistor, the +45mV offset drives the receiver output high. If the input is terminated and floating, the receiver output is driven high by the +45mV offset, and the 2:1 current sink to current source ratio (5A:2.5A) pulls the inputs to ground. This can be an advantage when switching between drivers on a multipoint bus because the change in common-mode voltage from ground to the typical driver offset voltage of 1.2V is not as much as the change from VCC to 1.2V (parallel fail-safe pulls the bus to VCC).
Figure 1. Input with Fail-Safe Network
sists of a 100pF capacitor charged to the ESD test voltage, which is then discharged into the test device through a 1.5k resistor.
Applications Information
Differential Traces
Input trace characteristics affect the performance of the MAX9173. Use controlled-impedance board traces. For point-to-point connections, match the receiver input termination resistor to the differential characteristic impedance of the board traces. Eliminate reflections and ensure that noise couples as common mode by running the differential traces close together. Reduce skew by matching the electrical length of the traces. Excessive skew can result in a degradation of magnetic field cancellation. Each channel's differential signals should be routed close to each other to cancel their external magnetic field. Maintain a constant distance between the differential traces to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities.
Cables and Connectors
LVDS transmission media typically have controlled differential impedance of 100. Use cables and connectors that have matched differential impedance to minimize impedance discontinuities. Avoid the use of unbalanced cables such as coaxial cable. Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.
7
ESD Protection
ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. The receiver inputs of the MAX9173 have 7.0kV of protection against static electricity (per Human Body Model). Figure 6a shows the Human Body Model, and Figure 6b shows the current waveform it generates when discharged into a low-impedance load. This model con-
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
Termination
The MAX9173 requires an external termination resistor. The termination resistor should match the differential impedance of the transmission line. Termination resistance values may range between 90 to 132, depending on the characteristic impedance of the transmission medium. When using the MAX9173, minimize the distance between the input termination resistors and the MAX9173 receiver inputs. Use 1% surface-mount resistors. inputs should be separated by 180 from the LVTTL/LVCMOS outputs to reduce crosstalk. For LVDS applications, a four-layer PC board that provides separate layers of power, ground, LVDS inputs, and output signals is recommended. When using the QFN package, solder the exposed pad (EP) to the ground plane using an array of vias for proper heat dissipation.
Board Layout
In general, separate the LVDS inputs from single-ended outputs to reduce crosstalk. Take special care when routing traces with the QFN package. Ideally, the LVDS TRANSISTOR COUNT: 1462 PROCESS: CMOS
Chip Information
IN_+ PULSE GENERATOR IN_50* 50* OUT_ CL
*50 REQUIRED FOR PULSE GENERATOR.
Figure 2. Propagation Delay and Transition Time Test Circuit
IN_1.2V (0V DIFFERENTIAL) IN_+ VID = 0.2V
1.3V
1.1V
tPLHD
tPHLD VOH 80% 1.5V 80% 1.5V
20% OUT_ tTLH tTHL
20% VOL
Figure 3. Propagation Delay and Transition Time Test Waveforms 8 _______________________________________________________________________________________
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
VCC S1
IN_+ GENERATOR 50 EN EN 1/4 MAX9173 IN_-
RL DEVICE UNDER TEST OUT_ CL
CL INCLUDES LOAD AND TEST JIG CAPACITANCE. S1 = VCC FOR tPZL AND tPLZ MEASUREMENTS. S1 = GND FOR tPZH AND tPHZ MEASUREMENTS.
Figure 4. High-Impedance Delay Test Circuit
EN WHEN EN = GND OR OPEN 1.5V 1.5V
3V
0
3V 1.5V EN WHEN EN = VCC tPZL tPLZ OUTPUT WHEN VID = -100mV OUTPUT WHEN VID = 0 0.5V tPHZ 0.5V 50% GND tPZH VOH VCC 50% VOL 1.5V 0
Figure 5. High-Impedance Delay Waveforms
RC 1M CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE
RD 1500 DISCHARGE RESISTANCE DEVICE UNDER TEST IP 100% 90% AMPERES Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE)
Cs 100pF
STORAGE CAPACITOR
36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM
Figure 6a. Human Body ESD Test Modules
Figure 6b. Human Body Current Waveform 9
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Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
Pin Configurations
OUT1 13 12 11 IN1+ IN115
TOP VIEW
IN1- 1 IN1+ 2 IN2+ 3 IN2- 4 IN3- 5 IN3+ 6 IN4+ 7 IN4- 8 16 EN 15 OUT1 14 OUT2 IN2+ IN2IN3IN3+ 1 2 3 4
16
14
EN
OUT2 VCC GND OUT3
MAX9173
13 VCC 12 GND 11 OUT3 10 OUT4 9 EN
MAX9173
10 9
5
6
7 EN
IN4+
IN4-
TSSOP/SO
THIN QFN-EP
Functional Diagram
VCC
IN1+ OUT1 IN1-
IN2+ OUT2 IN2-
IN3+ OUT3 IN3-
IN4+ OUT4 IN4-
EN EN
MAX9173
GND
10
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OUT4
8
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9173
______________________________________________________________________________________
TSSOP4.40mm.EPS
11
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
D2 b
0.10 M C A B
D D/2
D2/2
E/2
E2/2
C L
-A-
E
(NE - 1) X e
E2
L
-B-
e
k (ND - 1) X e
C L
C L
0.10 C 0.08 C
C L
A A2 A1 L L
e
e
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0136
1 2
C
12
______________________________________________________________________________________
12x16L QFN THIN.EPS
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9173
EXPOSED PAD VARIATIONS
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.20 mm AND 0.25 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220 REVISION C.
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE 12 & 16L, QFN THIN, 3x3x0.8 mm
DOCUMENT CONTROL NO. REV.
APPROVAL
21-0136
2 2
C
______________________________________________________________________________________
13
Quad LVDS Line Receiver with Flow-Through Pinout and "In-Path" Fail-Safe MAX9173
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D C
A e B A1
0 -8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
14 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.
SOICN .EPS

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