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SPLC562C
240 COM/SEG Driver for STN LCD
SEP. 17, 2004 Version 1.2
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPLC562C
Table of Contents
PAGE
1. GENERAL DESCRIPTION .......................................................................................................................................................................... 3 2. FEATURES .................................................................................................................................................................................................. 3 3. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3.1. BLOCK FUNCTION .................................................................................................................................................................................. 4 3.2. INPUT/OUTPUT CIRCUITS ....................................................................................................................................................................... 4 4. SIGNAL DESCRIPTIONS............................................................................................................................................................................ 6
4.1. PIN CONNECTION .................................................................................................................................................................................. 6 5. FUNCATIONAL DESCRIPTIONS ............................................................................................................................................................... 7
5.1. PIN FUNCTIONS..................................................................................................................................................................................... 7 5.2. FUNCTION OPERATIONS ....................................................................................................................................................................... 10
5.3. RELATIONSHIP BETWEEN THE DISPLAY DATA AND DRIVER OUTPUT PINS .............................................................................................. 10 5.4. PRECAUTIONS ..................................................................................................................................................................................... 16 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................. 17 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................. 17 6.2. RECOMMENDED OPERATING CONDITIONS............................................................................................................................................. 17 6.3. DC CHARACTERISTICS......................................................................................................................................................................... 17 6.4. AC CHARACTERISTICS ......................................................................................................................................................................... 18 7. APPLICATION CIRCUIT ........................................................................................................................................................................... 23 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 24 8.1. PAD ASSIGNMENT AND LOCATIONS....................................................................................................................................................... 24 8.2. ORDERING INFORMATION ..................................................................................................................................................................... 24 9. DISCLAIMER............................................................................................................................................................................................. 25 10. REVISION HISTORY ................................................................................................................................................................................. 26
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SPLC562C
240 COM/SEG DRIVER FOR STN LCD
1. GENERAL DESCRIPTION
The SPLC562C is a 240-output segment/common driver IC suitable for driving large/medium scale dot matrix LCD panels, and is used in personal computers/work-stations. Through the use of SST (Super Slim TCP) technology, it is ideal for substantially decreasing the size of the frame section of the LCD module. The SPLC562C is good both as a segment driver and a common driver, and it can create a low power consuming, high-resolution LCD. Common Mode g Built-in 240 bits bi-directional shift register (divisible into 120-bits X 2) g Shift clock frequency: 4.0MHz (Max.) (VDD = +2.5V to +5.5V) g Available in a single mode(240 bits shift register) or in a dual mode (120 bits shift register x 2) 1). Y1 -> Y240 2). Y240 -> Y1
2. FEATURES
Both Segment Mode and Common Mode g Number of LCD drive outputs: 240
3). Y1 -> Y120, Y121 -> Y240 4). Y240 -> Y121, Y120 - Y1
g Supply voltage for LCD drive: +15V to +30V g Low power consumption g Low output impedance
g Supply voltage for the logic system: +2.5V to +5.5V
g CMOS silicon gate process (P-type silicon substrate) g Package: 278-pin TCP (Tape Carrier Package) & Au bump chip Segment Mode
g Shift clock frequency:
1). 20MHz (Max.) (VDD = +5.0V D 10%)
2). 15MHz (Max.) (VDD = +3.0V to +4.5V) 3). 12MHz (Max.) (VDD = +2.5V to +3.0V) g Adopts a data bus system
g 4-bit / 8-bit parallel input modes are selectable with a mode (MD) pin g Automatic transfer function of an enable signal
g Automatic counting function which, in the chip select mode, causes the internal clock to be stopped by automatically counting 240 bit of input data g Line latch circuits are reset when DISPOFF active
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3. BLOCK DIAGRAM
V0R V12R V43R V5R FR LEVEL SHIFTER Y1 Y2
DISPOFF
240
The above 4 shift directions are pin-selectable
g Shift register circuit reset function when DISPOFF active
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Single mode Single mode
Dual mode Dual mode
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Y239 Y240
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V5L V43L V12L V0L
240 BIT 4-LEVEL DRIVER
EIO1 EIO2
ACTIVE CONTROL
240 BIT LEVEL SHIFTER
240
240 BIT LINE LATCH/SHIFTER REGISTER
16
16
16
16
16
16
LP
XCK
CONTROL LOGIC
8BITS*2 DATA LATCH
L/R
8
DATA CONTROL
MD
S/C
SP CONVERSION & DATA CONTROL (4 to 8 or 8 to 8)
TEST CIRCUIT
DI 0
DI 1
DI 2
DI 3
DI 4
DI 5
DI 6
DI 7
TEST1
TEST1
VDD
VSS
Remark: The TCP's external shape is customized.
To order your TCP's external shape, please contact SUNPLUS salesperson.
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SPLC562C
3.1. Block Function 3.1.1. Active control
In case of segment mode, controls the selection or non-selection of the chip. Following a LP signal, and after the chip select signal Once data input has been completed, a is input, a select signal is generated internally until 240 bits of data have been read in. non-selected. select signal for cascade connection is output, and the chip is In case of common mode, controls the input/output
3.1.5. Data latch
In case of segment mode, latches the data on the data bus. The latched state of each LCD driver output pin is controlled by the control logic and the data latch control, 240 bits of data are read in 30 sets of 8 bits.
3.1.6. Test circuit
The circuit is for the test. During normal operation, it doesn't act.!
data of bidirectional pins.
3.1.2. SP Conversion & Data Control
In case of segment mode, keep input data which are 2 clocks of XCK at 4-bit parallel mode into latch circuit, or keep input data which are 1 clock of XCK at 8-bits parallel mode into latch circuit, after that they are put on the internal data bus 8 bits at a time.
3.1.7. Line latch/shift register
In case of segment mode, all 240 bits which have been read into LP signal, and output to the level shifter block. edge of the LP signal.
the data latch are simultaneously latched on the falling edge of the
3.1.3. Data latch control
In case of segment mode, selects the state of the data latch which reads in the data bus signals. The shift direction is controlled by
the control logic, for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit.
3.1.4. Control logic
Controls the operation of each block.
when a LP signal has been input, all blocks are reset and the control block.
control logic waits for the selection signal output from the active Once the selection signal has been output, operation of the data latch and data transmission are controlled, 240 bits of data are read in, and the chip is non-selected. case of common mode, controls the direction of data shift.
3.2. Input/Output Circuits
VDD
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3.1.8. Level shifter
level, and output to the driver block.
common mode, shifts data from the data input pin on the falling
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In case of
The logic voltage signal is level-shifted to the LCD driver voltage
3.1.9. 4-level driver
In case of segment mode,
Drives the LCD driver output pins from the line latch/shift register data, selecting one of 4 levels (V0, V12, V43, V5) based on the S/C,
FR and DISPOFF signals.
In
I
To Internal Circuit 1/4 Applicable pins1/2 L/R, S/C, DI6-0, DISPOFF, LP, FR, MD
VSS (0 V)
Figure1: Input Circuit (1)
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SPLC562C
VDD
I
Control Signal
To Internal Circuit
1/4
VSS (0 V) VSS (0 V)
Figure2: Input Circuit (2)
VDD
I/O
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Control Signal VSS(0 V) VSS (0 V) VDD Output Signal Control Signal 1/4
Figure3: Input/Output Circuit
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Applicable pins1/2 DI7, XCK
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To Internal Circuit
Applicable pins1/2 EIO 1, EIO 2
V0
V0
V12
Control Signal 1
Control Signal 2
O
Control Signal 3
To Internal Circuit
Control Signal 4
1/4 Applicable pins1/2
Y240 - 1 VSS(0 V)
43
VSS (0 V)
5
Figure4: LCD Drive Output Circuit
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SPLC562C
4. SIGNAL DESCRIPTIONS
Mnemonic Y240 - 1 V0L V0R V12L, V12R V43L, V43R V5L, V5R L/R VDD S/C EIO1 EIO2 DI6 - 0 DI7 XCK PIN No. #32, #33 #2, #3 #31, #4 #30, #5 #29, #6 #11 I Power supply for LCD driver Power supply for LCD driver Power supply for LCD driver Input for selecting the reading direction of display data at segment mode/Input for Power supply for logic system (+2.5V to +5.5V) selecting the shift direction of shift register at common mode Type O LCD driver output Power supply for LCD driver Description
DISPOFF
LP FR MD VSS
4.1. PIN Connection
NC NC Y1 Y2 Y3
Note: Doesn't prescribe TCP outline.
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NC V0R V0R V12R V43R V5R NC VSS NC MD L/R FR EIO1 LP DISPOFF XCK DI7 DI6 DI5 DI4 DI3 DI2 DI1 DI0 EIO2 S/C VDD NC V5L V43L V12L V0L V0L NC
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#27 #26 I Segment mode/common mode selection #13 #25 I/O I Input/output for chip selection at segment mode/Shift clock input/output for shift register Display data input for segment mode at common mode #18 - #24 #17 I Display data input for segment mode/Dual mode data input at common mode #16 I Clock input for taking display data at segment mode Control input for output of non-select level #15 I #14 I Latch pulse input for display data at segment mode/Shift clock input for shift register at AC-converting signal input for LCD driver waveform common mode #12 I #10 #8 I Mode selection input Ground (0V)
CHIP SURFACE
#10
#11
#18
#20
#22
#25
#16
#17
#21
#27
#29
#31
#12
#13
#14
#15
#19
#23
#24
#26
#28
#30
#32
#33
#34
#3
#1
#2
#4
#5
#6
#7
#8
#9
Y238 Y239 Y240 NC NC
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SPLC562C
5. FUNCATIONAL DESCRIPTIONS
5.1. PIN Functions 5.1.1. Segment mode
Mnemonic VDD VSS V0R, V0L, V12R, V12L, V43R, V43L, V5L, V5R Description Logic system power supply pin connects to +2.5V to +5.5V Ground pin connects to 0V Bias Power supply pin for LCD driver voltage 1). Normally, the bias voltage used is set by a resistor divider. 2). Ensure that voltage are set such that VSS V5 3). ViL and ViR (I = 0, 12, 43, 5) must connect to an external power supply, and supply regular voltage which is assigned by specification for each power pin. V5 should not be shorted directly on the panel. connect-pin. DI7 - 0 Input pins for display data 4). In COG applications, even though VSS and V5 have the same voltage level, the ITO layout of VSS and That is, VSS and V5 should have individual path and
XCK LP L/R
DISPOFF
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1). In 4-bit parallel input mode, input data into the 4 pins, DI3 - DI0. 2). In 8-bit parallel input mode, input data into the 8 pins, DI7-DI0. Operations. Clock input pin for taking display data 1). Data is read at the falling edge of the clock pulse. Latch pulse input pin for display data 1). Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data 1). When set to VSS level "L", data is read sequentially from Y240 to Y1. 2). When set to VDD level "H", data is read sequentially from Y1 to Y240. Operations. Control input pin for output non-select level drive circuit. 2). When set to VSS level "L", the LCD drive output pins (Y240 - 1) are set to level V5. can not output the reading data correctly. 4). Table of truth values is shown in "5.2.1 Truth table" in Function Operations. Segment mode/common mode selection pin 1). When set to VDD level "H", segment mode is set. AC signal input pin for LCD driving waveform circuit. 2). Normally, inputs a frame inversion signal.
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Connect DI7 - 4 to VSS or VDD.
3). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional
3). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional
1). The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD
3). While set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of DISPOFF . When the DISPOFF function is canceled, the driver outputs non-select level (V12 or V43), then outputs the contents of the data latch at the next falling edge of the LP.
At that time, if DISPOFF removal time does not correspond to what is shown in AC characteristics, it
S/C FR
1). The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls LCD drive
3). The LCD driver output pin's output voltage level can be set using the line latch output signal and the FR signal. 4). Table of truth values is shown in "5.2.1 Truth table" in Function Operations.
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Mnemonic MD Mode selection pin 1). When set to VSS level "L", 8-bit parallel input mode is set. 2). When set to VDD level "H", 4-bit parallel input mode is set. 3). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional Operations. EIO1, EIO2 Input/output pins for chip selection 1). When L/R input is at VSS Level "L", EIO1 is set for output and EIO2 is set for input. 2). When L/R input is at VDD Level "H", EIO1 is set for input and EIO2 is set for output. 3). During output, set to "H" while LP Description
XCK is "H" and after 240 bits of data have been read, set to "L" for
one cycle (from falling edge to falling edge of XCK), after which it returns to "H". non-selected after 240 bits of data have been read. Y240 - 1 LCD driver output pins output.
4). During input, the chip is selected while EI is set to "L" after the LP signal is input. The chip is
5.1.2. Common mode
Mnemonic VDD VSS
V0R, V0L, V12R, V12L, V43R, V43L, V5L, V5R
LP EIO1
L/R
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2). Table of truth values is shown in "5.2.1 Truth table" in Function Operations. Description Logic system power supply pin connects to +2.5V to +5.5V. Ground pin connects to 0V Bias Power supply pin for LCD driver voltage 1). Normally, the bias voltage used is set by a resistor divider. 2). Ensure that voltage are set such that VSS V5 1). Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and
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3). ViL and ViR (I=0, 12, 43, 5) must connect to an external power supply, and supply regular voltage which is
4). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional
1). Data is shifted from Y240 to Y1 when set to VSS to level "L", and data is shifted from Y1 to Y240 when set
2). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional EIO2
4). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional Operations. S/C Segment mode / common mode selection pin 1). When set to VSS level "L", common mode is set.
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SPLC562C
Mnemonic FR AC signal input for LCD driving waveform 1). The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls LCD drive circuit. 2). Normally, input a frame inversion signal. 3). The LCD driver output pin's output voltage level can be set using the shift register output signal and the FR signal. 4). Table of truth values is shown in "5.2.1 Truth table" in Functional Operations. Control input pin for output non-select level drive circuit. Description
DISPOFF
1). The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls LCD 2). When set to VSS level "L", the LCD drive output pins (Y240 - 1) are set to level V5.
3). While set to "L", the contents of the shift register are reset not reading data.
function is canceled, the driver outputs non-select level (V12 or V43), and the shift data is reading at the
MD
DI6 - 0 XCK DI7
Y240 - 1
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AC characteristics, the shift data is not reading correctly. 4). Table of truth values is shown in "5.2.1 Truth table" in Functional Operations. Mode selection pin operation is selected. Operations. Not used 1). Connect DI6 - 0 to VSS or VDD, avoiding floating. Not used 1). XCK is pull-down in common mode, so connect to VSS or open. Dual mode data input pin bit. When the chip is used as dual mode, DI7 will be pull-down. When the chip is used as single mode, DI7 won't be pull-down. Operations. LCD driver output pins output. 2). Table of truth values is shown in "5.2.1 Truth table" in Functional Operations.
falling edge of the LP. At that time, if DISPOFF removal time does not correspond to what is shown in
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1). When set to VSS level "L", single mode operation is selected, when set to VDD level "H", dual mode 2). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional
1). According to the data shift direction of the data shift register, data can be input starting from the 121st
2). Refer to "5.3 Relationship between the Display Data and Driver Output PINs" in Functional
1). Corresponding directly to each bit of the shift register, one level (V0, V12, V43, or V5) is selected and
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SPLC562C
5.2. Function Operations 5.2.1. Truth table 5.2.1.1. Segment mode
FR Latch data DISPOFF Driver output voltage level (Y240 - 1) L L H H X L H L H X H H H H L V43 V5 V12 V0 V5
5.2.1.2. Common mode
FR Latch data DISPOFF Driver output voltage level (Y240 - 1) L L H H X
Note1: VSS
L H L H X
X: Don't care
H H H H L
V5 < V43 < V12 < V0,
Note2: "Don't care" should be fixed to "H" or "L", avoiding floating. drive voltage) for the LCD driver. power pin.
There are two kinds of power supply (logic level voltage and LCD
5.3. Relationship between the Display Data and Driver Output PINs 5.3.1. Segment mode
5.3.1.1. 4-bit parallel mode
MD L/R EIO1
H
L
H
H
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EIO2 Data Figure of clock .. Input DI0 DI1 DI2 60 Clock Y1 Y2 Y3 Y4 59 Clock Y5 Y6 Y7 Y8 58 Clock Y9 3 Clock Y229 Y230 Y231 Y232 Y12 Y11 .. .. .. .. .. .. .. .. Output Input Y10 Y11 DI3 DI0 DI1 DI2 Y12 Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 Y232 Y231 Y230 Y229 Input Output Y10 Y9 DI3
Supply regular voltage which is assigned by specification for each
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V43 V0 V12 V5 V5
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Y233 Y234 Y235 Y236 Y8 Y7 Y6 Y5
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2 Clock
1 Clock Y237 Y238 Y239 Y240 Y4 Y3 Y2 Y1
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SPLC562C
5.3.1.2. 8-bit parallel mode
MD L/R EIO1 EIO2 Data Input DI0 DI1 DI2 L L Output Input DI3 DI4 DI5 DI6 DI7 DI0 DI1 DI2 L H Input Output DI3 DI4 DI5 DI6 DI7 30 Clock Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y240 Y239 Y238 Y237 Y236 Y235 Y234 Y233 29 Clock Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y232 Y231 Y230 Y229 Y228 Y227 Y226 Y225 Figure of clock 28 Clock Y17 Y18 Y19 Y20 Y21 Y22 Y23 Y24 Y224 Y223 .. .. .. .. .. .. .. .. .. 3 Clock Y217 Y218 Y219 Y220 Y221 2 Clock Y225 Y226 Y227 Y228 Y229 Y230 Y231 Y232 Y16 1 Clock Y233 Y234 Y235 Y236 Y237 Y238
5.3.2. Common mode
MD L (Single)
H (Dual)
Note1: L: VSS (0V), H: VDD (+2.5V to +5.5V), X: Don't care
Note2: "Don't care" should be fixed to "H" or "L", avoiding floating.
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Y219 Y218 Y217 .. .. .. L/R Data transfer direction Y240 -> Y1 Y1 -> Y240 EIO1 L(shift to left) Output Input H(shift to right) L(shift to left) Y240 -> Y121 Y120 -> Y1 Output H(shift to right) Y1 -> Y120 Y121 -> Y240 Input
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Y221 Y220
Y222
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Y222 Y223 Y224 Y24 Y23 Y22 Y21 Y20 Y19 Y18 Y17
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EIO2 Input Output Input
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Y15 Y14 Y13 Y12 Y11 Y10 Y9
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Y239 Y240 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1
DI7 X X Input
Output
Input
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5.3.3. Connection examples of plural segment drivers
1). CASE OF L/R = "L" Top data Data flow Y240 EIO2 Y1 EIO1 L/R Y240 EIO2 Y1 EIO1 L/R Y240 EIO2 Y1 EIO1 L/R Last data
XCK LP MD FR DI7 - 0 VSS
2). CASE OF L/R = "H" VDD DI7 - 0 FR MD LP XCK
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8
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LP
DI7 - 0
DI7 - 0
O
8
FR
MD
LP
DI7 - 0
XCK
XCK
XCK
MD
MD
MD
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FR
FR
FR
LP
LP
DI7 - 0
DI7 - 0
XCK
XCK
L/R
L/R
EIO 1
EIO2
EIO1
EIO2
DI7 - 0
L/R EIO2 Y240 Last data
EIO1
Y1
Y240
Y1
Y240
Y1
Data flow
Top data
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XCK
LP
FR
MD
FR
MD
LP
SPLC562C
5.3.4. Timing chart of 4-device casecade connection of segment drivers
FR
LP
XCK TOP DATA DI7 - 0 n* 1 2 n* 1 2 n* 1 2 n* 1 2
LAST DATA
EI (device A) EO (device A)
EO (device B)
EO (device C)
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* n=60 in 4-bit parallel input mode. n=30 in 8-bit parallel input mode.
device A
device B
device C
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n* 1 2
device D
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H L
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SPLC562C
5.3.5. Connection examples for plural common drivers
1). Single MODE (L/R = "L")
First
Last
Y240
Y1
Y240
Y1
Y240
Y1
DISPOFF
DISPOFF
LP
VSS(VDD) VSS VSS
DISPOFF FR
2). Single Mode (L/R = "H") FR DISPOFF
VDD VSS VSS(VDD)
LP
DI
nO ee id s f nU o C ER sN lu I pM nT uR SA P r o F
LP LP DI7 DI7 L/R DISPOFF L/R MD MD DISPOFF L/R
EIO 1 Y1 EIO2 Y240
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FR
DISPOFF
DI
EIO2
L/R MD
DI 7
EIO1
FR
EIO2
DI7 MD L/R
EIO1
FR
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LP
EIO2
EIO1
7
LP
LP
DI
MD
L/R
DISPOFF
EIO 1 Y1
EIO 2 Y240
EIO1 Y1
MD
FR
FR
FR
DI7
EIO2 Y240
Y120 Y121
First
Last
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LP
SPLC562C
3). Dual MODE (L/R = "L")
First 1
Last 1 First 2
Last 2
Y240
Y1
Y240 Y121 Y120
Y1
Y240
Y1
DISPOFF
DISPOFF
LP DI2
VSS(VDD) VDD VSS
DISPOFF FR
4). Dual MODE (L/R = "H") FR
DISPOFF
VDD VSS VSS(VDD)
DI2 LP
DI1
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7
DISPOFF
DI1
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
MD
DI7 MD L/R
DI 7
MD
L/R
FR
FR
L/R
LP
LP
MD
LP
DI7
LP
L/R
MD
L/R
DI7
DISPOFF
DISPOFF
L/R
EIO 1
EIO2
DISPOFF
EIO 1
EIO 2
EIO1
MD
FR
FR
FR
Y1
Y240
Y1
Y120 Y121
Y240
Y1
DI7
EIO2
Y240
First 1
Last 1 First 2
Last 2
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LP
FR
LP
DI
SPLC562C
5.4. Precautions 5.4.1. Precaution when connecting or disconnecting the power
This LSI has a high-voltage LCD driver, so it may be permanently damaged by a high current which may flow if a voltage is supplied to the LCD driver power supply while the logic system power supply is floating. The detail is as follows. 1). When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD driver power. 2). We recommend you connecting the serial resistor (50~100: ) or fuse to the LCD drive power V0 of the system as a current limited. And set up a suitable value of the resistor in consideration of LCD display grade. And when connecting the logic power supply, the logic condition of this LSI inside is insecurity. Therefore connect the LCD driver power supply after resetting logic condition of this LSI inside on
DISPOFF function.
After that, cancel the DISPOFF function
after the LCD driver power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level V5 on DISPOFF function.
disconnect the logic system power after disconnecting the LCD drive power.
When connecting the power supply, follow the recommended sequence shown here.
VDD
DISPOFF
V0
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VDD VSS VDD VSS V0 VSS
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After that,
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6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Parameter Supply voltage (1) Symbol VDD V0 Supply voltage (2) V12 V43 V5 Input voltage Storage temperature
Note1: TA = +25: Note2: The maximum applicable voltage on any pin with respect to VSS (0V). conditions see AC/DC Electrical Characteristics.
Conditions
Applicable Pins VDD V0L, V0R
Ratings -0.3 to +6.5 -0.3 to +30 -0.3 to V0+0.3 -0.3 to V0+0.3
Unit V V V V V
TA = 25: Referenced to VSS(0V)
V12L, V12R V43L, V43R V5L, V5R DI7 - 0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF
VI TSTG -
-
Note3: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. Recommended Operating Conditions
Parameter Symbol VDD V0
Supply voltage (1)
Supply voltage (2)
Operating temperature
Note1: The applicable voltage on any pin with respect to VSS (0V). Note2: Ensure that voltage are set such that VSS V5 V43 V12 V0.
6.3. DC Characteristics 6.3.1. Segment mode
Parameter Input voltage
Output voltage
Input leakage current
Output resistance Stand-by current
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Conditions Applicable Pins VDD Min. +2.5 +15 -20 Referenced to VSS (0V) V0L, V0R TOPR Symbol VIH VIL Conditions Applicable Pins Min. DI7 - 0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 0.8VDD VOH VOL ILIH ILIL IOH = -0.4mA VDD-0.4 IOL = +0.4mA VI = VDD VI = VSS DI7 - 0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF Y240 - 1 VSS VDD VDD V0L, V0R RON ISTB IDD1 IDD2 I0 |ae VON| = 0.5V V0 = +30V V0 = +20V *1 *2 *3 *4 -
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-0.3 to V0+0.3
-0.3 to VDD+0.3 -45 to +125
O
For normal operational
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: Unit V V :
V
Typ.
Max. +5.5 +30 +85
(VSS = V5 = 0V, VDD = +2.5V to +5.5V, V0 = +15V to +30V, TA = +25: ) Typ. Max. 0.2VDD +0.4 +10 -10 2.0 2.5 75 2.0 12 1.5 Unit V V V V PA PA K: PA mA mA mA
1.5 2.0 -
Supply current (1) (Non-selection) Supply current (2) (Selection) Supply current (3)
Note1: VDD = +5.0V, V0 = +30V, VI = VSS Note2: VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load, EI = VDD. Note3: VDD = +5.0V, V0 = +30V, fXCK = 20MHz, No-load, EI = VSS. mode) The input data is turned over by data taking clock (4-bit parallel input mode) The input data is turned over by data taking clock (4-bit parallel input mode) The input data is turned over by data taking clock (4-bit parallel input
Note4: VDD = +5.0V, V0 = +30V, fXCK = 20MHz, fLP = 41.6KHz, fFR = 80Hz, no-load.
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6.3.2. Common mode
(VSS = V5 = 0V, VDD = +2.5V to +5.5V, V0 = +15V to +30V, TA = +25: ) Parameter Input voltage Symbol VIH VIL VOH VOL ILIH ILIL RON IPD ISTB IDD I0 Conditions IOH = -0.4mA IOL = +0.4mA VI = VDD VI = VSS |ae VON| = 0.5V V0 = +30V V0 = +20V Applicable Pins DI7 - 0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF EIO1, EIO2 DI7 - 0, XCK, LP, L/R, FR, MD, S/C, EIO1, EIO2, DISPOFF Y240 - 1 XCK, EIO1, EIO2, DI7 VSS Min. 0.8VDD VDD-0.4 Typ. Max. 0.2VDD +0.4 +10 -10 2.0 Unit V V V V PA PA K:
Output voltage
Input leakage current
Output resistance Input pull-down current Stand-by current Supply current (1) Supply current (2)
VI = VDD *1 *2 *2
V0L , V0R
Note1: VDD = +5.0V, V0 = +30V, VI = VSS
Note2: VDD = +5.0V, V0 = +30V, fLP = 41.6KHz, fFR = 80Hz in case of 1/480 duty operation, no-load.
6.4. AC Characteristics
6.4.1. Segment mode 1
Parameter Shift clock period *1
Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time
Latch pulse "H" pulse width
Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time
Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Input signal rise time *2 Input signal fall time *2 Enable setup time
nU o C ER sN lu I pM nT uR SA P r o F
Symbol TWCK Conditions Min. 50 TR, TF 10ns TWCKH TWCKL TDS CL = 15pF CL = 15pF CL = 15pF 15 15 10 12 15 0 TDH TWLPH TLD TSL 30 25 25 TLS TLH TR TF TS 10 TSD TWDL TD TPD1, TPD2 TPD3 100 1.2 -
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VDD
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1.5 2.0 -
2.5
100
e s
-
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Max. 50 50 30 1.2 1.2
75
120
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PA PA PA PA Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Ps ns Ps Ps
240
(VSS = V5 = 0V, VDD = +4.5V to + +5.5V, V0 = +15V to +30V, TA = +25: ) Typ.
DISPOFF removal time DISPOFF "L" pulse width
Output delay time (1) Output delay time (2) Output delay time (3)
Note1: Take the cascade connection into consideration.
Note2: (TWCK - TWCKH - TWCKL) / 2 is maximum in the case of high speed operation.
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6.4.2. Segment mode 2
(VSS = V5 = 0V, VDD = +3.0V to +4.5V, V0 = +15V to +30V, TA = +25: ) Parameter Shift clock period *1 Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time Latch pulse "H" pulse width Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Input signal rise time *2 Input signal fall time *2 Enable setup time Symbol TWCK TWCKH TWCKL TDS TDH TWLPH TLD TSL TLS TLH TR TF TS Conditions TR, TF 10ns Min. 66 23 23 15 23 30 0 50 Typ. Max. Unit ns ns ns ns ns ns
DISPOFF removal time
DISPOFF "L" pulse width
Output delay time (1) Output delay time (2) Output delay time (3)
Note1: Take the cascade connection into consideration.
Note2: (TWCK - TWCKH - TWCKL) / 2 is maximum in the case of high speed operation.
6.4.3. Segment mode 3
Parameter Shift clock period
Shift clock "H" pulse width Shift clock "L" pulse width Data setup time Data hold time
Latch pulse "H" pulse width
Shift clock rise to latch pulse rise time Shift clock fall to latch pulse fall time
Latch pulse rise to shift clock rise time Latch pulse fall to shift clock fall time Input signal rise time Input signal fall time Enable setup time
id se f nU o C ER sN lu I pM nT uR SA P r o F
15 TSD 100 1.2 TWDL TD CL = 15pF CL = 15pF CL = 15pF TPD1, TPD2 TPD3 Symbol TWCK Conditions Min. 82 Typ. TR, TF 10ns TWCKH TWCKL TDS TDH TLD TSL TLS TR TF TS TSD TWDL TD TPD1, TPD2 TPD3 CL = 15pF CL = 15pF CL = 15pF 28 28 20 23 30 0 TWLPH 65 30 30 15 100 1.2 TLH
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30
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50 50 41 1.2 1.2
-
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ns ns ns ns ns ns ns ns Ps ns Ps Ps
(VSS = V5 = 0V, VDD = +2.5V to +3.0V, V0 = +15V to +30V, TA = +25: ) Max. 50 50 57 1.2 1.2 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Ps ns Ps Ps
DISPOFF removal time DISPOFF "L" pulse width
Output delay time (1) Output delay time (2) Output delay time (3)
Note1: Take the cascade connection into consideration.
Note2: (TWCK - TWCKH - TWCKL) / 2 is maximum in the case of high speed operation.
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SPLC562C
6.4.3.1. Timing characteristics of segment mode
TWLPH
LP
TLD
TSL TLS
TLH TWCKH TWCKL
XCK
TR
TF TWCK TDS TOP DATA
DI7 - 0
LAST DATA
TWDL
TSD
DISPOFF
LP
XCK
EI
EO
id se f nU o C ER sN lu I pM nT uR SA P r o F
(*) n 1 2 TS TD * n = 60 in 4-bit parallel input mode. n = 30 in 8-bit parallel input mode.
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TDH
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SPLC562C
*Note: Recommand TPD4 > 10ns for COG application which reduce power noise.
6.4.4. Common mode
Parameter Shift clock period
Shift "H" pulse width Data setup time Data hold time
Input signal rise time Input signal fall time
DISPOFF removal time
DISPOFF "L" pulse width
Output delay time (1) Output delay time (2)
Output delay time (3)
id se f nU o C ER sN lu I pM nT uR SA P r o F
Symbol TWLP Conditions Min. 250 15 Typ. TR, TF 20ns TWLPH TSU TH TR TF VDD = +5.0V D 10% VDD = +2.5V ~ +4.5V 30 30 50 TSD 100 1.2 TWDL TDL CL = 15pF CL = 15pF CL = 15pF TPD1, TPD2 TPD3 -
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Max. 50 50 200 1.2 1.2
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Unit ns ns ns ns ns ns ns ns Ps ns Ps Ps
(VSS = V5 = 0V, VDD = +2.5V to +5.5V, V0 = +15V to +30V, TA = +25: )
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SPLC562C
6.4.4.1. Timing chart of common mode
TWLP
LP TR TWLPH TSU EIO2 (DI7) TDL EIO1 TSD TF TH
DISPOFF
*Note : Recommand TPD4 > 10ns for COG application which reduce power noise.
id se f nU o C ER sN lu I pM nT uR SA P r o F
TWDL
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SPLC562C
7. APPLICATION CIRCUIT
VEE VDD VSS (Case of 1/n bias) V0 V5 V4 R V2 ( n - 4) R V3 V1
Controller DISPOFF XCK XD7-0 6 6 8 EIO2 DI7-0 L/R S/C XCK DISP OFF LP FR MD EIO1 EIO2 DI7-0 L/R MD XCK DISP OFF LP FR
R
R
R
FR
YD
id se f nU o C ER sN lu I pM nT uR SA P r o F
DI7DI0 DI7DI0 SEG1 SEG2 S/C EIO1 EIO2 DI7-0 L/R S/C MD EIO1 EIO2 DI7-0 L/R S/C MD EIO1 XCK DISP OFF LP FR XCK DISP OFF LP FR SEG1919 SEG1920 Y1 - 240 Y1 - 240 EIO2 L/R S/C MD EIO1 EIO2 L/R S/C MD EIO1 DISP OFF XCK DISP OFF XCK FR FR LP LP COM479 COM480 COM1 COM2 Y240-1 Y240-1
LP
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50-100 :
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8
SPLC562 X 2
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SPLC562 X 8
1920 X 480 DOT MATRIX LCD PANEL
Y240-1 Y240-1
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SPLC562C
8. PACKAGE/PAD LOCATIONS
8.1. PAD Assignment and Locations
Please contact Sunplus sales representatives for more information.
8.2. Ordering Information
Product Number SPLC562C - C SPLC562C - P* Package Type Chip form with Bump Package form - TCP
Note: *The TCP's external shape is customized. To order your TCP's external shape, please contact SUNPLUS salesperson.
id se f nU o C ER sN lu I pM nT uR SA P r o F
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SPLC562C
9. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHER, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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SEP. 17, 2004 Version: 1.2
SPLC562C
10. REVISION HISTORY
Date SEP. 17, 2004 DEC. 09, 2003 FEB. 12, 2003 SEP. 03, 2002 APR. 23, 2002
Revision # 1.2 1.1 1.0 0.2 0.1 Correct Timing diagram and Note
Description
Page 21, 22 24
Remove "8. PACKAGE/PAD LOCATIONS" 1. Remove "Preliminary" 2. Correct Pad pitch in "8.1 PAD Assignment" 1. Correct type error Original 2. Modify: Pad pitch: 50 -> 55 in "8.1 PAD Assignment" and "8.3 COG Align Key Coordinate"
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