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19-4792; Rev 2; 5/04
KIT ATION EVALU ABLE AVAIL
+3.3V, 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs
General Description Features
Single +3.3V Supply Low Jitter: 10ps Low Power Consumption 190mW (MAX3750) 180mW (MAX3751) Large Output Signal Swing: >1000mVp-p Mismatch Tolerant Output Driver Stage 150 Differential On-Chip Termination on All Inputs 150 On-Chip Back Termination on All Output Ports
MAX3750/MAX3751
The MAX3750/MAX3751 are +3.3V, Fibre Channel port bypass ICs that include a high-speed multiplexer and output buffer stage for hot swapping a storage device. These devices are optimized for use in a Fibre Channel arbitrated loop topology. The MAX3750 has a 2.125Gbps data rate, while the MAX3751's data rate is 1.0625Gbps. Total power consumption (including output currents) is low: just 190mW for the MAX3750 and 180mW for the MAX3751. Low 10ps jitter makes these devices ideal for cascaded topologies. The output driver circuitry is tolerant of load mismatches commonly caused by board vias and inductive connectors. On-chip termination reduces external part count and simplifies board layout.
Ordering Information
PART MAX3750CEE MAX3750CEE MAX3751CEE TEMP RANGE 0C to +70C 0C to +70C 0C to +70C PIN-PACKAGE 16 QSOP 16 QSOP 16 QSOP
Applications
2.125Gbps Fibre Channel Arbitrated Loop 1.0625Gbps Fibre Channel Arbitrated Loop Mass Storage Systems RAID/JBOD Applications
Denotes lead-free package.
Typical Application Circuit
FC-AL DISK DRIVE
FC-AL DISK DRIVE
TX
RX C7
TX C8 C2
RX C1
TX
FC-AL DISK DRIVE RX LOUT+ LOUTLIN+ LINLOUT+ C5 IN+ INC6 VCC 3.3V GND OUT+ OUT-
LIN+
LIN-
LOUT+
LOUT-
LIN+
LIN-
OUT+ OUT-
MAX3750
MAX3750 MAX3751
SEL
C3 IN+ INC4 VCC 3.3V GND OUT+ OUT-
MAX3750
MAX3750 MAX3751
SEL
MAX3750
MAX3750 MAX3751
SEL
LOUTIN+ INVCC 3.3V
GND
C1-C8 = 100nF
MICROPROCESSOR
THREE MAX3750/MAX3751s CASCADED IN AN FC-AL APPLICATION
Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+3.3V, 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs MAX3750/MAX3751
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +5.0V Voltage at LOUT+, LOUT-, OUT+, OUT- ..............................(VCC - 1.65V) to (VCC + 0.5V) Current Out of LOUT+, LOUT-, OUT+, OUT- ...................22mA Voltage at SEL, LIN+, LIN-, IN+, IN- ..........-0.5V to (VCC + 0.5V) Differential Voltage at (LIN+ - LIN-), (IN+ - IN-).....................2V Continuous Power Dissipation (TA = +70C) 16 QSOP (derate 8.3mW/C above +70C) .................667mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range ...............................-55C to 150C Lead Soldering Temperature (soldering, 10s).................+300C
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) PARAMETER Supply Current Data Input Voltage Swing Differential Input Impedance Output Voltage at LOUT and OUT TTL Input Current TTL Input Low TTL Input High Note 1: Output currents included. CONDITIONS MAX3750 (Note 1) MAX3751 (Note 1) Total differential signal, peak-to-peak 150 load, total differential signal, peak-to-peak 200 132 1000 -10 -0.3 2 MIN TYP 57 54 150 MAX 84 78 2200 172 1600 10 0.8 VCC + 0.3 UNITS mA mV mV A V V
AC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, TA = 0C to +70C, unless otherwise noted. Typical values are at VCC = +3.3V and TA = +25C.) PARAMETER Data Rate Data Input Voltage Swing Output Edge Speed IN OUT, IN LOUT Deterministic Jitter IN OUT, IN LOUT, LIN OUT Random Jitter IN OUT, IN LOUT, LIN OUT Prop Delay IN OUT, IN LOUT, LIN OUT MAX3750 MAX3751 Total differential signal, peak-to-peak MAX3750 MAX3751 MAX3750, peak-to-peak (Notes 2, 4) MAX3751, peak-to-peak (Notes 3, 4) MAX3750, RMS (Note 2) MAX3751, RMS (Note 3) MAX3750 MAX3751 300 442 10 10 1.6 1.6 200 CONDITIONS MIN TYP 2.125 1.0625 2200 160 325 MAX UNITS Gbps mV ps ps ps ps
Note 2: Input tR and tF < 150ps, 20% to 80%. Note 3: Input tR and tF < 300ps, 20% to 80%. Note 4: Deterministic jitter is measured with 20 bits of the k28.5 pattern (00111110101100000101).
2
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+3.3V, 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs MAX3750/MAX3751
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE
58 SUPPLY CURRENT (mA) 57 MAX3750 56 55 54 MAX3751 53 52 51 50 -40 -20 0 20 40 60 80 100 TEMPERATURE (C)
MAX3750/51 toc01
59
Pin Description
PIN 1, 4, 5, 8, 16 2 3 6 7 9 10 11 12, 13 14 15 NAME GND LOUT+ LOUTOUT+ OUTSEL LINLIN+ VCC ININ+ Electrical Ground Noninverted Port Data Output Inverted Port Data Output Noninverted Data Output Inverted Data Output Select Input: SEL = Low: IN OUT SEL = High: LIN OUT Inverted Port Data Input Noninverted Port Data Input Positive Supply Voltage Inverted Data Input Noninverted Data Input FUNCTION
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3
+3.3V, 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs MAX3750/MAX3751
_________________Circuit Description
A simplified block diagram of the single port bypass is shown in Figure 1. IN+ and IN- drive an input buffer (INBUFF) with 150 of internal differential input termination. INBUFF drives an output buffer (LOBUFF) and an input to a multiplexer (MUX). A low TTL input at SEL selects the signal path of INBUFF through MUX to the output buffer (OUTBUFF). When SEL has a high TTL logic level present the signal path is into LIBUFF, through MUX, to OUTBUFF.
Layout Techniques
The MAX3750/MAX3751 are high-frequency products. The performance of the circuit is largely dependent upon layout of the circuit board. Use a multilayer circuit board with dedicated ground and VCC planes. Power supplies should be capacitively bypassed to the ground plane with surface-mount capacitors placed near the power-supply pins.
Low-Frequency Cutoff
The low-frequency cutoff is determined by the input resistance and the coupling capacitor as illustrated by the following equation: fC = 1 / (2RC) In a typical system where R = 150 and C = 100nF, resulting in fC = 10kHz.
LOUT+
LOUT-
LIN+
LOBUFF
LINLIBUFF
OUTBUFF IN+ INBUFF MUX D0 IND1 SEL Q OUTVCC OUT+
MAX3750 MAX3751
TTLIN GND
SEL
NOTE: SEE INTERNAL INPUT/OUTPUT SCHEMATICS FOR DETAILED TERMINATIONS (FIGURES 2-5).
Figure 1. MAX3750/MAX3751 Block Diagram
4
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+3.3V, 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs MAX3750/MAX3751
VCC ESD STRUCTURES (L)OUT+ VCC
75
75
(L)OUT-
SEL
ESD STRUCTURE GND
GND
Figure 2. LOUT/OUT Pins Internal Input/Output Schematic
Figure 3. SEL Pin Internal Input/Output Schematic
VCC ESD STRUCTURE 300 IN(L)IN75 75 43 IN+ OUT+ 43
IN+
OUT+
(L)IN+
MAX3750 MAX3751
OUT-
300
176 43 IN-
MAX3750 MAX3751
OUT-
176 43
GND
Figure 4. LIN/IN Pins Internal Input/Output Schematic
Figure 5. 50 Termination Applications
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5
+3.3V, 2.125Gbps/1.0625Gbps Fibre Channel Port Bypass ICs MAX3750/MAX3751
Pin Configuration
TOP VIEW
GND 1 LOUT+ 2 LOUT- 3 GND 4 GND 5 OUT+ 6 OUT- 7 GND 8
16 GND 15 IN+ 14 IN-
MAX3750 MAX3751
13 VCC 12 VCC 11 LIN+ 10 LIN9 SEL
QSOP
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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