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| a FEATURES Low Power Replacement for Burr-Brown OPA-111, OPA-121 Op Amps Low Noise 2.5 V p-p max, 0.1 Hz to 10 Hz 11 nV//Hz max at 10 kHz 0.6 fA//Hz at 1 kHz High DC Accuracy 250 V max Offset Voltage 3 V/ C max Drift 1 pA max Input Bias Current Low Power: 1.5 mA max Supply Current APPLICATIONS Low Noise Photodiode Preamps CT Scanners Precision l-to-V Converters Low Power, Low Noise Precision FET Op Amp AD795 CONNECTION DIAGRAMS 8-Pin SOIC (RN) Package NC 1 -IN 2 +IN 3 -V S 4 8 NC 7 +VS 6 OUTPUT 5 NC AD795 NC = NO CONNECT PRODUCT DESCRIPTION The AD795 is a low noise, precision, FET input operational amplifier. It offers both the low voltage noise and low offset drift of a bipolar input op amp and the very low bias current of a FET-input device. The 1014 W common-mode impedance insures that input bias current is essentially independent of common-mode voltage and supply voltage variations. The AD795 has both excellent dc performance and a guaranteed and tested maximum input voltage noise. It features 1 pA maximum input bias current and 250 mV maximum offset voltage, along with low supply current of 1.5 mA max. VOLTAGE NOISE SPECTRAL DENSITY - nV//Hz Furthermore, the AD795 features a guaranteed low input noise of 2.5 mV p-p (0.1 Hz to 10 Hz) and a 11 nV//Hz max noise level at 10 kHz. The AD795 has a fully specified and tested input offset voltage drift of only 3 mV/C max. The AD795 is useful for many high input impedance, low noise applications. The AD795J and AD795K are rated over the commercial temperature range of 0C to +70C. The AD795 is available in 8-pin SOIC. 1k 50 SAMPLE SIZE = 570 40 100 PERCENTAGE OF UNITS 30 10 20 10 1 10 100 1k FREQUENCY - Hz 10k 0 -5 -4 -3 -2 -1 0 1 2 3 4 5 INPUT OFFSET VOLTAGE DRIFT - mV/C AD795 Voltage Noise Spectral Density Typical Distribution of Average Input Offset Voltage Drift REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 AD795-SPECIFICATIONS (@ +25 C and Parameter INPUT OFFSET VOLTAGE 1 Initial Offset Offset vs. Temperature vs. Supply (PSRR) vs. Supply (PSRR) INPUT BIAS CURRENT 2 Either Input Either Input @ TMAX = Either Input Offset Current Offset Current @ TMAX = OPEN-LOOP GAIN Conditions 15 V dc unless otherwise noted) Min AD795JR Typ 100 300 3 110 100 1 23 1 0.1 2 110 100 120 108 1.0 20 12 11 9 13 0.6 1.6 16 1 10 11 2 3.3 50 40 17 11 Max 500 1000 10 Units mV mV mV/C dB dB pA pA pA pA pA dB dB mV p-p nV//Hz nV//Hz nV//Hz nV//Hz fA p-p fA//Hz MHz kHz V/ms ms ms ms dB W pF W pF V V V dB dB V V mA mA V V mA TMIN-TMAX 86 84 TMIN-TMAX VCM = 0 V VCM = 0 V VCM = +10 V VCM = 0 V VCM = 0 V VO = 10 V RLOAD 10 kW RLOAD 10 kW 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 0.1 Hz to 10 Hz f = 1 kHz G = -1 VO = 20 V p-p RLOAD = 2 kW VOUT = 20 V p-p RLOAD = 2 kW 10 V Step 10 V Step 50% Overdrive f = 1 kHz R1 10 kW VO = 3 V rms VDIFF = 1 V 2/3 1.0 INPUT VOLTAGE NOISE INPUT CURRENT NOISE FREQUENCY RESPONSE Unity Gain, Small Signal Full Power Response Slew Rate, Unity Gain SETTLING TIME To 0.1% To 0.01% Overload Recovery4 Total Harmonic Distortion INPUT IMPEDANCE Differential Common Mode INPUT VOLTAGE RANGE Differential5 Common-Mode Voltage Over Max Operating Temperature Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Voltage Current POWER SUPPLY Rated Performance Operating Range Quiescent Current 3 -108 1012 2 1014 2.2 20 11 110 100 VS -2.5 10 15 15 1.3 VCM = 10 V TMIN-TMAX RLOAD 2 kW TMIN-TMAX VOUT = 10 V Short Circuit 10 10 90 86 VS -4 VS -4 5 4 18 1.5 -2- REV. B AD795 NOTES 1 Input offset voltage specifications are guaranteed after 5 minutes of operation at T A = +25C. 2 Bias current specifications are guaranteed maximum at either input after 5 minutes of operation at T A = +25C. For higher temperature, the current doubles every 10C. 3 Gain = -1, R1 = 10 kW. 4 Defined as the time required for the amplifier's output to return to normal operation after removal of a 50% overload from the amplifier input. 5 Defined as the maximum continuous voltage between the inputs such that neither input exceeds 10 V from ground. All min and max specifications are guaranteed. Specifications subject to change without notice. ABSOLUTE MAXIMUM RATINGS 1 Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V Internal Power Dissipation2 (@ TA = +25C) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Output Short Circuit Duration . . . . . . . . . . . . . . . . Indefinite Differential Input Voltage . . . . . . . . . . . . . . . . . . +VS and -VS Storage Temperature Range (R) . . . . . . . . . -65C to +125C Operating Temperature Range AD795J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0C to +70C NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-Pin Small Outline Package: qJA = 155C/Watt ORDERING GUIDE Model AD795JR Temperature Range 0C to +70C Package Option* RN-8 *N = Plastic mini-DIP; R = SOIC package. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD795 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, p roper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE REV. B -3- AD795-Typical Performance Characteristics 20 INPUT COMMON MODE RANGE - Volts RL = 10kW 15 +VIN OUTPUT VOLTAGE RANGE - Volts 20 RL = 10k W 15 +VOUT 10 -VIN 5 10 -VOUT 5 0 0 5 10 SUPPLY VOLTAGE - Volts 15 20 0 0 5 10 15 SUPPLY VOLTAGE - Volts 20 Figure 1. Common-Mode Voltage Range vs. Supply Figure 2. Output Voltage Range vs. Supply Voltage 30 1.0 OUTPUT VOLTAGE SWING - Volts p-p Vs = 15V 25 INPUT BIAS CURRENT - pA 0.95 0.90 0.85 0.80 0.75 0.70 0.65 0.60 20 15 10 5 0 10 100 1k LOAD RESISTANCE - W 10k 0 5 10 SUPPLY VOLTAGE - Volts 15 20 Figure 3. Output Voltage Swing vs. Load Resistance Figure 4. Input Bias Current vs. Supply 50 SAMPLE SIZE = 1058 40 PERCENTAGE OF UNITS 10 -9 INPUT BIAS CURRENT - Amps 10 -10 30 10 -11 20 10 -12 10 10 -13 0 0 .5 1 1.5 2 INPUT BIAS CURRENT - pA 10 -14 -60 -40 -20 0 20 40 60 80 100 120 140 TEMPERATURE - C Figure 5. Typical Distribution of Input Bias Current Figure 6. Input Bias Current vs. Temperature -4- REV. B AD795 1.00 10-4 INPUT BIAS CURRENT - Amperes 0.95 10-5 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -6 -IIN +IIN INPUT BIAS CURRENT - pA 0.90 0.85 0.80 0.75 0.70 0.65 0.60 -15 -10 -5 0 +5 +10 +15 COMMON MODE VOLTAGE - Volts -5 4 3 -1 1 2 -4 -3 -2 0 DIFFERENTIAL INPUT VOLTAGE - Volts 5 6 Figure 7. Input Bias Current vs. Common-Mode Voltage Figure 8. Input Bias Current vs. Differential Input Voltage 15 f = 1kHz VOLTAGE NOISE - nV//Hz 100 1k Noise Bandwidth: 0.1 to 10Hz VOLTAGE NOISE VOLTAGE NOISE - mV p-p 12.5 10 CURRENT NOISE - fA//Hz 100 10 1.0 CURRENT NOISE 10 7.5 0.1 5 -60 -40 -20 0 20 40 60 80 100 120 TEMPERATURE - C 0.01 140 1.0 10 3 10 4 10 5 106 10 7 SOURCE RESISTANCE - W 10 8 10 9 Figure 9. Voltage and Current Noise Spectral Density vs. Temperature Figure 10. Input Voltage Noise vs. Source Resistance 50 SAMPLE SIZE = 344 40 PERCENTAGE OF UNITS f = 0.1 TO 10Hz VOLTAGE NOISE (REFERRED TO INPUT) - nV//Hz 1k 100 30 20 10 10 1.0 1 10 100 1k 10k 100k 1M 10M FREQUENCY - Hz 0 0 1 2 0.1 TO 10Hz INPUT VOLTAGE NOISE p-p - mV 3 Figure 11. Typical Distribution of Input Voltage Noise Figure 12. Input Voltage Noise Spectral Density REV. B -5- AD795 30 10 8 SHORT CIRCUIT CURRENT - mA OUTPUT SWING FROM 0 TO V 25 - OUTPUT CURRENT 20 6 0.1% 4 2 0 -2 -4 0.1% 0.01% ERROR 0.01% 15 + OUTPUT CURRENT 10 -6 -8 5 -60 -10 -40 -20 0 20 40 60 80 100 120 140 3 4 5 6 7 8 9 10 11 TEMPERATURE - C SETTING TIME - s Figure 13. Short Circuit Current Limit vs. Temperature Figure 14. Output Swing and Error vs. Settling Time 1000 ABSOLUTE INPUT ERROR VOLTAGE - mV 900 800 700 600 500 400 300 200 100 0 -15 120 POWER SUPPLY REJECTION - dB 100 +PSRR -PSRR 80 60 40 20 0 -5 0 5 10 -10 INPUT COMMON MODE VOLTAGE - Volts 15 1 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 15. Absolute Input Error Voltage vs. Input Common-Mode Voltage Figure 16. Power Supply Rejection vs. Frequency 120 120 120 COMMON MODE REJECTION - dB 100 100 PHASE 100 80 60 80 60 40 20 0 GAIN 80 60 40 20 0 -20 10M 40 20 0 1 10 100 1k 10k 100k FREQUENCY - Hz 1M 10M -20 10 100 1k 10k 100k 1M FREQUENCY - Hz Figure 17. Common-Mode Rejection vs. Frequency Figure 18. Open-Loop Gain & Phase Margin vs. Frequency -6- REV. B PHASE MARGIN - Degrees OPEN-LOOP GAIN - dB AD795 30 RL = 10kW 1000 CLOSED-LOOP OUTPUT IMPEDANCE - W 25 OUTPUT VOLTAGE - Volts p-p 100 20 15 10 10 1.0 5 0 1k 10k 100k FREQUENCY - Hz 1M 0.1 1k 10k 100k FREQUENCY - Hz 1M 10M Figure 19. Large Signal Frequency Response Figure 20. Closed-Loop Output Impedance vs. Frequency 2.0 -60 VIN = 3Vrms RL = 10k -70 QUIESCENT SUPPLY CURRENT - mA 1.5 -80 THD - dB 1.0 -90 -100 0.5 -110 0 -120 100 1k 10k FREQUENCY - Hz 100k 0 5 10 15 SUPPLY VOLTAGE Volts 20 Figure 21. Total Harmonic Distortion vs. Frequency Figure 22. Quiescent Supply Current vs. Supply Voltage Drift 50 SAMPLE SIZE = 1419 40 PERCENTAGE OF UNITS 30 20 10 0 -500 -400 -300 -200 -100 0 100 200 300 400 500 INPUT OFFSET VOLTAGE - V Figure 23. Typical Distribution of Input Offset Voltage REV. B -7- AD795 10kW +VS 0.1mF 100 20V 5ms 100 90 10mV 500ns 10kW VIN 2 7 90 AD795 3 4 6 VOUT CL 100pF 10 0% 10 0% RL 0.1mF 10kW -VS 5V Figure 24. Unity Gain Inverter Figure 25. Unity Gain Inverter Large Signal Pulse Response Figure 26. Unity Gain Inverter Small Signal Pulse Response +V S 0.1mF 100 20V 5ms 100 90 20mV 500n s 2 VIN 3 4 7 90 AD795 6 VOUT CL 100pF 10 0% RL 0.1mF 10kW 10 0% -V S 5V Figure 27. Unity Gain Follower Figure 28. Unity Gain Follower Large Signal Pulse Response Figure 29. Unity Gain Follower Small Signal Pulse Response MINIMIZING INPUT CURRENT The AD795 is guaranteed to 1 pA max input current with 15 volt supply voltage at room temperature. Careful attention to how the amplifier is used will maintain or possibly better this performance. The amplifier's operating temperature should be kept as low as possible. Like other JFET input amplifier's, the AD795's input current will double for every 10C rise in junction temperature (illustrated in Figure 6). On-chip power dissipation will raise the device operating temperature, causing an increase in input current. Reducing supply voltage to cut power dissipation will reduce the AD795's input current (Figure 4). Heavy output loads can also increase chip temperature, maintaining a minimum load resistance of 10 kW is recommended. -8- REV. B AD795 CIRCUIT BOARD NOTES The AD795 is designed for mounting on PC boards. Maintaining picoampere resolution in those environments requires a lot of care. Both the board and the amplifier's package have finite resistance. Voltage differences between the input pins and other pins as well as PC board metal traces will cause parasitic currents (Figure 30) larger than the AD795's input current unless special precautions are taken. Two methods of minimizing parasitic leakages are guarding of the input lines and maintaining adequate insulation resistance. Figures 31 and 32 show the recommended guarding schemes for follower and inverted topologies. Pin 1 is not connected, and can be safely connected to the guard. The high impedance input trace should be guarded on both edges for its entire length. RP CF RF VE 2 IS 3 AD795 6 VOUT + - IP CP IP = VS VS RP + dCP dT VS+ dV S dT CP Figure 30. Sources of Parasitic Leakage Currents CF GUARD 2 IS RF AD795 3 6 VOUT + - 1 2 3 4 TOP VIEW ("R" PACKAGE) 8 7 6 5 NOTE: ON THE "R" PACKAGE PINS 1, 5 AND 8 ARE OPEN AND CAN BE CONNECTED TO ANALOG COMMON OR TO THE DRIVEN GUARD TO REDUCE LEAKAGE. F Figure 31. Guarding Scheme-lnverter GUARD TRACES 1 2 INPUT TRACE -VS 3 4 8 7 - 6 5 GUARD 3 AD795 TOP VIEW + VS 2 AD795 6 RF VOUT + CONNECT TO JUNCTION OF R F AND R I, OR TO PIN 6 FOR UNITY GAIN. RI - Figure 32. Guard Scheme-Follower REV. B -9- AD795 Leakage through the bulk of the circuit board will still occur with the guarding schemes shown in Figures 31 and 32. Standard "G10" type printed circuit board material may not have high enough volume resistivity to hold leakages at the subpicoampere level particularly under high humidity conditions. One option that eliminates all effects of board resistance is shown in Figure 33. The AD795's sensitive input pin (either Pin 2 when connected as an inverter, or Pin 3 when connected as a follower) is bent up and soldered directly to a Teflon* insulated standoff. Both the signal input and feedback component leads must also be insulated from the circuit board by Teflon standoffs or low-leakage shielded cable. INPUT PIN: PIN 2 FOR INVERTER OR PIN 3 FOR FOLLOWER 1 2 3 4 8 INPUT SIGNAL LEAD some cases, a shield placed over the resistors, or even the entire amplifier, may be needed to minimize electrical interference originating from other circuits. Referring to the equation in Figure 30, this coupling can take place in either, or both, of two different forms--coupling via time varying fields: dV C dT P or by injection of parasitic currents by changes in capacitance due to mechanical vibration: dCp V dT *Teflon is a registered trademark of E.I. du Pont Co. AD795 7 6 5 PC BOARD AD795 Both proper shielding and rigid mechanical mounting of components help minimize error currents from both of these sources. OFFSET NULLING TEFLON INSULATED STANDOFF Figure 33. Input Pin to Insulating Standoff Contaminants such as solder flux on the board's surface and on the amplifier's package can greatly reduce the insulation resistance between the input pin and those traces with supply or signal voltages. Both the package and the board must be kept clean and dry. An effective cleaning procedure is to first swab the surface with high grade isopropyl alcohol, then rinse it with deionized water and, finally, bake it at 100C for 1 hour. Polypropylene and polystyrene capacitors should not be subjected to the 100C bake as they will be damaged at temperatures greater than 80C. Other guidelines include making the circuit layout as compact as possible and reducing the length of input lines. Keeping circuit board components rigid and minimizing vibration will reduce triboelectric and piezoelectric effects. All precision high impedance circuitry requires shielding from electrical noise and interference. For example, a ground plane should be used under all high value (i.e., greater than 1 MW) feedback resistors. In The circuit in Figure 34 can be used when the amplifier is used as an inverter. This method introduces a small voltage in series with the amplifier's positive input terminal. The amplifier's input offset voltage drift with temperature is not affected. However, variation of the power supply voltages will cause offset shifts. RF RI 2 + VI - 3 AD795 6 +V S VOUT + - 499kW 499kW 100kW 200W 0.1mF -VS Figure 34. Alternate Offset Null Circuit for Inverter -10- REV. B AD795 AC RESPONSE WITH HIGH VALUE SOURCE AND FEEDBACK RESISTANCE 10mV 100 90 5ms Source and feedback resistances greater than 100 kW will magnify the effect of input capacitances (stray and inherent to the AD795) on the ac behavior of the circuit. The effects of common-mode and differential input capacitances should be taken into account since the circuit's bandwidth and stability can be adversely affected. In a follower, the source resistance, RS, and input commonmode capacitance, CS (including capacitance due to board and capacitance inherent to the AD795), form a pole that limits circuit bandwidth to 1/2 p RSCS. Figure 35 shows the follower pulse response from a 1 MW source resistance with the amplifier's input pin isolated from the board, only the effect of the AD795's input common-mode capacitance is seen. 10mV 100 90 10 0% Figure 37. Inverter Pulse Response with 1 MW Source and Feedback Resistance, 1 pF Feedback Capacitance OVERLOAD ISSUES 5ms Driving the amplifier output beyond its linear region causes some sticking; recovery to normal operation is within 2 ms of the input voltage returning within the linear range. If either input is driven below the negative supply, the amplifier's output will be driven high, causing a phenomenon called phase reversal. Normal operation is resumed within 30 ms of the input voltage returning within the linear range. 10 0% Figure 35. Follower Pulse Response from 1 MW Source Resistance Figure 38 shows the AD795's input currents versus differential input voltage. Picoamp level input current is maintained for differential voltages up to several hundred millivolts. This behavior is only important if the AD795 is in an open-loop application where substantial differential voltages are produced. 10-4 10-5 -IN +IN INPUT BIAS CURRENT - Amperes In an inverting configuration, the differential input capacitance forms a pole in the circuit's loop transmission. This can create peaking in the ac response and possible instability. A feedback capacitance can be used to stabilize the circuit. The inverter pulse response with RF and RS equal to 1 MW, and the input pin isolated from the board appears in Figure 36. Figure 37 shows the response of the same circuit with a 1 pF feedback capacitance. Typical differential input capacitance for the AD795 is 2 pF. 10mV 100 90 10-6 10-7 10-8 10-9 10-10 10-11 10-12 10-13 10-14 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 5ms DIFFERENTIAL INPUT VOLTAGE - Volts Figure 38. Input Bias Current vs. Differential Input Voltage 10 0% Figure 36. Inverter Pulse Response with 1 MW Source and Feedback Resistance REV. B -11- AD795 INPUT PROTECTION The AD795 safely handles any input voltage within the supply voltage range. Some applications may subject the input terminals to voltages beyond the supply voltages--in these cases, the following guidelines should be used to maintain the AD795's functionality and performance. If the inputs are driven more than a 0.5 V below the minus supply, milliamp level currents can be produced through the input terminals. That current should be limited to 10 mA for "transient" overloads (less than 1 second) and 1 mA for continuous overloads, this can be accomplished with a protection resistor in the input terminal (as shown in Figures 40 and 41). The protection resistor's Johnson noise will add to the amplifier's input voltage noise and impact the frequency response. Driving the input terminals above the positive supply will cause the input current to increase and limit at 40 mA. This condition is maintained until 15 volts above the positive supply--any input voltage within this range does not harm the amplifier. Input voltage above this range causes destructive breakdown and should be avoided. RF RP SOURCE 3 AD795 2 6 Figure 40. Follower with Input Current Limit Figure 41 is a schematic of the AD795 as an inverter with an input voltage clamp. Bootstrapping the clamp diodes at the inverting input minimizes the voltage across the clamps and keeps the leakage due to the diodes low. Low leakage diodes (less than 1 pA), such as the FD333s should be used, and should be shielded from light to keep photocurrents from being generated. Even with these precautions, the diodes will measurably increase the input current and capacitance. In order to achieve the low input bias currents of the AD795, it is not possible to use the same on-chip protection as used in other Analog Devices op amps. This makes the AD795 sensitive to handling and precautions should be taken to minimize ESD exposure whenever possible. RF RP SOURCE 2 CF SOURCE 2 AD795 3 6 3 PROTECT DIODES (LOW LEAKAGE) AD795 6 Figure 39. Inverter with Input Current Limit Figure 41. Input Voltage Clamp with Diodes -12- REV. B AD795 10pF 10 9 W GUARD 2 will typically drop by a factor of two for every 10C rise in temperature. In the AD795, both the offset voltage and drift are low, this helps minimize these errors. Minimizing Noise Contributions OUTPUT PHOTODIODE AD795 3 8 6 FILTERED OUTPUT The noise level limits the resolution obtainable from any preamplifier. The total output voltage noise divided by the feedback resistance of the op amp defines the minimum detectable signal current. The minimum detectable current divided by the photodiode sensitivity is the minimum detectable light power. Sources of noise in a typical preamp are shown in Figure 44. The total noise contribution is defined as: OPTIONAL 26Hz FILTER V OUT = (in 2 + if 2 + is2 ) A E Rf Rf E 1+ s (Cd ) Rd 2 E 2 + (en 2 )A1+ Rd A 1+ s (Cf ) Rf A E 1+ s (Cf ) Rf E E Cf 10pF Rf 109 W Figure 42. The AD795 Used as a Photodiode Preamplifier Preamplifier Applications The low input current and offset voltage levels of the AD795 together with its low voltage noise make this amplifier an excellent choice for preamplifiers used in sensitive photodiode applications. In a typical preamp circuit, shown in Figure 42, the output of the amplifier is equal to: VOUT = ID (Rf) = Rp (P) Rf where: ID = photodiode signal current (Amps) Rp = photodiode sensitivity (Amp/Watt) Rf = the value of the feedback resistor, in ohms. P = light power incident to photodiode surface, in watts. iS PHOTODIODE en if Rd iS Cd 50pF in OUTPUT Figure 44. Noise Contributions of Various Sources An equivalent model for a photodiode and its dc error sources is shown in Figure 43. The amplifier's input current, IB, will contribute an output voltage error which will be proportional to the value of the feedback resistor. The offset voltage error, VOS, will cause a "dark" current error due to the photodiode's finite shunt resistance, Rd. The resulting output voltage error, VE, is equal to: VE = (1 + Rf/Rd) VOS + Rf IB A shunt resistance on the order of 109 ohms is typical for a small photodiode. Resistance Rd is a junction resistance which Cf 10pF Figure 45, a spectral density versus frequency plot of each source's noise contribution, shows that the bandwidth of the amplifier's input voltage noise contribution is much greater than its signal bandwidth. In addition, capacitance at the summing junction results in a "peaking" of noise gain in this configuration. This effect can be substantial when large photodiodes with large shunt capacitances are used. Capacitor Cf sets the signal bandwidth and also limits the peak in the noise gain. Each source's rms or root-sum-square contribution to noise is obtained by integrating the sum of the squares of all the noise sources and then by obtaining the square root of this sum. Minimizing the total area under these curves will optimize the preamplifier's overall noise performance. An output filter with a passband close to that of the signal can greatly improve the preamplifier's signal to noise ratio. The photodiode preamplifier shown in Figure 44--without a bandpass filter--has a total output noise of 50 mV rms. Using a 26 Hz single pole output filter, the total output noise drops to 23 mV rms, a factor of 2 improvement with no loss in signal bandwidth. Rf 109 W PHOTODIODE VOS Rd ID Cd 50pF IB OUTPUT Figure 43. A Photodiode Model Showing DC Error Sources REV. B -13- AD795 10mV OUTPUT VOLTAGE NOISE - Volts//Hz is & i f SIGNAL BANDWIDTH voltage contributions are also amplified by the "T" network gain. A low noise, low offset voltage amplifier, such as the AD795, is needed for this type of application. A pH Probe Buffer Amplifier 1mV in WITH FILTER NO FILTER 100nV en en A typical pH probe requires a buffer amplifier to isolate its 106 to 109 W source resistance from external circuitry. Just such an amplifier is shown in Figure 47. The low input current of the AD795 allows the voltage error produced by the bias current and electrode resistance to be minimal. The use of guarding, shielding, high insulation resistance standoffs, and other such standard methods used to minimize leakage are all needed to maintain the accuracy of this circuit. 10k 100k 10nV 1 10 100 1k FREQUENCY - Hz Figure 45. Voltage Noise Spectral Density of the Circuit of Figure 44 With and Without an Output Filter 10pF RG 10kW Rf 108 W Ri 1.1kW The slope of the pH probe transfer function, 50 mV per pH unit at room temperature, has a +3300 ppm/C temperature coefficient. The buffer of Figure 47 provides an output voltage equal to 1 volt/pH unit. Temperature compensation is provided by resistor RT which is a special temperature compensation resistor, part number Q81, 1 kW, 1%, +3500 ppm/C, available from Tel Labs Inc. V OS ADJUST 100kW +VS 0.1mF COM -VS 0.1mF -V S 4 5 OUTPUT 6 7 8 +VS 19.6kW 1VOLT/pH UNIT -15V +15V AD795 PHOTODIODE VOUT RG = I D Rf (1+ ) Ri VOUT GUARD 3 1 AD795 PH PROBE 2 Figure 46. A Photodiode Preamp Employing a "T" Network for Added Gain Using a "T" Network A "T" network, shown in Figure 46, can be used to boost the effective transimpedance of an I-to-V converter, for a given feedback resistor value. However, amplifier noise and offset RT 1kW +3500ppm/ C Figure 47. A pH Probe Amplifier -14- REV. B AD795 OUTLINE DIMENSIONS 8-Lead Standard Small Outline Package [SOIC] Narrow Body (RN-8) Dimensions shown in millimeters and (inches) 5.00 (0.1968) 4.80 (0.1890) 8 5 4 4.00 (0.1574) 3.80 (0.1497) 1 6.20 (0.2440) 5.80 (0.2284) 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY SEATING 0.10 PLANE 1.75 (0.0688) 1.35 (0.0532) 8 0.25 (0.0098) 0 0.19 (0.0075) 0.50 (0.0196) 0.25 (0.0099) 45 0.51 (0.0201) 0.33 (0.0130) 1.27 (0.0500) 0.41 (0.0160) COMPLIANT TO JEDEC STANDARDS MS-012AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN All brand or product names mentioned are trademarks or registered trademarks of their respective holders. REV. B -15- AD795 Revision History Location 10/02-Data Sheet changed from REV. A to REV. B Page Deleted Plastic Mini-DIP (N) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Edits to CIRCUIT BOARD NOTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edits to Figure 31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Edits to OFFSET NULLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Deleted Figure 34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Deleted Low Noise Op Amp Selection Tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 C00845-0-10/02(B) PRINTED IN U.S.A. -16- REV. B This datasheet has been download from: www..com Datasheets for electronics components. |
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