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ispLSI 2128V
3.3V High Density Programmable Logic Features
* HIGH DENSITY PROGRAMMABLE LOGIC -- -- -- -- -- 6000 PLD Gates 128 and 64 I/O Pin Versions, Eight Dedicated Inputs 128 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic
Output Routing Pool (ORP) D7 D6 D5 D4 Output Routing Pool (ORP) D3 D2 D1 D0 C7
(R)
Functional Block Diagram*
Output Routing Pool (ORP)
A0
A1
C6
A2
* 3.3V LOW VOLTAGE 2128 ARCHITECTURE -- Interfaces with Standard 5V TTL Devices -- The 128 I/O Pin Version is Fuse Map Compatible with 5V ispLSI 2128 * HIGH PERFORMANCE E CMOS TECHNOLOGY -- -- -- -- -- --
2 (R)
A3
Output Routing Pool (ORP)
A4
D
Q
GLB
C3
A5
C2
A7
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fmax = 80 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay
Electrically Erasable and Reprogrammable Non-Volatile 100% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power
A6
D
B0 B1 B2 B3 B4 Output Routing Pool (ORP)
D
Q
C1
Global Routing Pool (GRP)
B5 B6 B7
C0
Output Routing Pool (ORP)
*128 I/O Version Shown
N
CLK 0 CLK 1 CLK 2
0139A/2128V
* THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS -- -- -- -- -- -- Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity
I2
12 8
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-- 3.3V In-System Programmability (ISPTM) Using Boundary Scan Test Access Port (TAP) -- Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired-OR or Bus Arbitration Logic -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Devices for Faster Prototyping
* ispDesignEXPERTTM - LOGIC COMPILER AND COMPLETE ISP DEVICE DESIGN SYSTEMS FROM HDL SYNTHESIS THROUGH IN-SYSTEM PROGRAMMING -- Superior Quality of Results -- Tightly Integrated with Leading CAE Vendor Tools -- Productivity Enhancing Timing Analyzer, Explore Tools, Timing Simulator and ispANALYZERTM -- PC and UNIX Platforms
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Copyright (c) 2000 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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The ispLSI 2128V is a High Density Programmable Logic Device available in 128 and 64 I/O-pin versions. The device contains 128 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 2128V features insystem programmability through the Boundary Scan Test Access Port (TAP). The ispLSI 2128V offers nonvolatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the ispLSI 2128V device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1 .. D7 (see Figure 1). There are a total of 32 GLBs in the ispLSI 2128V device. Each GLB is made up of four macrocells. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device.
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* IN-SYSTEM PROGRAMMABLE
Description
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com
September 2000
2128v_14
1
Output Routing Pool (ORP)
Logic Array
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D Q
C5
D
Q
C4
Output Routing Pool (ORP)
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Specifications ispLSI 2128V
Functional Block Diagram
Figure 1. ispLSI 2128V Functional Block Diagram (128-I/O and 64-I/O Versions)
I/O 127 I/O 126 I/O 125 I/O 124 I/O 123 I/O 122 I/O 121 I/O 120 I/O 119 I/O 118 I/O 117 I/O 116 I/O 115 I/O 114 I/O 113 I/O 112 I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 I/O 49 I/O 48 IN 7* IN 6* IN 7 IN 6
RESET GOE 0 GOE 1 Input Bus
RESET GOE 0 GOE 1 Megablock Input Bus
Output Routing Pool (ORP)
Megablock
Generic Logic Blocks (GLBs)
Output Routing Pool (ORP)
D4 D3 D2 D1 D0 IN 5 IN 4 C7 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 I/O 79 I/O 78 I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64
Output Routing Pool (ORP)
Generic Logic Blocks (GLBs)
D7
D6
D5
D7
D6
D5
D4
D3
D2
D1
D0
IN 5* IN 4*
S
C7 A0
A0 C6
I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 TDI/IN 0 TMS/IN 1
A1 C5
ES IG N
C6 C5 C4 C3 C2 C1 C0 B4 B5 B6 B7
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
Output Routing Pool (ORP)
I/O 0 I/O 1 I/O 2 I/O 3
I/O 47 I/O 46 I/O 45 I/O 44
A1
A2
A3
Output Routing Pool (ORP)
Input Bus
C3
Output Routing Pool (ORP)
Input Bus
Global Routing Pool (GRP)
C4
Input Bus
A3
Input Bus
I/O 4 I/O 5 I/O 6 I/O 7
A2
Global Routing Pool (GRP)
Output Routing Pool (ORP)
I/O 43 I/O 42 I/O 41 I/O 40
A4
A4
Output Routing Pool (ORP)
C2
A5 C1
I/O 8 I/O 9 I/O 10 I/O 11
A5
D
I/O 39 I/O 38 I/O 37 I/O 36
A6 C0
A6 I/O 12 I/O 13 I/O 14 I/O 15 TDI/IN 0 TMS/IN 1
A7
A7
B0
B1
B2
B3
B4
B5
B6
B7
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I/O 35 I/O 34 I/O 33 I/O 32
B0
B1
B2
B3
CLK 0 CLK 1 CLK 2
Output Routing Pool (ORP)
Input Bus ispEN
Output Routing Pool (ORP)
N
Output Routing Pool (ORP)
Input Bus
ispEN
I/O 16 I/O 17 I/O 18 I/O 19
I/O 20 I/O 21 I/O 22 I/O 23
I/O 24 I/O 25 I/O 26 I/O 27
TDO/IN 2 TCK/IN 3
I/O 32 I/O 33 I/O 34 I/O 35
I/O 36 I/O 37 I/O 38 I/O 39
I/O 40 I/O 41 I/O 42 I/O 43
I/O 44 I/O 45 I/O 46 I/O 47
I/O 48 I/O 49 I/O 50 I/O 51
I/O 52 I/O 53 I/O 54 I/O 55
I/O 56 I/O 57 I/O 58 I/O 59
I/O 60 I/O 61 I/O 62 I/O 63
TDO/IN 2 TCK/IN 3
I/O 28 I/O 29 I/O 30 I/O 31
Y0 Y1 Y2
R
0139B/2128V
Y0 Y1 Y2
CLK 0 CLK 1 CLK 2
0139B/2128V.64IO
*Not available on 84-PLCC Device
The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI 2128V device are selected using the dedicated clock pins. Three dedicated clock pins (Y0, Y1,
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Eight GLBs, 32 or 16 I/O cells, two dedicated inputs and two or one ORPs are connected together to make a Megablock (see Figure 1). The outputs of the eight GLBs are connected to a set of 32 or 16 universal I/O cells by the two or one ORPs. Each ispLSI 2128V device contains four Megablocks.
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The 128-I/O 2128V contains 128 I/O cells, while the 64I/O version contains 64 I/O cells. Each I/O cell is directly connected to an I/O pin and can be individually programmed to be a combinatorial input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5V signal levels to support mixed-voltage systems.
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2
Y2) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the ispLSI 2128V are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. When this fuse is erased (JEDEC "1"), the output is configured as a totem-pole output. When this fuse is programmed (JEDEC "0"), the output is configured as an open-drain. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the ispDesignEXPERT software tools.
Specifications ispLSI 2128V
Absolute Maximum Ratings 1
Supply Voltage Vcc .................................. -0.5 to +5.6V Input Voltage Applied ............................... -0.5 to +5.6V Off-State Output Voltage Applied ............ -0.5 to +5.6V
Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
SYMBOL
PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial
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DC Recommended Operating Condition
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MIN. 3.0 3.0 VSS - 0.5 2.0 MAX. 3.6 3.6 0.8 5.25 UNITS V V V V
Table 2-0005/2128V
TA = -40C to + 85C
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Capacitance (TA=25C, f=1.0 MHz)
SYMBOL
FO
VIL VIH
R
N
VCC
TA = 0C to + 70C
PARAMETER Dedicated Input Capacitance I/O Capacitance
TYPICAL 10 10 15
UNITS pf pf pf
21
C1 C2 C3
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Clock and Global Output Enable Capacitance
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Data Retention Specifications
Data Retention
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PARAMETER
SI
MINIMUM 20 10000
MAXIMUM - -
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ispLSI Erase/Reprogram Cycles
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3
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UNITS Years Cycles
Case Temp. with Power Applied .............. -55 to 125C
TEST CONDITIONS VCC = 3.3V, VIN = 2.0V VCC = 3.3V, VI/O = 2.0V VCC = 3.3V, VY = 2.0V
Table 2-0006/2128V
Table 2-0008/2128V
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Storage Temperature ................................ -65 to 150C
Specifications ispLSI 2128V
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time Input Timing Reference Levels Output Timing Reference Levels Output Load GND to 3.0V 3ns 10% to 90% 1.5V 1.5V See Figure 2
Figure 2. Test Load
+ 3.3V R1
R2
Output Load Conditions (see Figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 316 316 316 R2 348 348 348 348 348 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
C
Table 2-0004/2128V
DC Electrical Characteristics
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current
Over Recommended Operating Conditions
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FO
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N
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D
CONDITION MIN. - 2.4 - - - - - - - TYP. - - - - - - - - 195
3
21
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.)
ES IG N
CL*
0.4 - -10 10 50 -150 -150 -100 -
3-state levels are measured 0.5V from steady-state Table 2 - 0003/2000 active level.
MAX. UNITS V V A A mA A A mA mA
Input or I/O High Leakage Current ispEN Input Low Leakage Current
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I/O Active Pull-Up Current
Output Short Circuit Current
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Operating Power Supply Current
Table 2-0007/2128V 1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 100% tested. 2. Measured using eight 16-bit counters. 3. Typical values are at VCC = 3.3V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum ICC .
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(VCC - 0.2)V VIN VCC V VIN 5.25V CC 0V VIN VIL 0V VIN VIL VCC = 3.3V, VOUT = 0.5V VIL = 0.0V, VIH = 3.0V fCLOCK = 1 MHz
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0213A/2128V
Device Output
Test Point
Specifications ispLSI 2128V
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 # COND. A A A - - - A - - - - A - B C B C - - 1 2 3 4 5 6 7 8 9
4
DESCRIPTION
1
-80 - - 80.0
1
-60 - - 61.7 51.3 71.4 9.0 - 0.0 - 0.0 - 8.0 - - - - 7.0 7.0 15.0 20.0 - - - -
MIN. MAX. MIN. MAX. 10.0 15.0 - - - -
UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns
18 External Synchronous Clock Pulse Duration, High 19 External Synchronous Clock Pulse Duration, Low
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tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl
1. 2. 3. 4.
Data Propagation Delay, 4PT Bypass, ORP Bypass Data Propagation Delay Clock Frequency with Internal Feedback 3 Clock Frequency with External Feedback ( tsu2 + tco1) Clock Frequency, Max. Toggle GLB Reg. Setup Time before Clock, 4 PT Bypass GLB Reg. Clock to Output Delay, ORP Bypass GLB Reg. Hold Time after Clock, 4 PT Bypass GLB Reg. Setup Time before Clock
100 7.0 -
0.0 9.0 -
D EW
0.0 - 7.0 - - - - 5.0 5.0
10 GLB Reg. Clock to Output Delay 11 GLB Reg. Hold Time after Clock 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable
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21
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Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions section.
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5
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6.5 - - - 14.0 - 15.0 15.0 10.0 10.0 - - 8.5 - - - 16.0 - 18.0 18.0 12.0 12.0 - - 11.0 7.5 9.5
64.5
Table 2-0030/2128V
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Specifications ispLSI 2128V
Internal Timing Parameters1
Over Recommended Operating Conditions
PARAMETER Inputs 21 Dedicated Input Delay 22 GRP Delay 23 4 Product Term Bypass Path Delay (Combinatorial) 24 4 Product Term Bypass Path Delay (Registered) 25 1 Product Term/XOR Path Delay 26 20 Product Term/XOR Path Delay 27 XOR Adjacent Path Delay 3 28 GLB Register Bypass Delay 29 GLB Register Setup Time before Clock 30 GLB Register Hold Time after Clock 31 GLB Register Clock to Output Delay 32 GLB Register Reset to Output Delay 33 GLB Product Term Reset to Register Delay 35 GLB Product Term Clock Delay 36 ORP Delay - - 1.3 1.2 - - 1.4 #
2
DESCRIPTION
-80
-60
MIN. MAX. MIN. MAX. - 0.4 - 0.6
UNITS
GRP
tgrp
GLB
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2.1 5.8 7.5 9.2 9.5 11.3 0.3 - - 1.6 2.5 5.6 8.5 5.6 1.4 0.4 2.2 12.2 4.9 4.9 5.1 2.3 2.3 7.9 - - - - - - 0.2 8.0 - - - - 6.5 - - - - - - - 4.2 4.2 - 9.6 10.3 12.3 12.3 14.4 1.3 - - 1.6 2.8 9.3 10.4 9.3 1.5 0.5 2.2 12.2 4.9 4.9 7.1 4.2 4.2 9.5
ORP
37 ORP Bypass Delay
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torp torpbp
Outputs
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t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
- - - - - -
D EW N
0.2 5.4 - - - - 3.8 - - - - - - - 2.3 2.3 -
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FO
34 GLB Product Term Output Enable to I/O Cell Delay
42 Global Output Enable
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tob tsl toen todis tgoe
Clocks
38 Output Buffer Delay
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39 Output Slew Limited Delay Adder 40 I/O Cell OE to Output Enabled 41 I/O Cell OE to Output Disabled
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Global Reset
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tgr
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tgy0 tgy1/2
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43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 44 Clock Delay, Y1 or Y2 to Global GLB Clock Line 45 Global Reset to GLB
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR adjacent path can only be used by hard macros.
Table 2-0036/2128V
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ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tio tdin
20 Input Buffer Delay
ns
Specifications ispLSI 2128V
ispLSI 2128V Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #23 GRP #22 Reg 4 PT Bypass #24 20 PT XOR Delays #25, 26, 27 Reset #45 D RST #29, 30, 31, 32 GLB Reg Bypass #28 GLB Reg Delay Q ORP Bypass #37 ORP Delay #36 GLB ORP I/O Cell
#21 I/O Delay #20
Y0,1,2 GOE 0
#43, 44 #42
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Control RE PTs OE #33, 34, CK 35
D
#40, 41
0491/2032
Derivations of tsu, th and tco from the Product Term Clock
= = = = = = = = Logic + Reg su - Clock (min) (tio + tgrp + t20ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#20+ #22+ #26) + (#29) - (#20+ #22+ #35) (0.4 + 1.2 + 9.5) + (0.2) - (0.4 + 1.2 + 3.8) Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t20ptxor) (#20+ #22+ #35) + (#30) - (#20+ #22+ #26) (0.4 + 1.2 + 5.6) + (5.4) - (0.4 + 1.2 + 9.5) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#20+ #22+ #35) + (#31) + (#36 + #38) (0.4 + 1.2 + 5.6) + (1.6) + (1.4 + 2.2)
th
1.5 ns
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Note: Calculations are based upon timing specifications for the ispLSI 2128V-80L.
Table 2-0042/2128V
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21
tco
= = = 12.4 ns =
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5.9 ns
FO
tsu
7
R
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I/O Pin (Input)
#38, 39
I/O Pin (Output)
Specifications ispLSI 2128V
Power Consumption
Power consumption in the ispLSI 2128V device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure 3. Typical Device Power Consumption vs fmax
275
Figure 3 shows the relationship between power and operating speed.
250
ispLSI 2128V 225
200
0
20
40
60
80
fmax (MHz)
Notes: Configuration of eight 16-bit counters Typical current at 3.3V, 25 C
21
The ICC estimate is based on typical conditions (VCC = 3.3V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
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Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz)
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ICC (mA) = 40 + (# of PTs * 0.6) + (# of nets * Max freq * 0.004)
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ICC can be estimated for the ispLSI 2128V using the following equation:
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175
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0127/2128V
When Lattice 3.3V 2000V devices are used in mixed 5V/ 3.3V applications, some consideration needs to be given to the power-up sequence. When the I/O pins on the 3.3V ispLSI devices are driven directly by 5V devices, a low impedance path can exist on the 3.3V device between its I/O and Vcc pins when the 3.3V supply is not present. This low impedance path can cause current to flow from the 5V device into the 3.3V ispLSI device. The maximum current occurs when the signals on the I/O pins are driven high by the 5V devices. If a large enough current flows through the 3.3V I/O pins, latch-up can occur and permanent device damage may result.
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Power-up Considerations
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This latch-up condition occurs only during the power-up sequence when the 5V supply comes up before the 3.3V supply. The Lattice 3.3V ispLSI devices are guaranteed to withstand 5V interface signals within the device operating Vcc range of 3.0V to 3.6V. The recommended power-up options are as follows: Option 1: Ensure that the 3.3V supply is powered-up and stable before the 5V supply is powered up. Option 2: Ensure that the 5V device outputs are driven to a high impedance or logic low state during power-up.
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ICC (mA)
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Specifications ispLSI 2128V
Pin Description
NAME
I/O 0 - I/O 4 I/O 5 - I/O 9 I/O 10 - I/O 14 I/O 15 - I/O 19 I/O 20 - I/O 24 I/O 25 - I/O 29 I/O 30 - I/O 34 I/O 35 - I/O 39 I/O 40 - I/O 44 I/O 45 - I/O 49 I/O 50 - I/O 54 I/O 55 - I/O 59 I/O 60 - I/O 64 I/O 65 - I/O 69 I/O 70 - I/O 74 I/O 75 - I/O 79 I/O 80 - I/O 84 I/O 85 - I/O 89 I/O 90 - I/O 94 I/O 95 - I/O 99 I/O 100 - I/O 104 I/O 105 - I/O 109 I/O 110 - I/O 114 I/O 115 - I/O 119 I/O 120 - I/O 124 I/O 125 - I/O 127 IN 4 - IN 7 GOE 0, GOE 1 RESET Y0, Y1, Y2
160-PIN PQFP PIN NUMBERS 176-PIN TQFP PIN NUMBERS
25, 30, 35, 41, 47, 52, 57, 66, 71, 76, 83, 88, 93, 106, 111, 116, 123, 128, 133, 138, 147, 152, 157, 4, 9, 14, 104, 100, 19 18, 103, 98 26, 31, 36, 43, 48, 53, 58, 67, 72, 77, 84, 89, 94, 107, 112, 117, 124, 129, 134, 143, 148, 153, 158, 5, 10, 15, 141, 21 27, 32, 37, 44, 49, 54, 63, 68, 73, 78, 85, 90, 95, 108, 113, 118, 125, 130, 135, 144, 149, 154, 160, 6, 11, 16 61, 28, 33, 38, 45, 50, 55, 64, 69, 74, 80, 86, 91, 96, 109, 114, 120, 126, 131, 136, 145, 150, 155, 1, 7, 12, 17 29, 34, 40, 46, 51, 56, 65, 70, 75, 81, 87, 92, 105, 110, 115, 121, 127, 132, 137, 146, 151, 156, 3, 8, 13, 28, 33, 39, 45, 51, 57, 62, 73, 79, 84, 91, 96, 102, 117, 122, 128, 135, 140, 146, 151, 162, 168, 173, 4, 10, 15, 114, 110, 21 20, 113, 29, 34, 40, 47, 52, 58, 63, 74, 80, 85, 92, 98, 103, 118, 123, 129, 136, 141, 147, 158, 163, 169, 174, 5, 11, 16, 155, 23 30, 35, 41, 48, 53, 59, 70, 75, 81, 86, 93, 99, 104, 119, 125, 130, 137, 142, 148, 159, 164, 170, 176, 6, 12, 17 67, 31, 37, 42, 49, 54, 60, 71, 76, 82, 88, 94, 100, 105, 120, 126, 132, 138, 144, 149, 160, 165, 171, 1, 7, 13, 19 32, 38, 44, 50, 56, 61, 72, 77, 83, 89, 95, 101, 116, 121, 127, 133, 139, 145, 150, 161, 167, 172, 3, 8, 14,
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
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TDI/IN 0
24
28
TCK/IN 3
97
21
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TMS/IN 1
60
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TDO/IN 2
140
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SE
GND
VCC NC1
22, 122, 2, 101, 102
62, 42, 139, 159 20, 39, 119, 142
79, 59,
VE
ispEN
23
25
FO
108
26
107
66
154
99, 82,
24, 134, 2, 111, 9, 64, 112, 157,
46, 68, 153, 175 22, 43, 131, 156 18, 69, 115, 166 27, 78, 124,
87, 65,
109, 90,
36, 55, 97, 106, 143, 152,
EW
Dedicated input pins to the device Global Output Enable input pins Active Low (0) Reset pin which resets all the registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs in the device. Input Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input This pin performs two functions. When ispEN is logic low, it functions as a serial data input pin to load programming data into the device. When ispEN is high, it functions as a dedicated input pin. Input This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the ISP/Boundary Scan state machine.When ispEN is high, it functions as a dedicated input pin. Input This pin performs two functions. When ispEN is logic low, it functions as a mode control pin for the ISP/Boundary Scan state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Ground (GND) Vcc No Connect.
D
Table 2-0002A/2128V
1. NC pins are not to be connected to any active signal, VCC or GND.
9
ES IG N
S
Specifications ispLSI 2128V
Pin Description
NAME
I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 I/O 32 - I/O 35 I/O 36 - I/O 39 I/O 40 - I/O 43 I/O 44 - I/O 47 I/O 48 - I/O 51 I/O 52 - I/O 55 I/O 56 - I/O 59 I/O 60 - I/O 63 IN 4 - IN 7 GOE 0, GOE 1 RESET Y0, Y1, Y2 ispEN TDI/IN 0 64, 20 19, 24 25 22
84-PIN PLCC PIN NUMBERS
26, 30, 34, 38, 45, 49, 53, 57, 68, 72, 76, 80, 3, 7, 11, 15, 27, 31, 35, 39, 46, 50, 54, 58, 69, 73, 77, 81, 4, 8, 12, 16, 28, 32, 36, 40, 47, 51, 55, 59, 70, 74, 78, 82, 5, 9, 13, 17, 29, 33, 37, 41, 48, 52, 56, 60, 71, 75, 79, 83, 6, 10, 14, 18
100-PIN TQFP PIN NUMBERS
17, 22, 27, 32, 40, 45, 49, 55, 67, 72, 77, 82, 90, 95, 99, 5, 66, 62, 11 10, 15 16 18, 23, 28, 33, 41, 46, 51, 56, 68, 73, 78, 83, 91, 96, 1, 6, 19, 24, 29, 34, 42, 47, 52, 57, 69, 74, 79, 84, 92, 97, 2, 7, 20, 26, 30, 35, 43, 48, 53, 58, 70, 76, 80, 85, 93, 98, 3, 8 9
DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
88, 38, 13
Dedicated input pins to the device
67, 62
65, 60
TCK/IN 3
61
59
TMS/IN 1
43
37
TDO/IN 2
1
87
21
28
Input -- Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. Input -- This pin performs two functions. When ispEN is logic low, it functions as a serial data input pin to load programming data into the device. When ispEN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the ISP/Boundary Scan state machine. When ispEN is high, it functions as a dedicated input pin. Input -- This pin performs two functions. When ispEN is logic low, it functions as a mode control pin for the ISP/Boundary Scan state machine. When ispEN is high, it functions as a dedicated input pin. Output/Input -- This pin performs two functions. When ispEN is logic low, it functions as an output pin to read serial shift register data. When ispEN is high, it functions as a dedicated input pin. Ground (GND)
GND VCC NC1
23, 44, 2, 66
63,
84
14, 39,
21, 42,
65
12, 36, 63,
VE
61,
86 89 31, 64, 94,
SI
pL
4, 21, 25, 44, 50, 54, 71, 75, 81, 100
FO
Vcc No Connect.
R
N
Active Low (0) Reset pin which resets all the registers in the device. Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs in the device.
EW
Global Output Enable input pins
D
Table 2-0002B/2128V
1. NC pins are not to be connected to any active signal, VCC or GND.
U
SE
is
10
ES IG N
S
Specifications ispLSI 2128V
Pin Configuration
ispLSI 2128V 176-Pin TQFP Pinout Diagram
I/O 112 GND I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 NC1 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 NC1 VCC IN 5 TDO/IN 2 GND NC1 I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 NC1 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 GND I/O 79 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133
is
I/O 15 GND I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 NC1 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 NC1 VCC TMS/IN 1 IN 6 GND NC1 I/O 32 I/O 33 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 NC1 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 GND I/O 48
pL
SI
I/O 113 VCC I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 1NC I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 1 NC IN 7 Y0 RESET VCC GOE 1 GND ispEN TDI/IN 0 1NC I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1NC I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 VCC I/O 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
21
28
VE
FO
R
Top View
N
ispLSI 2128V
132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89
EW
D
11
1. NC pins are not to be connected to any active signals, VCC or GND.
U
SE
ES IG N
176-TQFP/2128V
S
I/O 78 VCC I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 NC1 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 NC1 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 NC1 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 NC1 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 VCC I/O 49
Specifications ispLSI 2128V
Pin Configuration
ispLSI 2128V 160-Pin PQFP Pinout Diagram
I/O 112 GND I/O 111 I/O 110 I/O 109 I/O 108 I/O 107 I/O 106 I/O 105 I/O 104 I/O 103 I/O 102 I/O 101 I/O 100 I/O 99 I/O 98 I/O 97 I/O 96 VCC IN 5 TDO/IN 2 GND I/O 95 I/O 94 I/O 93 I/O 92 I/O 91 I/O 90 I/O 89 I/O 88 I/O 87 I/O 86 I/O 85 I/O 84 I/O 83 I/O 82 I/O 81 I/O 80 GND I/O 79
is
SE
1. NC pins are not to be connected to any active signal, VCC or GND.
U
I/O 15 GND I/O 16 I/O 17 I/O 18 I/O 19 I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 I/O 25 I/O 26 I/O 27 I/O 28 I/O 29 I/O 30 I/O 31 VCC TMS/IN 1 IN 6 GND I/O 32 I/O 34 I/O 34 I/O 35 I/O 36 I/O 37 I/O 38 I/O 39 I/O 40 I/O 41 I/O 42 I/O 43 I/O 44 I/O 45 I/O 46 I/O 47 GND I/O 48
pL
41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
SI
I/O 113 VCC I/O 114 I/O 115 I/O 116 I/O 117 I/O 118 I/O 119 I/O 120 I/O 121 I/O 122 I/O 123 I/O 124 I/O 125 I/O 126 I/O 127 IN 7 Y0 RESET VCC GOE 1 GND ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 VCC I/O 14
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Top View
21
28
VE
FO
R
ispLSI 2128V
N
EW
D
12
ES IG N
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
I/O 78 VCC I/O 77 I/O 76 I/O 75 I/O 74 I/O 73 I/O 72 I/O 71 I/O 70 I/O 69 I/O 68 I/O 67 I/O 66 I/O 65 I/O 64 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 63 I/O 62 I/O 61 I/O 60 I/O 59 I/O 58 I/O 57 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 I/O 51 I/O 50 VCC I/O 49
160-PQFP/2128LV
S
Specifications ispLSI 2128V
Pin Configuration
ispLSI 2128V 100-Pin TQFP Pinout Diagram
NC1 I/O 56 I/O 55 I/O 54 I/O 53 I/O 52 NC1 I/O 51 I/O 50 I/O 49 I/O 48 VCC IN 5 TDO/IN 2 GND I/O 47 I/O 46 I/O 45 I/O 44 NC1 I/O 43 I/O 42 I/O 41 I/O 40 I/O 39
pL
I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 1 NC I/O 12 I/O 13 I/O 14 I/O 15 VCC TMS/IN 1 IN 6 GND I/O 16 I/O 17 I/O 18 I/O 19 1 NC I/O 20 I/O 21 I/O 22 I/O 23 I/O 24 1 NC
SI
21
28
I/O 57 I/O 58 I/O 59 1 NC I/O 60 I/O 61 I/O 62 I/O 63 IN 7 Y0 RESET VCC GOE 1 GND ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 1 NC I/O 4 I/O 5 I/O 6 1 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
ispLSI 2128V
Top View
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VE
FO
R
N
EW
D
13
1. NC pins are not to be connected to any active signals, VCC or GND.
U
SE
is
ES IG N
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC1 I/O 38 I/O 37 I/O 36 NC1 I/O 35 I/O 34 I/O 33 I/O 32 IN 4 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 NC1 I/O 27 I/O 26 I/O 25
100-TQFP/2128V
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
S
Specifications ispLSI 2128V
Pin Configuration
ispLSI 2128V 84-Pin PLCC Pinout Diagram
TDO/IN 2
I/O 56
I/O 55
I/O 54
I/O 53
I/O 52
I/O 51
I/O 50
I/O 49
I/O 48
I/O 47
I/O 46
I/O 45
I/O 44
I/O 43
I/O 42
I/O 41
I/O 40
I/O 39
GND
VCC
I/O 57 I/O 58 I/O 59 I/O 60 I/O 61 I/O 62 I/O 63 Y0 RESET VCC GOE 1 GND ispEN TDI/IN 0 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6
12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
D EW N
Top View
R
ispLSI 2128V
FO
VE
28
21
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
pL
I/O 7
I/O 8
I/O 9
SI
VCC
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
GND
I/O 16
I/O 17
I/O 18
I/O 19
I/O 20
I/O 21
I/O 22
I/O 23
SE
1. NC pins are not to be connected to any active signals, VCC or GND.
0123/2128V
U
is
TMS/IN1
14
I/O 24
ES IG N
74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 I/O 38 I/O 37 I/O 36 I/O 35 I/O 34 I/O 33 I/O 32 Y1 NC1 VCC GOE 0 GND Y2 TCK/IN 3 I/O 31 I/O 30 I/O 29 I/O 28 I/O 27 I/O 26 I/O 25
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
S
Specifications ispLSI 2128V
Part Number Description
ispLSI
Device Family Device Number Speed 80 = 80 MHz fmax 60 = 60 MHz fmax
2128V - XX
X
XXXX X
Grade Blank = Commercial I = Industrial Package T176 = 176-Pin TQFP Q160 = 160-Pin PQFP T100 = 100-Pin TQFP J84 = 84-Pin PLCC Power L = Low
D
ispLSI 2128V Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 80 80 80 80 ispLSI 60 60 60 60
*Contact factory for availability.
tpd (ns) 10 10 10 10 15 15 15 15
I/Os 128 128 64 64 128 128 64 64
ORDERING NUMBER ispLSI 2128V-80LQ160 ispLSI 2128V-80LT100 ispLSI 2128V-80LJ84 ispLSI 2128V-60LT176 ispLSI 2128V-60LQ160 ispLSI 2128V-60LT100 ispLSI 2128V-60LJ84
N
EW
R
ispLSI 2128V-80LT176
FO
VE
28
21
INDUSTRIAL
I/Os 128 64 ORDERING NUMBER ispLSI 2128V-60LT176I ispLSI 2128V-60LT100I PACKAGE 176-Pin TQFP 100-Pin TQFP
Table 2-0041B/2128V
pL
ispLSI
60 60
U
SE
is
SI
FAMILY
fmax (MHz)
tpd (ns) 15 15
15
ES IG N
PACKAGE 176-Pin TQFP 160-Pin PQFP 100-Pin TQFP 84-Pin PLCC 176-Pin TQFP 160-Pin PQFP 100-Pin TQFP 84-Pin PLCC
0212/2128V
Table 2-0041A/2128V
S

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