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SI9241AEY
Vishay Siliconix
Single-Ended Bus Transceiver
FEATURES
D Operating Power Supply Range 6 V v VBAT v 36 V D Reverse Battery Protection Down to VBAT w -24 V D Standby Mode With Very Low Current Consumption IBAT(SB) = 1 mA @ VDD = 0.5 V D Low Quiescent Current in OFF Condition IBAT = 120 mA and IDD v 10 mA D ISO 9141 Compatible D D D D D D D Overtemperature Shutdown Function For K Output Defined K Output OFF for Open GND Defined Receive Output Status for Open K Input Defined K Output OFF for TX Input Open Open Drain Fault Output 2-kV ESD Typical Transmit Speeds of 200 kBaud
DESCRIPTION
The SI9241AEY is a monolithic bus transceiver designed to provide bidirectional serial communication in automotive diagnostic applications. The SI9241AEY is built on the Vishay Siliconix BiC/DMOS process. An epitaxial layer prevents latchup. The RX output is capable of driving CMOS or 1 LSTTL load.
The device incorporates protection against overvoltages and short circuits to VBAT. The transceiver pin is protected and can be driven beyond the VBAT voltage.
The SI9241AEY is available in a space efficient 8-pin SO package. It operates reliably over the automotive temperature range (-40 to 125_C). The SI9241AEY is available in both standard and lead (Pb)-free packages.
PIN CONFIGURATION AND FUNCTIONAL BLOCK DIAGRAM
VDD
VBAT VBAT
RX VDD
- +
2
K CS TX FAULT Fault Detector
GND
Document Number: 70787 S-40137--Rev. E, 16-Feb-04
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SI9241AEY
Vishay Siliconix
OUTPUT TABLE AND STATE DIAGRAMS
Over Temp Power On A=1 Over Temp @CS Short Circuit Power On B=1 CS Note: Over Temp is an internal condition, not meant to be a logic signal. B=0 A=0
STATE INPUTS VARIABLE
CS
0 0 X 0 1 1
OUTPUT TABLE
RX
0 1 K K 0 1
TX
0 1 X X X X
A
1 1 0 1 1 1
B
1 1 1 0 1 1
K
0 1 HiZ HiZ 0 1
FAULT
1 1 0 0 1 1
Comments
Over Temp Short Circuit Receive Mode
X = "1" or "0" HiZ = High Impedance State
ABSOLUTE MAXIMUM RATINGS
Voltage Referenced to Ground Voltage On VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -24 V to 45 V Voltage K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -16 V to (VBAT + 1 V) Voltage Difference V(VBAT, K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 V Voltage or Max. Current On Any Pin (Except VBAT , K) . . . . . . . . . . . . . . . . . . . . . -0.3 V to (VDD + 0.3 V) or 10 mA Voltage on VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V K Pin Only, Short Circuit Duration (to VBAT or GND) . . . . . . . . . . Continuous Operating Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 to 125_C Junction and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . -55 to 150_C Thermal Resistance QJA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125_C/W
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING RANGE
Voltage Referenced to Ground VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5 V to 5.5 V VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V to 36 V K . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V to 36 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VDD
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Document Number: 70787 S-40137--Rev. E, 16-Feb-04
SI9241AEY
Vishay Siliconix
SPECIFICATIONS
Test Conditions Unless Specified Parameter Transmitter and Logic Levels
CS, TX Input Low Voltage CS, TX Input High Voltage TX Input Capacitanced CS, TX Input Pull-up Resistance VILT VIHT CINT RTX, RCS VDD = 5.5 V, TX or CS = 1.5 V, 3.5 V Full Full Full Full 10 20 3.5 10 40 1.5 V pF kW
Limits
-40 to 125_C
Symbol
VDD = 4.5 to 5 5 V 4 5 5.5 VBAT = 6 to 36 V
Tempa
Minb
Typc
Maxb
Unit
K Transmit
RL = 510 W "5% , VBAT = 6 to 18 V K Output Low Voltage p g VOLK RL = 1 kW "5% , VBAT = 16 to 36 V RL = 510 W "5% , VBAT = 4.5 V K Output High Voltage K Rise, Fall Times K Output Sink Resistance K Output Capacitanced VOHK tr, tf Rsi CO RL = 510 W "5% , VBAT = 4.5 to 18 V RL = 1 kW "5% , VBAT = 16 to 36 V See Test Circuit CS = 0 V TX = 0 V V, Full Full Full Full Full Full Full Full 0.95 VBAT 0.95 VBAT 9.6 110 20 ms W pF 0.2 VBAT 0.2 VBAT 1.2 V
Receiver
K Input Low Voltage K Input High Voltage K Input Hysteresis,c, d K Input Currents RX Output Low Voltage RX Pull-up Resistance VILK VIHK VHYS IIHK VOLR RRX td( ) d(on) RL = 510 W "5% , VBAT = 6 to 18 V CL = 10 nF, See Test Circuit RL = 1 kW "5% , VBAT = 16 to 36 V CL = 4.7 nF, See Test Circuit RL = 510 W "5% , VBAT = 6 to 18 V CL = 10 nF, See Test Circuit RL = 1 kW "5% , VBAT = 16 to 36 V CL = 4.7 nF, See Test Circuit CS = 4 V VIHK = VBAT VILK = 0.35 VBAT IOLR = 1 mA Full Full Full Full Full Full Full Full Full Full 5 3 3 3 3 0.65 VBAT 0.05 VBAT 20 0.4 20 10 10 10 10 ms mA V kW 0.35 VBAT V
RX Turn On Delay
RX Turn Off Delay
td( ff) d(off)
Supplies
Bat Supply Current On Bat Supply Current Off Bat Supply Current Standby Logic Supply Current On Logic Supply Current Off IBAT(on) IBAT(off) IBAT(SB) IDD(on) IDD(off) CS = TX = 0 V, VBAT v 16 V CS = High, VBAT v 12 V, TX = Highf VDD v 0.5 V, VBAT v 12 V VDD v 5.5 V, TX = 0 V CS = High, VBAT v 12 V, TX = Highf Full Full Full Full Full 1.2 120 t1 1.4 3 220 10 2.3 10 mA mA mA mA
Miscellaneous
TX Transmit Baud Rate RX Receive Baud Ratec Transmission Frequency Fault Output Low Voltage CS Minimum Pulse Widthd, e Over Temperature Shutdownd Temperature Shutdown Hysteresisc BRT BRR fK-RXK VOLF tcs TSHUT THYST Temperature Rising RL = 510 W , CL = 10 nF 6 V t VBAT < 16 V, CRX = 20 pF 6 V t VBAT < 16 V, RK = 510 W, CK v 1.3 nF CS = TX = 0 V, K = VBAT, IOLF = 1 mA Full Full Full Full Full 1 160 180 30 50 10.4 200 200 0.4 kBaud kHz V ms _C
Notes a. Room = 25_C, Cold and Hot = as determined by the operating temperature suffix. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. Guaranteed by design, not subject to production test. e. Minimum pulse width to reset a fault condition. f. High referes to Logic High and Low refers to Logic Low.
Document Number: 70787 S-40137--Rev. E, 16-Feb-04
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SI9241AEY
Vishay Siliconix
PIN CONFIGURATION
Narrow Body SO Package VDD TX CS FAULT 1 2 3 4 8 7 6 5 RX VBAT K GND
ORDERING INFORMATION
Part Number
SI9241AEY -T1 SI9241AEY -T1--E3 (Lead (Pb)-Free) -40 to 125_C 40
Temperature Range
Top View
PIN DESCRIPTION
Pin Number
1 2 3 4 5 6 7 8
Symbol
VDD TX CS FAULT GND K VBAT RX
Description
Positive Power Supply Transmit, Input Chip Select, Input Fault, Open Drain Output Ground Connection Transmit/Receive, Bidirectional Battery Power Supply Receiver, Output
FUNCTIONAL DESCRIPTION
The SI9241AEY can be either in transmit or receive mode and it contains over temperature, and short circuit VBAT fault detection circuits. The voltage on K is internally compared to VBAT/2. If the voltage on the K pin is less than VBAT/2 then RX output will be "low." If the voltage on the K pin is greater than VBAT/2 then RX output will be "high." In order to be in transmit mode, CS must be set "low." When CS and TX are set "low" the internal MOSFET will turn on, causing the K pin to be "low." In the transmit mode, the processor monitors RX and TX. When the two mirror each other there is no fault. In the event of over temperature, or short
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circuit to VBAT, the SI9241AEY will turn off the K output to protect the IC and the external open drain FAULT pin will be asserted. The K pin will stay in high impedance and RX will follow the K pin. The fault will be reset when CS is toggled high. RX, CS and TX pins have an internal pull up resistor to VDD while the K pin has internal pull down resistors. When any one of the TX, VBAT or GND pins is open the K output is off. When CS is set "high" the SI9241AEY is in receive mode and the internal MOSFET for the K pin is turned off. The RX output will follow the K pin. If CS is "low" while the IC is receiving data, an incorrect fault signal will occur. To inhibit the short detect, tie CS and TX together.
Document Number: 70787 S-40137--Rev. E, 16-Feb-04
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SI9241AEY
Vishay Siliconix
TEST CIRCUIT AND TIMING DIAGRAMS (TRANSMIT ONLY)
VDD VBAT RX td(off) td(on)
SI9241AEY
VDD VBAT RX VDD + - V + - RL K 80% TX TXmin VBAT
80%
CL TX VK
20%
20%
tr
tf
GND CS
RL = 510 W, CL = 10 nF, VBAT = 6 V to 18 V RL = 1 kW, CL = 4.7 nF, VBAT = 16 V to 36 V
APPLICATION CIRCUIT
ECU VDD
SI9241AEY
Diagnostic Tester
+ - V
VB + - K-Line 510 W
VDD
I/Os
Microcontroller 0.4 W
VDD
SI9241AEY
VDD VBAT C1 0.1 mF 50 V
+ - V
+ -
L-Line
VDD C1 0.1 mF Bus
ECU = Electronic Control Unit Document Number: 70787 S-40137--Rev. E, 16-Feb-04 www.vishay.com
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