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| Final Electrical Specifications LTC1067/LTC1067-50 Rail-to-Rail, Very Low Noise Universal Dual Filter Building Block February 1998 FEATURES s s s s s DESCRIPTION The LTC (R)1067/LTC1067-50 consist of two identical railto-rail, high accuracy and very wide dynamic range 2nd order switched-capacitor building blocks. Each building block, together with three to five resistors, provides 2nd order filter functions such as bandpass, highpass, lowpass, notch and allpass. High precision 4th order filters are easily designed. The center frequency of each 2nd order section is tuned by the external clock frequency. The internal clock-to-center frequency ratio (100:1 for the LTC1067 and 50:1 for the LTC1067-50) can be modified by the external resistors. These devices have a double sampled architecture which places aliasing and imaging components at twice the clock frequency. The LTC1067-50 is a low power device consuming about one half the current of the LTC1067. The LTC1067-50's typical supply current is about 1mA from a 3.3V supply. The LTC1067 and LTC1067-50 are available in 16-pin GN and SO packages. Mask programmable versions of the LTC1067 and LTC1067-50, with thin film resistors on-chip and custom clock-to-cutoff frequency ratios, can be designed to realize application specific monolithic filters, in an SO-8 package. Please contact LTC Marketing for more details. s s s s Dual 2nd Order Filter in a 16-Lead SO Package Rail-to-Rail Input and Output Operation Operates from a Single 3V to 5V Supply > 80dB Dynamic Range on Single 3.3V Supply Clock-to-Center Frequency Ratio of 100:1 for the LTC1067 and 50:1 for the LTC1067-50 Internal Sampling-to-Center Frequency Ratio of 200:1 for the LTC1067 and 100:1 for the LTC1067-50 Center Frequency Error < 0.2% Typ Low Noise: < 40VRMS, Q 5 Customizable with Internal Resistors APPLICATIONS s s s Data Acquisition Filters Telecom Filters Noise Reduction Systems , LTC and LT are registered trademarks of Linear Technology Corporation. TYPICAL APPLICATION Single 3.3V Supply Rail-to-Rail, 4th Order, 5kHz Bandpass Filter 1 2 3.3V 0.1F 3 4 5 R31, 200k R21, 10k R11 200k IN 6 7 8 V+ NC V+ LTC1067 SA LPA BPA SB LPB BPB CLK AGND V- 16 15 14 13 12 11 10 9 TOTAL OUTPUT NOISE: 90VRMS S/N RATIO: 80dB 1067 TA01 0 fCLK = 500kHz 1F GAIN (dB) -10 -20 OUT R32, 200k R22, 10k -30 HPA/NA HPB/NB INV A INV B RB1, 200k -40 4.0 Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. U U U Frequency Response 4.5 5.0 FREQUENCY (kHz) 5.5 6.0 1067 * TA02 1 LTC1067/LTC1067-50 ABSOLUTE MAXIMUM RATINGS Total Voltage Supply (V + to .............................. 12V Input Voltage ........................ (V + + 0.3V) to (V - - 0.3V) Output Short-Circuit Duration .......................... Indefinite Power Dissipation............................................... 500mV Operating Temperature Range LTC1067C................................................ 0C to 70C LTC1067I............................................ - 40C to 85C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec).................. 300C V -) PACKAGE/ORDER INFORMATION TOP VIEW V+ 1 16 CLK 15 AGND 14 V - 13 SB 12 LPB 11 BPB 10 HPB/NB 9 INV B ORDER PART NUMBER LTC1067CGN LTC1067-50CGN LTC1067IGN LTC1067-50IGN LTC1067CS LTC1067-50CS LTC1067IS LTC1067-50IS NC 2 V+ 3 SA 4 LPA 5 BPA 6 HPA/NA 7 INV A 8 GN PACKAGE S PACKAGE 16-LEAD PLASTIC SSOP 16-LEAD PLASTIC SO TJMAX = 110C, JA = 135C/ W (GN) TJMAX = 110C, JA = 115C/ W (S) Consult factory for Military grade parts. ELECTRICAL CHARACTERISTICS PARAMETER Operating Supply Range Positive Output Voltage Swing CONDITIONS VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = 5V, RL = 10k VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = 5V, RL = 10k VS = 3V VS = 4.75V VS = 5V RL = 10k RL = 10k RL = 10k LTC1067 (internal op amps) VS = 4.75V, TA = 25C, unless otherwise noted. MIN 3 2.65 4.25 4.15 TYP 2.80 4.50 4.50 0.020 0.025 - 4.96 16/1.0 33/2.2 70/7.2 90 2.8 2.25 MAX 11 UNITS V V V V V V V mA mA mA dB MHz V/s q q q q q q Negative Output Voltage Swing 0.200 0.225 - 4.80 Output Short-Circuit Current (Source/Sink) DC Open-Loop Gain GBW Product Slew Rate LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25C, unless otherwise noted. PARAMETER Center Frequency Range, fO (Note 1) Input Frequency Range Clock-to-Center Frequency, fCLK/fO CONDITIONS MIN TYP 0.001 to 20 0 to 1 100:1 0.2 100:1 0.2 q MAX Clock-to-Center Frequency Ratio, Side-to-Side Matching VS = 3V, fCLK = 250kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 4.75V, fCLK = 250kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 5V, fCLK = 500kHz, Mode 1, fO = 5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 3V, fCLK = 250kHz, Q = 5 VS = 4.75V, fCLK = 250kHz, Q = 5 VS = 5V, fCLK = 500kHz, Q = 5 q 0.70 0.70 0.70 0.35 0.35 0.35 100:1 0.2 q q q q 0.1 0.1 0.1 UNITS kHz MHz % % % % % % % % % 2 U W U U WW W LTC1067/LTC1067-50 ELECTRICAL CHARACTERISTICS LTC1067 (complete filter) VS = 4.75V, fCLK = 250kHz, TA = 25C, unless otherwise noted. PARAMETER Q Accuracy CONDITIONS VS = 3V, fCLK = 250kHz, Q = 5 VS = 4.75V, fCLK = 250kHz, Q = 5 VS = 5V, fCLK = 500kHz, Q = 5 MIN q q q fO Temperature Coefficient Q Temperature Coefficient DC Offset Voltage (See Table 2) VOS1 (DC Offset of Input Inverter) VOS2 (DC Offset of First Integrator) VOS3 (DC Offset of Second Integrator) Q < 2.5, VS = 5V VS = 3V, fCLK = 250kHz VS = 4.75V, fCLK = 250kHz VS = 5V, fCLK = 500kHz q q q Clock Feedthrough Maximum Clock Frequency Power Supply Current q q q TYP 0.5 0.5 0.5 1 5 3 4 4 150 2.0 2.50 3.00 4.35 MAX 2 2 2 12.5 15.0 15.0 4.5 5.5 7.5 UNITS % % % ppm/C ppm/C mV mV mV VRMS MHz mA mA mA LTC1067-50 (internal op amps) VS = 4.75V, TA = 25C, unless otherwise noted. PARAMETER Operating Supply Range Positive Output Voltage Swing CONDITIONS VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = 5V, RL = 10k VS = 3V, RL = 10k VS = 4.75V, RL = 10k VS = 5V, RL = 10k VS = 3V VS = 4.75V VS = 5V RL = 10k RL = 10k RL = 10k q q q q q q MIN 2.7 2.65 4.25 4.15 TYP 2.80 4.50 4.50 0.020 0.025 - 4.96 16/0.6 33/1.2 70/5.7 90 1.9 0.8 MAX 11 Negative Output Voltage Swing 0.200 0.225 - 4.80 Output Short-Circuit Current (Source/Sink) DC Open-Loop Gain GBW Product Slew Rate UNITS V V V V V V V mA mA mA dB MHz V/s LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25C, unless otherwise noted. PARAMETER Center Frequency Range, fO (Note 1) Input Frequency Range Clock-to-Center Frequency, fCLK/fO CONDITIONS MIN TYP 0.001 to 40 0 to 1 50:1 0.2 50:1 0.2 q MAX Clock-to-Center Frequency Ratio, Side-to-Side Matching Q Accuracy VS = 3V, fCLK = 125kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 4.75V, fCLK = 125kHz, Mode 1, fO = 2.5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 5V, fCLK = 250kHz, Mode 1, fO = 5kHz, Q = 5 R1 = R3 = 49.9k, R2 = 10k VS = 3V, fCLK = 125kHz, Q = 5 VS = 4.75V, fCLK = 125kHz, Q = 5 VS = 5V, fCLK = 250kHz, Q = 5 VS = 3V, fCLK = 125kHz, Q = 5 VS = 4.75V, fCLK = 125kHz, Q = 5 VS = 5V, fCLK = 250kHz, Q = 5 q 0.75 0.75 0.75 0.55 0.55 0.55 2 2 2 50:1 0.3 q q q q q q q 0.2 0.2 0.2 0.5 0.5 0.5 UNITS kHz MHz % % % % % % % % % % % % 3 LTC1067/LTC1067-50 ELECTRICAL CHARACTERISTICS LTC1067-50 (complete filter) VS = 4.75V, fCLK = 125kHz, TA = 25C, unless otherwise noted. PARAMETER fO Temperature Coefficient Q Temperature Coefficient DC Offset Voltage (See Table 2) CONDITIONS MIN TYP 1 5 3 4 4 150 2.0 1.00 1.45 2.35 MAX UNITS ppm/C ppm/C mV mV mV VRMS MHz mA mA mA VOS1 (DC Offset of Input Inverter) VOS2 (DC Offset of First Integrator) VOS3 (DC Offset of Second Integrator) Q < 2.5, VS = 5V VS = 3V, fCLK = 125kHz VS = 4.75V, fCLK = 125kHz VS = 5V, fCLK = 250kHz q q q 12.5 15.0 15.0 Clock Feedthrough Maximum Clock Frequency Power Supply Current q q q 2.5 3.0 4.0 The q denotes the specifications which apply over the full operating temperature range. Note 1: See Typical Performance Characteristics. TYPICAL PERFORMANCE CHARACTERISTICS LTC1067 Maximum Q vs Center Frequency (Modes 1, 1B, 2 where R4 10R2) 50 VS = 5V fCLK(MAX) = 2MHz 50 VS = 5V fCLK(MAX) = 2MHz VS = 5V fCLK(MAX) = 1.5MHz VS = 3.3V fCLK(MAX) = 1MHz 40 MAXIMUM Q 30 MAXIMUM Q 20 10 0 0 10 5 15 CENTER FREQUENCY, fO (kHz) LTC1067-50 Maximum Q vs Center Frequency (Modes 1, 1B, 2 where R4 10R2) 50 VS = 5V fCLK(MAX) = 2MHz MAXIMUM Q 40 MAXIMUM Q 30 20 10 0 0 20 10 30 CENTER FREQUENCY, fO (kHz) 4 UW LTC1067 Maximum Q vs Center Frequency (Modes 2 where R4 < 10R2, 3) 40 VS = 5V fCLK(MAX) = 1.5MHz VS = 3.3V fCLK(MAX) = 1MHz 30 20 10 20 0 0 10 5 15 CENTER FREQUENCY, fO (kHz) 20 LTC1067 * TPC01 LTC1067 * TPC02 LTC1067-50 Maximum Q vs Center Frequency (Modes 2 where R4 < 10R2, 3) 50 VS = 5V fCLK(MAX) = 2MHz VS = 5V fCLK(MAX) = 1.5MHz 30 VS = 3.3V fCLK(MAX) = 800kHz VS = 3V fCLK(MAX) = 600kHz 40 VS = 5V fCLK(MAX) = 1.5MHz VS = 3.3V fCLK(MAX) = 800kHz VS = 3V fCLK(MAX) = 600kHz 20 10 0 40 0 20 10 30 CENTER FREQUENCY, fO (kHz) 40 LTC1067 * TPC03 LTC1067 * TPC04 LTC1067/LTC1067-50 PIN FUNCTIONS V +, V - (Pins 1, 3,14): The V + (Pins 1, 3) and the V - (Pin 14) should each be bypassed with a 0.1F capacitor to an adequate analog ground. The filter's power supplies should be isolated from other digital or high voltage analog supplies. A low noise linear supply is recommended. Using a switching power supply will lower the signal-tonoise ratio of the filter. The supply's power-up slew rate should be less than 1V/s. When V + is applied before V -, and V - is allowed to go above ground, a diode should clamp V - to prevent latch-up. Figures 1 and 2 show typical connections for dual and single supply operation. SA, SB (Pins 4, 13): Summing Inputs. The summing pins' connection, along with the other resistor connections, determine the circuit topology (mode) of each 2nd order section. These pins should never be left floating. LPA, BPA, HPA/NA, HPB/NB, BPB, LPB (Pins 5, 6, 7, 10, 11, 12): Output Pins. Each 2nd order section of the LTC1067 has three outputs which typically source 33mA and sink 2mA. Driving coaxial cable, capacitive loads or resistive loads less than 10k will degrade the total harmonic distortion performance of any filter design. When evaluating the distortion or noise performance of a filter, the output should be buffered with a wideband amplifier. INV A, INV B (Pins 8, 9): Inverting Input. These pins are the high impedance inverting inputs of internal op amps. 1 2 V+ 0.1F 3 V+ NC CLK AGND 16 15 V- 0.1F V+ 0.1F 1 2 3 V+ NC CLK AGND 16 15 1F 14 V + LTC1067 V - LTC1067-50 4 13 SA SB 5 12 LPA LPB 6 11 BPA BPB 7 10 HPA/NA HPB/NB 8 9 INV A INV B STAR SYSTEM GROUND Figure 1. Dual Supply Ground Plane Connections U U U They are susceptible to stray capacitance coupling to low impedance nodes such as signal outputs and power supply lines. Resistors that are connected from a signal output to the inverting input pin should be located as close to the inverting input as possible. AGND (Pin 15): Analog Ground. The filter performance depends on the quality of the analog signal ground. For either dual or single supply operation, an analog ground plane surrounding the package is recommended. The analog ground plane should be connected to any digital ground at a single point. For dual supply operation Pin 6 is connected to the analog ground plane. For single supply operation Pin 6 should be bypassed to the analog ground plane with at least a 1F capacitor. An on-chip resistive voltage divider sets the bias at one-half of the supply. CLK (Pin 16): Clock Input. Any CMOS logic clock source with a square-wave output and a 50% duty cycle (10%) is an adequate clock source for the device. The power supply for the clock source should not be the filter's power supply. The analog ground for the filter should be connected to the clock's ground at a single point only. Table 1 shows the clock's low and high level threshold values for dual supply or single supply operation. 14 V + LTC1067 V - LTC1067-50 4 13 SA SB 5 12 LPA LPB 6 11 BPA BPB 7 10 HPA/NA HPB/NB 8 9 INV A INV B DIGITAL GROUND PLANE 200 CLOCK SOURCE 1067 F02 STAR SYSTEM GROUND DIGITAL GROUND PLANE 200 CLOCK SOURCE 1067 F03 FOR MODE 3, THE SA AND SB SUMMING NODE PINS ARE TIED TO THE AGND PIN Figure 2. Single Supply Ground Plane Connections 5 LTC1067/LTC1067-50 PIN FUNCTIONS Table 1. Clock Source High and Low Threshold Levels POWER SUPPLY 5V Single 5V Single 3V, 3.3V HIGH LEVEL 2.2V 2.2V 2V LOW LEVEL 0.50V 0.50V 0.40V Sine waves are not recommended for the clock input. The clock signal should be routed from the right side of the IC BLOCK DIAGRA APPLICATIONS INFORMATION A switched capacitor integrator generally exhibits a higher input offset than a discrete RC integrator. The larger offset is mainly due to the charge injection from the CMOS switches into the integrated capacitor. The integrator's op amp offset, typically a couple of millivolts, also adds to the Table 2. Output DC Offsets for a Second Order Section MODE 1 1b 2 3 VOSHP/N VOS1 [1 + (R2/R3) + (R2/R1)] - (VOS3)(R2/R3) VOS1 [1 + (R2/R3) + (R2/R1)] - (VOS3)(R2/R3) VOS1 [1 + (R2/R3) + (R2/R1) + (R2/R4) - (VOS3) (R2/R3)](R4/R2 + R4) + (VOS2)(R2/R2 + R4) VOS2 VOSBP VOS3 VOS3 VOS3 VOS3 VOSHP/N - VOS2 (VOSHP/N - VOS2)[1 + (R5/R6)] VOSHP/N - VOS2 VOS1 [1 + (R4/R1) + (R4/R2) + (R4/R3)] - (VOS2) (R4/R2) - (VOS3)(R4/R3) VOSLP 6 U W W U U U U U package to avoid coupling to any power supply lines or input or output signal paths. A 200 resistor between the clock source and Pin 16 will slow down the rise and fall times of the clock to reduce charge coupling of the clock. This will result in less clock feedthrough noise on the output signal. V+ (1) INV A (8) V (3) + HPA/NA (7) BPA (6) LPA (5) - 15k AGND (15) + SA (4) HPB/NB (10) BPB (11) LPB (12) V- (14) 15k INV B (9) + - CLK (16) SB (13) 1067 BD overall offset value. Figure 3 shows the input offsets from a single 2nd order section. Table 2 lists the formula for the output offset voltage for various modes and output pins. LTC1067/LTC1067-50 APPLICATIONS INFORMATION HP/N INV VOS1 BP LP - VOS2 VOS3 1067 F01 + S Figure 3. Block Diagram of a 2nd Order Section Showing the Input Offsets PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. GN Package 16-Lead Plastic SSOP (Narrow 0.150) (LTC DWG # 05-08-1641) 0.189 - 0.196* (4.801 - 4.978) 0.015 0.004 x 45 (0.38 0.10) 0.007 - 0.0098 (0.178 - 0.249) 0.016 - 0.050 (0.406 - 1.270) * DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE ** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE 0 - 8 TYP 0.229 - 0.244 (5.817 - 6.198) 0.150 - 0.157** (3.810 - 3.988) 0.053 - 0.068 (1.351 - 1.727) 0.004 - 0.0098 (0.102 - 0.249) 16 15 14 13 12 11 10 9 0.008 - 0.012 (0.203 - 0.305) S Package 16-Lead Plastic Small Outline (Narrow 0.150) (LTC DWG # 05-08-1610) 0.386 - 0.394* (9.804 - 10.008) 0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0.053 - 0.069 (1.346 - 1.752) 0 - 8 TYP 0.228 - 0.244 (5.791 - 6.197) 0.150 - 0.157** (3.810 - 3.988) 0.004 - 0.010 (0.101 - 0.254) 16 15 14 13 12 11 10 9 0.016 - 0.050 0.406 - 1.270 0.014 - 0.019 (0.355 - 0.483) *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE U U W U U 0.025 (0.635) BSC GN16 (SSOP) 1197 1 23 4 56 7 8 0.050 (1.270) TYP S16 0695 1 2 3 4 5 6 7 8 7 LTC1067/LTC1067-50 TYPICAL APPLICATION 1.02kHz Notch Filter for Telecom Systems 0 5V 0.1F 1 2 3 R61* 9.88k R51* 4.99k R32 61.9k R21 10k C21** 300pF R11 18.7k VIN*** 8 4 V+ NC V+ LTC1067 SA SB CLK AGND 16 15 1F R62* 10k R52* 4.99k R32 464k R22 75k C22** 30pF INV A INV B 9 VOUT GAIN (dB) 14 V- 13 5 6 7 LPA BPA HPA/NA LPB BPB HPB/NB RH1 40.2k 1067 TA03 * R51, R61, R52, R62 ARE 0.1% TOLERANCE RESISTORS ** C21 AND C22 IMPROVE THE NOTCH DEPTH WHERE 1 (30)(f NOTCH) < < (75)(f NOTCH) WITHOUT 2(R2x)(C2X) C21 AND C22 THE NOTCH DEPTH IS LIMITED TO -35dB *** VIN 1.25VP-P RELATED PARTS PART NUMBER LTC1064 LTC1068 LTC1164 LTC1264 DESCRIPTION Low Noise, Low Power Quad Building Block Filter Quad Universal Building Block Filter Low Power Quad Universal Building Block Filter High Speed Quad Universal Building Block Filter COMMENTS 100:1 Clock-to-fO Ratio 100:1 Clock-to-fO Ratio 50:1 and 100:1 Clock-to-fO Ratio 20:1 Clock-to-fO Ratio 8 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com U Frequency Response -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 800 900 1000 1100 FREQUENCY (kHz) 1200 LT1067-9 * TA04 200 fCLK = 125kHz 12 11 10 10675ia LT/TP 0298 2K REV A * PRINTED IN USA (c) LINEAR TECHNOLOGY CORPORATION 1997 |
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