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| VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Features * Four Channel 2.488 Gb/s Data Recovery * SONET Quality Jitter Tolerance * Fastlock Data Acquisition less than 200 Bit Times * Loss of Signal Indicators * Long Strings of Static Data Tolerated by the Clock Recovery Circuit without Loss of Signal * First Order Clock Recovery Loop Minimizes Jitter Accumulation 2.488 Gb/s Quad Data Re-timer * Differential on Chip Terminated Serial Data I/O * Bypass for OC3, OC12 Data Rates * 155.52 MHz Reference Clock Frequency * 3.3V Supply Operation * 14 x 14mm, 100 Pin Thermally Enhanced TQFP Package General Description The VSC8124 is a four channel, 2.5 Gb/s data re-timer for cleaning up data downstream of optical links or cross point switches. Serial data at the 2.5 Gb/s rate is independently re-timed on four channels, and driven differentially by CML drivers. The re-timing function on each channel can be individually bypassed for lower rate signals or test purposes. The VSC8124 provides four independent loss of signal indicators in the event of loss of synchronous data transitions. G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 1 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 VSC8124 Block Diagram SD3+ CML SD3RTBYP3 TTL 1 0 CML RDAT3+ RDAT3- RDAT2+ LOSREL TTL RTBYP2 TTL SD2+ CML SD2REFCK0+ PECL REFCK0REFCK1+ PECL REFCK1REFCK+ TTL Clock Recovery Unit CML RDAT2LOSALMN 1 0 TTL LOS3N 0 1 Clock Recovery Unit LOS Logic TTL LOS2N TTL LOS1N SD1+ CML SD11 0 TTL LOS0N RTBYP1 TTL FASTLOCK Clock Recovery Unit CML RDAT1+ RDAT1- TTL RTBYP0 TTL 1 0 CML RDAT0+ RDAT0- SD0+ CML SD0- Clock Recovery Unit Page 2 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Functional Description Reference Clock 2.488 Gb/s Quad Data Re-timer A clean reference clock should be provided to meet jitter specifications. An arbitrary discontinuity in reference clock phase can be tolerated without data error at slightly reduced jitter tolerance. (See Table 1) Phase changes must not occur more often than every 20 s. Serial data transition density must average 0.5 for that period. Two reference clock input ports are provided. The REFSEL pin selects the active port. When REFSEL is not driven, it floats low, selecting REFCK0. Changing REFSEL implies a phase change. Clock Recovery The incoming serial data on each channel is presented to a clock recovery and data re-timing circuit. For each channel, a phase detector and low pass filter force a local clock to track the average phase of the incoming serial data. The low pass filter is first order to prevent jitter peaking in cascaded devices. Figure 1: Serial Input Data Eye Diagram JT Eye Opening Period Table 1: Serial Input Data Specification Parameter JT JT JT Period Description Jitter tolerance Jitter tolerance Jitter tolerance Min 220 150 190 - Typ 170 210 401.88 Max - Units ps ps ps ps Conditions Normal Operation Fast Lock Mode Within 20s after REFCLK phase change NOTE: 1) Jitter tolerance is measured at worst case power supply and temperature, using 155.52 MHz clean reference clock (REFCK to meet 2.0 ps RMS jitter at less than 10 Mhz in bandwidth), and 600mV swing differential PRBS data with150ps maximum rise time. 2) Jitter tolerance and re-timed data jitter are degraded in FASTLOCK mode. 3) Reference clock frequency tolerance: f <= 100 ppm 4) Jitter tolerance specifications do not apply in re-timer bypass mode. G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 3 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 Figure 2: Re-timed Serial Output Data Eye Diagram Period 80% 20% tr , tf JG Table 2: Serial Output Data Specification Parameter JG JG JG tr, tf Description Jitter generation Jitter generation Jitter generation Rise time, fall time Min - Typ - Max 12ps rms 15 ps rms 14ps rms 140 Units Conditions Normal Operation Fast Lock Mode Within 40 s after REFCK phase change ps 20 to 80% NOTES: 1) Jitter generation is measured at worst case power supply and temperature using 155.52 MHz clean reference clock and clean serial data. 2) Jitter generation and rise, fall time specifications do not apply in re-timer bypass mode. Page 4 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Figure 3: Fastlock Timing Diagram 200 Bit Times Input Data Valid Data 1010... 80 Bit Times Fastlock 200 Bit Times Output Data Valid Data 2.488 Gb/s Quad Data Re-timer Valid Data Valid Data Fast Lock The VSC8124 supports a fastlock clock recovery mode which enables the clock recovery unit to lock the retiming clock to the incoming data within 80 bit periods of initiation. As a requirement for the operation of the fastlock function, the driving system must send a 0101 bit pattern while the fastlock pin is at a high logic level. The FASTLOCK function is active simultaneously on all four data channels The fastlock pin has a TTL input receiver meeting the specifications contained in Table 7. Note that jitter tolerance and re-timed data jitter are degraded in FASTLOCK mode. Loss of Signal The loss of signal (LOS) circuitry is shared among four serial data channels, sampling the signal condition on each channel sequentially. There is a loss of signal latch and active low indicator pin (LOS[0:3]N) for each channel. In addition, there is an alarm pin (LOSALMN) which indicates the OR of the latched states of the four channel indicators. The alarm pin uses an open drain output, so the alarm pins from multiple parts can be wired together. A weak external pull resistor (approximately 1k Ohm) must be provided to utilize the wired NOR alarm function. To facilitate system troubleshooting, the LOS latches can only be cleared by the active high LOSCLR input. The loss of signal clear (LOSCLR) input will cause all four loss of signal indicators LOS[0:3]N and the loss of signal alarm (LOSALM) to be cleared. The LOSCLR input is asynchronous. It must be held active for at least two reference clock cycles. A channel found to be missing after the error latch has been cleared, will again set its error latch and the LOSALMN. The LOS circuit examines a selected clock recovery channel for expected data transition activity. Expected data activity includes pseudo-random data at a baud rate 16 times the reference clock frequency, and data including at least 8500 consecutive bits of a 101010... pattern. The detector will allow the OC-48 framing pattern to pass without triggering LOS. The LOS detector is disabled when FASTLOCK mode is active. To assist diagnostic procedures, the effect of individual loss of signal indicators in the loss of signal alarm can be masked. This is controlled by the MASK[0:3] pins. Each of those pins, when pulled high, disables the effect of its respective channel on the loss of signal alarm (LOSALM). If all MASK pins are pulled high, the LOSALM signal will not pull down. The loss of signal indicators for individual channels are not affected by the MASK pins. G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 5 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 Re-timer Bypass The serial data re-timer can be individually bypassed for data channels. This allows asynchronous data signals to pass through the part. The bypass function is controlled by the RTBYP[0:3] pins. High Speed Interfaces Figure 4: High Speed Data Input Termination- AC Coupled Xpnt switch Zo = 50 0.1 F Quad data Re-timer DI 50 VTERM 50 Zo = 50 0.1 F DIN Notes: 1)It is recommended that VTERM pins from multiple inputs NOT be tied together, unless driven from a low impedance supply. 2) The high speed data receivers have self biased inputs. 3) For unused serial data receivers, it is recommended to tie one side low by connecting a 1k Ohm resistor to Vee and letting the other side float. Page 6 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Figure 5: High Speed Data Output Termination - AC Coupled AC Coupled 2.488 Gb/s Quad Data Re-timer Quad data Re-timer DOUT VCC 50 0.1 F Zo = 50 VCC 50 DOUTN 50 VCC 0.1 F Zo = 50 50 VCC DC Coupled Quad data Re-timer DOUT VCC Zo = 50 50 50 50 Zo = 50 VCC DOUTN 50 Figure 6: REFCK Input Termination - AC Coupled REFCK Driver Zo = 50 0.1 F Quad data Re-timer DI 50 VTERM 50 Zo = 50 0.1 F DIN Notes: 1) It is recommended that the VTERM pins from multiple inputs NOT be tied together, unless driven from a low impedance supply. 2) The reference clock receivers have self-biased inputs. 3) For unused reference clock receivers, it is recommended to tie one side low by connecting a 1k Ohm resistor to Vee, and letting the other side float. G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 7 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 Figure 7: Unused High Speed and REFCK Input Termination. VCC 5.1 k Quad data Re-timer DI 50 VTERM 50 DIN 5.1 k VEE High Speed Specifications Figure 8: Definition of I/O Levels Vh V Vcm Vl NOTE: Diagram applies to all I/O swing specifications Table 3: High Speed Driver Specification Parameter V=(Vh - Vl) VCM ZOUT Description Single ended peak-topeak Output common mode Ouput impedance Min 600 1.8V 40 Typ 50 Max 1000 2.2 60 Units mV V Conditions Terminated as in Fig. 5 (DC Coupled) Terminated as in Fig.5 (DC Coupled) Measured Singleended Page 8 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Table 4: AC Coupled High Speed Receiver Specifications Parameter V=Vh-Vl Zin NOTE: 1) See Figure 8 2.488 Gb/s Quad Data Re-timer Description Input swing (1) Min 200 80 Typ - Max 1200 120 Units mV Conditions Differential input impedance Table 5: DC Coupled High Speed Receiver Specifications Parameter Vcm Vih Vil V=Vh-Vl Description Input common mode Input high level Input low level Input swing Min VEE+0.9 VEE 200 Typ 0.43VCC - Max VCC-1.0 VCC-1.2 1200 Units V V V mV Conditions Table 6: REFCK Receiver Specifications Parameter V=Vh-Vl Vcm Zin Description Input swing(1) Input common mode Differential input impedance Min 400 1.27 80 Typ - Max 1300 1.49 120 Units mV V Conditions NOTE: 1) See Figure 8 Table 7: TTL Input (internal pull-down) Receiver Specifications Parameter Vih Vil Iilh Iill Description Input high level Input low level Input leakage current high Input leakage current low Min 2000 - Typ - Max 800 1 1 Units mV mV mA mA Conditions Vin = 3.3V Vin = 0V Table 8: TTL Output Driver Specifications Parameter Voh Vol Description Output high level Output low level Min 2400 - Typ - Max 400 Units mV mV Conditions G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 9 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Parameter tr tf Iolh Ioll toez Target Specification VSC8124 Description Rise Time Fall Time Output leakage current high Output leakage current low Min - Typ - Max 5 5 2 4 10 Units ns ns mA mA ns Conditions 10 to 90% 10pF load 10 to 90% 10pF load Vout = 2.0V, tristate enabled Vout = 0.8V, tristate enabled Tristate enabled to high Z Table 9: Power Supply Specifications Parameter Power supply voltage Power dissipation Description Min 3.15 - Typ 3.30 2.7 Max 3.46 3.25 Units V W Conditions Page 10 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Absolute Maximum Ratings 2.488 Gb/s Quad Data Re-timer Power Supply Voltage, (VCC) ......................................................................................................-0.5 V to +4.0 V DC Input Voltage (Differential inputs) .................................................................................-0.5 V to VCC + 0.5V DC Input Voltage (TTL inputs)............................................................................................ -0.5 V to VCC + 0.5 V DC Output Voltage (TTL outputs .........................................................................................-0.5 V to VCC + 0.5V Output Current (TTL outputs) ..................................................................................................................+/- 50mA Output Current (Differential outputs).......................................................................................................+/- 50mA Case Temperature Under Bias........................................................................................................-55o to + 100oC Note: Caution: Stresses listed under "Absolute Maximum Ratings" may be applied to devices one at a time without causing permanent damage. Functionality at or exceeding the values listed is not implied. Exposure to these values for extended periods may affect device reliability. Recommended Operating Conditions Power Supply Voltages (VCC)............................................................................................................. +3.3V 5 % Operating Case Temperature Range (T)................................................................................................ 0o to 85oC Notes: (1) Customer may require cooled/heatsink environment to meet thermal requirements of 100TQFP. (2) Contact factory for package thermal performance information. (3) JC = 6oC/W ESD Ratings Proper ESD procedures should be used when handling this product. The VSC8124 is rated to the following ESD voltages based on the human body model: 1. High speed pins are rated 200V 2. All other pins are rated at or above 1500V. G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 11 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 Figure 9: Package Pin Diagram Package Pin Descriptions VSC8124 2.488 Gb/s Re-timer FASTLOCK LOSALMN LOSCLR RDAT3+ RDAT2+ RDAT3- RDAT2- TRITTL VCCA2 VEEA2 LOS3N LOS2N LOS1N LOS0N VCC VCC 100 99 98 97 96 95 94 93 92 91 90 89 85 84 87 86 83 88 82 79 78 77 81 80 76 75 74 73 72 71 70 69 68 67 66 65 64 VCC VEE VEE VTT VEE VEE 3VS NC NC VCC REV VEE SDAT3+ VTERM3 SDAT3VEE VCC SDAT2+ VTERM2 SDAT2VEE 1 2 3 4 5 6 7 8 9 10 11 12 VCC VEE MASK3 MASK2 MASK1 MASK0 VCC REFCK1+ VTERM5 REFCK1VEE REFCK0+ VCC VCC SDAT1+ VTERM1 SDAT1VCC VEE SDAT0+ VTERM0 SDAT0VCC VEE VCC 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 35 36 37 33 34 41 42 63 62 61 60 59 58 57 56 55 54 53 52 51 VTERM4 REFCK0VCC REFSEL VCC_ANA VEE_ANA TEST57 TEST56 TEST55 TEST54 TEST53 VEE VCC 39 40 43 38 44 47 48 49 VEE 45 RDAT0- RDAT0+ RDAT1+ RDAT1- RTBYP0 RTBYP1 RTBYP2 RTBTP3 CKBYP VCC VCC NC VCC 46 VCC TEST30 VCCA1 VEEA1 TEST47 Page 12 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 VCC VEE VEE NC VTT VEE 50 Drawing is heat sink up Cavity Down Package 100 Pin TQFP 14x14x1.4 mm BODY + 2.0mm footprint G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Table 10: Package Pin Identification Signal VCC REV VEE SDAT3+ VTERM3 SDAT3VEE VCC SDAT2+ VTERM2 1 SDAT2VEE VCC VCC SDAT1+ VTERM1 1 SDAT1VCC VEE SDAT0+ VTERM0 SDAT0VCC VEE VCC VCC VEE VCC TEST29 TEST30 VEE RDAT0+ NC RDAT0VCCA1 2 1 1 2.488 Gb/s Quad Data Re-timer Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 I/O PWR O PWR I PWR I PWR PWR I PWR I PWR PWR PWR I PWR I PWR PWR I PWR I PWR PWR PWR PWR PWR PWR I I PWR O O PWR PWR O Level +3.3V ANALOG GND CML VTERM CML GND +3.3V CML VTERM CML GND +3.3V +3.3V CML VTERM CML +3.3V GND CML VTERM CML +3.3V GND +3.3V +3.3V GND +3.3V TTL TTL GND CML NC CML +3.3V GND CML Pin Description Do not connect High speed data input High speed data input High speed data input High speed data input High speed data input High speed data input High speed data input High speed data input Do not connect Do not connect Retimed data output Retimed data output VEEA1 2 RDAT1+ Retimed data output G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 13 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Table 10: Package Pin Identification Signal NC RDAT1VEE VCC VTT RTBYP0 RTBYP1 RTBYP2 RTBYP3 TEST47 VCC VEE VCC VCC VEE TEST53 TEST54 TEST55 TEST56 TEST57 VEE_ANA VCC_ANA REFSEL VCC REFCK0VTERM4 VEE REFCK11 Target Specification VSC8124 Pin 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 I/O O PWR PWR PWR I I I I I PWR PWR PWR PWR PWR I I I I I PWR PWR I PWR I PWR I PWR I Level NC CML GND +3.3V +1.3V TTL TTL TTL TTL TTL +3.3V GND +3.3V +3.3V GND GND +3.3V TTL +3.3V LVPECL VTERM LVPECL GND LVPECL Pin Description Retimed data output Do not connect Re-timer bypass Re-timer bypass Re-timer bypass Re-timer bypass Do not connect Do not connect Do not connect Do not connect Do not connect Do not connect Reference clock select 155 MHz ref. clock 155 MHz ref. clock Alternate ref. clock REFCK0+ Page 14 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Table 10: Package Pin Identification Signal VTERM5 VCC MASK0 MASK1 MASK2 MASK3 VEE VCC VCC VEE TRITTL LOSALMN LOS0N LOS1N LOS2N LOS3N VTT VCC VEE RDAT2NC RDAT2+ VEEA2 2 1 2.488 Gb/s Quad Data Re-timer Pin 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O PWR I PWR I I I I PWR PWR PWR PWR I O O O O O PWR PWR PWR O O PWR PWR O O PWR I I PWR PWR PWR Level VTERM LVPECL +3.3V TTL TTL TTL TTL GND +3.3V +3.3V GND TTL Open Drain TTL TTL TTL TTL +1.3V +3.3V GND CML NC CML GND +3.3V CML NC CML GND TTL TTL GND +3.3V Pin Description Alternate ref. clock LOS mask enable LOS mask enable LOS mask enable LOS mask enable REFCK1+ Tri-state enable Loss of signal alarm Loss of signal indicator Loss of signal indicator Loss of signal indicator Loss of signal indicator Do not connect Retimed data output Retimed data output VCCA2 2 RDAT3NC RDAT3+ VEE LOSCLR FASTLOCK VEE 3VS VCC 1 Retimed data output Retimed data output LOS clear Fast lock enable Do not connect All pins indicated with superscript (1), while having different names, use the same voltage, but are isolated in the part for noise immunity. 2All pins indicated with superscript (2), while having different names, use the same voltage, but are isolated in the part for noise immunity. G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 15 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 Table 11: Power Supply Pin Summary Signal VCC Pin 1,8,13,14,18,23, 25,26,28,41,48,50, 51,62,70,75,76,85, 100 3,7,12,19,24,27, 31,40,49,52,65, 74,77,86,95,98 42,84 35 91 36 90 59 58 5,10,16,21,64,68, 72 I/O PWR Level +3.3V Pin Description VEE VTT VCCA1 VCCA2 VEEA1 VEEA2 VCC_ANA VEE_ANA VTERM[0:5] PWR PWR PWR PWR PWR PWR PWR PWR PWR GND +1.3V +3.3V +3.3V GND GND +3.3V GND VCC/2 dirty VCC for RDAT[0:1] dirty VCC for RDAT[2:3] dirty VEE for RDAT[0:1] dirty VEE for RDAT[2:3] clean VCC for VCO/CMU clean VEE for VCO/CMU All supplies which reference the same voltage may be connected to the same power supply plane. The VCCANA and VEEANA are noise sensitive supplies, while the VCCA1, VCCA2, VEEA1 and VEEA2 are noise generating supplies. Appropriate power supply noise suppression should be applied to optimize the performance of the device. Page 16 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Typical Application 2.488 Gb/s Quad Data Re-timer This table lists the suggested connections for non-data path pins for a typical 2.5 Gb/s application which does not use the fast locking, channel re-timer bypassing, or loss of signal alarm masking. Users of those features should take care to understand the functions before connecting to the control pins. Table 12: Recommended Pin Usage Pin Number 2 29 30 42 43 44 45 46 47 53 54 55 56 57 60 62 64 66 68 70 71 72 73 78 79 80 81 82 83 84 96 97 99 Pin Name REV CKBYP TEST30 VTT RTBYP0 RTBYP1 RTBYP2 RTBYP3 TEST47 TEST53 TEST54 TEST55 TEST56 TEST57 REFSEL REFCK0REFCK0+ REFCK1REFCK1+ MASK0 MASK1 MASK2 MASK3 TRITTL LOSALMN LOS0N LOS1N LOS2N LOS3N VTT LOSCLR FASTLOCK 3VS Do not connect Do not connect Do not connect Recommended Hook-up Internally generated power supply; Do not connect Re-timer bypass; Do not connect Re-timer bypass; Do not connect Re-timer bypass; Do not connect Re-timer bypass; Do not connect Do not connect Do not connect Do not connect Do not connect Do not connect Do not connect Reference clock select; to use REFCK0, do not connect Reference clock 0-; Connect your reference clock true here Reference clock 0+; Connect your reference clock complement here Reference clock 1-; 1k Ohm to Vee Reference clock 1+; Do not connect Mask alarm; Do not connect Mask alarm; Do not connect Mask alarm; Do not connect Mask alarm; Do not connect Tri-state TTL outputs; Do not connect Loss of signal alarm; if used, 1k Ohm to Vcc otherwise do not connect Loss of signal channel 0; connect to CMOS input Loss of signal channel 0; connect to CMOS input Loss of signal channel 0; connect to CMOS input Loss of signal channel 0; connect to CMOS input Internally generated power supply; Do not connect Loss of signal clear; CMOS input (3.3V max.) Enable fast lock; Do not connect Power supply sense; Vcc or do not connect G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 17 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 100 TQFP Package Drawings Package Information Key A A1 A2 D D1 E E1 L e b q R R1 mm 1.6 0.15 1.4 16.00 14.00 16.00 14.00 .60 .50 .22 0-7 .20 .20 Tolerance MAX MAX .05 .20 .05 .20 .05 +.15/-.10 BASIC .05 TYP TYP NOTES: (1) Drawings not to scale. (2) All units in millimeters unless otherwise noted Package #: 101-318-3 Issue #: 1 Page 18 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 VITESSE SEMICONDUCTOR CORPORATION Target Specification VSC8124 Ordering Information 2.488 Gb/s Quad Data Re-timer The order number for this product is formed by a combination of the device number, and package type. VSC8124 Device Type VSC8124: 2.488Gb/s Quad Re-timer RE Package RE: 100 TQFP, 14x14mm Body Notice This document contains information about a proposed product during its design phase of development and is subject to change without notice at any time. All features and specifications are design goals only. Please contact Vitesse Semiconductor to obtain the latest product status and most recent versions of this specification. Warning Vitesse Semiconductor Corporation's products are not intended for use in life support appliances, devices or systems. Use of a Vitesse product in such applications without the written consent is prohibited. G52271-0, Rev. 1.14 2/23/00 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 Page 19 VITESSE SEMICONDUCTOR CORPORATION 2.488 Gb/s Quad Data Re-timer Target Specification VSC8124 Page 20 (c) VITESSE SEMICONDUCTOR CORPORATION 741 Calle Plano, Camarillo, CA 93012 * 805/388-3700 * FAX: 805/987-5896 G52271-0, Rev. 1.14 2/23/00 |
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