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Final Electrical Specifications
LTC1650 16-Bit Voltage Output DAC
June 1998
FEATURES
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DESCRIPTION
The LTC1650 is a deglitched rail-to-rail voltage output 16-bit digital-to-analog converter (DAC) available in a 16-pin narrow SO package. It has 16-bit monotonicity over temperature and includes a rail-to-rail output buffer amplifier and an easy to use three-wire cascadable serial interface. The LTC1650 operates with dual 5V supplies. The LTC1650 has excellent accuracy over its full operating temperature range along with very low power dissipation of 50mW with dual 5V supplies. This, along with the small outline package, makes it the most flexible high resolution digital-to-analog converter available today. The LTC1650 has a fast settling time of 4s to 16 bits and a low midscale glitch of under 2nV-s. This makes the LTC1650 ideal for waveform generation or other applications where output dynamic performance is important.
, LTC and LT are registered trademarks of Linear Technology Corporation. MICROWIRE is a trademark of National Semiconductor Corporation.
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16-Bit Monotonic Over Temperature Low Glitch Impulse: 2nV-s Low Noise: 30nV/Hz Buffered Rail-to-Rail Voltage Output Low Power: 50mW from 5V Supplies Unipolar or Bipolar Output 4-Quadrant Multiplying Capability Asynchronous Clear to User-Defined Voltage Power-On Reset Three-Wire SPI and MICROWIRETM Compatible Serial Interface Schmitt Trigger On CLK Input Allows Direct Optocoupler Interface 16-Pin Narrow SO Package
APPLICATIONS
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Industrial Process Control Precision Industrial Equipment Waveform Generation Automatic Test Equipment High Resolution Offset and Gain Adjustment
TYPICAL APPLICATION
5V 5V 3 CS/LD CLK DIN 8 DVDD 4.096V 11 REFHI RSTOUT 10 15 AVDD
7 5
POWER-ON RESET SUPPLY SENSE
9 2
CLR VRST
16-BIT SHIFT REGISTER
16-BIT DAC REGISTER
DNL ERROR (LSB)
16-BIT DAC
+
1 VOUT
-
DOUT
6 16 4 12,13 14 - 5V AVSS UNI/BIP
DGND
REFLO
1650 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Differential Nonlinearity vs Input Code
1.0 0.8 0.6 0.4 0.2 0 - 0.2 - 0.4 - 0.6 - 0.8 - 1.0 0 16384 32768 CODE 49152 65535
1650 TA02
1
LTC1650
ABSOLUTE MAXIMUM RATINGS
AVDD, DVDD to DGND .............................. - 0.5V to 7.5V TTL Input Voltage .................................... - 0.5V to 7.5V VOUT, VRST .................................. - 0.5V to AVDD + 0.5V AVSS ......................................................... 0.5V to - 7.5V Operating Temperature Range LTC1650C............................................... 0C to 70C LTC1650I............................................ - 40C to 85C Maximum Junction Temperature ......................... 125C Storage Temperature Range ................. - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER INFORMATION
TOP VIEW VOUT 1 VRST 2 DVDD 3 DGND 4 DIN 5 DOUT 6 CLK 7 CS/LD 8 16 UNI/BIP 15 AVDD 14 AVSS 13 REFLO S 12 REFLO F 11 REFHI 10 RSTOUT 9 CLR
ORDER PART NUMBER LTC1650CS LTC1650IS
S PACKAGE 16-LEAD PLASTIC SO
TJMAX = 125C, JA = 130C/ W
Consult factory for PDIP, A grade and Military grade parts.
ELECTRICAL CHARACTERISTICS
AVDD = 4.75V to 5.25V, AVSS = - 4.75V to - 5.25V, DVDD = 4.75V to 5.25V, REFLO = 0V, REFHI = 4.096V, VOUT unloaded, TA = TMIN to TMAX unless otherwise noted.
SYMBOL PARAMETER Resolution Monotonicity DNL INL Differential Nonlinearity Integral Nonlinearity Bipolar Zero Error Bipolar Zero Error VOS VOSTC Unipolar Offset Error Offset Error Temperature Coefficient Gain Error Gain Error Temperature Coefficient Bipolar Negative Full-Scale Error Bipolar Negative Full-Scale Error Tempco Power Supply Characteristics AVDD DVDD AVSS IAVDD IAVSS IDVDD PSRR Positive Supply Voltage Positive Supply Voltage Negative Supply Voltage AVDD Supply Current AVSS Supply Current DVDD Supply Current AVDD, DVDD Supply Rejection AVSS Supply Rejection 4.75V AVDD 5.25V (Note 4) - 5.25V AVSS - 4.75V (Note 4) 4.75V DVDD 5.25V (Note 4) 4.75V AVDD, DVDD 5.25V - 5.25V AVSS - 4.75V
q q q q q q q q
CONDITIONS
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MIN 16 16
TYP
MAX
UNITS Bits Bits
DAC Characteristics, Unipolar/Bipolar Output Unless Otherwise Noted
Guaranteed Monotonic (Note 1) Integral Nonlinearity (Note 1) TA = 25C TA = TMIN to TMAX TA = TMIN to TMAX TA = 25C TA = TMIN to TMAX TA = 25C TA = TMIN to TMAX
q q q q
0.15 4 5 0.5 10 4
0.9 16 12 18 12 12 18 12 16
V/C LSB LSB LSB/C LSB LSB V/C 5.25 5.25 - 5.25 7.5 0.1 1.5 1.5 V V V mA mA mA LSB/V LSB/V
q
0.05 1
q
10 4.75 4.75 - 4.75 - 7.5 5.0 5.0 - 5.0 5 -5 0.02 0.5 0.5
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WW
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LSB LSB LSB LSB LSB
LTC1650
ELECTRICAL CHARACTERISTICS
AVDD = 4.75V to 5.25V, AVSS = - 4.75V to - 5.25V, DVDD = 4.75V to 5.25V, REFLO = 0V, REFHI = 4.096V, VOUT unloaded, TA = TMIN to TMAX unless otherwise noted.
SYMBOL RIN PARAMETER Reference Input Resistance REFHI Range REFLO Range Op Amp DC Performance Short-Circuit Current Low Short-Circuit Current High Output Impedance AC Performance Voltage Output Slew Rate Voltage Output Settling Time Midscale Glitch Impulse Digital Feedthrough Output Noise Voltage Density SINAD VIH VIL VOH VOL ILK CIN RON Signal-to-Noise + Distortion Ratio Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Digital Input Capacitance VOUT and VRST Switch Resistance Threshold Voltage for Reset IOUT = -1mA, DOUT Only IOUT = 1mA, DOUT Only VIN = GND to VCC (Note 2) VRST = 0.5V (Note 6) AVDD or DVDD (Note 7) AVSS(Note 7)
q q q q
CONDITIONS
q q q
MIN 2.5 - 4.0 - 1.0
TYP 5 4.0 0 25 25 0.15
MAX 7.5 4.5 1.0 50 50
UNITS k V V mA mA V/s s nV-s nV-s nV/Hz dB V
Reference Input
VOUT Shorted to GND VOUT Shorted to VCC Measured at Midscale
q q
0.8
2.0 4 1.8 0.05
(Note 3)
1kHz to 100kHz (Note 5) REFHI = 1kHz 4VP-P
q q q q q
30 96 2.4 0.8 VCC - 1.0 0.4 10 10 200 1.5 1.5 2.5 2.5 500 3.2 3.2
Digital I/O Characteristics V V V A pF V V
Reset Characteristics
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LTC1650
ELECTRICAL CHARACTERISTICS
AVDD = 4.75V to 5.25V, AVSS = - 4.75V to - 5.25V, DVDD = 4.75V to 5.25V, REFLO = 0V, REFHI = 4.096V, VOUT unloaded, TA = TMIN to TMAX unless otherwise noted.
SYMBOL t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 PARAMETER DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK DOUT Output Delay CLK Low to CS/LD Low CLR Pulse Width (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) CLOAD = 100pF (Note 2) CONDITIONS
q q q q q q q q q q
MIN 40 0 40 40 50 40 20 5 20 50
TYP
MAX
UNITS ns ns ns ns ns ns ns
Switching Characteristics
45
150
ns ns ns
The q denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from code 0 to code 65535 (full scale) (end point INL, see Definitions section). Note 2: Guaranteed by design. Not subject to test. Note 3: To 1LSB. Unipolar mode. DAC switched between all 1s and all 0s.
Note 4: Digital Inputs at 0V or DVDD. Note 5: Measured at VOUT. REFHI = REFLO = 0V, unipolar mode. Note 6: When part powers up or when it is reset, the output is connected to VRST through this switch. Note 7: Reset is active when any supply goes below this threshold.
PIN FUNCTIONS
VOUT (Pin 1): The Rail-to-Rail Deglitched DAC Output. VRST (Pin 2): The user-defined voltage to which the output gets reset when CLR is active or when any of the supplies drop below 2.5V. The output will stay at this voltage until a new code is loaded into the DAC register. DVDD (Pin 3): The Digital Positive Supply Input. 4.75V DVDD 5.25V. Requires a bypass capacitor to ground. DGND (Pin 4): Digital Ground. DIN (Pin 5): The TTL Level Input for the Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. Data is loaded as one 16-bit word, MSB first. DOUT (Pin 6): The output of the shift register that becomes valid on the rising edge of the serial clock. CLK (Pin 7): The TTL Level Input for the Serial Interface Clock. CS/LD (Pin 8): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low, the CLK signal is enabled so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output. CLR (Pin 9): The DAC is cleared to VRST when this pin is pulled low. It should be logic high for normal operation. RSTOUT (Pin 10): The logic output pin that goes active when any of the supplies drop below 2.5V. This pin is active low. REFHI (Pin 11): The Reference Input Pin. The DAC is capable of 4-quadrant multiplying; this pin can swing from 4.5V to - 4V. REFLO F/REFLO S (Pins 12, 13): The Force and Sense Pin for the Lower Reference Input. This should nominally be tied to ground. This pin can swing from - 1V to 1V.
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LTC1650
PIN FUNCTIONS
AVSS (Pin 14): The Analog Negative Supply Input. - 5.25V AVSS - 4.75V. Requires a bypass capacitor to ground. AVDD (Pin 15): The Analog Positive Supply Input. 4.75V AVDD 5.25V. Requires a bypass capacitor to ground. UNI/BIP (Pin 16): The Unipolar/Bipolar Selection Pin. For unipolar operation, tie this pin to VOUT and for bipolar operation, tie this pin the REFHI.
TI I G DIAGRA
DEFINITIONS
Resolution (n) Resolution is defined as the number of digital input bits, n. It defines the number of DAC output states (2n) that divide the full-scale range. The resolution does not imply linearity. Full-Scale Voltage (VFS) This is the output of the DAC when all bits are set to 1. The output will swing from REFLO to REFHI in unipolar mode and from - REFHI to REFHI when in bipolar mode. Voltage Offset Error (VOS) This is the voltage at the output when the DAC is loaded with all zeros. Least Significant Bit (LSB) One LSB is the ideal voltage difference between two successive codes. LSB = (VFS - VOS)/2n - 1 = (VFS - VOS)/65535 Integral Nonlinearity (INL) Endpoint INL is the maximum deviation from a straight line passing through the endpoints of the DAC transfer curve. It is measured after adjusting out gain and offset error for the DAC. Differential Nonlinearity (DNL) DNL is the difference between the measured change and the ideal 1LSB change between any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB VOUT = The measured voltage difference between two adjacent codes. Gain Error (GE) Gain error is the difference between the full-scale output of a DAC from its ideal full-scale value after offset error has been adjusted for.
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t2 t1 CLK t4 t3
t6 t7
DIN
B16 MSB t9
B15
B14
B1
B0 LSB t5
CS/LD t8 DOUT B16 (PREVIOUS WORD) B15 B14 B1 B0
1650 TD
5
LTC1650
OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register on the rising edge of the clock. Data is loaded as one 16-bit word, MSB first. The DAC register loads the data from the shift register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. The buffered output of the 16-bit shift register is available on the DOUT pin which swings from DGND to DVDD. Multiple LTC1650s may be daisy-chained together by connecting the DOUT pin to the DIN pin of the next chip while the clock and CS/LD signals remain common to all chips in the daisy chain. The serial data is clocked to all of the chips, then the CS/LD signal is pulled high to update all of them simultaneously. When CLR is pulled low or when the part powers up, the output connects through an internal pass gate to VRST and will go to whatever voltage is on VRST. When any of three supplies (DVDD, AVDD, |AVSS|) goes below 2.5V, the RSTOUT pin goes low and stays low as long as the supply is below 2.5V. The power-on reset is also activated when one of the supplies drops below 2.5V and the output is
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then connected to VRST. The output connects to VRST when any of three conditions occur: CLR goes low, the part powers up or one of the supplies drops below 2.5V. This condition exists as long as CS/LD is low. As soon as CS/ LD goes high, the DAC register is loaded with the data in the shift register and the output will settle to its new value. Voltage Output The LTC1650 rail-to-rail buffered output can source or sink 5mA over the entire operating temperature range. The outputs swing to within a few millivolts of either supply rail when unloaded and have an equivalent output resistance of 50 when driving a load to the rails. The buffer amplifier can drive 1000pF without going into oscillation. The LTC1650 has a deglitched voltage output. The midscale glitch is less than 2nV-s. The digital feedthrough is about 0.05nV-s. The LTC1650 is capable of unipolar or bipolar output swing. When the UNI/BIP pin is connected to VOUT the part is configured for unipolar operation and the output will swing from REFLO to REFHI. When connected to REFHI the part is configured in bipolar mode and the output will swing from (- REFHI - REFLO) to (REFHI - REFLO) and will be at - REFLO at midscale.
LTC1650
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508)
0.008 - 0.010 (0.203 - 0.254) 0 - 8 TYP
0.016 - 0.050 0.406 - 1.270 *DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
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Dimensions in inches (millimeters) unless otherwise noted.
S Package 16-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.386 - 0.394* (9.804 - 10.008) 16 15 14 13 12 11 10 9
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
5
6
7
8
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
S16 0695
7
LTC1650 RELATED PARTS
PART NUMBER LTC1257 LTC1446/LTC1446L LTC1448 LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1456 LTC1458/LTC1458L LTC1595 LTC1596 LTC1659 DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V Dual 12-Bit VOUT DACs in SO-8 Package Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality 16-Bit Multiplying IOUT DAC in SO-8 16-Bit Multiplying IOUT DAC Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package, VCC: 2.7V TO 5.5V Parallel I/O Multiplying 12-Bit DAC Serial I/O Multiplying IOUT 12-Bit DACs Serial I/O Multiplying IOUT 12-Bit DAC COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Output Swings from GND to REF. REF Input Can Be Tied to VCC LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 5V, Low Power Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 1LSB Max INL/DNL, Low Glitch, DAC8043 16-Bit Upgrade 1LSB Max INL/DNL, Low Glitch, AD7543/DAC8143 16-Bit Upgrade Low Power Multiplying VOUT DAC in MSOP-8 Package. Output Swings from GND to REF. REF Input Can be Tied to VCC 12-Bit Wide Input Clear Pin, Serial Data Output (LTC8143) 8-PIn SO and PDIP
LTC7541A LTC7543/LTC8143 LTC8043
8
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 q FAX: (408) 434-0507 q www.linear-tech.com
1650I LT/TP 0698 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1998

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