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PMC-Sierra, Inc. REFERENCE DESIGN
ISSUE 3
PM5355 S/UNI-622
SATURN USER NETWORK INTERFACE
PM5355 S/UNITM
622
S/UNI-622TM ATM Reference Design with Multimode Optics
Preliminary Information Issue 3: October 11, 1996
PMC-Sierra, Inc.
105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 415 6000
PMC-Sierra, Inc. REFERENCE DESIGN
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PM5355 S/UNI-622
SATURN USER NETWORK INTERFACE
Table of Contents OVERVIEW .................................................................................................. 1 BLOCK DIAGRAM........................................................................................ 3 IMPLEMENTATION DESCRIPTION ............................................................ 4 Sheet 1: Power Supply Protection & Regulation, SCI-PHY Expansion Board Connectors. .............................................................. 4 Sheet 2: S/UNI-622 Interconnect. ......................................................... 5 Sheet 3: Vitesse VSC8110 Interconnect .............................................. 7 Sheet 4: Optics Interface. ..................................................................... 8 LAYOUT DESCRIPTION ............................................................................. 10 APPENDIX1: JITTER TEST RESULTS....................................................... 17 APPENDIX2: SCHEMATICS ....................................................................... 22 NOTES ........................................................................................................ 23
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OVERVIEW The S/UNI-622 implements the SONET/SDH overhead processing and ATM convergence layer functionality required in an ATM system. This device integrates duplex operation by appropriate termination (or origination) of the SONET overhead and the extraction ( or mapping) of the ATM payload in the receive (or transmit) path. In the receive direction, the SONET section (SOH), line (LOH) and path (POH) overhead are terminated and the ATM cells are extracted from the SONET payload. These extracted cells are made available to the external AAL processor via the SCIPHY interface on the DROP side. In the transmit direction, the ATM cells received through the SCI-PHY interface are mapped into the SONET payload prior to the addition of the section (SOH), line (LOH) and path (POH) overhead. Once the SONET signal is assembled, it is transmitted out in a byte serial manner. To build the core functionality of an ATM switching system (or an ATM router or an ATM terminal) the S/UNI-622 must be interfaced appropriately to the optical line and the SCI-PHY interface. In the receive direction the process required is to convert the optical data to electrical format, recover the clock and transform the serial data into a bytewise parallel form before connection to the S/UNI-622. The S/UNI-622 then handles the termination of the SONET line and the extraction of the ATM payload. In the transmit direction, the reverse process of converting the byte serial ATM mapped SONET data (from the S/UNI-622) to serial before conversion to the optical format is required. Logically, this is a simple function. However, because of the high speed signals involved in this design, the layout task must be effectively designed to minimize reflections due to transmission line effects at the 622MHz and 77MHz interfaces. This includes controlling the characterization of the transmission lines, keeping line distances short and incorporating extra circuitry dedicated for termination. In this reference design the O/E conversion and the E/O conversion is carried out by the Hewlett Packard HFBR-5207 Multimode Fiber Transceiver. In the receive direction the HP HFBR-5207 converts the optical data to electrical PECL. This device also contains an integrated clock recovery circuit. The extracted clock and data is connected to a Vitesse VSC8110 which does the serial to parallel conversion before interfacing to the S/UNI-622. Note that the PECL serial receive data is levelshifted to interface properly with the Vitesse ECL input, which expects input signals between 0 to +2v. In the transmit direction, the S/UNI-622's bytewise data is taken by the Vitesse VSC8110 and converted to a serial stream at the 622Mhz rate. The HP HFBR-5207 takes the 622MHz serial data stream and converts it to optical format at the same frequency. Note that the serial transmit data from the Vitesse VSC8110 is level-shifted to PECL levels to interface properly with the HP optics. As already mentioned above, the layout between the HP HFBR-5207, and the VSC8110 is critical and should be controlled to minimize transmission line distances. Also, appropriate termination (with the characteristic impedance) at the end of the line is required to eliminate transmission line effects.
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At the system side, the DROP and ADD interfaces to the S/UNI-622 allow the reception and transmission of ATM cells. The DROP side passes the extracted cells to the ATM/AAL layer processor device via the receive SCI-PHY interface. The ADD side receives the assembled ATM cells from the ATM/AAL processor via the transmit SCI-PHY interface. Both the DROP and ADD interfaces are configurable to be either 8 bit wide or 16 bit wide. The microprocessor interface allows access to the S/UNI-622 internal registers. These are used to configure the S/UNI-622 into its various operating modes as well as to monitor the performance and status of its internal functions. When operating in the STM12c/STM-4 mode the internal configuration registers will default (on power up) to a state where microprocessor access is not required. In this mode, it is possible to do without a microprocessor interface and therefore avoid some expense. However, it should be noted that this will also limit the observability of internal status and general performance information that is normally available through the reading of internal registers. This reference design implementation is shown in the block diagram below.
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BLOCK DIAGRAM
19.44 MHz Ref. Clock
REFCLK_P/N TXLSCKOUT TXDATAOUT_P/N TXLSCKIN TXIN[7:0] TCLK TCA TXPRTY[1:0] TDAT[15:0] TXIN[7:0] TDAT[15:0] POUT[7:0] TSOC TWRENB TSOC TWRENB TFCLK
TSD+/TXDP/N
TCLK
TCA TXPRTY[1:0]
TX
HP HFBR-5207
RXDP/N RX CLKP/N RSDATAIN+/RSCLKIN+/-
TFCLK
VSC8110 PISO/SIPO & CLOCK SYNTHESIS
RXDATAIN_P/N RXLSCKOUT RXCLKIN_P/N FP RXOUT[7:0] OOF PIN[7:0] PICLK FPIN
PM5355 S/UNI-622 SATURN USER NETWORK INTERFACE
RCA RXPRTY[1:0] PICLK RDAT[15:0] FPIN PIN[7:0] OOF OOF RSOC RRDENB RFCLK
RCA RXPRTY[1:0] RDAT[15:0] RSOC RRDENB RFCLK
Microprocessor Interface
Figure 1. Block Diagram of 622 SONET/ATM Core.
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IMPLEMENTATION DESCRIPTION Sheet 1: Power Supply Protection & Regulation, SCI-PHY Expansion Board Connectors. FUNCTION The function of this sheet is to provide a regulated VMM (+2V) output for the Vitesse VSC8110, and to provide the SCI-PHY and microprocessor interface to the S/UNI622. IMPLEMENTATION Power Supply Protection & Regulation All capacitors shown are for power supply decoupling. The voltage regulator (LM317) supplies the +2V as controlled by resistors R10 and R29. The Vitesse VSC8110 utilizes power from the VMM output for its serial 622 serial input/output interface with the HP optics. SCI-PHY Expansion Board Connectors The AMP103911-8 and the AMP103911-2 together make up a 120 pin connector for interfacing to an external SCI_PHY motherboard, microprocessor and power supply module. This interface will be connected to the SCI-PHY motherboard and the microprocessor motherboard via an intermediate translation board that will map these pins to the target motherboard. This intermediate board will supply GND (0.0V) and VDD (+5.0V) power on the various connector inputs. For microprocessor interfacing the address is received on the A[7:0] inputs and the data is transported on the D[7:0] pins. The read, write, address latch enable and chip select signals are received on the RDB, WRB, ALE and CSB inputs. All signals ending in "B" are active low. For the micro access timing, refer to the S/UNI-622 PMC-Sierra data book. The remaining pins in these connectors, with the exception of the power supply pins, are dedicated to the SCI-PHY interface. The transmit cell available signal is received on the TCA input. The receive cell available signal is received on the RCA input. The receive data parity signals are received on the RXPRTY[1:0] inputs. The receive start of cell indication is indicated on the RSOC input. The receive cell data in transferred on the RDAT[16:0] inputs from the S/UNI-622 to the SCI-PHY device. The transmit cell data is transferred from the SCI-PHY device to the S/UNI-622 on the TDAT[16:0] outputs. The writing of the data into the S/UNI-622 is timed synchronous to the TFCLK output. The transmit start of cell indication is signaled to the S/UNI-622 on the TSOC output. The transmit data parity signals are conveyed on the TXPRTY[1:0] outputs. The cell data write enable is validated with the WRENB output. The data
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read from the S/UNI-622 is synchronously controlled by the RFCLK clock output and the RRDENB output The remaining pins on this 120 pin connector are dedicated to the power supply inputs from an external power supply module. The VDD (+5.0V) will be supplied on 8 connector inputs and the GND (0.0V) will be supplied on 34 connector inputs. The power supply decoupling and rumble capacitor is also shown on this sheet. These components must be placed close to the connector inputs and the rumble capacitor must be 10F polarized. Sheet 2: S/UNI-622 Interconnect. FUNCTION The function of this sheet is to provide interconnect between the S/UNI-622, the VSC8110 (serial to parallel converter and parallel to serial converter), the SCI-PHY interface, and the microprocessor interface. Other functionality contained in this sheet provides retiming of the POUT[7:0] output, pullup/pulldown of the unused inputs and an LED display of some alarm indications. IMPLEMENTATION The connections to the S/UNI-622 are depicted in the block diagram shown in figure1. The five main interfaces are the byte serial receive interface, the byte serial transmit interface, the SCI-PHY transmit interface, the SCI-PHY receive interface and the microprocessor interface. All unused inputs are connected to pulldown or pullup resistors via 1K resistor packs. The byte serial receive interface consists of the PICLK, FPIN, FPOS and PIN[7:0] inputs. The PICLK input is a 77MHz signal derived by the VSC8110 by dividing the recovered clock by 8. This clock is used by the S/UNI-622 to sample the FPIN and PIN[7:0] inputs. The PICLK is terminated at the S/UNI-622 with the resistor network consisting of R18 and R13. FPOS is pulled high via a 1K resistor to enable FPIN to mark the third byte of the A2 byte of the SONET frame. The diagram below shows the marginal setup time that exists between the VSC8110 outputs and the S/UNI-622 PICLK and PIN[7:0] inputs. This identical timing exists with the FPIN input as well as the PIN[7:0]. Since there is only a 0.2ns timing margin on the setup time (data valid to the rising edge of clock) on the FPIN and PIN[7:0] inputs, precautions must be taken to avoid skew between these inputs. In fact, a slight delay (in the order of 15ns) in the data path would be advantageous and a slight delay (greater than 0.2ns) in the clock path would be intolerable. Hold time is not a concern on this interface since only 3ns are required and there are 11.9ns available.
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0 ns 3.12 ns 6.25 ns
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9.38ns 12.50 ns
PICLK PIN[7:0] 4.9 ns 4.9 ns 2.5 ns min req 12.8 ns
The byte serial transmit interface consists of the TCLK and TFP inputs and the FPOUT and POUT[7:0] outputs. The TCLK input is a 77MHz signal derived by the VSC8110 by dividing the synthesized TXCK 622MHz clock by 8. The TFP input is tied low via a pull down resistor and the output data is arbitrarily aligned after powerup reset. TCLK is used by the S/UNI-622 to retime its FPOUT and POUT[7:0] outputs and is terminated at the S/UNI-622 with the resistor network consisting of R27 and R23. The VSC8110 has a setup time of 1.0ns on its TXIN[7:0] inputs. Combined with the propagation delay through the S/UNI-622 gives 12.0ns. Since this is less than one clock cycle, the transfer of data into the VSC8110 is guaranteed. The following timing diagram shows this more clearly. The S/UNI_POUT[7:0] waveform shows the relationship between the data out of the S/UNI-622 and its transmit clock, S/UNI-622_TCLK. This same clock is used to clock the data into the VSC8110.
11ns Max.
S/UNI-622_TCLK
2ns Min. 1.86ns Min.
VSC8110 samples here (1ns setup)
S/UNI_POUT[7:0]
D1
The SCI-PHY transmit interface is implemented by the TFCLK, TSOC, TXPRTY[1:0], TWRENB and TDAT[15:0] inputs and the TCA output. These connections connect directly to the SCI-PHY interface connector on sheet 1.
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The SCI-PHY receive interface is implemented by the RRDENB, RFCLK inputs and the RSOC, RXPRTY[1:0], RDAT[15:0] and RCA outputs. These connections also connect directly to the SCI-PHY interface connector on sheet 1. The outputs POP0 to POP5 are used by the VSC8110 to determine the mode of operation. These outputs can be set to any value by writing to the internal S/UNI-622 registers associated with this port. The microprocessor interface is implemented by the D[7:0] (bidirectional), A[7:0], ALE, CSB, WRB and RDB inputs. These connections connect directly to the microprocessor interface connector on sheet 1. The 74HCT245 and the LED display circuitry interfaces to eight alarm signals generated by the S/UNI-622. Various other outputs of the S/UNI-622 are connected to observation points for easy probing during debug; these are provided by the TPn test points. All capacitors are for power supply decoupling local to the S/UNI-622, and 74HCT245. Sheet 3: Vitesse VSC8110 Interconnect FUNCTION The function of this sheet is to provide serial to parallel conversion (of the data received from the optics) and parallel to serial conversion (of the data transmitted to the optics). Clock synthesis is also implemented in this schematic. IMPLEMENTATION All data and clock traces are characterized with a 50 characteristic impedance (terminated accordingly at the end of the line) and should be kept short to reduce transmission line effects. The VSC8110 transforms the bit serial receive data on its RXDATAIN_P and RXDATAIN_N inputs into a bytewise parallel form on the RXOUT[7:0] outputs. It is vital that the layout of the interface between the HP HFBR-5207 optics outputs and the VSC8110 inputs introduce no clock skew between the VSC8110 RXCLKIN_P and the RXDATAIN_P signals. This is achievable if layout and termination precautions are taken as mentioned in the overview. Note that AC-coupling capacitors are used to interface the PECL level clock and data signals from the HP HFBR-5207 to the 0V to +2V levels required by the VSC8110. The DC bias into the VSC8110 is set to 0.7V by the resistor network (147ohm to VMM (+2V) and 76 ohm to ground). In the opposite direction there is no required clock and data relationship, since the HP HFBR-5207 only requires the transmit data. However, the same layout precautions should be taken so that there is no skew between the VSC8110 differential data pair outputs TXDATAOUT_N and TXDATAOUT_P. Note that AC-coupling capacitors are
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used to interface the 0V to +2V level data signals from the VSC8110 to the PECL levels required by the HP HFBR-5207. The pull-down resistors, R17 and R32, at the VSC8110 TXDATAOUT_P and TXDATAOUT_N outputs have a value of 50 ohms, as opposed to 270ohms as recommended by Vitesse. This is done to increase the signal swing from 300mV to 500mV, which will be sufficient for the HP HFBR-5207 inputs. The VSC8110 also generates a byte rate clock and a frame pulse on the FPIN and PICLK outputs. In the transmit direction, the POUT[7:0] byte serial data is converted into a bit serial output stream on the TSD+/- outputs. The VSC8110 also synthesizes a 77MHz TCLK and the 622MHz TXCK outputs using a 19.44MHz reference on its REFCLK_P/REFCLK_N PECL clock input. The remaining passive circuitry implements transmission line termination and pullup pulldown and power supply decoupling functions. Sheet 4: Optics Interface. FUNCTION The function of this sheet is to provide the optical interface in the receive and transmit directions. In the receive direction clock and data recovery is also implemented. IMPLEMENTATION The HP HFBR-5207 receives the optical signal and outputs the electrical recovered data on its RXDP and RXDN outputs, and the recovered clock on its CLKP and CLKN outputs. In applications where the recovered clock frequency is not allowed to drift upon loss of input optical signal, the HP HFBR-5207 can generate a local clock output by multiplying an external 19.44MHz reference clock (connected to the REF_CLK input) to 622MHz. This feature is controlled by the active-low lock to reference input (LCK_REFB). This input is driven by the Signal Detect (SD) output from the HP HFBR-5207. That is, if the receiver section detects loss of optical signal, SD will be asserted, and this will cause the HP HFBR-5207 to lock to the reference clock. The passive components around the receiver section of the HP HFBR-5207 are for decoupling the power supply, providing emitter pulldown and termination of the 50 transmission line. The termination resistors should be placed at the end of the transmission line and the power supply decoupling capacitors should be placed as close as possible to the HP HFBR-5207. The HP HFBR-5207 transmits the optical signal to the line. This device takes the serial electrical data on the TSD+/- inputs and converts the signal to an optical format. The passive components around the HP HFBR-5207 are for decoupling the power supply and termination of the 50 transmission line. The DC bias of the TXDP and TXDN inputs are set to 3.7V by a resistor network (191ohms to +5V and 68.1ohms to
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ground). The decoupling capacitors should be placed as close as possible to the HP HFBR-5207.
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LAYOUT DESCRIPTION In general the layout must be designed to minimize the noise coupling between the different interfaces on this board. Besides the usual capacitive decoupling methodology, further isolation can be provided by dedicating power and ground planes to distinguishable sections of circuitry. Such divisions can be made by grouping transmit and receive circuitry into two separate groups and further into analog and digital groups. By isolating in this way, the general noise level on the whole board can be kept minimal. An example of such a scheme is illustrated in the two diagrams below.
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The actual layout can be seen in the layout schematic provided in this document. Throughout this design, high speed signal termination and noise reduction techniques outlined in the following text have been considered. High Speed Signal Termination Trace Impedance Control To reduce signal degradation due to reflection and radiation, the impedance of all high frequency signals should be treated as transmission lines and terminated with a matching impedance at the destination. In this design, all high speed signal traces use 50 Ohm transmission lines.
TSD+/-
HP HFBR-5207 RSD+/-
VSC8110
RSC+/-
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All high frequency traces are modeled as microstrip transmission lines. calculation of the trace width is calculated using the following formula. Zo = 87 5.98 x h x ln 0.8 x w + t r + 1.41
The
and based on the following layer setup:
w t
1 Oz Copper
dielectric
Ground Plane 1 Oz Copper
r
h1 t h2 h3
dielectric
Power Plane 1 Oz Copper
r
dielectric
t
1 Oz Copper
r
where
r = relative dielectric constant , nominally 5.0 for G -10 fibre - glass epoxy t = thickness of the copper , fixed according to the weight of copper selected . For 1 oz copper, the thickness is 1.4 mil. This thickness can be ignored if w is great enough. h1, h2, h3 = thickness of dielectric . w = width of copper
The parameters h1, h2, and h3 can be specified. For example, if a 20 mil (including the copper thickness on both sides of the board) two layer core is selected, dielectric material that have the same relative dielectric constant can be added to both sides of the core to construct a 4 layer board. Since all the controlled impedance traces are on the component side, only h1 is relevant in calculating the trace width. The calculation for the reference design is shown in the table below: Note: The relative dielectric constant is specified to be between 4.8 and 5.4.
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Parameter
Data 4.8 62 1.4 50 108.9 5.4 62 1.4 50 101.6 4.8 62 1.4 100 24.7 5.4 62 1.4 100 21.3
r
h (mil) t (mil) Zo (Ohm) W (mil)
The value of the parameter h1 is chosen to be 62 mil. Since h1 is directly proportional to the width of the traces, a small h1 will result in the 100 Ohm traces being too thin to be accurately fabricated. Wider traces can be more precisely manufactured, but they take up too much board space. Therefore, the thickness of the board should be chosen so that the traces take up as little board space as possible yet still leaving enough margin to allow accurate fabrication. In the layout enclosed, the width of the 100 Ohm traces is 24 mil and that of the 50 Ohm traces is 104 mil. Routing High speed signal routing is based on design considerations as well as manufacturability. Several suggestions are listed below: 1. Turns and corners should be rounded to curves to avoid discontinuity in the signal path. 2. Allow at least 10 mil clearance among vias, traces, and pads to prevent shorts and reduce crosstalk. If possible, allow 20 mil or more clearance around vias as manufacturers may have minimum clearance requirements. For the traces that runs between pads of the 100 pin edge connector, clearance of 6 mil and trace width of 8 mil can be used. However, the number and lengths of such traces should be kept to a minimum. 3. The differential signal pairs should be of equal length so that both signals arrive at the inputs at the same time. They should also run parallel and close to one another for as long as possible so that noise will couple onto both lines and become common mode noise which is ignored by the differential inputs. 4. All power and ground traces should be made as wide as possible, up to 24 mil to provide low impedance paths for the supply current as well as to allow quick noise dissipation.
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Termination "Termination" applies to terminating a signal propagating down a transmission line to the characteristic impedance of line. If the line is not terminated to it's characteristic impedance, there will be reflections back down the line. The amount of reflection at the load (receiver) is given by the load reflection coefficient: rL = (RT-Zo)/(R T+Zo) where R T is the load impedance and Zo is the characteristic impedance of the line. The amount of reflection at the source (transmitter) is given by the source reflection coefficient: rS = (RS -Zo)/(R S+Zo) where R S is the source impedance and Zo is the characteristic impedance of the line. The reflected signal propagates back and forth until the "ringing" dies out. There are 4 basic types of terminations used for PECL (or ECL). They are open line termination, series termination, parallel termination, and Thevenin parallel termination. Since PECL (or ECL) signals only drive high, external biasing is needed to pull the PECL signal low. This biasing has to be incorporated into the termination scheme. In the design, the Thevenin termination method has been used. The terminated lines are terminated to the characteristic impedance and sets the terminating (VT) voltage. The Thevenin equivalent parallel termination is shown below:
Vcc R1 Transmitter Receiver R2
Zo
The resistors R1 and R2 in parallel must equal Zo and the voltage at the input must pull the output of the transmitting gate to VBB Volts. Working out the equations for PECL +5 Volt supply for Vcc gives: R2 = 2.5 * Zo R1 = R2*2/3
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Note that the above examples show only one of the differential inputs. With the Thevenin termination care must be taken so that the Vcc and grounds of the differential signals are taken in close proximity of each other or the noise on Vcc and ground will not be in common with each other. Power and Ground Plane Noise Decoupling Bypass capacitors can supply transient current and help filter out power and ground noise. They are placed as close to the pins as possible. Minimum of one 0.1 uF bypass capacitor per device is used. Wherever possible, one 0.1 uF bypass capacitor is placed at each power pin of each IC. For decoupling at the supply inputs, large electrolytic bypass capacitors (100 uF) are placed near the 5 volt power supply inputs. It is also necessary to isolate power and ground planes supplying analog circuitry from the digital circuitry. The digital CMOS circuits have high immunity to external noise (approximately 0.3 * Vcc) whereas a small amount of external noise coupled into the analog circuits can be devastating since the analog circuits operate on low voltage swings (600 mVolts for the PECL inputs) compared to the large (5 Volt) voltage swings of the CMOS inputs. The CMOS circuits can also generate a lot of switching noise, especially when a large number of circuits are running synchronously all timed to the same system clock. If the analog power and grounds are not isolated from each other it is unlikely that the board will be able to meet the 0.01 U.I. rms. jitter specified by Bellcore. Therefore, it is necessary to isolate the digital from the analog, otherwise the analog performance can be degraded to a point of non-conformance. It is also necessary to isolate the transmit analog circuitry from the receive analog circuitry. Any noise on the receive analog power and ground or on the receive inputs will degrade jitter tolerance and add jitter to the recovered clock. It is also important to keep the analog optical transceiver receive path in common with the receive portion of the VSC8110, especially the grounds. On the transmit side the, 622 MHz clock is synthesized from a 19.44 MHz reference clock. Any added noise on the power or ground inputs impacts the resulting synthesized 622 MHz clock. This added noise will result in an increased intrinsic jitter at the transmitter. The power and ground of the transmit portion of the HP HFBR5207 optical transceiver should be in common with the analog transmit power and ground of the VSC8110 to reduce ground plane imbalance. Since only one ground layer and one power layer is normally available, the transmit, receive, and digital power and grounds can be isolated by channels cut into the respective planes. The power and grounds should be brought from a quiet part of the board, usually where the power and grounds enter the board. Ferrite beads can also be used on the receive and transmit analog powers to prevent digital noise from
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entering analog circuits of the 19.44 MHz oscillator, VSC8110 and the optical transceiver. Ferrite beads are mainly used on power rails to pass DC current but to attenuate the higher frequency noise that is created by other sources. The impedance of Ferrite beads increases with frequency. At DC the ferrite bead is like a short but at higher frequency the impedance of a ferrite bead can increase to over 100 ohms (depending on the bead and frequency). Ferrite beads attenuate high frequency noise from the power supply from getting into a circuit, but they also stop high frequency noise from leaving the circuit. It is important, therefore, to use proper bypass decoupling when using ferrite beads. Ferrite beads should be avoided on CMOS I/O power pins as the high current switching of the CMOS circuits causes a I/t noise to be introduced into the power rail. Ferrite beads should also be avoided on the ground bus as this inhibits the return currents. To reduce digital circuit switching noise, it is important to decouple every digital power pin of all devices so that the switching currents can be satisfied and thereby reduce the amount of noise introduced into the power plane.
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APPENDIX1: JITTER TEST RESULTS This appendix includes results obtained from jitter measurements performed on the S/UNI-622 reference design board using various optical modules. These results are for reference only, and were obtained in the absence of appropriate standards at the time of execution. Compliance to future standards should be checked using these results. 1. HP HFBR-2507 version 5.4 Jitter Tolerance Measured using the S/UNI-622 reference design board, with the following components: HP HFBR-2507 622 multimode optics with CRU, version 5.4 Vitesse VSC8110 SIPO S/UNI-622 to monitor the bit error rate Method: - HP STS-12 SONET Tester used to generate and receive STS-12 electrical serial signal, with PRBS-23 data in one of the STS-3c's (HP does not have STS-12c mode). - This goes into the SJ300 Jitter Analyzer, which converts the signal into optical form and adds the jitter for tolerance testing. - Optical attenuator provides the necessary attenuation. Attenuation was added till the Section BIP error rate was about 1x10 -10 (monitored at the tester by looking at FEBE's sent back by the S/UNI-622 to the Tester). Then the attenuation was reduced by 1 dB for the actual jitter tolerance test. Setup:
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Results:
622 Multi Mode Transceiver Reference Design Jitter Tolerance
HP-HFBR5207 v5.4 and VSC8110 (UIpp) OC-12 Template 10000
Jitter
Tolerance
0.1
Frequency (Hz)
Attenuation = 17.4 dB Actual optical power at optical receiver = -28.2 dB Conclusion: Jitter tolerance failed at 700kHz, 0.14UI.
2. HP HFBR-5207 version 5.2 Jitter Tolerance Measured using the S/UNI-622 reference design board, with the following components: HP HFBR-5207 622 multimode optics with CRU, version 5.2 Vitesse VSC8110 SIPO S/UNI-622 to monitor the bit error rate Method: Same as with HP HFBR-5207 version 5.4.
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Setup:
Results:
622 Multimode Reference Design Jitter Tolerance
100000
HP HFBR-5207 v5.2, VSC8110 OC-12 Template
Tolerance
(UIpp)
Jitter
0.1
10000
1
Frequency (Hz)
Attenuation = 18.7 dB Actual optical power at optical receiver = -27.7 dB Conclusion: Jitter tolerance passed with at least 0.06UI margin.
19
PMC-Sierra, Inc. REFERENCE DESIGN
ISSUE 3
PM5355 S/UNI-622
S/UNI-622 Multimode Optics Reference Design
Jitter Transfer of CRU Method: - HP STS-12 SONET Tester used to generate and receive STS-12 electrical serial signal, with PRBS-23 data in one of the STS-3c's (HP does not have STS-12c mode). - This goes into the SJ300 Jitter Analyzer, which converts the signal into optical form and adds the jitter for transfer testing. - Optical attenuator used to set the same attenuation as in jitter tolerance test (17.7dB). - The recovered clock from the optics is fed back into the SJ300 Setup:
Results:
100
HP Multimode Optics CRU Jitter Transfer
(dB)
-15
-20
-25
Jitter
Transfer
-30
10
Frequency (Hz) OC-12 Template HFBR-5207 CRU
Conclusion: Jitter Transfer failed. Peaking of about 4dB at 110kHz observed.
20
PMC-Sierra, Inc. REFERENCE DESIGN
ISSUE 3
PM5355 S/UNI-622
S/UNI-622 Multimode Optics Reference Design
Jitter Generation of VSC8110 CSU Method: - Optical signal from HFBR-5207 measured directly by SJ300 - 2 different oscillator frequencies used to feed VSC8110 CSU - RMS jitter measured with 12kHz high pass filter - Peak-to-peak jitter measured with 10Hz high pass filter Results: VDD (Volts) 4.7 5.0 5.3 4.7 5.0 5.3 Ref. Frequency (MHz) 19.44 RMS Jitter (UI) 0.009 0.009 0.008 0.008 0.008 0.009 Peak-to-Peak JItter (UI) 0.14 0.14 0.13 0.12 0.12 0.11
51.84
Conclusions: According to Bellcore GR-253, Dec 94, the maximum RMS jitter generated should be 0.01UI, and the maximum peak-to-peak jitter generated should be 0.10UI. The measured RMS jitter passed but the measured peak-to-peak jitter failed.
21
PMC-Sierra, Inc. REFERENCE DESIGN
ISSUE 3
PM5355 S/UNI-622
S/UNI-622 Multimode Optics Reference Design
APPENDIX2: SCHEMATICS
22
10
9
8
7
6
5 VCC
4
3
2
1
REVISIONS
ZONE REV DESCRIPTION DATE APPR
H
MICROPORCESSOR INTERFACE
H
2D4 2D1>
C33 100UF RXPRTY1
8 9 10 11 12 13 14 15
1
+
2
P1
A1 A3 A5 A7 A9 A11 A13
RDAT<8> RDAT<9> RDAT<10> RDAT<11> RDAT<12> RDAT<13> RDAT<14> RDAT<15>
A1 A3 A5 A7 A9 A11 A13 A15 A17 A19
A2 A4 A6 A8 A10 A12 A14 A16 A18 A20
A2 A4 A6 A8 A10 A12 A14 A16 A18 A20
TXPRTY1 TDAT<15..0>
2E10< 1F4 1G4 2E10<
G
1G7 1E7 2C5 1D7 2C4 2C1> 1H7
A15 A17
RDAT<15..0>
A19
TDAT<8> TDAT<9> TDAT<10> TDAT<11> TDAT<12> TDAT<13> TDAT<14> TDAT<15>
8 9 10 11 12 13 14 15
G
AMP 103911-2
A1 A3
P2 A1 A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 A39 A41 A43 A45 A47 A49 A51 A53 A55 A57 A59 A61 A63 A65 A67 A69 A71 A73 A75 A77 A79 A81 A83 A85 A87 A89 A91 A93 A95 A97
A2 A4 A6 A8 A10 A12 A14 A16 A18 A20 A22 A24 A26 A28 A30 A32 A34 A36 A38 A40 A42 A44 A46 A48 A50 A52 A54 A56 A58 A60 A62 A64 A66 A68 A70 A72 A74 A76 A78 A80 A82 A84 A86 A88 A90 A92 A94 A96 A98
A2 A4 A6 A8 A10 A12 A14 A16
VCC F
1
A5 A7
TDAT<4> TDAT<0> TDAT<5> TDAT<1> TDAT<6> TDAT<2> TDAT<7> TDAT<3>
4 0 5 1 6 2 7 3
POLARIZED
1 1
POLARIZED
1 1 1 1
A9 1 A11
F TXPRTY0 TSOC
2E10< 2E10<
+C71 10UF
+C55 10UF
+C58 10UF
+C62 10UF
C61 0.1UF
2 2
C64 0.1UF
2
C70 0.1UF
2
C67 0.1UF
A13 A15 A17
2
2
2
2
POLARIZED
A18 A20 A22 A24 A26 A28
POLARIZED
A19 A21
TFCLK
2E10<
DECOUPLING CAPS FOR CONNECTORS
A23 A25 A27
E
4 0 5 1
TWRENB
A30 A32 A34 A36 A38 A40 A42 A44 A46 A48 A50 A52 A54 10 21 32 43 54 65 76 87
A29
2E10<
RDAT<4> RDAT<0> RDAT<5> RDAT<1> RDAT<2> RDAT<6> RDAT<3> RDAT<7>
E
A31 A33 A35
2 6 3 7
A37 A39 A41 A43 A45
2D4 2D4 2B4
2D1> 2D1> 2B1> 2B1> 2B1>
RXPRTY0 RSOC RCA
A47
D
2B4
TCA INTB
A49 A51 A53 A55 A57
RRDENB RFCLK A<7..0>
RES_ARRAY_15
2D10< 2D10< 2B10<
D
A58 A60 A62 A64 A66 A68 A70 A72
POWER
VCC
3
A59 A61
4 0 5 1
VCC
1K RN1
16 15 14 13 12 11 10 9
A56
U2 LM317 VIN VOUT ADJ
1 1 1 21 2
A63
VMM
A65 A67 A69 A71
6 2 7 3 0 1 2 3 4 5 6 7
D<7..0>
1 2 3 4 5 6 7 8
2D10<
C C49 0.1UF
2
C
RES_ARRAY_15
240
1 2 2
2
R29 R10
A75 A77 A79 A81 A83 A85 A87
A76 A78 A80 A82 A84 A86 A88 A90 A92 A94 1 A96 A98 A100 2 5 2 6 3 7
VCC
143
1K RN2
16 15 14 13 12 11 10 9
+ C23 0.1UF
C53 10UF POLARIZED
A73
A74
0 4 1
1
VCC
B
A89 A91
CSB RSTB RDB ALE WRB DRAWING TITLE=SUNI_622_MULTI ABBREV=SUNI622M
2B10< 2B10< 3C10< 2B10< 2B10< 2B10<
B
VCC
VDD_RA
VDD_TA
A93
R19 1K
NOTE:
VDD_RA = +5V = RECEIVE ANALOG POWER FOR OPTICS TO VSC8110 VDD_TA = +5V = TRANSMIT ANALOG POWER FOR VSC8110 TO OPTICS RA TA VCC = +5V = DIGITAL POWER VMM = +2V = VMM POWER FOR VSC8110 ONLY GND_RA = 0V = RECEIVE ANALOG GROUND FOR OPTICS TO VSC8110 GND_TA = 0V = TRANSMIT ANALOG GROUND FOR VSC8110 TO OPTICS GND = 0V = DIGITAL GROUND
A95 A97 A99
LAST_MODIFIED=Wed Feb 14 13:32:23 1996 VCC
A99 A100
AMP 103911-8
1 1
C22 100UF
+
2 2
+C31 100UF
+C76 100UF DOCUMENT NUMBER: TITLE:
PMC-Sierra, Inc.
PMC-950860 ISSUE: ISSUE 2 DATE: FEB 14, 1996 PAGE: 1 2 TRUE 1 OF 4 A
A
2
1
PM5955-3: S/UNI_622 ATM REF DESIGN WITH MULTIMODE OPTICS
BULB DECOUPLING CAPS FOR TX AND RX PLANES 10 9 8 7 6 5 4 3
ENGINEER:
P. CHOHAN
10
9
8
7
6
5
4
3
2
1
REVISIONS
R18 & R13 PLACE CLOSE TO U13 S/UNI 622 PIN
330 1 21 220 2
ZONE
VCC
REV
DESCRIPTION
DATE
APPR
H
R18 H 1K
16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9
RES_ARRAY_15 RES_ARRAY_15
R13
RN4
RN6 1K
10 27 81 120 152 183 205
11 28 40 66 80 98 110 119 129 138 165 179 189 206
3D1> 3G1> 3G1> 3F1>
TCLK PICLK PIN<7..0> FPIN
1 2 3 4 5 6 7 8
U13
137 1K 1 2 150 149 148 147 146 145 144 143 142 141 88 103 94 93 89 91 92 86 85 84 83 101
1 2 3 4 5 6 7 8
97 74
PICLK FPOS FPIN PIN0 PIN1 PIN2 PIN3 PIN4 PIN5 PIN6 PIN7 TLAIS TSD TSOW TSUC TLRDI TLD TLOW TTOH1 TTOH2 TTOH3 TTOH4 TTOHEN TPOH TPOHEN TPAIS TPRDI RSICLK RSIN TSICLK TFCLK XOFF TSOC TXPRTY0 TXPRTY1 TWRENB TDAT0 TDAT1 TDAT2 TDAT3 TDAT4 TDAT5 TDAT6 TDAT7 TDAT8 TDAT9 TDAT10 TDAT11 TDAT12 TDAT13 TDAT14 TDAT15 RRDENB RFCLK TSEN TGFC D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3 A4 A5 A6 A7 ALE CSB WRB RDB RSTB TCK TMS TDI TDO TRSTB
S/UNI 622
1
VDD_AC7 VDD_AC6 VDD_AC5 VDD_AC4 VDD_AC3 VDD_AC2 VDD_AC1
VDD_DC14 VDD_DC13 VDD_DC12 VDD_DC11 VDD_DC10 VDD_DC9 VDD_DC8 VDD_DC7 VDD_DC6 VDD_DC5 VDD_DC4 VDD_DC3 VDD_DC2 VDD_DC1
TFP TCLK FPOUT 123 POUT0 POUT1 POUT2 POUT3 POUT4 POUT5 POUT6 POUT7 OOF LOF LOS TSDCLK TOWCLK RSDCLK RSD ROWCLK RSOW RSUC OHFP LAIS LRDI RLDCLK RLD RLOW TLDCLK RTOH1 RTOH2 RTOH3 RTOH4 RTOHCLK RTOHFP TTOHCLK TTOHFP RPOH RPOHCLK RPOHFP TPOHCLK TPOHFP LOP PAIS PRDI TSOUT GTOCLK GROCLK LCD RSOC RXPRTY0 RXPRTY1 RDAT0 RDAT1 RDAT2 RDAT3 RDAT4 RDAT5 RDAT6 RDAT7 RDAT8 RDAT9 RDAT10 RDAT11 RDAT12 RDAT13 RDAT14 RDAT15 RCA TCA RCP RGFC TCP POP0 POP1 POP2 POP3 POP4 POP5 PIP0 PIP1 PIP2 PIP3 INTB
122 121 116 115 114 113 112 111 164 163 169 102 95 159 160 168 162 161 175 171 170 173 172 167 90 156 155 154 153 157 158
R33
0 1 2 3 4 5 6 7
TP5 T FPOUT
0 1 2 3 4 5 6 7
G
G
POUT<7..0> OOF LOS
3F10< 3C10< 2F1> 2F1>
F
VCC
2
82 77 73
LOF LOS LAIS LRDI LOP PAIS PRDI LCD
2 3 4 5 6 7 8 9 1 19
A1 A2 A3 A4 A5 A6 A7 A8 G1 G2
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8
18 17 16 15 14 13 12 11
220
R22
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
16 15 14 13 12 11 10 9
RES_ARRAY_8
1 2 3 4 5 6 7 8
F
72 139 140 104
3D1> 1F4 1G2> 1G4 1E2>
SCLK TDAT<15..0> TFCLK TSOC TXPRTY0 TXPRTY1 TWRENB
2
74HC541 U10
LED10 U7
RN3 270
1
65 63
E
1F2> 1F2> 1H2> 1E2>
E
60 58 59 61 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 186 190 192 62 2 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 23 24 25 26 31 32 33 34 15 16 17 18 19 20 21 22 14 36 37 38 35 2
S/UNI 622
99 100 181 176 177 75 76 178 182 185 124 87 174 1 188 195 196 197 198 199 200 201 202 203 204 1 2 3 4 5 6 7 8 9 194 67 187 193 68 135 134 133 132 131 130 108 107 106 105 39 1 2 3 4 5 6 7 8 1
330
R7
R39
1
50
GTOCLK TP7 T GROCLK TP6 T RN9 0
16 15 14 13 12 11 10 9
RES_ARRAY_8
1
PLACE AT FAR END D
1C2> 1D2> 1D2>
2
C75 0.01UF
D NOTE: RN7, RN8 RN9 ARE SHORT CIRCUIT ON PCB RSOC RXPRTY0 RXPRTY1
4 0 5 1 6 2 7 3
D<7..0> RRDENB RFCLK
RSOC RXPRTY0 RXPRTY1
NOTE: FOR LAYOUT PURPOSE ONLY
RN7 0
16 15 14 13 12 11 10 9
RES_ARRAY_8
1D10< 2D4 1D10< 2D4 1H10< 2D4
1
R36
50
RDAT<0> RDAT<1> RDAT<2> RDAT<3> RDAT<4> RDAT<5> RDAT<6> RDAT<7>
0 1 2 3 4 5 6 7
4 0 5 1 6 2 7 3
1 2 3 4 5 6 7 8
GND TP8 T
GND TP3 T
GND TP2 T
GND TP1 T
1
1
1
1 2 3 4 5 6 7 8
RES_ARRAY_8
16 15 14 13 12 11 10 9
8 9 10 11 12 13 14 15
2
1D2>
A<7..0> ALE CSB WRB RDB RSTB VCC
1 1K
RDAT<15..0> RCA TCA RN8 0 RCA TCA POP0 POP1 POP2 POP3 POP4 POP5
2C5 1D7 1G7
1
C
C10 0.01UF
RDAT<15..0> RDAT<8> RDAT<9> RDAT<10> RDAT<11> RDAT<12> RDAT<13> RDAT<14> RDAT<15>
C
1E7 1H7
1G10< 2C4
1D10< 2B4 1D10< 2B4 3C10< 3C10< 3C10< 3C10< 3C10< 3C10<
1B2> 1B2> 1B2> 1B2> 1B2>
B
R30
2 70 126 127 71 125
B
NC69 VSS_DC14 VSS_DC13 VSS_DC12 VSS_DC11 VSS_DC10 VSS_DC9 VSS_DC8 VSS_DC7 VSS_DC6 VSS_DC5 VSS_DC4 VSS_DC3 VSS_DC2 VSS_DC1
VSS_AC7 VSS_AC6 VSS_AC5 VSS_AC4 VSS_AC3 VSS_AC2 VSS_AC1
INTB
1D10<
1
1
1
1
1
1
1
C68
2 2
C69
0.1UF 2
C8
0.1UF 2
C12
0.1UF 2
C25
0.1UF 2
C9
0.1UF 2
C13
0.1UF 2
1
C44
0.1UF
VCC
0.1UF
VCC
13 30 78 117 151 184 208 12 29 41 64 79 96 109 118 128 136 166 180 191 207 69 1K 1 2
R14 C50
0.1UF
PMC-Sierra, Inc.
DOCUMENT NUMBER: TITLE: PMC-950860 ISSUE: ISSUE 2 DATE: FEB 14, 1996 PAGE: 2 2 TRUE 1 OF 4 A
1
1
1
1
1
1
C19
0.1UF 2 2
C14
0.1UF 2
C11
0.1UF 2
C56
0.1UF 2
C15
0.1UF 2
C38
0.1UF 2
A
1
0
1 1 1 1 1 1 1 1 2
R44 C43
0.1UF
C65
0.1UF 2 2
C66
0.1UF 2
C72
0.1UF 2
C6
0.1UF 2
C20
0.1UF 2
C29
0.1UF 2
DECOUPLING CAPS FOR SUNI-622 +5V & 74HC541 10 9 8 7 6 5
DRAWING TITLE=SUNI_622_MULTI ABBREV=SUNI622M LAST_MODIFIED=Wed Feb 14 13:33:01 1996 4 3
PM5955-3: S/UNI_622 ATM REE DESIGN WITH MULTIMODE OPTICS P. CHOHAN
ENGINEER:
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
H R27 & R23 PLACE CLOSE TO U5 VSC8110 TXLSCKIN PIN
2
REV
DESCRIPTION
DATE
APPR
H
MUX/DMUX
VCC R23
220
VCC VCC_VT<16..0> VTTL<7..0> VMM_VT<6..0>
VMM
NOTE: PLACE NEAR VSC8110 VMM
330
21
R27
U5 VCC<16..0> VTTL<7..0> VMM<6..0>
1
2
2
2
2
0.1UF
C48 147
147
147
R26
R46
C35 0.01UF
R16
147
C32 0.01UF
R9
1
2
G
4E2> 4E2> 4E2> 4E2>
PIN<7..0> RXOUT<0> RXOUT<1> RXOUT<2> RXOUT<3> RXOUT<4> RXOUT<5> RXOUT<6> RXOUT<7> RXLSCKOUT FP RX50MCK TXDATAOUT_P TXDATAOUT_N TXCLKOUT_P TXCLKOUT_N TXLSCKOUT
35 36 38 39 41 42 44 45 47 48 33 10 11 2 2 13 14 0 1 2 3 4 5 6 7
2G10<
G
1
1
1
RA
2 1
RXDATAIN_P RXDATAIN_N RXCLKIN_P RXCLKIN_N
50 OHM 50 OHM 50 OHM 50 OHM
1
1
2 1
24 25
RXDATAIN_P RXDATAIN_N RXCLKIN_P RXCLKIN_N OOF
0.01UF
0.01UF
2 1
2 2 2 2 2
19 20 22
C24
C26
R45
R42
R40
R11
76
76
76
76
RX
PICLK FPIN C17 0.01UF 2 1 50 OHM 1 50 OHM C16 0.01UF 50 TSD+ TSD-
2G10< 2G10<
1
1
1
1
RA F
2G1>
POUT<7..0> VMM
1
83
TXLSCKIN
TX
TA
2
147
R12
147
C1 0.1UF
2 2
C28 0.01UF
14 7
2
FB
C4 0.01UF
1
2 1 1
1
Y2 P5_0V 0V OUT OUT2
8 1 1
1
R37
VDD_RA L3
0.1UF
1
2
100 1 6 7 8 97 56 57
C87
EQULOOP FACLOOP B<0> B<1> B<2> STS12 REFCLK_P REFCLK_N
VSC8110
_VSCOPNC _VSCIPNC PLLM EXTVCO
32 98
RA 0.01UF
2 1 2
C41
2
RA
76
R4
76
2
2
R3
EXTCLK_P EXTCLK_N
1
330
330
1
30
U3
2 3
R21 2
R1
R2
4
RESET
ECLFP5Q_19_44
16 17 2
_VSCTE
E
2
1
0 1 2 3 4 5 6 7
95 94 92 91 89 88 86 85
TXIN<0> TXIN<1> TXIN<2> TXIN<3> TXIN<4> TXIN<5> TXIN<6> TXIN<7>
2
4C9< 4C9<
R32
50 R17
82
F
E
0
3
1
1
RA
1
DP
Q
7 4 2
R25 0
VMM
MC100ELT21 PLACE INPUT OF ELT21 AS CLOSE TO OSCILLATOR AS POSSIBLE
1
27 R5 U4
1 2 74HC32 3
1
RA
DN VBB
PLACE SERIES TERMINATION AS CLOSE TO THE MC100ELT21 AS POSSIBLE.
5
TCLK SCLK
2H10< 2E10<
D
D
REF_CLK
4E9<
2
2G1> 2B1> 2B1> 2B1> 2B1> 2B1> 2B1>
OOF POP0 POP1 POP2 POP3 POP4 POP5 U1
C
1
74HC04
C
1B2>
RSTB
VMM VDD_RA
1
B
B DECOUPLING CAPS FOR VSC8110 VMM_VT<6..0> C54 0.1UF
2
DRAWING TITLE=SUNI_622_MULTI ABBREV=SUNI622M LAST_MODIFIED=Wed Feb 14 18:21:59 1996
1
1
1
1
1
C7
0.1UF 2 2
C83 0.1UF
2
C78 0.1UF
2
C63 0.1UF
2
C57 0.1UF
2
C59 0.1UF
RA VCC DECOUPLING CAP FOR MC100ELT21
1 1 1 1 1 1 1
1
C85 0.1UF
2
C84 0.1UF
2
C82 0.1UF
2
C81 0.1UF
2
C79 0.1UF
2
C77 0.1UF
2
C60 0.1UF
DECOUPLING CAPS FOR VSC8110 VTTL<7..0>
& 74HC04
PMC-Sierra, Inc.
DOCUMENT NUMBER: TITLE: PMC-950860 ISSUE: ISSUE 2 DATE: FEB 14, 1996 PAGE: 3 2 TRUE 1 OF 4 A
A
2
PM5955-3: S/UNI_622 ATM REF DESIGN WITH MULTIMODE OPTICS P. CHOHAN
ENGINEER: 10 9 8 7 6 5 4 3
10
9
8
7
6
5
4
3
2
1
REVISIONS
ZONE
H
REV
DESCRIPTION
DATE
APPR
H
OPTICAL INTERFACE
G G
SD F
1
VCC C46 0.01UF
2
F L2 FB
1 2 1
1
0.1UF
2 14
2
J1 IS FOR PROTO HFBR-5207 ONLY J1
1
U9
2 5 1
VCCR LCK_REFB NC_5 REF_CLK
18
RA
RA
RA
RA
VEER SD RXDP RXDN CLKP CLKN
15 17 16 4 3 2 2 2 2
3D1>
REF_CLK
2 3
1
+C47 10UF
10K
2
C89
R6
50 OHM 50 OHM 50 OHM 50 OHM TA
2
RXDATAIN_P RXDATAIN_N RXCLKIN_P RXCLKIN_N
3G10< 3G10< 3G10< 3G10<
E
RX
OPTICAL SIGNAL
E
191
R48
191
R47
330
R20
330
R15
330
TX
VCCT
13
TXDP TXDN VEET
10
11 12
1
1
2
2
68.1
68.1
1
1
R43
R41
VCC
1
2
TA C40 0.01UF
1
1
D
VCC L1
1 2 1 1
C39 0.1UF TA RA
2
1
1
R8
PROTO
R24
2
330
HFBR-5207
D
FB +C45 10UF TA
1
C91 0.1UF
2
TA
C
3F1> 3F1>
TSDTSD+
2
50 OHM 50 OHM C
B DRAWING TITLE=SUNI_622_MULTI ABBREV=SUNI622M LAST_MODIFIED=Wed Feb 14 18:20:17 1996 VCC
1
B
C52
0.1UF 2
PMC-Sierra, Inc.
DOCUMENT NUMBER: TITLE: PMC-950860 ISSUE: ISSUE 2 DATE: FEB 14, 1996 PAGE: 4 2 TRUE 1 OF 4 A
A
DECOUPLING CAPS FOR 74HC32
PM5955-3: S/UNI_622 ATM REF DESIGN WITH MULTIMODE OPTICS P. CHOHAN
ENGINEER: 10 9 8 7 6 5 4 3
REYAL_MOTTOB
4 1
5991 0.2.VER SCITPO EDOMITLUM HTIW DR MTA 226-INU/S ARREIS-CMP
RES_DES TOP V C C _ P L A N E
MOTTOB SED_SER REYAL_MOTTOB
34 11
U2
R29
01R
TP3
48C 34R
100 97C 81
+
84R
72R
74C
74R
1L
C17 C16
45C
04C 64C
98C
C24 C26 C35
8R
73R 21R
3R 4R
C32 6R
TP2
J1
30
51 50
31
C60
93C 22R
96C
92C
05C
51C
81R
6C
8C
31C 31R RN6
U7
U10
27C
3NR 91C
02C RN4
1NR
2NR
86C
U13
57C
C22
C76
C31
RN9
RN7
P2 26C
+
Connection Side
59 PMC-SIERRA9 1 90 . 2 . V E R ES C I T P O PE D O M I T L U M UH T I W ID R DM T A T2 2 6 - I N U / S /A R R E I S - C M P M P PMC-SIERRA5S/UNI-622 ATM CRD WITH OMULTIMODE OPTICS REV.2.0 N1995 A R R E I S - C S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995 9 1 0.2.V R S IT O ED MITL M HT W R M A 226-I U S
85C
46C
16C
07C
+
91R
8NR
+
21C
41C
TP8
55C
7C
95C
78C
R1
7R
03R
3U
C41
C4
75C
44R
84C
62R
61R
64R
9R
83C
11C
9C
54R
24R
04R
51R
28C
12R
18C
U5
77C R2
3L
32R
1 87C
38C
35C
94C 32C
+
36C 33R 65C 66C
C52
U1
80
71R 23R 11R 52R 63R
C44
4U
17C
76C
+
14R 42R 02R
1C 82C
19C
2L
54C
+
U9
Y2
5R
C85 01C 52C
TP1 TP5 TP6 TP7
93R
41R
56C
34C
C33
P1
Connection Side
52C FU1.0-PAC
56C FU1.0-PAC
34C FU1.0-PAC 41R K1-ROTSISER
65C FU1.0-PAC
66C FU1.0-PAC
93R 05-ROTSISER
01C FU10.0-PAC
9C FU1.0-PAC
83C FU1.0-PAC 27C FU1.0-PAC
3NR 072-8_YARRA_SER
0-ROTSISER 4 4 R
0 2 2 - R O T S I S E R3 1 R
11C FU1.0-PAC
96C
92C FU1.0-PAC 81R 033-ROTSISER 05C FU1.0-PAC
8C FU1.0-PAC
51C FU1.0-PAC
6C FU1.0-PAC
033-ROTSISER
7R
63R 05-ROTSISER
33R K1-ROTSISER
5R 72-ROTSISER
11R 04R
64R 741-ROTSISER 62R 741-ROTSISER 9R 84C 741-ROTSISER FU1.0-PAC 61R 741-ROTSISER
12R 0-ROTSISER
98C FU1.0-PAC
FU01-LOP ROTICAPAC
BF-ROTCUDNI
72R 033-ROTSISER
36C FU1.0-PAC
32R 022-ROTSISER 48C FU1.0-PAC
32C FU1.0-PAC 35C FU01-LOP ROTICAPAC
01R 341-ROTSISER
+
94C FU1.0-PAC
97C FU1.0-PAC
BF-ROTCUDNI
34R 1.86-ROTSISER
84R 191-ROTSISER 74R 191-ROTSISER
3L
19C FU1.0-PAC
87C FU1.0-PAC 45C FU1.0-PAC
28C FU1.0-PAC 18C FU1.0-PAC 38C FU1.0-PAC
1.86-ROTSISER 1 4 R
FU01-LOP ROTICAPAC
71R
05-ROTSISER
BF-ROTCUDNI
23R
04C FU10.0-PAC
05-ROTSISER
64C FU10.0-PAC
5 2 R 0-ROTSISER
1C FU1.0-PAC 82C FU10.0-PAC
51R 033-ROTSISER
67-ROTSISER
2L
54C 74C
1-12TLE001CM
67-ROTSISER
42R 033-ROTSISER
+
1L
5991 0.2.VER SCITPO EDOMITLUM HTIW DR MTA 226-INU/S ARREIS-CMP
+
FU1.0-PAC 07C 55C
46C FU1.0-PAC
21C FU1.0-PAC 41C FU1.0-PAC
K1-ROTSISER 03R
02C FU1.0-PAC
2-CIOS_23XXX47
7C FU1.0-PAC 3U
24R 54R
67-ROTSISER
8R 033-ROTSISER
67-ROTSISER
6R K01-ROTSISER
75C
95C
78C FU1.0-PAC
FU1.0-PAC
93C FU1.0-PAC
FU1.0-PAC
16C FU1.0-PAC
+
2NR K1-51_YARRA_SER 1NR K1-51_YARRA_SER FU1.0-PAC
77C FU1.0-PAC
FU01-LOP ROTICAPAC
26C
85C
FU01-LOP ROTICAPAC
+
17C FU01-LOP ROTICAPAC 76C FU1.0-PAC
67-ROTSISER 73R 3R 741-ROTSISER 21R 4 R 67-ROTSISER 741-ROTSISER
86C FU1.0-PAC
91C FU1.0-PAC
31C FU1.0-PAC
2 2 R 022-ROTSISER
MOTTOB SED_SER
+
FU01-LOP ROTICAPAC
91R
K1-ROTSISER
8NR 0-8_YARRA_SER 57C FU10.0-PAC 4U 02R 033-ROTSISER
+
RES_DES TOP
U2
R29 RESISTOR-240
C52 CAP-0.1UF
LM317_TO220ABH-2
HFBR5207_PROTO-1
TP3 TST_PT-1
100 1 81 80 U1
C17 CAP-0.01UF C16 CAP-0.01UF
U5
74XXX04_SOIC-2
TP2 TST_PT-1
30 31 50
C60 CAP-0.1UF
U7 LED10-1
U10
74XXX541_SOIC-2
U13
TP8 TST_PT-1
CAPACITOR POL-100UF C22 C76 C31
RN9 RES_ARRAY_8-0
SUNI622-1
CAPACITOR POL-100UF
CAPACITOR POL-100UF
CONN100-1
RN7 RES_ARRAY_8-0
P2
Connection Side
PMC-SIERRA S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995
C41 CAP-0.01UF C 4 CAP-0.01UF
51
C24 CAP-0.01UF C26 CAP-0.01UF C35 CAP-0.01UF C32 CAP-0.01UF
VSC8110-1
R2 RESISTOR-330 ECLFP5Q_19_44-1
Y2
C44 CAP-0.1UF
HEADER_3-1 J1
U9
R1 RESISTOR-330
C85 CAP-0.1UF
TP1 TST_PT-1 TP5 TST_PT-1 TP6 TST_PT-1 TP7 TST_PT-1
RN6 RES_ARRAY_15-1K
RN4 RES_ARRAY_15-1K
C33
CAPACIT OR POL-100 UF
CONN20-1
P1
Connection Side
GND_PLANE
2 1
PMC-SIERRA S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995
MOTTOB KSAM_REDLOS
5991 0.2.VER SCITPO EDOMITLUM HTIW DR MTA 226-INU/S ARREIS-CMP
SOLDER_MASK TOP
PMC-SIERRA S/UNI_622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995
1 A
2
3
4
5
6
7
8
9
10
11
12
REV
1.0 1.0
13
DESCRIPTION
14
REVISIONS
15
DATE
YY 96 96 MM 01 01 DD 16 16
16
APPROVED
A
NCDRILL_FIGURE MECHANICAL DRAWING
B
4.550
Board Material Details
Material # COPPER FR-4 COPPER FR-4 COPPER FR-4 Layer Type CONDUCTOR DIELECTRIC CONDUCTOR DIELECTRIC CONDUCTOR DIELECTRIC CONDUCTOR Etch Name TOP _____ GND_PLANE _____ VCC_PLANE _____ BOTTOM Film type POSITIVE _____ POSITIVE _____ POSITIVE _____ POSITIVE Thickness 1.44 mil 10 mil 2.88 mil 33.4 mil 2.88 mil 10 mil 1.44 mil
Dielectric Constant
B
_____ 4.2 _____ 4.2 _____ 4.2 _____
C
C
D
5.000
ARTWORK FILM
#
COPPER
D
E
TOP LAYER GROUND PLANE VCC PLANE BOTTOM LAYER SILKSCREEN TOP
# Note: 50 ohm controlled impedence traces with trace width of 17 mil are on Top and Bottom layers.
E
F
SILKSCREEN BOTTOM SOLDER MASK TOP SOLDER MASK BOTTOM MECH. DRAWING
Notes: 1. Copper thickness is 2 oz. on vcc_plane & gnd_plane, 1 oz. on all others layers. 2. Total thickness of board shall be 62 mil +/- 7 mil. 3. The outline dimension are specified on this drawing. 4. Material: See board material details above. 5. All holes shall have 1 mil mimimum copper wall thickness.
F
G
G
H
Hole Chart / FIGURE / HOLESIZE / QTY / 15.000-P 22.000-P 25.000-P 237 120 62 17 48 3
DIMENSIONS ARE IN INCHES
6. Dielectric constant: See board material details above. 7. Silk screen shall be screened in monoconductive white based ink. 8. Maximum warp and twist of finished PCB shall not exceed 0.010 in./in. per IPC-D-300. 9. All material comprising the PCB must be recongized by UL to the 94V-0 rating.
H
NC drill origin 0,0
PMC-SIERRA S/UNI-622 ATM REFERENCE DESIGN WITH MULTIMODE OPTICS REV.2.0 1995
J
32.000-P 36.000-P 55.000-P 79.000-P
J
DATE
UNLESS OTHERWISE SPECIFIED
YY DRAWN
MM
DD
S. SIU
96 01 16
PMC-Sierra, Inc.
8501 Commerce Court, Burnaby B.C. Canada, V5A 4A3 Tel: 604 668 7300 Fax: 604 668 7301 SIZE B SCALE FSCM NO NTS DWG NO SHEET
1
4 1
TOLERANCES ON: 2 PL DECIMALS +
K
150.000-P
3 PL DECIMALS +
+/- .03 +/- .005 ENGINEER
APPROVED
CHECKED
K
Note: P = Plated N = Non-Plated
ANGLES + FRACTIONS +
OF
1
L 1 2 3 4 5 6 7 8 9 10 11 12 12 14 15 16
L
MOTTOB NEERCS_KLIS
94C
01R
35C 32C 48C
+ 84R 97C 74R 34R 14R 04C 51R 42R 64C 8R 02R 6R
1L
19C
74C+
36C
87C 45C 71R 23R
52R
3L 38C 18C 28C 77C 84C 3R 4R 21R 73R 64R 1C 82C
12R
54C
04R 11R 54R 24R 95C 78C
61R
9R 62R
2L 98C
5R 3U
92C 81R 05C
33R
8C
4U 93C
6C 51C
96C
01C
66C
52C
65C
56C
34C
41R
8NR
1A 1A 2A 76C 16C + 26C
+
+
5991 0.2.VER SCITPO EDOMITLUM HTIW DR MTA 226-INU/S ARREIS-CMP
+
+
75C
7C
22R 7R 31C 31R 44R 91C 02C 03R 86C 93R 57C
3NR 27C 83C 9C
11C
41C 21C
63R
1NR
2NR
46C 85C
07C
2A 91R
55C
17C
SILK_SCREEN TOP
U2
PMC-SIERRA S/UNI 622 ATM REFERENCE DESIGN WITH MULTIMODE OPTICS REV.1.0 1995
U9 TXGND
1 100
R29 U5
81 80
U1
C17 C16 C24 C26 C35 1 J1 RXGND C85 C60 C32
30 31 51 50
Y2 R2 C41
C4 R1
156
105
GND FPOUT GROCLK GTOCLK
104
C44 U7 U10
157
LOF LOS LAIS LRDI LOP PAIS PRDI LCD
GND C22 C76 C31 RN9
RN6
RN4 U13
208 1 52 53
+
+
+
+ RN7 P2 1
C33 P1 1
S/N
PMC-SIERRA S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995
C52
TOP LAYER
1 1
PMC-SIERRA S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995
RES_DES TOP TOP LAYER
GND_PLANE
MOTTOB SED_SER
12 11
U2
R29
01R
TP3
48C 34R
100 97C 81
+
84R
72R
74C
74R
1L
C17 C16
45C
04C 64C
98C
C24 C26 C35
8R
73R 21R
3R 4R
C32 6R
TP2
J1
30
51 50
31
C60
93C 22R
96C
92C
05C
51C
81R
6C
8C
31C 31R RN6
U7
U10
27C
3NR 91C
02C RN4
1NR
2NR
86C
U13
57C
C22
C76
C31
RN9
RN7
P2 26C
+
Connection Side
59 PMC-SIERRA 9S/UNI-622 ATM TRD WITH IMULTIMODE OPTICS REV.2.0 /1995 R E I S - C M P PMC-SIERRA 1 0 . 2 . V E R S C I P O E D O M T L U M H T I W D R M T A 2 2 6 - I N U S A R PMC-SIERRA S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995 S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995
85C
46C
16C
07C
+
91R
8NR
+
21C
41C
TP8
55C
7C
95C
78C
R1
7R
03R
3U
C41
C4
75C
44R
84C
62R
61R
64R
9R
83C
11C
9C
54R
24R
04R
51R
28C
12R
18C
U5
77C R2
3L
32R
1 87C
38C
35C
94C 32C
+
36C 33R 65C 66C
C52
U1
80
71R 23R 11R 52R 63R
C44
4U
17C
76C
+
14R 42R 02R
1C 82C
19C
2L
54C
+
U9
Y2
5R
C85 01C 52C
TP1 TP5 TP6 TP7
93R
41R
56C
34C
C33
P1
Connection Side
VCC_PLANE
3 1
PMC-SIERRA S/UNI-622 ATM RD WITH MULTIMODE OPTICS REV.2.0 1995
PMC-Sierra, Inc. REFERENCE DESIGN
ISSUE 3
PM5355 S/UNI-622
S/UNI-622 Multimode Optics Reference Design
NOTES Contact us for applications support: FAX: PHONE: Email: Website: (604) 415-6206 (604) 415-6000 apps@pmc-sierra.bc.ca http://www.pmc-sierra.com
______________________________________________________________________________________________
Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of third-party rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1996 PMC-Sierra, Inc. PMC-950860(R3) Issue date: October 11, 1996.
23

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