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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
PM7364 FREEDM FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Issue 1: February, 1997
PMC-Sierra, Inc. 105 - 8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415 6000
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
CONTENTS OVERVIEW .......................................................................................................... 3 Design Objectives ......................................................................................... 4 Known Design Constraints ........................................................................... 4 Assumptions ................................................................................................. 5 CALCULATION OF PCI BUS CYCLES ................................................................ 7 Transmit Packets .......................................................................................... 7 Receive Packets ........................................................................................... 8 Interrupt Service Overhead .......................................................................... 9 Average Number of Cycles Per Packet ........................................................ 10 BUS UTILIZATION .............................................................................................. 11 Utilization With Maximum Bus Efficiency...................................................... 11 Bus Access Prioritization .............................................................................. 12 Receive Prioritization .................................................................................... 12 Transmit Prioritization ................................................................................... 13 Avoiding Receive Overrun ............................................................................ 14 Avoiding Transmit Underrun ......................................................................... 14 BUS LATENCY .................................................................................................... 15 Maximum Tolerable Channel Latency .......................................................... 15 Calculating Bus Latency ............................................................................... 16 Priority Receive Channel......................................................................... 16 Expedited Transmit Channel ................................................................... 17 Receive Channel ..................................................................................... 18 Transmit Channel .................................................................................... 19 PCI PEFORMANCE FOR TYPICAL APPLICATIONS ........................................ 21 High Speed Serial Interface (HSSI) .............................................................. 21 Unchannelized E1......................................................................................... 23 Unchannelized T1 ......................................................................................... 25 64 Kbps Channelized E1 or T1..................................................................... 27 384 Kbps Channelized T1 ............................................................................ 30 Combining Unchannelized E1 with 64Kbps Channelized E1 ....................... 32 CONCLUSIONS AND RECOMMENDATIONS ................................................... 36
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
REFERENCES .................................................................................................... 37 CONTACTING PMC-SIERRA ............................................................................. 38
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
OVERVIEW The FREEDM provides HDLC processing of up to 32 bi-directional serial links in Frame Relay, PPP and FUNI applications. It interfaces directly to a host via a 32 bit PCI local bus interface [1], across which data is read or written by the FREEDM's DMA controller. The bus allows for the transfer of data between the host RAM and the FREEDM, at a high rate, without intervention by the host CPU. Figure 1. System Block Diagram Showing the Data Path
PM7364 FREEDM HDLC PROCESSOR AND CHANNEL ASSIGNER Rx/Tx Data PCI DMA CONTROLLER PCI BUS PCI -TO-HOST BUS BRIDGE HOST
Tx 32 bi-directional serial links Rx
HOST BUS OTHER FREEDM OR PCI BUS DEVICE(S) RAM PCI BUS
CPU
The flow of data is shown for a typical system in Figure 1. The receive data from a serial link is mapped to one or more HDLC channels by the Receive Channel Assigner (RCAS). Each channel is independently processed, and packet data of a channel is stored in a Channel FIFO. When the level within the buffer reaches a user defined limit, the data is burst written, by the Receive DMA Controller (RMAC), across the PCI bus. Upon completion of a packet the FREEDM notifies the host CPU by placing a reference to the packet in the RPDR Ready Queue, by setting the third byte of the RPDR to zero, and optionally by interrupt. The CPU host must replenish the RPDR Small Free Queue, and the RPDR Large Free Queue, which identifies available host RAM addresses where the FREEDM may write the receive data. An overrun condition occurs when data from the serial data link must be written to a Receive Channel FIFO, but the Receive Channel FIFO is full. This condition can be caused by excessively long bus access latency, bandwidth starvation as the result of the FREEDM serving other channels, or insufficient replenishment of the RPDR Small (or Large) Free Queue.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The host CPU prepares transmit packets in host RAM and places a reference to each packet in the TDR Ready Queue. After the FREEDM is signaled that this queue is no longer empty, the Transmit DMA Controller (TMAC) burst reads the packet data across the bus and deposits this data into the Transmit Channel FIFO. The Transmit HDLC Processor (THDL) performs HDLC processing of the data and the Transmit Channel Assigner (TCAS) maps the data to one of the 32 transmit serial links. The FREEDM returns the packet reference to the TDR Free Queue allowing the host CPU to confirm the transmission and reuse the descriptor memory for subsequent packets. An underrun condition may occur during transmit of a packet, when data must be driven on the serial link but the Transmit Channel FIFO is empty. In this case, the FREEDM was unable to read data across the bus in time. This condition can be created by excessively long bus access latency, or bandwidth starvation as the result of FREEDM serving other channels. Design Objectives A system design will typically be optimized for one or more of the following criterion, all of which are affected by the PCI bus utilization of a FREEDM: * To maximize the PCI bus efficiency. Thus allowing the FREEDM to be configured with the highest number of channels, and/or the highest data rate on each channel. Also, the designer may choose to integrate multiple FREEDM's on the same PCI bus. * To avoid receive overrun. * To avoid transmit underrun. * To minimize the bus latency in either the receive or transmit direction. * To ensure the system performs at the aggregate link rate, and no bandwidth on the serial links is lost. The purpose of this application note is to outline the factors which affect PCI bus utilization and thereby to provide enough information for a designer to estimate the most optimal configuration of the FREEDM for the intended application. The calculations of PCI bus performance which are presented here are believed to be accurate although the actual bus performance may differ. The objectives are to define limits of performance and to provide insight into optimizing the configuration of a FREEDM for the application. Known Design Constraints There are a number of known design constraints which limit the configuration of a FREEDM. Namely the serial links must comply with the FREEDM longform datasheet[2]. The datasheet states the following characteristics:
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
*
The FREEDM supports a single bi-directional HDLC channel on an unchannelized arbitrary rate link of up to 45 MHz when SYSCLK is at 25MHz, and up to 52 MHz when SYSCLK is at 33 MHz. The FREEDM supports up to 32 bi-directional HDLC channels, each assigned to an unchannelized arbitrary rate link of up to 10 MHz. The FREEDM supports up to 128 bi-directional HDLC channels assigned from a maximum of 32 channelised T1 or E1 links, 32 unchannelized links, or a combination of these. The FREEDM supports up to 128 bi-directional channels assigned to a maximum of 32 channelised T1 or E1 links. The number of time-slots assigned to an HDLC channel is programmable from 1 to 24 (for T1) and from 1 to 31 (for E1). The FREEDM supports a mix of channelised and unchannelised links, subject to the constraint of a maximum of 128 channels, and a maximum aggregate link clock rate of 64 MHz in each direction. The FREEDM interfaces directly to a PCI local bus which is revision 2.1 compliant, and has a 32 bit data path. This places a limit on the maximum number of FREEDM devices interfaced to a PCI bus and on the aggregate data rate of all the serial links which can be handled by the bus.
* *
*
*
*
Assumptions The bus performance is affected by the system design choices made in integrating the FREEDM with an embedded host. The following list of design choices are important: * * * * * RAM access time and contention PCI bus clock speed PCI bridge design and arbitration algorithm System software running on the host CPU, and the processing capability of the CPU Other PCI devices on the PCI bus
A thorough discussion of these choices are outside the scope of this document, and for the purposes of this analysis the following list of assumptions are made. Additional assumptions are stated in this document when encountered. * The PCI bus Latency Timer is set large enough such that none of the transactions are broken.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
* * * * *
The host RAM is always available when required. The PCI bus does not disconnect the FREEDM from accessing the host RAM. The host CPU has enough processing power that it will not be a bottleneck. The bridge uses a fair round-robin arbitration algorithm to grant PCI devices access to the bus. There are one or more FREEDM devices and the host CPU which utilize bus cycles. No other PCI devices are present. The serial link is fully satured with HDLC data, and there is only one flag byte between frames. The data bit rate of the serial link is the same as the clock rate of the serial link. FCS fields are not DMA'd across the PCI bus. The packet length used in the calculations does not include the FCS bytes. The FCS can be optionally dropped in the receive direction and are not DMA'd across the PCI bus in the transmit direction. The effective data rate of a serial link or channel used in the analysis does not account for bit stuffing, bit destuffing and the overhead associated with T1/E1/T3 framing which normally occurs. This overhead is not DMA'd across the PCI bus.
*
*
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
CALCULATION OF PCI BUS CYCLES There are four PCI bus transactions that are used to transfer data between the FREEDM, the host RAM and the host CPU. The PCI bus utilization during transmit and receive of packets is composed entirely of these four transactions, which are defined in the longform datasheet[2]: * Burst read from host RAM: This PCI read transaction has 3 + D + r bus cycles. These cycles consist of an address cycle, bus turn around cycle, RAM access latency cycles, data cycles, and a final bus turn around cycle. Burst write to host RAM: This PCI write transaction has 2 + D + w bus cycles. These cycles consist of an address cycle, data cycles, RAM access latency cycles, and a final bus turn around cycle. Read FREEDM register: This PCI read transaction has 7 bus cycles (for PCICLK=SYSCLK= 33MHz). This value is based on simulation of the FREEDM and is expected to increase with a slower SYSCLK. Write FREEDM register: This PCI write transaction has 7 bus cycles (for PCICLK=SYSCLK= 33MHz). This value is based on simulation of the FREEDM and is expected to increase with a slower SYSCLK.
*
*
*
Here D is the data size in DWORDs (32 bits), r is the read latency cycles, and w is the write latency cycles. The latency cycles are inherent to the host RAM, the bridge, the host CPU, and the system software. This analysis assumes that none of the bus masters are disconnected, and that transactions complete without being stopped. Transmit Packets For this analysis it is assumed that the transmit packets are composed of a single descriptor or buffer. Linking of multiple descriptors to form a packet involves additional overhead activity on the PCI bus. For a transmit packet the following bus transactions are required on a per packet basis: * Host writes packets to transmit ready queue in blocks of up to B references, thereby writing the TMAC Descriptor Reference Ready Queue Write register every B 'th reference, and reading the TMAC Descriptor Reference Ready Queue Read register approximately every Q'th reference. Here Q is the size of the queue and B is number of references in the block. This activity has approximately 7 B + 7 Q bus cycles per packet. FREEDM reads one reference from the transmit ready queue. This activity has 3 + 1 + r bus cycles per packet.
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*
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
*
FREEDM reads 3 DWORD's of transmit descriptor to determine the TCC (transmit channel code) as well as other information. This activity has 3 + 3 + r bus cycles per packet. FREEDM chains the reference to the current list of references by writing 2 DWORDS into the transmit descriptor. This activity has 2 + 2 + w bus cycles per packet. FREEDM reads 4 DWORDs of the transmit descriptor. This activity has 3 + 4 + r bus cycles per descriptor. FREEDM writes the reference to transmit free queue. If the CACHE bit is enabled within the TMAC Control register then this activity is completed once every 6 references, and has (2 + w + 6) 6 bus cycles per descriptor. Host reads references from the transmit free queue in blocks of up to B references, thereby writing the TMAC Descriptor Reference Free Queue Read register approximately every B 'th reference, and reading the TMAC Descriptor Reference Free Queue Write register every Q'th reference. Here Q is the size of the queue and B is number of references in the block. This activity has approximately 7 B + 7 Q bus cycles. FREEDM reads the transmit descriptor buffer. This may require multiple burst read transactions since the FREEDM can only DMA XFER blocks of data per transaction. This activity has P 4 + (3 + r ) P (16 X ) bus cycles.1 Here P is the packet length in bytes, and X is the XFER size in 16 byte blocks.
*
* *
*
*
Receive Packets For this analysis it is assumed that the receive packets are composed of a single descriptor or buffer. Linking of multiple descriptors to form a packet involves additional overhead activity on the PCI bus.
1The Roof function outputs an integer value, whereby a non-zero remainder receives the value 1. For
example the Roof Function output of 3.
3.03 gives an output of 4, whereas the Roof Function 3.00 gives an
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
For a receive packet the following bus transactions are required on a per packet basis: * Host writes references to receive free queue in blocks of up to B references, thereby writing the RMAC Packet Descriptor Reference Small Buffer Free Queue Write register aproximately every B 'th reference, and reading the RMAC Packet Descriptor Reference Small Buffer Free Queue Read register every Q'th reference. Here Q is the size of the queue and B is number of references in the block. This activity has 7 B + 7 Q bus cycles per packet. FREEDM writes reference to receive ready queue. This activity has 2 + 1 + w bus cycles per packet. Host reads references from receive ready queue in blocks of up to B references, thereby writing RMAC Packet Descriptor Reference Ready Queue Read register aproximately every B 'th reference queued, and reading the R M A C Packet Descriptor Reference Ready Queue Write register every Q'th reference. Here Q is the size of the queue and B is number of references in the block. This PCI transaction has 7 B + 7 Q bus cycles. FREEDM writes 2 DWORDs of receive descriptor. This activity has 2 + 2 + w bus cycles. FREEDM reads 4 DWORDs of receive descriptor. This activity has 3 + 4 + r bus cycles. FREEDM writes to the receive descriptor buffer. This may require multiple burst write transactions since the FREEDM can only DMA XFER blocks of data per transaction. This PCI transaction has P 4 + (2 + w ) P (16 X ) bus cycles. Here P is the packet length in bytes, and X is the XFER size in 16 byte blocks. FREEDM reads references from the receive small buffer queue. The SCACHE bit of the RMAC Control register is set such that 6 free references are read from the queue every 6'th reference. This PCI transaction has (3 + r + 6) 6 bus cycles.
* *
* * *
*
Interrupt Service Overhead It is assumed that bus cycles due to interrupt servicing are negligable in comparison to the number and size of packets DMA'd on the bus. This assumption is ensured by programming the FREEDM to interrupt the host less frequently than with every packet or descriptor processed by the FREEDM. This is done via the LCACHE, SCACHE, RPQ_RDYN, RPQ_LFN and RPQ_SFN bits within the RMAC Control register and via the CACHE, TDQ_RDYN and TDQ_FRN bits of the TMAC Control register.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
It is assumed that the interrupt service routine processes each interrupt by reading/clearing the Master Interrupt Status register, and then storing the status within the software for deferred processing. The bus cycles due to interrupt servicing is assumed negligable compared to the other PCI bus activity. Average Number of Cycles Per Packet For a receive packet the average number of bus cycles to write the receive data into host RAM is derived by summation of all activities described in the previous section on receive packets. The bus cycles per byte of packet received is expressed as CRx Byte = 1 1 P 1 P + 1.17 r + 2 w 15.5 + 14 + + + (2 + w ) B Q 4 P X 16
For a transmit packet the average number of bus cycles to read the transmit data from host RAM is derived by summation of all activities described in the previous section on transmit packets. The bus cycles per byte of transmit packet is expressed as CTx Byte = 1 1 P 1 P + 3 r + 1.17 w 22.33 + 14 + + + (3 + r ) B Q 4 P X 16
The total cycles to transmit and receive one byte of packet data is expressed as CByte = 1 1 1 P P + 4.17 r + 3.17 w 37.83 + 28 + + 2 + (5 + r + w ) B Q P 4 X 16
where P is the packet length in bytes, and X is the XFER size in blocks, Q is the size of each queue, B is number of queued references accessed by the host CPU at a time, r is the read latency cycles, and w is the write latency cycles. These equations are derived under the assumption that PCI bus activitiy due to interrupts, provisioning/unprovisioning of channels, and performance counter polling is negligable.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
BUS UTILIZATION Bus utilization is defined as the ratio of the number of clock cycles that transfer data to the number of cycles that is available to transfer data during a time interval. The traffic on the PCI bus due to the FREEDM is bursty by nature, and the time interval must be sufficiently large. If too small a time interval is choosen, and the time interval being measured occurs when there is much traffic on the bus, the measured bus utilization could be higher than the long term average. Alternatively, if the measurement interval is choosen when there is little traffic on the bus the measured utilization could be much lower than the long term average. Utilization With Maximum Bus Efficiency The best estimate for measuring bus utilization is obtained by using the longest time interval to make the measurement. This is expressed mathematically as the average bus utilization, and is derived below. The average number of bus cycles required to transmit and receive is a function of the data rate for each channel provisioned on a FREEDM. It is expressed as follows, Bus Cycles =
Channel
(C
Byte
f Channel 8
)
where f Channel is the channel data rate in bits per second and CByte is the average number of cycles to DMA one transmit and one receive byte on that channel . The number of PCI bus cycles available during the one second interval is f PCI , the PCI bus clock frequency. The PCI bus utilization, expressed as the ratio of these is U= 1 CByte f Channel 8 f PCI Channel
(
)
where CByte was derived in the previous section. This expresses the PCI bus utilization due to a bi-directional serial link with channel rate specified in bits per second. The total bus utilization for multiple FREEDM devices on a bus is obtained by the summation over all provisioned channels, and on all FREEDM devices connected to the bus. Configuration of the FREEDM channels and serial ports such that the average utilization does not exceed 1 (or 100%), based on this equation, does not guarantee the avoidance of underrun or overrun. These can only be guaranteed by ensuring each Channel FIFO is large enough to tolerate the bus latencies. This problem will be examined in a later section with calculations of bus latency.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Bus Access Prioritization Overutilization of the bus may cause receive channel overrun or transmit channel underrun. The channels that are affected would depend on their prioritization in relation to all the other provisioned channels, and any other activities on the bus. The following list identifies the prioritization of transactions on the PCI bus(1 = highest priority). 1) PCI bus interrupt acknowledge cycles due to PCI bus interrupts may occur on some systems with ISA bus bridges. These are assumed not to occur in this analysis and will not be discussed further. 2) Host CPU accesses to the FREEDM Master Interrupt Status register 3) Host CPU accesses to any of the FREEDM queue write (or read) index registers 4) FREEDM accesses to queue references, descriptors and buffers as required to transfer packets between the FREEDM and the host RAM. In the case of multiple FREEDM's on the same bus, the host bridge would dictate whether each FREEDM is granted access in a round-robin basis. Receive Prioritization Receive transactions of a FREEDM differ in priority as follows (1 = highest priority): 1) FREEDM accesses to the RPDRF Large Queue, or the RPDRF Small Queue. This transaction occurs whenever the internal cache of free buffers needs to be replenished. 2) Transactions for priority receive channels. These are provisioned channels with the PRIORITY bit set within the RHDL Indirect Channel Data #2 register. 3) Transactions for remaining receive channels. Each receive channel of the same priority is polled in a round robin basis for access to the bus, but there are two sequences of bus transactions that are atomic (ie each sequence of transactions cannot be pre-empted by receive transactions of another channel, although successive read-read or write-write transactions can be preempted by transmit transactions). The sequences are: Start of Packet Sequence * FREEDM reads upto 6 references from the Receive Packet Descriptor Reference Small Free Queue (or the Receive Packet Descriptor Reference Large Free Queue). This transaction only occurs once every sixth start of packet sequence. FREEDM reads 4 DWORD's of descriptor.
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*
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
*
FREEDM writes receive data into buffer of the descriptor.
End of Packet Sequence * FREEDM writes final bytes of a packet to the receive buffer. This transaction writes upto XFER bytes to host RAM, where XFER is the maximum number of Channel FIFO blocks that is written per transaction, and is specified on provisioning of a channel. FREEDM writes 2 DWORDs of receive descriptor. FREEDM writes a receive packet reference to the Receive Packet Descriptor Reference Ready Queue.
* *
Transmit Prioritization Transmit transactions of a FREEDM differ in priority as follows (1= highest priority): 1) FREEDM accesses to the Transmit Packet Descriptor Reference Free Queue. This transaction occurs if the internal cache of transmit references has reached the cache size limit of 6, assuming the CACHE bit of the TMAC Control register is set. 2) FREEDM accesses host RAM for a transmit channel which is not inhibited and where the Channel FIFO has reached the expedite level. These are provisioned channels with the PRIORITYB=0 within the THDL Indirect Channel Data #2 register. 3) FREEDM accesses to the Transmit Packet Descriptor Reference Ready Queue and linking of each transmit descriptor read. These transactions occur if the host has written transmit packet references into the queue, so that this queue is not empty. 4) FREEDM accesses packet data, descriptors, and queue references for any transmit channel which has enough space in it's Channel FIFO for the remaining bytes of a packet or the XFER size. Each transmit channel is polled in a round robin basis for access to the bus, but there are two sequences of bus transactions that are atomic (ie each sequence of transactions cannot be pre-empted by transmit transactions of another channel, although successive read-read or write-write transactions can be pre-empted by receive transactions). The sequences are: Chain Packets of TDR Ready Queue Sequence * * FREEDM reads transmit reference from TDR Ready Queue. FREEDM reads 3 DWORD's of the transmit descriptor.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
*
FREEDM writes 2 DWORDs of another transmit descriptor to link packets of a channel.
End of Packet Sequence * FREEDM reads final bytes of a packet from the transmit buffer. This transaction reads upto XFER bytes from host RAM, where XFER is the maximum number of Channel FIFO blocks that is read per transaction, and is specified on provisioning of the transmit channel. FREEDM writes 6 transmit references to the Transmit Descriptor Free Queue if the cache of free references has reached 6. FREEDM reads 4 DWORDs of transmit descriptor of the following packet.
* *
Avoiding Receive Overrun In systems in which there are multiple channel rates, the metric f Channel F can be used to evaluate which channels should have higher priority. The variable f Channel is the data rate of the channel and F is the number of partial packet buffer blocks which are provisioned for the channel. Channels with a higher value of this metric could be provisioned with the PRIORITY bit set within the RHDL Indirect Channel Data #2 register. Avoiding Transmit Underrun In systems in which there are multiple transmit channel rates the metric f Channel F can be used to evaluate which channels should have higher priority access to the bus. The variable f Channel is the data rate of the channel and F is the number of Channel FIFO blocks which are provisioned for the channel. Channels with a higher value of this metric should be provisioned with the PRIORITYB bit reset within the THDL Indirect Channel Data #2 register. This will ensure that the bus access latency is reduced for channels where the Channel FIFO has reached the expedite level.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
BUS LATENCY The bus latency is a measure of the time interval beginning when a channel requires access to the bus and ending when access has been granted, or when the DMA transaction is completed. The worst case latency for data transfers to/from host RAM is analyzed here. The bus latency calculation is used to determine the possibility of underrun or overrun. Maximum Tolerable Channel Latency The Channel FIFO of each channel must be serviced at least once within a time interval to prevent the occurance of an overrun, or underrun. This time interval is the channel latency, given by LChannel . For a receive channel, the time interval is measured from when the receive channel has filled XFER blocks of its Channel FIFO. The interval ends when the channel has been given access to the bus, or in the worst case, when the Channel FIFO is full. For a transmit channel, the time interval is measured from when the Channel FIFO has reached the start, or expedite level. The interval ends when the channel has read XFER blocks of data across the bus, or in the worst case, when the Channel FIFO is empty. The equations which specify the channel latency are: LChannel = LChannel = LChannel = 128 ( F - X ) f Channel for receive channel, PRIORITY = 0 or 1
128 ( F - S ) 3 + 4 X + r - for transmit channel, PRIORITYB = 1 f Channel f PCI 128 ( F + E - 2 S ) 3 + 4 X + r - f Channel f PCI for transmit channel, PRIORITYB = 0
where F is the Channel FIFO size specified in blocks, X is the channel XFER size specified in blocks, S is the start transmit level specified in free blocks, E is the expedite DMA level specified in free blocks, and f Channel is the channel rate specified in bits per second. The start transmit level and the expedite transmit level are configured by the TRANS bit and the LEVEL[3:0] bits within the THDL Indirect Channel Data #3 register as described in the longform datasheet[2].
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
To prevent an underrun or overrun condition that is caused by bus activity from other channels or the host, the bus latency must be less than the channel latency. This is expressed as LPCI < LChannel
where LPCI is the worst case PCI bus latency due to activity from other channels, or the host on the bus. Calculating Bus Latency The PCI bus latency is estimated as LPCI = 1 f PCI
Channel
C
Transaction
where CTransaction is the maximum bus cycles utilized by a channel. The summation is performed over provisioned channels of the FREEDM that have equal or higher priority access to the PCI bus than the channel being evaluated for underrun or overrun. Utilization of bus cycles by the host is assumed negligable. The following sections provide equations for a variety of channel configurations. Priority Receive Channel This section provides an estimate of bus latency for a priority receive channel. This is a receive channel for which the PRIORITY bit is set. The bus access latency is due to all other priority receive channels, and transmit channels. Each priority receive channel is granted access in a round robin algorithm and utilization of the bus by the host CPU to access FREEDM registers is assumed negligable. The time interval is measured starting from when the channel requires bus access and ending when the bus access has been granted. The time to DMA XFER blocks of data across the bus is not required for this calculation as the FREEDM double buffers the XFER blocks of data before granting access to the bus. The bus access latency is due to: * * * completion of the current PCI transaction, which in the worst case is the receive channel start of packet sequence and involves caching of 6 free references. completion of the end-of-packet sequence on all the other priority receive channels, and pre-emption of each sequence by transmit channel transactions. DMA of XFER blocks of transmit packet data between each of the receive channel transactions.
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PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The equation which estimates the worst case bus latency is: LPCI 1 f PCI 24 + 12 X + w + 4 r + (18 + 12 XTx + 4 XRx + 3 w + 3 r ) Other Pr iority Rx
where X Rx is the XFER blocks of other priority receive channels, XTx is the largest XFER blocks of a provisioned transmit channel, X is the largest channel XFER size of a provisioned transmit or receive channel, r is the read latency cycles, and w is the write latency cycles. The summation is performed over all other priority receive channels of the same FREEDM. Expedited Transmit Channel This section provides an estimate of bus latency for an expedited transmit channel. This is a transmit channel for which the PRIORITYB bit is zero, the Channel FIFO contains less than one packet of data, and the expedite level has been reached. The bus access latency is due to all other expedited transmit channels and receive channels. Each expedited transmit channel is granted access in a round robin algorithm and utilization of the bus by the host CPU to access FREEDM registers is assumed negligable. The time interval is measured starting from when the channel requires bus access and ending when the XFER blocks of data has been transfered across the bus. The bus access latency is due to: * completion of the current PCI transaction, which in the worst case is a transmit channel end-of-packet sequence, and the channel was provisioned with PRIORITYB=1. completion of the end-of-packet sequence on all the other transmit channels for which PRIORITYB=0. DMA of XFER blocks of receive packet data between each of the transmit channel transactions.
* *
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PMC-Sierra, Inc. APPLICATION NOTE
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PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The equation for this estimate is LPCI 1 f PCI 1 20 + 8 X + 2 (r + w ) + (8 + w ) Channel - 5 6 Expedited Tx +
Expedited Tx Channel
(12 + 4 X
Rx
+ 4 XTx + 2 r + w )
where X Rx is the largest value of XFER blocks of a receive channel, XTx is the XFER blocks of an expedited transmit channel, r is the read latency cycles, and w is the write latency cycles. The summation is performed over all expedited transmit channels. Receive Channel This section provides an estimate of bus latency for a FREEDM configuration in which the receive channel has PRIORITY = 0. The worst case bus latency is due to activity from all other receive and transmit channels. The host accesses to FREEDM registers are assumed negligable. The time interval is measured starting from when the channel requires bus access and ending when the bus access has been granted. The time to DMA XFER blocks of data across the bus is not required for this calculation as the FREEDM double buffers the XFER blocks of data before granting access to the bus. The bus access latency is due to: * * * completion of the current PCI transaction, which in the worst case is a transmit channel transaction involving DMA of XFER blocks of packet data. completion of the start-of-packet sequence on all the other receive channels, and pre-emption of these transactions by transmit channel transactions. DMA of XFER blocks of transmit packet data between each of the receive channel transactions.
18
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The equation which estimates the worst case bus latency is: LPCI = 1 f PCI 1 f 3 + 4 XTx + r + ( 4 XTx + 12 + 2 r ) Channel 6 f Channel Other Rx + 1 f Channel
Other Rx
f
Channel
(15 + 8 XTx + 4 X Rx + w + 3 r )
where X Rx is the XFER blocks of other receive channels, XTx is the largest XFER blocks of a provisioned transmit channel, r is the read latency cycles, and w is the write latency cycles. The summation is performed over all other receive channels. Transmit Channel This section provides an estimate of bus latency for a FREEDM configuration in which the transmit channel is not in an expedited state, due to PRIORITYB=1 or the Channel FIFO not having reached the expedite level. The worst case bus latency is due to activity from all receive and transmit channels. The host accesses to FREEDM registers are assumed negligable. The time interval is measured starting from when the channel requires bus access and ending when the XFER blocks of data has been transfered across the bus. The bus access latency is due to: * * * chaining and linking of packets read by the FREEDM from the TDR ready queue. end-of-packet processing on all transmit channels. DMA of XFER blocks of receive packet data between all of the transmit channel transactions.
19
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The equation for this estimate is LPCI 1 f PCI + 1 f (10 + 4 X Rx + 2 w ) Channel 6 f Channel Tx Channel 1 f Channel N f PCI
Channel Tx Channel
f
(14 + 4 XTx + 8 X Rx + 2 r + 2 w )
+
(20 + 12 X Rx + 2 r + 4 w )
where X Rx is the largest XFER blocks of a receive channel, XTx is the XFER blocks of a transmit channel, N is the number of references in the TDR ready queue, r is the read latency cycles, and w is the write latency cycles. The summation is calculated over all transmit channels provisioned. Note: The software running on the host must ensure that there are few transmit references in the ready queue, otherwise the value of N would be large, and the bus latency would also be large.
20
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
PCI PEFORMANCE FOR TYPICAL APPLICATIONS High Speed Serial Interface (HSSI) HSSI is a 52 Mbps link that must be physically connected to either port 0, 1 or 2 of a FREEDM device. Only one bi-directional HSSI link is attached, thereby ensuring the maximum aggregate link rate of 64 MHz is not exceeded. The designer could choose to use multiple FREEDM devices on a PCI bus where more than one HSSI link is required. Only one channel of each FREEDM is provisioned. The estimates for the HSSI application are based on the following configuration: Configurable Parameter F X S E Q B N f PCI f Channel PRIORITY PRIORITYB Value 512 blocks 8 blocks 256 blocks 384 blocks 32 6 32 33 MHz 52 MHz X X Description size of buffer assigned to channel DMA transfer size for transmit and receive transmit start level of buffer (free blocks) transmit expedite level of buffer (free blocks) size of each queue number of references accessed at a time by the host software maximum references in TDR ready queue PCI bus clock frequency Channel data rate receive channel priority not relevant transmit channel priority not relevant
The average PCI bus utilization for one HSSI is shown in figure 3 as a function of the packet length. Two of the curves are for zero RAM latency, the third includes RAM latency with a ratio of 1:7 for read and write latency. The figure shows that utilization improves with B - the number of references cached in software before being read from, or written to, a FREEDM queue.
21
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The PCI bus utilization is strongly dependant on the packet length. For small packets the utilization increases dramatically. Figure 3. Utilization of a FREEDM With One HSSI link
0.65 0.55 Utilization 0.45 0.35 0.25 0.15 0.05 128 256 512 1024 2048 4096 8192 32 64 16384
B=1, Q=32 B=6, Q=32 B=6, Q=32, 1:7 RAM latency
32768
Packet Length (bytes)
The utilization graph indicates that multiple FREEDM devices, each with one HSSI channel, could be handled on a PCI bus. It also indicates that the system design (ie the number of references accessed at a time by the host software, the average packet length, and the host RAM latency) plays a major role in determining exactly how many HSSI channels, or FREEDM devices, can be supported. Table 1 below shows the maximum tolerable channel latencies and the worst case PCI bus latencies, assuming zero RAM latency. Since the worst case PCI bus latencies are less than the tolerable channel latencies the graph of figure 3 should be used to estimate the number of FREEDM's supported on a PCI bus.
22
65535
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Table 1. Latency Estimates For HSSI FREEDM's on bus receive LChannel (msec) transmit LChannel (msec) receive LPCI (msec) transmit LPCI (msec) 1 1.24 0.94 0.001 0.1 2 1.24 0.94 0.0058 0.12 0.0074 3 1.24 0.94 0.0091 0.13 0.0097 4 1.24 0.94 0.013 0.13 0.012 8 1.24 0.94 0.027 0.14 0.021
expedited transmit LPCI (msec) 0.005 Unchannelized E1
Up to 32 unchannelized E1 links may be physically connected to a FREEDM device. In this case there are 32 FREEDM channels provisioned. The estimates for the Unchannelized E1 application are based on the following configuration: Configurable Parameter F X S E Q B N f PCI f Channel PRIORITY Value 16 blocks 4 blocks 4 blocks 8 blocks 64 6 32 33 MHz 2.048 Mbps 0
23
Description size of buffer assigned to channel DMA transfer size for transmit and receive transmit start level of buffer (free blocks) transmit expedite level of buffer (free blocks) size of each queue number of references accessed at a time by the host software maximum references in TDR ready queue PCI bus clock frequency Channel data rate receive channel is not high priority
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
PRIORITYB
0
transmit channel is not inhibited
The average PCI bus utilization for one FREEDM is shown in figure 4 as a function of the packet length. Two of the curves are for zero RAM latency, the third includes RAM latency with a ratio of 1:7 for read and write latency states. The figure shows that utilization improves with B - the number of references cached in software before being read from, or written to, a FREEDM queue. The PCI bus utilization is strongly dependant on the packet length. For small packets the utilization increases dramatically. Figure 4. Utilization of a FREEDM With 32 Unchannelized E1 Links
0.75 0.65 Utilization 0.55 0.45 0.35 0.25 0.15 0.05 128 256 512 32 64 1024 2048 4096 8192 16384
B=1 B=6 B=6, 1:7 RAM latency
32768
Packet Length (bytes)
The utilization graph indicates that multiple FREEDM devices, each with 32 E1 channels, could be handled on a PCI bus. It also indicates that the system design (ie the number of references accessed at a time by the host software, the average packet length, and the host RAM latency) plays a major role in determining exactly how many FREEDM devices can be supported.
24
65535
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Table 2 below shows the maximum tolerable channel latencies and the worst case PCI bus latencies, assuming zero RAM latency. Since the worst case PCI bus latencies are less than the tolerable channel latencies the average utilization should be used to determine how many FREEDM devices can be supported. Table 2. Latency Estimates With 32 E1 Channels Per FREEDM FREEDM's on bus receive LChannel (msec) transmit LChannel (msec) receive LPCI (msec) transmit LPCI (msec) 1 0.75 1.0 0.065 0.13 2 0.75 1.0 0.13 0.19 0.087 3 0.75 1.0 0.20 0.26 0.13 4 0.75 1.0 0.26 0.32 0.17 8 0.75 1.0 0.52 0.58 0.34
expedited transmit LPCI (msec) 0.044 Unchannelized T1
Up to 32 unchannelized T1 links may be physically connected to a FREEDM device. In this case there are 32 FREEDM channels provisioned. The estimates for the Unchannelized T1 application are based on the following configuration: Configurable Parameter F X S E Q B N Value 16 blocks 4 blocks 4 blocks 8 blocks 64 6 32 Description size of buffer assigned to channel DMA transfer size for transmit and receive transmit start level of buffer (free blocks) transmit expedite level of buffer (free blocks) size of each queue number of references accessed at a time by the host software maximum references in TDR ready queue
25
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
f PCI f Channel PRIORITY PRIORITYB
33 MHz 1.544 Mbps 0 0
PCI bus clock frequency Channel data rate receive channel is not high priority transmit channel is not inhibited
The average PCI bus utilization for one FREEDM is shown in figure 5 as a function of the packet length. Two of the curves are for zero RAM latency, the third includes RAM latency with a ratio of 1:7 for read and write latency. The figure shows that utilization improves with B - the number of references cached in software before being read from, or written to, a FREEDM queue. The PCI bus utilization is strongly dependant on the packet length. For small packets the utilization increases dramatically. Figure 5. Utilization of a FREEDM With 32 Unchannelized T1 Links
0.65 0.55 Utilization 0.45 0.35 0.25 0.15 0.05 128 256 512 32 64 1024 2048 4096 8192 16384
B=1 B=6 B=6, 1:7 RAM latency
32768
Packet Length (bytes)
26
65535
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The utilization graph indicates that multiple FREEDM devices, each with 32 T1 channels, could be handled on a PCI bus. It also indicates that the system design (ie the number of references accessed at a time by the host software, the average packet length, and the host RAM latency) plays a major role in determining exactly how many FREEDM devices can be supported. Table 3 below shows the maximum tolerable channel latencies and the worst case PCI bus latencies, assuming zero RAM latency. Since the worst case PCI bus latencies are less than the tolerable channel latencies the average utilization should be used to determine how many FREEDM devices can be supported. Table 3. Latency Estimates With 32 T1 Channels Per FREEDM FREEDM's on bus receive LChannel (msec) transmit LChannel (msec) receive LPCI (msec) transmit LPCI (msec) 1.3 0.99 0.065 0.13 1 1.3 0.99 0.13 0.19 0.087 2 1.3 0.99 0.20 0.26 0.13 3 1.3 0.99 0.26 0.32 0.17 4 1.3 0.99 0.52 0.58 0.34 8
expedited transmit LPCI (msec) 0.044 64 Kbps Channelized E1 or T1
In this configuration any combination of T1 or E1 links, where some or all of the timeslots within a link are assigned to FREEDM channels, is possible. There are a total of 128 T1 and/or E1 time-slots mapped to FREEDM channels, for a total of 128 channels.
27
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
The estimates for the 64Kbps application are based on the following configuration: Configurable Parameter F X S E Q B N f PCI f Channel PRIORITY PRIORITYB Value 4 blocks 2 blocks 1 blocks 2 blocks 256 6 128 33 MHz 64 Kbps 0 0 Description size of buffer assigned to channel DMA transfer size for transmit and receive transmit start level of buffer (free blocks) transmit expedite level of buffer (free blocks) size of each queue number of references accessed at a time by the host software maximum references in TDR ready queue PCI bus clock frequency Channel data rate receive channel is not high priority transmit channel is not inhibited
The average PCI bus utilization for one FREEDM is shown in figure 6 as a function of the packet length. Two of the curves are for zero RAM latency, the third includes RAM latency with a ratio of 1:7 for read and write latency. The figure shows that utilization improves with B - the number of references cached in software before being read from, or written to, a FREEDM queue. The PCI bus utilization is strongly dependant on the packet length. For small packets the utilization increases dramatically.
28
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Figure 6. Utilization of a FREEDM With 128 Channels of 64 Kbps Rate
0.1 0.09 0.08 Utilization 0.07 0.06 0.05 0.04 0.03 0.02 0.01 128 256 512 1024 2048 4096 8192 32 64 16384
B=1 B=6 B=6, 1:7 RAM latency
32768
Packet Length (bytes)
The utilization graph indicates that more than 10 FREEDM devices could be supported. This value is too great for the loading constraints of the PCI bus. The PCI local bus specification only allows up to 4 devices, and the Compact PCI specification[3] allows up to 8 devices on a PCI bus. Table 4 below shows the maximum tolerable channel latencies and the worst case PCI bus latencies, assuming zero RAM latency. These values in combination with the utilization graph indicates that the maximum number of FREEDM devices on a compact PCI bus can be supported.
29
65535
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Table 4. Latency Estimates With 128 64Kbps Channels Per FREEDM FREEDM's on bus receive LChannel (msec) transmit LChannel (msec) receive LPCI (msec) transmit LPCI (msec) 4.0 8.0 0.16 0.33 1 4.0 8.0 0.33 0.48 0.22 2 4.0 8.0 0.49 0.65 0.33 3 4.0 8.0 0.66 0.81 0.44 4 4.0 8.0 1.3 1.44 0.87 8
expedited transmit LPCI (msec) 0.11 384 Kbps Channelized T1
Up to 128 channels can be configured on a FREEDM by assigning a number of timeslots to each channel. For this example there are 6 time-slots assigned to each channel for a total of 128 channels, each with a channel rate of 384 Kbps. All 32 ports of the FREEDM are attached to T1 links. The estimates for the 384Kbps T1 application are based on the following configuration: Configurable Parameter F X S E Q B N f PCI Value 4 blocks 2 blocks 1 blocks 2 blocks 256 6 128 33 MHz Description size of buffer assigned to channel DMA transfer size for transmit and receive transmit start level of buffer (free blocks) transmit expedite level of buffer (free blocks) size of each queue number of references accessed at a time by the host software maximum references in TDR ready queue PCI bus clock frequency
30
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
f Channel PRIORITY PRIORITYB
384 Kbps 0 0
Channel data rate receive channel is not high priority transmit channel is not inhibited
The average PCI bus utilization for one FREEDM is shown in figure 7 as a function of the packet length. Two of the curves are for zero RAM latency, the third includes RAM latency with a ratio of 1:7 for read and write latency. The figure shows that utilization improves with B - the number of references cached in software before being read from, or written to, a FREEDM queue. The PCI bus utilization is strongly dependant on the packet length. For small packets the utilization increases dramatically. Figure 7. Utilization of a FREEDM With 384Kbps Channelized T1
B=1 0.72 0.62 Utilization 0.52 0.42 0.32 0.22 0.12 0.02 128 256 512 32 64 1024 2048 4096 8192 16384 32768 65535 B=6 B=6, 1:7 RAM latency
Packet Length (bytes)
Table 5 below shows the maximum tolerable channel latencies and the worst case PCI bus latencies, assuming zero RAM latency. Both the latency estimates and the utilization graph indicate that 8 FREEDM cannot be supported.
31
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Table 5. Latency Estimates With 128 384Kbps T1 Channels Per FREEDM FREEDM's on bus receive LChannel (msec) transmit LChannel (msec) receive LPCI (msec) transmit LPCI (msec) 6.7 1.3 0.16 0.33 1 6.7 1.3 0.33 0.48 0.22 2 6.7 1.3 0.49 0.65 0.33 3 6.7 1.3 0.66 0.81 0.44 4 6.7 1.3 1.3 1.4 0.87 8
expedited transmit LPCI (msec) 0.11
Combining Unchannelized E1 with 64Kbps Channelized E1 For this configuration the FREEDM serial ports are attached to E1 links. Four of the links are assigned to 4 unchannelized E1 channels. The remaining 124 channels are assigned from time-slots within the remaining E1 links, each channel being assigned to one time-slot, for 124 64Kbps channels. The estimates for this application are based on the following configuration: Configurable Value Value Parameter (E1 (64Kbps Channel) Channel) F X S E Q B 4 blocks 2 blocks 1 block 2 blocks 256 6 4 blocks 2 blocks 1 block 2 blocks 256 6 Description
size of buffer assigned to channel DMA transfer size for transmit and receive transmit start level of buffer (free blocks) transmit expedite level of buffer (free blocks) size of each queue (select per FREEDM) number of references accessed at a time by the host software (select per FREEDM)
32
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
N f PCI f Channel PRIORITY PRIORITYB
128 33 MHz 2.048 Mbps 1 0
128 33 MHz 64 Kbps 0 1
maximum references in TDR ready queue (select per FREEDM) PCI bus clock frequency (select per PCI bus segment) Channel data rate 1 = priority receive channel 1 = inhibited transmit channel
The average PCI bus utilization for one FREEDM is shown in figure 8 as a function of the packet length. Two of the curves are for zero RAM latency, the third includes RAM latency with a ratio of 1:7 for read and write latency. The figure shows that utilization improves with B - the number of references cached in software before being read from, or written to, a FREEDM queue. The PCI bus utilization is strongly dependant on the packet length. For small packets the utilization increases dramatically.
33
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Figure 8. Utilization of a FREEDM With E1 and 64Kbps Channels
0.25
B=1, Q=32 B=6, Q=32
0.2 Utilization B=6, Q=32, 1:7 RAM latency
0.15
0.1
0.05
0 128 256 512 1024 2048 4096 8192 32 64 16384 32768 65535
Packet Length (bytes)
Table 6 and 7 below shows the maximum tolerable channel latencies and the worst case PCI bus latencies, assuming zero RAM latency. Both the latency estimates and the utilization graph indicate that 8 FREEDM can be supported with this configuration. Table 6. Latency Estimates For Unchannelized E1 Channels FREEDM's on bus receive LChannel (msec) transmit LChannel (msec) priority receive LPCI (msec) 1 0.12 0.24 0.006 2 0.12 0.24 0.012 0.0068 3 0.12 0.24 0.018 0.010 4 0.12 0.24 0.024 0.013 8 0.12 0.24 0.049 0.027
expedited transmit LPCI (msec) 0.0034
34
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
Table 7. Latency Estimates For 64Kbps Channels FREEDM's on bus receive LChannel (msec) transmit LChannel (msec) receive LPCI (msec) transmit LPCI (msec) 4.0 5.9 0.31 0.48 1 4.0 5.9 0.47 0.80 2 4.0 5.9 0.63 1.1 3 4.0 5.9 0.79 1.4 4 4.0 5.9 1.4 2.7 8
35
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
CONCLUSIONS AND RECOMMENDATIONS This document provides insight into the performance of a FREEDM on the PCI bus. A summary of what has been learned in this analysis includes: * Overutilization of the PCI bus can lead to receive packet overrun or transmit packet underrun. A designer needs to ensure the rate of the links attached to a FREEDM does not exceed the capabilities of the PCI bus, and the FREEDM. Registers of a FREEDM need to be configured to optimize bus utilization for the intended application. The application can greatly affect the PCI bus utilization. Transfers involving more small packets tend to increase the bus utilization. Since the data rate, rather than the link rate, affects bus utilization, and since the estimates have assumed the links are fully saturated with data, the utilization will be lower for LAN applications that have bursty traffic. The estimates have shown that RAM latency of the host has an adverse affect on the PCI bus utilization, especially with small packets. The host software should be designed to reduce utilization of the bus by accessing the FREEDM registers less frequently than with every packet. This can help to reduce the utilization during transfers of small packets. The host software should configure the size of queues so that they are large enough to handle the number of channels provisioned. The size should be at least 32 to ensure there are no adverse effects on the bus utilization, and generally must be larger than the number of channels provisioned. The TDR Ready queue should never be too large as the number of references in this queue will adversely affect the bus latency for transmit channels. A FREEDM channel can be provisioned to optimize use of the bus. configurable parameters have been presented. The
*
* *
*
* *
The bus utilization and latencies should be calculated to ensure a configuration does not lead to transmit underrun or receive overrun. Equations for estimating these have been presented. When an application has multiple channel rates the metric f Channel F can be used to identify which channels should be provisioned with receive priority, or inhibited transmit.
*
36
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
REFERENCES [1] PCI SIG, PCI Local Bus Specification, June 1, 1995, Version 2.1 [2] PMC-960113, PMC-Sierra, "Frame Relay Protocol Engine and Datalink Manager" Standard Product Datasheet, December, 1996, Issue 2 [3] PCI Compact Specification, PCI Industrial Computers Manufacturers Group, 1995, Version 1.0
37
PMC-Sierra, Inc. APPLICATION NOTE
ISSUE 1
PM7364 FREEDM
FREEDM PCI BUS UTILIZATION AND LATENCY ANALYSIS
CONTACTING PMC-SIERRA PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, B.C. Canada V5A 4V7 Telephone: Facsimile: 604-415-6000 604-415-6200 info@pmc-sierra.bc.ca apps@pmc-sierra.bc.ca http://www.pmc-sierra.com
Product Information: Applications information: World Wide Web Site:
Seller will have no obligation or liability in respect of defects or damage caused by unauthorized use, mis-use, accident, external cause, installation error, or normal wear and tear. There are no warranties, representations or guarantees of any kind, either express or implied by law or custom, regarding the product or its performance, including those regarding quality, merchantability, fitness for purpose, condition, design, title, infringement of third-party rights, or conformance with sample. Seller shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon, the information contained in this document. In no event will Seller be liable to Buyer or to any other party for loss of profits, loss of savings, or punitive, exemplary, incidental, consequential or special damages, even if Seller has knowledge of the possibility of such potential loss or damage and even if caused by Seller's negligence. (c) 1997 PMC-Sierra, Inc. PMC-961061(R1) Issue date: February, 1997
PMC-Sierra, Inc.
105 - 8555 Baxter Place, Burnaby, BC Canada V5A 4V7 604 415 6000

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