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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
PM7346 S/UNITM
QJET
S/UNI-QJET
REFERENCE DESIGN
ISSUE 2: JANUARY 1999
PMC-Sierra, Inc. 105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
CONTENTS 1 OVERVIEW............................................................................................... 1 1.1 2 3 4 APPLICATION PERSPECTIVE...................................................... 1
REFERENCES ......................................................................................... 2 FEATURE OVERVIEW ............................................................................. 3 FUNCTIONAL DESCRIPTION ................................................................. 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 OVERVIEW .................................................................................... 4 BLOCK DIAGRAM ......................................................................... 5 DATA FLOW ................................................................................... 5 S/UNI-QJET ................................................................................... 6 LOOPBACK FPGA ........................................................................ 9 J2 LINE INTERFACE ..................................................................... 9 DS-3 LINE INTERFACE............................................................... 10 E3 LINE INTERFACE................................................................... 10 3.3 VOLT TO 5 VOLT CONVERTER ............................................. 10 HIGH SLEW RATE BUFFERS ..................................................... 11 UTOPIA LEVEL 2 WITH MICROPROCESSOR INTERFACE ...... 11
5
EXTERNAL INTERFACE SIGNAL DESCRIPTION ................................ 12 5.1 UTOPIA WITH MICROPROCESSOR INTERFACE ..................... 12
6 7
SOFTWARE INTERFACE....................................................................... 18 IMPLEMENTATION DESCRIPTION ....................................................... 21 7.1 SHEET 1: ROOT DRAWING ........................................................ 21
i Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
7.2 7.3 7.4 7.5 7.6 7.7 8
SHEET 2: LOOPBACK FPGA BLOCK......................................... 21 SHEET 3: QJET BLOCK.............................................................. 21 SHEET 4: J2 LINE INTERFACE................................................... 22 SHEETS 5 AND 6: E3 LINE INTERFACE AND T3 LINE INTERFACE ................................................................................. 22 SHEET 7: UTOPIA AND MICRO INTERFACE............................. 22 SHEET 8: POWER SUPPLY AND DECOUPLING ....................... 23
OPERATIONS......................................................................................... 24 8.1 8.2 8.3 SYSTEM SETUP ......................................................................... 24 BOARD CONFIGURATION.......................................................... 24 JITTER ATTENUATION FOR E3.................................................. 25
9 10 11 12
BILL OF MATERIALS ............................................................................. 26 SCHEMATICS......................................................................................... 29 LAYOUT .................................................................................................. 30 APPENDIX A: FRAMING FORMATS...................................................... 31
ii Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
LIST OF FIGURES FIGURE 1 - ATM OVERVIEW ............................................................................ 1 FIGURE 2 - REFERENCE DESIGN CARD BLOCK DIAGRAM......................... 5 FIGURE 3 - ONBOARD REGISTER HARDWARE........................................... 18 FIGURE 4 - J2 FRAME FORMAT .................................................................... 31 FIGURE 5 - G.751 E3 FRAME FORMAT ......................................................... 31 FIGURE 6 - G.832 E3 FRAME FORMAT ......................................................... 32 FIGURE 7 - DS-3 FRAME FORMAT ................................................................ 32
iii Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 - MICROPROCESSOR WITH UTOPIA CLOCK CONNECTOR DEFINITION................................................................................. 12 - UTOPIA CONNECTOR DEFINITION ........................................... 15 - ONBOARD CONFIGURATION REGISTER.................................. 19 - BILL OF MATERIALS................................................................... 26
iv Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
1 1.1
OVERVIEW Application Perspective The S/UNI-QJET standard product is a Quad ATM User Network Interface with on chip J2, E3, and DS-3 framers and Utopia Level 2 interface. The S/UNI-QJET provides ATM cell mapping to J2, E1, E3, DS-1, and DS-3 frame formats. The S/UNI-QJET may be interfaced to an ATM layer device such as the RCMP-800 using the Utopia Level 2 interface to create the ingress circuitry for an ATM switch port card. ATM is a high performance networking technology that supports data transfer over connection oriented virtual paths. Data is transmitted in fixed sized cells containing header data used for switching, cell priority, flow control and header error control. It is capable of mixing various rates and types of traffic with minimal loss of service to users. The versatility of ATM allows it to be used in nearly any data networking environment including internet backplanes, wide area networks, and local area networks. Typical line options include SONET/SDH, DS-1/E1, DS-3/E3, and J2. Figure 1 below illustrates the possible configurations for WAN and LAN ATM switch ports. Figure 1 - ATM Overview
LAN ATM Switch LAN WAN SUBNET ATM Switch ATM Switch ATM Switch
ATM Switch
LAN Switch Port Implementation
UTOPIA Switch Interface
WAN Switch Port Implementation
UTOPIA Switch Interface
PM7322 RCMP-800 UTOPIA Bus PM5346 S/UNI-155 LITE
EGRESS DEVICE
PM7322 RCMP-800
EGRESS DEVICE
PM7322 RCMP-800 UTOPIA Bus PM7346 S/UNI-QJET J2/E3/T3 LIU 6, 34, 45 Mbps PM7344 S/UNI-MPH PM4314 QDSX 1.5, 2 Mbps
EGRESS DEVICE
PM5346 S/UNI-155 DUAL Optics 155 Mbps
PM7346 S/UNI-QJET J2/E3/T3 LIU 6, 34, 45 Mbps
PM5355 S/UNI-622
PM5347 S/UNI-155 PLUS Optics 155 Mbps
PM7345 S/UNI-PDH
Optics 34, 45 Mbps
Optics 155 Mbps
Optics 622 Mbps
1 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
2
REFERENCES [1] [2] [3] [4] [5] [6] [7] PMC-960835, PMC-Sierra Inc., PM7346 S/UNI-QJET Data Sheet, Issue 4, December 1997 PMC-940904, PMC-Sierra Inc., PM7322 RCMP-800 Data Sheet, Issue 6, August 1997 PMC-940212, PMC-Sierra Inc., SCI-PHY Level 2, Issue 3, November 1995 PMC-960148, PMC-Sierra Inc., PM7322 RCMP-800 Reference Design, Issue 2, August 1997 ATM Forum - Utopia, An ATM PHY Interface Specification, Level 2, Version 1", June 1995 PMC-950946, PMC-Sierra Inc., Interfacing the D3MX to the SSI 78P7200 T3 LIU, Issue 1, September 1995 PMC-971136, PMC-Sierra Inc., Channelizing J2 Data Streams with S/UNI-QJET and FREEDM-8, Issue 2, February 1998
2 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
3
FEATURE OVERVIEW This reference design provides the following features: * * * * * * PLCP and direct mapping of ATM cells to DS-3, E3, and J2 frame formats. Two DS-3, one E3, and one J2 line interfaces. Line performance monitoring performed by PM7346 S/UNI-QJET. 8 or 16 bit, 50 MHz Utopia interface for ATM cell transfer. FPGA for terminal side loopback. Reference design provides an aggregate bandwidth of 130 Mbit/s.
3 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
4 4.1
FUNCTIONAL DESCRIPTION Overview The S/UNI-QJET reference design is an ATM line card that implements ATM physical layer circuitry for J2, E3, and DS-3 lines. The line interface to this reference design is capable of interfacing to either one of the J2, E3, or DS-3 Plesiochronous Digital Hierarchy transport systems. This reference design consists of one S/UNI-QJET with an FPGA for loopback and circuitry to interface line signals to the S/UNI-QJET. The card interfaces to two DS-3 lines, one E3 line, and one J2 line. There is also a Utopia Level 2 interface for cell transfer and a host access port to monitor and configure the board. A block diagram of the reference design is shown in Figure 2.
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
4.2
Block Diagram Figure 2 - Reference Design Card Block Diagram
DS3 Line Interface (2x) 2 2 2 2 2 2 E3 Line Interface Unit High Slew Rate Buffer 3
6.312 MHz Osc 34.368 MHz Osc
E3 Line Interface 2
J2 Line Interface 2 J2 Line Interface Unit
DS3 Line Interface Unit (2x) High Slew Rate Buffer
44.736 MHz Osc
3.3V to 5V Buffers 3 3 3 3 TPOS[1:2], TNEG[1:2], TCLK[1:2]
3.3V to 5V Buffers 3 3
3
TICLK[4]
160 pin Connector
Utopia 2 with Microcontroller Interface
TICLK[1:2]
RPOS[1:2], RNEG[1:2], RCLK[1:2] A[10:0] D[7:0]
S/UNI-QJET
TICLK[3]
PM7346
RPOS[3], RNEG[3], RCLK[3]
RPOS[4], RNEG[4], RCLK[4]
TPOS[3], TNEG[3], TCLK[3]
TPOS[4], TNEG[4], TCLK[4]
Micro Bus
8/16 Bit Utopia Level
A[10:0], D[7:0]
Loopback FPGA
50 MHz Osc
160 pin Connector
4.3
Data Flow Data flowing to the host is received on one of the J2, E3, or DS-3 line interfaces. LIU units for each line decode the analog signals on the line to digital signals indicating negative and positive line pulses. Clock information is also recovered and converted to a digital signal. These signals are then passed to the line side link interfaces of the S/UNI-QJET device. Each line side link interface consists of
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
two data pins to receive the negative and positive pulse signals, and a clock signal corresponding to pins RNEG, RPOS, and RCLK respectively. The data is framed by the S/UNI-QJET units and ATM cells are delineated from the payload of the J2, E3, and DS-3 data streams. Received cells are stored in a four cell FIFO which outputs the data via the Utopia Level 2 interface. Each channel has a separate 4 cell FIFO. Data transferred from the S/UNI-QJET over the Utopia interface is controlled by an external ingress ATM layer device such as the PM7322 RCMP-200. ATM cells to be transmitted over the J2, E3, and DS-3 lines are transferred to the card via the Utopia Level 2 interface, from an external egress ATM layer device. Cells are then mapped to the frame format for each channel and the resulting positive and negative pulse, and clock information are sent to the LIU's. Transmit clock information is derived from external crystal oscillators running at the transmit line rates. LIU units for each link encode the digital signals to J2, E3, or DS-3 analog signals. 4.4 S/UNI-QJET The PM7346 S/UNI-QJET is a quad ATM physical layer processor with integrated DS3 E3, and J2 framers. PLCP sublayer DS1, DS3, E1, and E3 processing is supported as is ATM cell delineation. The S/UNI-QJET contains integral DS3 framers, which provide DS3 framing and error accumulation in accordance with ANSI T1.107, and T1.107a, integral E3 framers, which provide E3 framing in accordance with ITU-T Recommendations G.832 and G.751, and integral J2 framers, which provide J2 framing in accordance with ITU-T Recommendation G.704. When configured for DS3 transmission system sublayer processing, the S/UNI-QJET accepts and outputs either or both digital B3ZS-encoded bipolar and unipolar signals compatible with M23 and C-bit parity applications. When configured for E3 transmission system sublayer processing, the S/UNI-QJET accepts and outputs either or both HDB3-encoded bipolars or unipolar signals compatible with G.751 and G.832 applications. When configured for J2 transmission system sublayer processing, the S/UNI-QJET accepts and outputs either or both B8ZS-encoded bipolar or unipolar signals compliant with G.704 and NTT 6.312 Mbit/s applications. In the DS3 receive direction, the S/UNI-QJET frames to DS3 signals with a maximum average reframe time of 1.5 ms and detects line code violations, loss
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
of signal, framing bit errors, parity errors, path parity errors, AIS, far end receive failure and idle code. The DS3 overhead bits are extracted and presented on serial outputs. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bitoriented codes in the FEAC channels are detected and are available through the microcontroller port. In the E3 receive direction, the S/UNI-QJET frames to G.751 and G.832 E3 signals with a maximum average reframe times of 135s for G.751 frames and 250s for G.832 frames. Line code violations, loss of signal, framing bit errors, AIS, and remote alarm indication are detected. Further, when processing G.832 formatted data, parity errors, far end receive failure, and far end block errors are also detected; and the Trail Trace message may be extracted and made available through the microcontroller port. HDLC receivers are provided for either the G.832 Network Requirement or the G.832 General Purpose Data Link support. In the J2 receive direction, the S/UNI-QJET frames to G.704 6.312 Mbit/sec signals with a maximum average reframe time of 5.07ms. An alternate framing algorithm which uses the CRC-5 bits to rule out 99.9% of all static mimic framing patterns is available with a maximum average reframe time of 10.22ms when -4 operating with a 10 bit error rate. Line code violations, loss of signal, loss of frame, framing bit errors, physical layer AIS, payload AIS, CRC-5 errors, Remote End Alarm, and Remote Alarm Indication are detected. HDLC receivers are provided for Data Link support. Error event accumulation is also provided by the S/UNI-QJET. Framing bit errors, line code violations, parity errors, path parity errors and far end block errors are accumulated, when appropriate, in saturating counters for DS3, E3, and J2 frames. Loss of Frame detection for DS3, E3, and J2 is provided as recommended by ITU-T G.783 with integration times of 1ms, 2ms, and 3ms. In the DS3 transmit direction, the S/UNI-QJET inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication Signals can be inserted by using internal register bits; other status signals such as the idle signal can be inserted when enabled by internal register bits. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M subframe) is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at 1 C-bits for C-bit Parity application. In the E3 transmit direction, the S/UNI-QJET inserts E3 framing in either G.832 or G.751 format. When enabled for G.832 operation, an HDLC transmitter is
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
provided for insertion of either the Network Requirement or General Purpose Data Link into the appropriate overhead bits. The Alarm Indication Signal and other status signals can be inserted by internal register bits. In the J2 transmit direction, the S/UNI-QJET inserts J2 6.312 Mbit/s G.704 framing. HDLC transmitters are provided for insertion of the Data Channels. CRC-5 check bits are calculated and inserted into the J2 multiframe. External pins are provided to enable overwriting of any of the overhead bits within the J2 frame. The S/UNI-QJET also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. The S/UNI-QJET provides cell delineation for ATM cells using the PLCP framing format, or by using the header check sequence octet in the ATM cell header as specified by ITU-T Recommendation I.432. DS1, DS3, E1 and E3 based PLCP frame formats can be processed. Non-PLCP-based cell delineation is accomplished with either bit, nibble, or byte-wide search algorithms, depending on the line interface used. An interface consistent with the generic physical interface defined by ITU-T Recommendation I.432 is provided for arbitrary rates up to 52 Mbit/s. This interface is used to provide physical layer support for transmission systems that do not have an associated PLCP sublayer, or to provide an efficient means of directly mapping ATM cells to existing transmission system formats (such as DS3 and DS1). In the PLCP receive direction, framing, path overhead extraction and cell extraction is provided. BIP-8 error events, frame octet error events and far end block error events are accumulated. In the PLCP transmit direction, the S/UNI-QJET provides overhead insertion using inputs or internal registers, DS3 nibble and E3 byte stuffing, automatic BIP8 octet generation and insertion and automatic far end block error insertion. Diagnostic features for BIP-8 error, framing error and far end block error insertion are also supported. In the cell receive path, idle cells may be dropped according to a programmable filter. By default, incoming cells with single bit HCS errors are corrected and written to the FIFO buffer. Optionally, cells can be dropped upon detection of a HCS error. Cell delineation may optionally be disabled to allow passing of all cells, regardless of cell delineation status. Assigned cells containing no detectable HCS errors are written to a FIFO buffer. Cells data is read from the FIFO using a synchronous 50 MHz 8-bit wide or 16-bit wide Utopia Level 2
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
compatible interface. Cell data parity is also provided. Counts of error-free assigned cells, and cells containing HCS errors are accumulated independently for performance monitoring purposes. In the cell transmit path, cell data is written to a FIFO buffer using a synchronous 50 MHz 8-bit wide or 16-bit wide Utopia Level 2 interface. Cell data parity is also examined for errors. Idle cells are automatically inserted when the FIFO contains less than one full cell. HCS generation, cell payload scrambling, and cell header scrambling (for use with PPP packets) are optionally provided. Counts of transmitted cells are accumulated for performance monitoring purposes. Both receive and transmit cell FIFOs provide buffering for four cells. The FIFOs provide the rate matching interface between the higher layer ATM entity and the S/UNI-QJET. The S/UNI-QJET is configured, controlled and monitored via a generic 8-bit microcontroller bus through which all internal registers are accessed. All sources of interrupts can be identified, acknowledged, or masked via this interface. 4.5 Loopback FPGA A single FPGA is used to perform loopback on the Utopia bus. This loops back the cells received by the S/UNI-QJET. The FPGA acts as a Utopia master in both transmit and receive directions. The FPGA uses direct cell indication and a round robin scheme to select input PHY sources for each cell transmission. Received data is transmitted through the same port from which it was received. Loopback is enabled by writing a `1' to bit 4 of the onboard configuration register and asserting the "REG_OEB" signal low or closing jumper J3 (refer to schematics). The FPGA also implements channelized J2 functionality for the J2 port of the reference design. This is included to verify the logic design presented in [7] PMC-971136, "Channelizing J2 Data Streams with S/UNI-QJET and FREEDM8". 4.6 J2 Line Interface One Transwitch MRT TXC02050 J2 LIU is used to provide the J2 line interface to the S/UNI-QJET device. The LIU converts the digital B8ZS encoded data to its analog equivalent and converts analog B8ZS to it's digital equivalent. In the receive direction, the LIU provides TTL level receive clock, and positive and negative receive data. In the transmit direction the LIU receives TTL level transmit clock, and positive and negative transmit data. The TTL input and output
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
levels are directly compatible with the S/UNI-QJET. Buffers are required on the line side to drive the line transformers. 4.7 DS-3 Line Interface Two TDK TSC 78P7200 LIUs are used to provide two DS-3 interfaces to ports 1, and 2 of the S/UNI-QJET device. The LIU converts transmit digital B8ZS encoded data to its analog equivalent and converts receive analog B8ZS to its digital equivalent. In the receive direction, the LIU provides a CMOS level receive clock, and positive and negative receive data. In the transmit direction the LIU receives a CMOS level transmit clock, and positive and negative transmit data. CMOS level signals are compatible with the S/UNI-QJET's inputs, however, as the S/UNIQJET is a 3.3 V device, a voltage buffer is required to boost the output signals of the S/UNI-QJET to match the levels required by the 78P7200. Also, because of the low slew rate of the TDK TSC 78P7200 device, buffers are used to increase the slew rate of the signals sent to the S/UNI-QJET. 4.8 E3 Line Interface One TDK TSC 78P7200 LIU is used to provide an E3 interface to port 3 of the S/UNI-QJET device. The LIU converts transmit digital HDB3 encoded data to its analog equivalent and converts receive analog HDB3 to its digital equivalent. Note that although this is the same LIU as used for the DS-3 line interface, the surrounding circuitry is different. In the receive direction, the LIU provides a CMOS level receive clock, and positive and negative receive data. In the transmit direction the LIU receives a CMOS level transmit clock, and positive and negative transmit data. CMOS level signals are compatible with the S/UNI-QJET's inputs, however, as the S/UNIQJET is a 3.3 V device, a voltage buffer is required to boost the output signals of the S/UNI-QJET to match the levels required by the 78P7200. Also, because of the low slew rate of the TDK TSC 78P7200 device, buffers should be used to increase the slew rate of the signal sent to the S/UNI-QJET. 4.9 3.3 Volt to 5 Volt Converter The S/UNI-QJET uses a 5 volt reference pin to allow inputs to tolerate 5 volt input signals. However, the S/UNI-QJET can only produce a guaranteed output high voltage of 2.4 volts. In this design, 74ACT125, advanced TTL compatible CMOS buffers, are used to convert the 2.4 volt output high voltage to the required 3.5 volt level required by the E3/DS-3 LIU units. Note that the J2 LIU
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
used in this design is voltage compatible with the S/UNI-QJET and thus does not require a buffer. Note that the Utopia clock signals TFCLK and RFCLK are not 5 volt tolerant. 4.10 High Slew Rate Buffers High slew rate buffers are required to correct possible problems caused by the slow slew rate of the E3 and DS-3 LIU's combined with the TTL logic levels expected by the S/UNI-QJET. Without this buffer the duty cycle of signals sent from the E3 and DS-3 LIU's to the S/UNI-QJET will suffer duty cycle distortion. A detailed explanation of this problem is found in [6] PMC-950946, "Interfacing the D3MX to the SSI 78P7200 T3 LIU". Note that the SSI 78P7200 has an identical slew rate to the TDK TSC 78P7200 used in this design. 4.11 Utopia Level 2 with Microprocessor Interface Two 160 pin male connectors provide necessary connections for Utopia operation and microprocessor access. The first 160 pin connector is used to carry 5V and 3V power, microprocessor and Utopia clock signals. The second carries the Utopia bus signals.
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
5
EXTERNAL INTERFACE SIGNAL DESCRIPTION This board has a 160 pin male Utopia Level 2 compliant interface for data transfer to and from the board. The 160 pin microprocessor interface provides a user interface for configuration and monitoring of the board as well as the receive and transmit clock signals for the Utopia bus. The Utopia interface connects the board to ATM layer devices. The 160 pin Utopia interface provides a large number of ground connections physically distributed along the connector to reduce interference between circuits and provide a similar characteristic impedance across the connector for critical signals.
5.1
Utopia with Microprocessor Interface The table below indicates the use of each pin in the 160 pin microprocessor and Utopia clock connector of the Utopia with Microprocessor interface. Table 1 Pin Name D[0] D[1] D[2] D[3] D[4] D[5] D[6] D[7] A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] A[10] - Microprocessor with Utopia Clock Connector Definition Type INPUT / OUTPUT Pin No. D1 C1 D2 C2 D3 C3 D4 C4 D9 D10 D11 D12 D13 D14 D15 D16 C9 C10 C11 Function Data Bus. D[7:0] is a eight bit bidirectional data used for microprocessor read and write access
INPUT
Address Bus. A[10:0] is an eleven bit address bus that selects specific registers in the S/UNI-QJET during microprocessor access
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
Pin Name REG_OEB
Type INPUT
Pin No. B17
Function Register output enable signal. This active low signal enables the output of the configuration register Active Low Chip select for onboard configuration register. PHY Address select signals for external selection of board PHY address. Active Low Reset for the board. Address Latch Enable Read Enable. Active low signal Write Enable. Active low signal Chip Select for S/UNI-QJET. The active-low chip select is low during S/UNI-QJET register accesses Active low interrupt from S/UNI-QJET. Negative differential receive clock signal. This signal, along with RFCLK+ comprise the differential RFCLK clock signal sent across the connector. RFCLK is to be used as a reference to sample RDAT. Positive differential receive clock signal. This signal, along with RFCLKcomprise the differential RFCLK clock signal sent across the connector. RFCLK is to be used as a reference to sample RDAT. Positive differential receive clock signal. This signal, along with TFCLKcomprise the differential TFCLK clock signal sent across the connector. TFCLK is used as a reference to sample TDAT.
REG_CSB PHY_ADR[0] PHY_ADR[1] PHY_ADR[2] RSTB ALE RDB WRB CSB
INPUT INPUT
C23 A14 A15 A16 B18 A22 B22 C22 D23
INPUT INPUT INPUT INPUT INPUT
INTB RXLCK-
OUTPUT OUTPUT
D27 D35
RXCLK+
OUTPUT
D36
TXCLK+
INPUT
D39
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
Pin Name TXCLK-
Type INPUT
Pin No. D40
Function Negative differential receive clock signal. This signal, along with TFCLK+ comprise the differential TFCLK clock signal sent across the connector. TFCLK is used as a reference to sample TDAT. Test port clock. Provides timing for test operations. This signal controls the operations that can be carried out using the test access port Test Data Input. This signal carries test data into the S/UNI-QJET. Test Data Output. This signal carries test data out of the S/UNI-QJET. Not Connected.
TCK TMS
INPUT INPUT
B28 A28
TDI TDO NC
INPUT OUTPUT NC
C28 D28 A20 - A21 A23 - A40 B19 - B21 B23 - B30 C5 - C8 C12 - C17 C19 - C21 C24 - C30 D5 - D8 D20 - D22 D24 - D26 D28 - D34 D37 - D38 A1 - A2 B1 - B2 A3 - A9 B3 - B9 A10 - A13 A17 - A19 B10 - B16 B31 - B40 C31 - C40
+ 5V + 3.3V GND
POWER POWER GND
+ 5 Volt supply + 3.3 Volt supply Ground
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PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
Table 2 below indicates the use of each pin in the 160 pin Utopia Data and Control portion of the Utopia with Microprocessor interface. Table 2 Pin Name RXDAT[0] RXDAT[1] RXDAT[2] RXDAT[3] RXDAT[4] RXDAT[5] RXDAT[6] RXDAT[7] RXDAT[8] RXDAT[9] RXDAT[10] RXDAT[11] RXDAT[12] RXDAT[13] RXDAT[14] RXDAT[15] RXPRTY - Utopia Connector Definition Type OUTPUT Pin No. A1 D1 A2 D2 A3 D3 A4 D4 A5 D5 A6 D6 A7 D7 A8 D8 A9 Function Receive Cell Data Bus. This bus carries the ATM cell octets that are read from the selected receive FIFO.
OUTPUT
DXRCA[1] DXRCA[2] DXRCA[3] DXRCA[4] RXADDR[0] RXADDR[1] RXADDR[2] RXADDR[3] RXADDR[4] RXENB
OUTPUT
A10 A11 A12 A13 D9 D10 D11 D12 D13 A14
INPUT
Receive bus parity. The receive parity signal indicates the parity of the RXDAT bus. Direct Receive Cell Available. These signals indicate available cells to be transferred across the Utopia bus for each of the four PHY ports of the S/UNI-QJET. Receive Address. The RXADDR[4:0] bus is used to select the port that is to be read from or being polled.
INPUT
RXCLAV
OUTPUT
A15
Receive Multi-PHY Read Enable. The RXENB signal is an active low input which is used to initiate reads from the receive FIFOs of the S/UNI-QJET. Receive Multi-PHY Cell Available signal. This signal is used to indicate an available cell during receive PHY port polling
15
Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
Pin Name RXSOC
Type OUTPUT
Pin No. D14
Function Receive Start of Cell. The Receive start of cell signal marks the start of cell on the RXDAT bus. Transmit Multi-PHY Write Enable. The TXENB signal is an active low input which is used to initiate writes to the transmit FIFOs of the S/UNI-QJET. Transmit cell available signal. This signal is used to indicate available cell FIFO space by polled PHY ports. Transmit Start of Cell. The transmit start of cell signal marks the start of cell on the TXDAT bus. Transmit Address. The TXADDR[4:0] bus is used to select the port that is to be written to or being polled.
TXENB
INPUT
A27
TXCLAV
OUTPUT
D26
TXSOC
INPUT
A28
TXADDR[0] TXADDR[1] TXADDR[2] TXADDR[3] TXADDR[4] DTCA[1] DTCA[2] DTCA[3] DTCA[4] TXPRTY
INPUT
OUTPUT
D27 D28 D29 D30 D31 A29 A30 A31 A32 D32
INPUT
Direct Receive Cell Available. These signals indicate available cells to be transferred across the Utopia bus for each of the four PHY ports of the S/UNI-QJET Transmit bus parity. The transmit parity signal indicates the parity of the TDAT bus.
16 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
Pin Name TXDAT[0] TXDAT[1] TXDAT[2] TXDAT[3] TXDAT[4] TXDAT[5] TXDAT[6] TXDAT[7] TXDAT[8] TXDAT[9] TXDAT[10] TXDAT[11] TXDAT[12] TXDAT[13] TXDAT[14] TXDAT[15] GND NC
Type INPUT
Pin No. A40 D40 A39 D39 A38 D38 A37 D37 A36 D36 A35 D35 A34 D34 A33 D33 B1 - B40 C1 - C40 A16 - A26 D15 - D25
Function Transmit Cell Data Bus. This bus carries the ATM cell octets that are written to the selected transmit FIFO.
GND NC
Ground pins. No Connection
17 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
6
SOFTWARE INTERFACE Software configuration for the S/UNI-QJET Reference design requires microprocessor access to the S/UNI-QJET configuration registers and the onboard configuration register. Access to the registers of the S/UNI-QJET registers requires an eight bit data, eleven bit address microprocessor interface with chip select, read enable and write enable signals. The outputs of the on board configuration register drive control signals through an HC541 buffer to the rest of the board. These control signals include signals to that uniquely identify the Utopia PHY address of the board. This is illustrated in Figure 3 below. Figure 3 - Onboard Register Hardware
PHY_ADR[2:0]
Pull up/down resistors tied to PHY_ADR[2:0] on connector HC541 D[7:5] Onboard Configuration Register Q[4:1] Signals to drive PHY_ADR[2:0] of S/UNI-QJET
160 Pin Connector
D[7:0]
Control signals to the rest of the board Pull down resistors
REG_CSB WRB
REG_OEB
Pull up and pull down resistors are placed on the outputs of the buffer to put the board into a default state when the buffer is tri-stated. The output enable of the buffer is controlled by the REG_OEB signal on the Utopia with Microprocessor connector. By default the buffer is tri-stated (REG_OEB is `1'). When the buffer is tri-stated, the Utopia PHY address is set by the value of the PHY_ADR[2:0] signals present on the connector. This allows multiple S/UNI-QJET boards to be
18 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
plugged into a single host board since different PHY addresses using these hardwired values can be automatically set by the host board after power up. This prevents contention on the Utopia bus before the microprocessor has a chance to set the PHY address by software. After the value of the configuration register is set, the REG_OEB signal is driven low by the microprocessor of the host board to enable the outputs of the buffer. When REG_OEB is `1' and the buffer is not driving, the control signals LB_EN, LBO1, LBO2, and J2_EN are pulled low. To write to the onboard configuration register, the register must be selected using REG_CSB. New values for the register are latched on the rising edge of WRB+REG_CSB. For more details on the S/UNI-QJET register space, refer to [1] PMC-960835 "PM7346 S/UNI-QJET Data Sheet". Table 3 below describes the bits of the onboard configuration register. Table 3 Bit 7 6 5 4 3 2 1 0 - Onboard Configuration Register Type W W W W W W W Function PHY_ADR[2] PHY_ADR[1] PHY_ADR[0] LB_EN LBO[1] LBO[2] J2_EN Unused Default X X X X X X X
Note that the value of the onboard register has no effect unless the REG_OEB signal is low. PHY_ADR[2:0] The PHY_ADR bits set the Utopia PHY address of the S/UNI-QJET device. LB_EN When a `1' is written to the LB_EN bit and the J2_EN bit is a `0', the board is placed into loopback mode. If the J2_EN bit is also a `1' then the board is put in channelized J2 mode.
19 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
LBO[2:1] These bits set the line build out for the two DS-3 ports (ports 1 and 2) of the reference design. Line build out for port 1 is set by the LBO[1] bit and line build out for port 2 is set by the LBO[2] bit. When a `1' is written to either of the LBO bits, the LBO for the corresponding port will be configured for transmission distances less than 225 feet. When a `0' is written to either of the LBO bits, the LBO for the corresponding port will be configured for transmission distances greater than 225 feet. J2_EN The J2_EN bit, together with the LB_EN bit, configure the board for channelized J2 operation. When the value of both bits is `1', then the board is put into channelized J2 mode. When the LB_EN bit is `0' the J2_EN bit has no effect.
20 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
7 7.1
IMPLEMENTATION DESCRIPTION Sheet 1: Root Drawing This sheet gives a simplified overview of the design, dividing it into it's major components. These are the line interfaces, the S/UNI-QJET, the loopback FPGA, and the Utopia with microprocessor interface.
7.2
Sheet 2: Loopback FPGA Block * * An ACTEL 42MX09 is used to implement Utopia loopback and channelized J2. PI5C16212 Bus switches U3, U4, U15, U17, and U18 connect the Utopia signals from the S/UNI-QJET to either the Loopback FPGA or the board connectors. These switches are controlled by the LB_EN signal. When in loopback, the signals driving the board connector are tied low by resistor arrays connected through the bus switches. The receive Utopia clock of the S/UNI-QJET may be driven from a board interfaced to the Utopia with Microprocessor Interface or from the 74FCT3807 3.3V clock driver U2. To drive the clock from U2, resistors R16 and R20 are populated while jumper JP1 is left open. To drive the clock from a board connected through the Utopia with Microprocessor Interface, R16 and R20 should be left unpopulated and JP1 should be set. The transmit clock is supplied from the board connector. During loopback, transmit and receive clocks are both supplied by the 74FCT3807 clock driver. Headers are provided to allow access to signals to verify the channelized J2 logic.
*
* * 7.3
Sheet 3: QJET Block * * A diode D3 is used to ensure that the voltage applied to the BIAS pins on the S/UNI-QJET is always greater or equal to that on the 3.3v power pins. Three oscillators provide clocks for the three line rates used in this reference design. Y2 provides clocks for the two DS-3 quadrant of the S/UNI-QJET, Y3 provides a clock for the E3 quadrant of the S/UNI-QJET, and Y4 provides clocks for the J2 quadrant of the S/UNI-QJET, and the J2 LIU.
21 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
*
A configuration register U24 allows software configuration of the board through microprocessor access. The register controls loopback, channelized J2 operation, line build out for the DS-3 LIU's, and the PHY address for the board. A tri-state buffer is used to drive control signals with the corresponding register output. Placing the buffer in tri-state leaves the board in it's default configuration of no loopback, no channelized J2, line build out for 225' or longer DS-3 transmission, and PHY address of "000". 74ACT125 buffers are used to translate the 3v CMOS level outputs of the S/UNI-QJET to the 5v CMOS levels required by the TDK72P7800 LIU units U16, U19, and U20.
*
7.4
Sheet 4: J2 Line Interface * 74ACT125 buffers are used to drive the line transformer, ensuring that the output capability of the LIU U28 is not exceeded.
7.5
Sheets 5 and 6: E3 Line Interface and T3 Line Interface * * Analog receive and transmit power are separated by ferrite beads to prevent interference between the two power planes. 74ACT08 AND gates U26 are used to increase the slew rate of the signals output from the LIU U16. When the signal received by the LIU is too low, the LOWSIGB signal of the LIU disables the data and clock output from the device to avoid erroneous data being passed to the S/UNI-QJET device. Component values are chosen according to manufacturer specification for the line rate used (E3 or DS-3)
* 7.6
Sheet 7: Utopia and Micro Interface * Balun transformer T8 is used to transform the differential Utopia transmit clock signal from the Micro and Utopia Clock connector to a single ended signal for the S/UNI-QJET. Balun transformer T7 is used to transform the single ended Utopia receive clock from the board to a differential clock for the Micro and Utopia Clock connector. LED's are used driven by the S/UNI-QJET FRMSTAT pins to indicate various framing status conditions according to the contents of the STATSEL bits in the S/UNI-QJET's Configuration Register 2.
*
22 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
*
The reset signal RSTB may be activated from either the push button on board or an external signal from the connector. An AND gate U38 is used to drive RSTB from either of these two sources.
7.7
Sheet 8: Power Supply and Decoupling * Power may be supplied through the Microprocessor with Utopia Clock connector or through a separate 4 pin Molex connector, but not both. Solder bridges are used to select the desired power source. De-coupling capacitors for the S/UNI-QJET are placed such that each power pin has a capacitor nearby.
*
23 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
8 8.1
OPERATIONS System Setup The S/UNI-QJET reference board is designed to transmit and receive data at DS-3, E3, and J2 data rates on the line side while transferring ATM cells across the 50 MHz Utopia Level 2 bus. The board is controlled through the microprocessor portion of the Utopia with Microprocessor interface. The PHY address of the board is configured using pins also residing on the Utopia with Microprocessor interface. These pins should be tied low by the ATM layer board if only one PHY board is interfaced to the Utopia bus. If more than one board is to reside on the Utopia bus, each PHY board connector must have it's own default PHY address set by tying the PHY_ADR pins of the connector to a unique value. However, if the value is "111" the fourth quadrant of the PHY device would have the same address as the Utopia null address "11111" and will not be used.
8.2
Board Configuration Before data can be transmitted or received, each quadrant of the S/UNI-QJET must be configured for the correct line rate. Other options may be modified as desired, see [1] "PM7346 S/UNI-QJET Data Sheet" for more information. The onboard register may be written to configure the board for loopback, enable channelized J2, change the PHY address, and line build out for the DS-3 LIU's. Writing to the register requires clocking data in using REG_CSB + WRB. Bits 5 to 7 of the register set the PHY address of the board, bit 4 puts the board into loopback, bits 2 and 3 determine the line build out of the DS-3 LIU's and bit 1 with bit 4, sets the board to perform channelized J2. After writing to the register, the REG_OEB signal must be held low to drive the appropriate control signals and PHY_ADR pins of the S/UNI-QJET. Otherwise, the PHY_ADR signals from the connector determine the PHY address, and the other control signals are pulled low (normal operation). The DS-3 line interfaces have a default line build out for transmission length greater than 225 feet. Setting the LBO signals of either DS-3 interface to 1 will set the line build out for transmission distance less than 225 feet. Setting the board to loopback mode requires that the S/UNI-QJET be set to deassert DRCA 5 cycles early at the end of cells. Bit 4 should be set to one to enable loopback.
24 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
To enable the channelized J2 operation, the S/UNI-QJET should be put in framer only mode and bits 4 and 1 of the register should also be set to `1'. 8.3 Jitter Attenuation for E3 This reference design does not provide circuitry to attenuate output jitter as required by E3 related standards. Jitter attenuation circuitry for the TDK72P7800 line interface units are available directly from TDK semiconductor for TDK customers. To contact TDK semiconductor please visit their web page at www.tsc.tdk.com.
25 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
9
BILL OF MATERIALS Table 4
NO.
- Bill of Materials
Part Number
1N4148W 1N5817M 42MX09_PL84 SN74F32D PI49FCT3807 SN74HC08D SN74HC541DW SN74HCT377DW 74AC08D 74ACT125D PI74LPT541CS TSC78P7200-IH TDK Toko 617DB-1024 DIGI-KEY - ARF1065-ND NEWARK - 499-225
Description
Reference Description
D6 D3 U21 U22 U2 U38 U25 U24 U26, U27, U29 U8, U10-U13 U9 U16, U19, U20 T7, T8 J4-J11 C34, C35, C38-C40, C51C55, C59, C64, C69, C72, C73, C77, C80, C88, C90, C104, C107, C108, C127 C61, C82, C84 C1-C28, C30, C31, C37, C41-C44, C48-C50, C56, C58, C63, C65, C68, C76, C78, C86, C87, C91, C92, C94, C95, C98, C101-C103, C105, C106, C111, C112, C115-C119, C122, C125 C60, C79, C81 C36, C45-C47, C71, C110, C114 C66, C93, C97, C99, C100
Qty
1 1 1 1 1 1 1 1 3 5 1 3 2 8 23
1 1N4148 2 1N5817 3 42MX09_PL84 4 74F32 5 74FCT3807 6 74HC08 7 74HC541 8 74HCT377 9 74AC08 10 74ACT125 11 74LPT541 12 78P7200 13 BALUN-BASE 14 BNC_AMPHENOL-BASE 15 CAPACITOR-0.01UF, 50V, X7R_805
16 CAPACITOR-0.022UF, NEWARK - 578-198 50V, X7R_805 17 CAPACITOR-0.1UF, 25V, NEWARK - 52F020 Y5V_805
3 66
18 CAPACITOR-0.22UF, 16V, Y5V_805 19 CAPACITOR-1000PF, 50V, X7R_805 20 CAPACITOR-10PF, 50V, NPO_805 21 CAPACITOR-10UF, 6.3V, TANT TE
NEWARK - 52F022 NEWARK - 499-201 NEWARK - 499-158
3 7 5 12
DIGI-KEY - PCS1106CT-ND C29, C32, C57, C62, C74, C75, C83, C85, C89, C96, C121, C124 22 CAPACITOR-3PF, 50V, DIGI-KEY - PCC030CNCT- C67 NPO_805 ND 23 CAPACITOR-68UF, 6.3V, DIGI-KEY - PCT1686CT-ND C120, C123 TANT TEH
26 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
1 2
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
NO.
Description
Part Number
Reference Description
Qty
3 2 1 1 1 1 1 1 1 15 3 3 1 2 1 1 1 1 1 1 1 1 6 5 8
24 CAPACITOR-82PF, 50V, NPO_805 25 CONN160_MALE_71624 -2000-BASE 26 DIODEZENER_SMD4.7V, 1W 27 DIODEZENER_SMD6.2V, 1W 28 FUSE__SMD-1.500A, NANO 29 FUSE__SMD-2.500A, NANO 30 HEADER2_100 MILBASE 31 HEADER2_JUMPERBASE 32 HEADER_10X2-BASE 33 INDUCTOR-FAIR RITE 34 INDUCTOR-470NH, , PANASONIC 35 INDUCTOR-6.8UH, , PANASONIC 36 INDUCTOR-FB, 133_100MHZ, FAIR RIA 37 LED-RED, PCB RIGHT ANGLE 38 LED10-RED, 25MA, 2.1V 39 MOLEX_8981_4R-BASE 40 MRT_PLCC-BASE 41 OSC_TTL_DIP34.368MHZ, 25 PPM 42 OSC_TTL_DIP44.736MHZ, 20 PPM 43 OSC_TTL_DIP50.0000MHZ, 100 PPM 44 OSC_TTL_DIP6.312MHZ , 25 PPM 45 Push Button Normally Open-BASE 46 PE65969-BASE 47 PI5C16212 48 RESISTOR-1.0K, 5%, 805
DIGI-KEY - PCC820CGCT- C70, C109, C113 ND 51-24-1040 U1, U6 DIGI-KEY - ZM4732ACT-ND D5 DIGI-KEY - ZM4735ACT-ND D4 DIGIKEY -- F1144TR-ND DIGIKEY -- F1146TR-ND DIGI-KEY S1011-36-ND DIGI-KEY S1011-36-ND DIGI-KEY S2012-36-ND FAIR RITE 2743019447 F1 F2 J3 JP1
J2 L1, L2, L4, L5, L8-L15, L20L22 DIGI-KEY PCD1216CT-ND L6, L16, L18 DIGI-KEY - PCD1071CTND FAIR RITE - 2743002112 DIGI-KEY - LU20091-ND L7, L17, L19 L3 D1, D2 U7 J1 U28 Y3 Y2 Y1 Y4 SW2 T1-T6 U3, U4, U15, U17, U18 R59, R70, R71, R75, R99R102
DIGI-KEY - LT1066-ND MOLEX 8981_4R TXC-02050-AIPL MMD Components MA025H-34.368MHZ MMD Components MA020H-44.736MHZ MMD Components MA100H-50.000MHZ MMD Components MA025H-6.312MHZ DIGIKEY - CKN4002-ND PE65969 Pericom PI5C16212A DIGI-KEY - P1,0KACT-ND
27 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
NO.
Description
Part Number
Reference Description
R34 R57, R79, R81
Qty
1 3 1 1 2 2 2 2 28
49 RESISTOR-100, 5%, 805 DIGI-KEY - P100ACT-ND 50 RESISTOR-100K, 1%, DIGI-KEY - P100KCCT-ND 805 51 RESISTOR-10K, 5%, 805 DIGI-KEY - P10KACT-ND 52 RESISTOR-270, 5%, 805 DIGI-KEY - P270ACT-ND 53 RESISTOR-120,5%,805 DIGI-KEY - P120ACT-ND 54 RESISTOR-180,5%,805 DIGI-KEY - P180ACT-ND 55 RESISTOR-301, 1%, 805 DIGI-KEY -- P301CCT-ND 56 RESISTOR-36, 5%, 805 DIGI-KEY - P36ACT-ND 57 RESISTOR-51,5%,805 DIGI-KEY - P51ACT-ND
R10 R23 R15,R18 R14,R17 R92, R94 R67, R68 R19,R21,R22, R24-R33, R35-R43,R83, R104, R111, R151-R153 58 RESISTOR-4.7K, 5%, DIGI-KEY - P4.7KACT-ND R1, R3-R6, R11-R13, R49, 805 R61, R87-R90, R103, R108R110, R134-R140, R142R150, R180-R182 59 RESISTOR-422, 1%, 805 DIGI-KEY - P422CCT-ND R62, R91, R93 60 RESISTOR-470, 5%, 805 DIGI-KEY - P470ACT-ND R65 61 RESISTOR-5.23K, 1%, DIGI-KEY - P5.23KCCT-ND R84, R86 805 62 RESISTOR-6.04K, 1%, DIGI-KEY -- P6.04KCCT-ND R58, R80, R82 805 63 RESISTOR-604, 1%, 805 DIGI-KEY - P604CCT-ND R64 64 RESISTOR-6K81, 1%, DIGI-KEY -- P6.81KCCT-ND R60 805 65 RESISTOR-75, 5%, 805 DIGI-KEY - P75ACT-ND R2,R7-R9,R16, R20,R44R48, R50-R56,R63, R72R74, R76-R78,R85, R112R117,R162, R163,R176 66 RESISTOR-75.0, 1%, DIGI-KEY -- P75.0CCT-ND R66, R69, R95-R98 805 67 RES_ARRAY_15_SMD- DIGI-KEY -- 766-161RN1, RN2 10K R10KND 68 RES_ARRAY_8_SMDDIGI-KEY -- 766-163-R270- RN4 270 ND 69 RES_ARRAY_8_SMDDIGI-KEY -- 766-163-R4.7K- RN3 4.7K ND 70 RES_ARRAY_8_SMD-68 DIGI-KEY-- 66-163-R68-ND RN17-RN20 71 SUNI_QJET_SBGAPM7346 U14 BASE 72 TST_PT-BASE DIGI-KEY S1011-36-ND TP1-TP9, TP87-TP95 73 WB1010-BASE Coilcraft WB1010SM U23, U32
37
3 1 2 3 1 1 35
6 2 1 1 4 1 18 2
28 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
10
SCHEMATICS
29 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
11
LAYOUT
30 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
12
APPENDIX A: FRAMING FORMATS This appendix presents relevant framing formats used in this reference design. The G.704 J2 standard specifies transmission at 6312 kbps with a 789 bit frame structure. The frame is divided into 98 byte time slots with 5 framing bits to end each frame. Four such structures are combined to create a J2 superframe. This structure is illustrated in Figure 4 below. Figure 4 - J2 Frame Format 125 s TS 1 - TS96 (96 Octets) TS 1 - TS96 (96 Octets) TS 1 - TS96 (96 Octets) TS 1 - TS96 (96 Octets) TS97 TS97 TS97 TS97 TS98 TS98 TS98 TS98 11 10 x1 x2 e1 e2 0 1 x3 e3 0 0 a e4 m 0 m e5
The E3 standard specifies a 34.368 Mbit/sec transmission rate. Both the G.751 and G.832 E3 specifications for frame formats are supported by the S/UNI-QJET. These frame formats are shown in Figures 5 and 6 respectively. Figure 5
1 1 1 1 0 1 0
- G.751 E3 Frame Format
0 0 0 RAI Na
C C C C 11 2 31 41 1 C C C C 12 22 32 42 C C C C 13 23 33 43 J 1 J 2 J 3 J 4
372 Payload bits 380 Payload bits 380 Payload bits 376 Payload bits
31 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
Figure 6
- G.832 E3 Frame Format 59 columns
FA1 FA2 EM TR MA NR GC
530 octet payload
9 r o w s
The S/UNI-QJET is also compatible with C-bit parity and M23 DS3 frame formats operating at 44.736 Mbit/sec. Both frame formats use a common structure shown in Figure 7 below, with the differences being in the use of the C overhead bits. Figure 7 - DS-3 Frame Format
84 bits M-subframe 1 X 1 M-subframe 2 X 2 M-subframe 3 P 1 M-subframe 4 P 2 M-subframe 5 M1 M-subframe 6 M2 M-subframe 7 M3 F1 F1 F1 F1 F1 F1 F1 84 bits C1 C1 C1 C1 C1 C1 C1 84 bits F2 F2 F2 F2 F2 F2 F2 84 bits C2 C2 C2 C2 C2 C2 C2 84 bits F3 F3 F3 F3 F3 F3 F3 84 bits C3 C3 C3 C3 C3 C3 C3 84 bits F4 F4 F4 F4 F4 F4 F4 84 bits
32 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
NOTES
33 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use
PM7346 S/UNI-QJET
REFERENCE DESIGN PMC-980182 ISSUE 2 S/UNI-QJET REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Web Site:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PM-980182 Issue date: January 1999
PMC-Sierra, Inc.
105 - 8555 Baxter Place Burnaby, BC Canada V5A 4V7 604 .415.6000 Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers' Internal Use

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