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| PMC-Sierra,Inc. PM5349 S/UNI-155-QUAD Quad 155 Mb/s ATM Physical Layer Device FEATURES * Quad-channel ATM OC-3c (155 Mb/s) PHY. * Provides on-chip clock and data recovery and clock synthesis. * Exceeds Bellcore-GR-253 jitter requirements. * Provides a generic 8-bit microprocessor interface for device control and register access. * Provides standard IEEE 1149.1 JTAG test port for boundary scan. * Counts received section BIP-8 (B1), line BIP-24 (B2), and BIP-8 (B3) errors, and line and path FEBEs. * Detects LOS, OOF, LOF, LAIS, LRDI, LOP, PAIS, PRDI, and PERDI. * Provides individual divide by eight recovered clocks for each channel. * Provides individual 8 kHz receive frame pulses for each channel. ATM PROCESSOR * Implements the ATM Forum User Network Interface Specification. * Inserts and extracts ATM cells into and from the SONET SPE. * Performs cell payload scrambling and descrambling. * Provides a UTOPIA Level 2-compliant system interface. * Provides synchronous 4-cell transmit and receive FIFO buffers. SONET TRANSMITTER * Synthesizes the 155.52 MHz transmit clock from a 19.44 MHz reference. * Provides a single transmit frame pulse input to align the transport frames to a system reference. * Provides single transmit clock as timing reference for transmit outputs. * Inserts register programmable APS (K1 and K2) and synchronization status (S1) bytes. * Inserts PAIS, PRDI, LAIS, and LRDI. * Scrambles the transmit data stream. PACKAGING * Implemented in low power 3.3 V CMOS technology. * Packaged in a 304-pin Ball Grid Array (BGA) package. * Industrial temp. range (-40 to +85C). SONET RECEIVER * Recovers clock and data. * Frames to and descrambles recovered stream. * Filters and captures Automatic Protection Switch (APS) byes (K1, K2) and detects APS byte failure. * Detects signal degrade and signal failure threshold crossing alarms. * Captures and debounces synchronization status byte (S1). APPLICATIONS * Enterprise and Edge ATM Switches * ATM Switches and Hubs * Multiprotocol Switches JTAG Test Access Port DTCA[4:1] TDAT[15:0] TPRTY TXD[4:1]+ TXD[4:1]TSOC UTOPIA Level 2 System Interface Transmit Line Interface Transmit Section Transmit Line O/H Processor O/H Processor Transmit Path O/H Processor Transmit ATM Cell Processor TRSTB TFPO TCLK TFPI TDI TMS TDO TCK BLOCK DIAGRAM TCA TADR[4:0] TENB TFCLK PHY_OEN RFCLK RENB RADR[4:0] RCA RSOC RPRTY ATB[3:0] REFCLK RXD[4:1]+ RXD[4:1]SD[4:1] Receive Line Interface Receive Section Receive Line O/H Processor O/H Processor Receive Path O/H Processor Receive ATM Cell Processor Receive APS, Sync, BERM Microprocessor Interface RDAT[15:0] DRCA[4:1] RALRM[4:1] RCLK[4:1] D[7:0] RFPO[4:1] A[10:0] ALE CSB WRB RDB RSTB PMC-980863 (R3) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1999 PMC-Sierra, Inc. INTB PM5349 S/UNI-155-QUAD Quad 155 Mb/s ATM Physical Layer Device TYPICAL APPLICATION STS-3c (STM-1) ATM SWITCH PORT APPLICATION UTOPIA Level 2 Interface ATM Layer Device PM5349 681,48$'A Quad 155 Mb/s ATM Physical Layer Device TxClk TxEnb TxAddr[4:0] TxClav TxSOC TxPrty TxData[15:0] RxClk RxEnb RxAddr[4:0] RxClav RxSOC RxPrty RxData[15:0] TFCLK TENB TADR[4:0] TCA TSOC TPRTY TDAT[15:0] RFCLK RENB RADR[4:0] RCA RSOC RPRTY RDAT[15:0] RX1+/SD1 TXD1+/Optical Transceiver RX2+/SD2 TXD2+/Optical Transceiver RX3+/SD3 TXD3+/Optical Transceiver RXD4+/SD4 TXD4+/Optical Transceiver Head Office: PMC-Sierra, Inc. #105 - 8555 Baxter Place Burnaby, B.C. V5A 4V7 Canada Tel: 604.415.6000 Fax: 604.415.6200 To order documentation, send email to: document@pmc-sierra.com or contact the head office, Attn: Document Coordinator All product documentation is available on our web site at: http://www.pmc-sierra.com For corporate information, send email to: info@pmc-sierra.com PMC-980863 (R3) 1999 PMC-Sierra, Inc. August, 1999 SATURN and S/UNI-155-QUAD are trademarks of PMC-Sierra, Inc. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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