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PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA PM5349 S/UNI- (R) 155-QUAD S/UNI-QUAD SATURN USER NETWORK INTERFACE (155-QUAD) ERRATA PRELIMINARY ISSUE 3: JUNE 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA REVISION HISTORY Issue No. 3 Issue Date June 1999 Jan 1999 Details of Change This document contains errata information corresponding to the issue 5 data sheet and device revision E. This document contains errata information corresponding to the issue 5 data sheet and device revision C. 2 1 Nov 1998 This document contains errata information corresponding to the issue 4 data sheet and device revision C. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA CONTENTS 1 ISSUE 3 ERRATA ..................................................................................... 1 1.1 2 3 DEVICE IDENTIFICATION............................................................. 1 S/UNI-QUAD FUNCTIONAL DESCREPANCIES...................................... 2 S/UNI-QUAD DATASHEET DISCREPANCIES.......................................... 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 PAGE 49 INCORRECT LINE AIS INSERT DESCRIPTION ........... 3 PAGE 137 INCORRECT EPRDISRC AND EPRDIEN DESCRIPTION .............................................................................. 3 PAGE 147 INCORRECT G[1:0] DESCRIPTION ............................ 4 PAGE 147 INCORRECT PRDI DESCRIPTION ............................. 4 PAGE 161 INCORRECT BIT 4 (PSLMPRDI) IN 0X91 (CHANNEL AUTO PATH RDI CONTROL) DESCRIPTION................................ 4 PAGE 163 INCORRECT BIT 4 IN 0X92 (CHANNEL AUTO ENHANCED PATH RDI CONTROL) DESCRIPTION ..................... 4 PAGE 165 INCORRECT BIT 1,0 AND EPRDI_EN ONLY WRITE ONLY IN 0X93 (CHANNEL RECEIVE RDI AND ENHANCED RDI CONTROL EXTENSIONS) ............................................................ 5 PAGE 167 INCORRECT BIT 4 AND 5 IN 0X95 (CHANNEL RECEIVE PATH AIS CONTROL) DESCRIPTION.......................... 5 PAGE 171 INCORRECT BIT 5 IN 0X96 (CHANNEL RECEIVE ALARM CONTROL #1) .................................................................. 6 PAGE 188 INCORRECT LOPCONPRDI DESCRIPTION .............. 6 PAGE 204 INCORRECT BIT 7 Z1/S1_CAP DESCRIPTION IN 0X95 (RASE CONFIGURATION/CONTROL) ................................ 6 PAGE 229 INCORRECT PATH OVERHEAD BYTE H4 DESCRIPTION .............................................................................. 7 PG. 263 REVISED TFPI SETUP AND HOLD TIMES..................... 8 3.8 3.9 3.10 3.11 3.12 3.13 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA 3.14 PG. 30 REVISED PIN DESCRIPTION NOTES.............................. 9 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA 1 ISSUE 3 ERRATA This issue 3 contains errata applied to the PMC-971239 S/UNI-QUAD Issue 5 datasheet. The issue 5 datasheet and issue 3 errata supersede all prior editions and versions 1.1 Device Identification The information contains in this document applies to the PM5349 S/UNI-QUAD revision E device only. The device revision code is marked at the end of the Wafer Batch Code on the face of the device (as shown in Figure 1). PM5349 S/UNI-QUAD revision E is packaged in a 304 pin Super BGA package. Figure 1: PM5349 S/UNI-QUAD Branding Format Pin A1 Index Mark PMC Logo S/UNI QUAD Logo S/UNI155-QUAD TOP VIEW SCALE: 2:1 (APPROX) R Part Number Wafter Batch Code Assembly Date Code PM5349-BI-P C E Myyww PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA 2 S/UNI-QUAD FUNCTIONAL DESCREPANCIES There are no known functional deficiencies for Revision E of S/UNI-QUAD (as of the publication date of this document). Please report any functional deficiencies to PMC-Sierra. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: App Support: Fax: (604) 415-6000 (604) 415-4533 (604) 415-6001 Product information: info@pmc-sierra.com Applications information: apps@pmc-sierra.com Web Site: http://www.pmc-sierra.com PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA 3 S/UNI-QUAD DATASHEET DISCREPANCIES This section lists known documentation errata with regards to issue 5 of the S/UNI QUAD datasheet. Legend 1. unaltered text is unchanged to add context to changes 2. new material is bold and Italicized 3. obsolete material is struck out 4. comments specific to this document are in italics 5. A vertical bar in left margin indicates that this is a new item which was not present in the previous issue of this document. 3.1 Page 49 Incorrect Line AIS Insert Description Line AIS insertion results in all bits of the SONET/SDH frame being set to 1 before scrambling except for the section overhead. The Line AIS Insert Block substitutes all ones as described when enabled by the TLAIS input or through an internal register (Reg 0x14 TSOP) accessed through the microprocessor interface. Activation or deactivation of line AIS insertion is synchronized to frame boundaries. 3.2 Page 137 Incorrect EPRDISRC and EPRDIEN Description EPRDISRC The enhanced path receive defect indication alarm source bit (EPRDISRC) controls the source of RDI input to be inserted onto the G1 byte. When EPRDIEN is logic zero, this bit is ignored. When EPRDIEN is logic zero, the extended RDI bits of the G1 byte are always inserted according to value in register 0x49 bits G1[1:0]. When EPRDIEN is logic one and EPRDISCR is logic zero, the extended RDI bits of the G1 byte, bits 6 and 7, are inserted according to the value in the G1[1:0] register bits (register 0x49). When EPRDIEN is logic one and EPRDISCR is logic one, the value in register 0x49 G1[1:0] is ignored and the EPRDI bits in the G1 byte are set according to the setting of the Channel Auto Enhanced Path RDI Control registers (0x92 and 0x93). EPRDIEN The enhanced path receive defect indication alarm enable bit (EPRDIEN) controls the use of 3-bit RDI mode. When EPRDIEN is set to logic 0, the basic path RDI scheme is used and only G1[5] is used to indicate PRDI and the value of the G1 byte, bits 6 and 7 are PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA controlled by the G1[1:0] register bits (register 0x49). When EPRDIEN is set to logic 1, the enhanced path RDI scheme is used and the three G1[7:5] bits are used to indicate PRDI. The actual three bit code will be controlled according to the EPRDISRC. 3.3 Page 147 Incorrect G[1:0] Description G[1:0]: The G1[1:0] bits are inserted in bits 1 and 2 of the path status byte G1. These bits are ignored when EPRDIEN is logic zero or when EPRDIEN and EPRDISRC are both logic one. These bits are ignored when EPRDIEN and EPRDISRC are both logic one. See the description of EPRDIEN and EPRDISRC for more details on how G1 can be controlled. 3.4 Page 147 Incorrect PRDI Description PRDI: The PRDI bit controls the insertion of the path remote defect indication. When a logic one is written to this bit position, the PRDI bit position in the path status byte is set high. When a logic zero is written to this bit position, the PRDI bit position in the path status byte is set low. This bit is ignored when EPRDIEN is logic zero or when EPRDIEN and EPRDISRC are both logic one and the PRDI bit in the G1 byte (bit 6) is set according to the setting of the Channel Auto Enhanced Path RDI Control registers (0x92 and 0x93). 3.5 Page 161 Incorrect Bit 4 (PSLMPRDI) in 0x91 (Channel Auto Path RDI Control) Description Register 0x91: S/UNI-QUAD Channel Auto Path RDI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 3.6 Type R/W R/W R/W R/W R/W R/W R/W R/W Function LCDPRDI ALRMPRDI PAISPRDI PSLMPRDI Reserved LOPPRDI LOPCONPRDI Reserved Reserved Default 0 0 1 1 1 1 1 1 Page 163 Incorrect Bit 4 in 0x92 (Channel Auto Enhanced Path RDI Control) Description Register 0x92: S/UNI-QUAD Channel Auto Enhanced Path RDI Control PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 BIT 0 TYPE R/W R/W R/W R/W R/W R/W R/W R/W FUNCTION LCDEPRDI NOALMEPRDI NOPAISEPRDI PSLMEPRDI Reserved NOLOPEPRDI NOLOPCONEPRDI Reserved Reserved DEFAULT 0 0 0 1 0 0 0 1 3.7 Page 165 Incorrect Bit 1,0 and EPRDI_EN only write only in 0x93 (Channel Receive RDI and Enhanced RDI Control Extensions) Register 0x93: S/UNI-QUAD Channel Receive RDI and Enhanced RDI Control Extensions BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TYPE R/W R/W FUNCTION PAISCONPRDI NOPAISCONEPRDI Unused Unused Unused EPRDI_EN UNEQPRDI Reserved UNEQEPRDI Reserved DEFAULT 0 0 X X X 0 1 1 W R/W R/W EPRDI_EN was indicated as a Read/Write bit. It is Write only bit. 3.8 Page 167 Incorrect Bit 4 and 5 in 0x95 (Channel Receive Path AIS Control) Description Register 0x95: S/UNI-QUAD Channel Receive Path AIS Control PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA BIT Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TYPE R/W R/W R/W R/W R/W R/W R/W R/W FUNCTION PAISCONPAIS LOPCONPAIS PSLUPAIS Reserved PSLMPAIS Reserved LOPPAIS PAISPAIS Reserved Reserved DEFAULT 1 1 1 1 1 1 1 1 3.9 Page 171 Incorrect Bit 5 in 0x96 (Channel Receive Alarm Control #1) Register 0x96: S/UNI-QUAD Channel Receive Alarm Control #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W Function Unused Reserved PSLMEN Reserved PERDIEN PRDIEN PAISEN LCDEN LOPEN Default X 0 0 0 0 0 0 0 3.10 Page 188 Incorrect LOPCONPRDI Description The Loss of Pointer Concatenation Indication PRDI (LOPCONPRDI) controls the insertion of a Path RDI in the transmit data stream upon detection of this alarm condition. When LOPCONPRDI is set to logic zero one, the transmit line RDI will be inserted. When LOPCONPRDI is set to logic zero, no action is taken. This register bit has effect only if the AUTOPRDI register bit is also set to logic one. 3.11 Page 204 Incorrect Bit 7 Z1/S1_CAP description in 0x95 (RASE Configuration/Control) Z1/S1_CAP: The Z1/S1_CAP bit enables the Z1/S1 Capture algorithm. When Z1/S1_CAP is a logic one, the Z1/S1 clock synchronization status message nibble must have the same value for three eight consecutive frames before writing the new value into the RASE Receive Z1/S1 register. When Z1/S1_CAP is logic zero, the Z1/S1 nibble value is written directly into the RASE Receive Z1/S1 register. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA 3.12 Page 229 Incorrect Path overhead byte H4 description H4: The multiframe indicator byte is a payload specific byte, and is not used for ATM payloads. This byte is forced to 0x00 in the transmit direction, and is ignored in the receive direction. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA 3.13 Pg. 263 Revised TFPI Setup and Hold times Table 1: Transmit and Receive Frame Pulse Timing (Figure 1) Symbol tSTFPI tHTFPI tPTFPO tPRFPO Description TFPI Set-up Time to TCLK High TFPI Hold Time to TCLK High TCLK High to TFPO Valid RCLK1-4 High to RFPO1-4 Valid Min 10 15 10 0 0 0 Max Units ns ns 10 10 ns ns Figure 1: Transmit and Receive Frame Pulses TC LK tS TF P I tH TF P I TF P I tP T FPO T FP O R C LK 1-4 tP R F P O R FP O 1-4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA 3.14 Pg. 30 Revised Pin description notes 2. The RDAT[7:0], RPRTY, RSOC, RCA, TCA, TCLK and RCLK1-4 outputs have a 16 4 mA drive capability. All other output pins have a 2 mA drive capability. The TXD+ and TXD- outputs should be terminated in a passive network and interface at PECL levels. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PRELIMNARY ERRATA PMC-981005 ISSUE 3 PM5349 S/UNI-QUAD S/UNI-QUAD DATASHEET ERRATA CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 Document Information: document@pmc-sierra.com Corporate Information: info@pmc-sierra.com Application Information: apps@pmc-sierra.com (604) 415-4533 Web Site: http://www.pmc-sierra.com None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1998, 1999 PMC-Sierra, Inc. PMC-981005 (P3) ref PMC-971239 (R5) Issue date: May 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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