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| PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN PM7390 S/UNI-MACH48 REFERENCE DESIGN ISSUE 2:FEBRUARY 2001 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN PUBLIC REVISION HISTORY Issue No. 1 2 Issue Date May 2000 Feb 2001 Details of Change Document created Section 6: Modify block diagram to reflect actual layout Section 7.1.4: Include recommendation to use series source termination resistors based on simulation graph. Section 7.2.3: Added FPGA UL3/PL3 timing section. Added note on FPGA selection Section 7.2.8: Updated FPGA Register Descriptions Section 8.2.3: Added HS3 Pinout Section 13: Remove EEPROM code table. 2 Update schematics. Page 2: Added 44.736 MHz clock to DS3TICLK pin, which is required for DS3 applications. Page 6: Add PLX_EN output from FPGA to control PCI9054 reset state. This allows code to download from SPROM prior to PCI9054 coming out of reset. Page 7: Change clocking of TFCLK to run directly from buffer and not from FPGA. This eliminates unnecessary delay in the clock line. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN CONTENTS 1 2 3 4 5 DEFINITIONS .......................................................................................... 1 FEATURES .............................................................................................. 2 APPLICATIONS ....................................................................................... 3 REFERENCES......................................................................................... 4 APPLICATION EXAMPLES ..................................................................... 5 5.1 5.2 6 7 CHANNELIZED ROUTER/ATM SWITCH PORT CARD ............... 5 MULTI-SERVICE ADMS AND SWITCHES ................................... 6 BLOCK DIAGRAM ................................................................................... 7 FUNCTIONAL DESCRIPTION................................................................. 8 7.1 S/UNI MACH48 ............................................................................. 9 7.1.1 777.6 MBPS LVDS SERIAL TELECOMBUS ...................... 9 7.1.2 PARALLEL TELECOMBUS INTERFACE ......................... 10 7.1.3 TIME SLOT INTERCHANGE.............................................11 7.1.4 UL3/PL3 INTERFACE ...................................................... 12 7.2 FPGA .......................................................................................... 14 7.2.1 SYSCLK CLOCK SOURCE SELECTION ........................ 15 7.2.2 UTOPIA/POS-PHY LEVEL 3 INTERFACE ....................... 16 7.2.3 UL3/PL3 BUS TIMING...................................................... 17 7.2.4 UL3/PL3 SOURCE/DESTINATION SELECT ................... 20 7.2.5 TYPICAL UL3/PL3 BUS LAYOUT .................................... 22 7.2.6 WORKING/PROTECTION DATA LINK SELECTION ....... 23 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.7 CONNECTION MEMORY PAGE SELECTION................. 24 7.2.8 MICROPROCESSOR INTERFACE.................................. 24 1.1.1 FPGA................................................................................ 25 7.2.9 REGISTER DESCRIPTION.............................................. 25 7.3 COMPACTPCI INTERFACE........................................................ 28 7.3.1 INTERFACE AND BRIDGE HARDWARE......................... 28 7.3.2 HOT SWAP CAPABILITY ................................................. 29 7.4 8 POWER SUPPLY........................................................................ 30 IMPLEMENTATION DESCRIPTION ...................................................... 31 8.1 8.2 SHEET 1, ROOT DRAWING....................................................... 31 SHEET 2,3,4,5 MACH48 BLOCK................................................ 31 8.2.1 SHEET 2: MICROPROCESSOR INTERFACE................. 31 8.2.2 SHEET 3: UTOPIA/POS-PHY LEVEL 3 INTERFACE ...... 31 8.2.3 SHEET 4: SERIAL TELECOMBUS INTERFACE ............. 31 8.2.4 PORT RE-MAPPING OF SERIAL TELECOMBUS ........... 32 8.2.5 SHEET 5:S/UNI MACH48 POWER BLOCK..................... 35 8.3 SHEET 6,7 FPGA BLOCK........................................................... 36 8.3.1 SHEET 6: FPGA BLOCK .................................................. 36 8.3.2 SHEET 7: UL3/PL3 BUS SWITCHING BLOCK................ 36 8.4 8.5 SHEET 9 SYSTEM INTERFACE BLOCK ................................... 36 SHEET 9,10 COMPACTPCI BLOCK........................................... 36 8.5.1 SHEET 9: I/O ACCELERATOR BLOCK ........................... 36 8.5.2 SHEET 11: COMPACTPCI CONNECTOR ....................... 37 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 8.6 9 10 11 SHEET 12, POWER SUPPLY AND HOT SWAP CONTROLLER BLOCK ........................................................................................ 37 SCHEMATICS........................................................................................ 39 LAYOUT ................................................................................................. 40 BILL OF MATERIALS............................................................................. 41 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN LIST OF FIGURES FIGURE 1 -ROUTER/ATM SWITCH PORT CARD ........................................... 5 FIGURE 2 MULTI-SERVICE SWITCH USING S/UNI MACH48 DEVICE.......... 6 FIGURE 3 - S/UNI MACH48 REFERENCE DESIGN BLOCK DIAGRAM ......... 7 FIGURE 4 - BOARD LAYOUT OF S/UNI MACH48 REFERENCE DESIGN ..... 8 FIGURE 5 - S/UNI MACH48 SERIAL LVDS LAYOUT ....................................... 9 FIGURE 6 - TYPICAL PARALLEL TELECOMBUS INTERFACE .................... 10 FIGURE 7 - HYPERLYNX SIMULATIONS ON 4" 50 TRACE ...................... 13 FIGURE 8 - FPGA LOGIC ............................................................................... 14 FIGURE 9 - FPGA CLOCK SOURCE SELECT FUNCTIONAL BLOCK.......... 15 FIGURE 10-LOOPBACK MODE FOR FPGA/UL3/PL3 INTERFACE ............... 16 FIGURE 11 - UL3/PL3 BUS TIMING: RECEIVE AT FPGA ............................... 17 FIGURE 12- UL3/PL3 BUS TIMING: TRANSMIT AT FPGA ............................. 18 FIGURE 13- TIMING ON UL3/PL3 RECEIVE BUS (VIRTEXE / APEX20KE) .. 19 FIGURE 14-UTOPIA/POS-PHY INTERFACE SWITCHING............................. 21 FIGURE 15-POINT TO POINT UL3/PL3 INTERCONNECT............................. 22 FIGURE 16- MULTIPLE SOURCES FOR RWSEL .......................................... 23 FIGURE 17-FPGA/MICROPROCESSOR INTERFACE ................................... 24 FIGURE 18-COMPACTPCI BLOCK DIAGRAM. .............................................. 28 FIGURE 19- POWER SUPPLY BOARD SYSTEM BLOCK.............................. 30 FIGURE 20- TBS-MACH48 LVDS INTERCONNECTIONS.............................. 33 FIGURE 22- ROUTING WITH SOFTWARE RE-MAPPING ............................. 34 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN LIST OF TABLES TABLE 1 TABLE 2: TABLE 3 TABLE 4 TABLE 5 TABLE 6 UTOPIA/POS-PHY L3 SWITCHING TRUTH TABLE..................... 21 TRUTH TABLE FOR SYSCLK SWITCHING ................................. 27 PINOUT OF S-TCB HS3 CONNECTOR........................................ 32 STS-12 PORT REMAPPING FOR S-TCB ..................................... 34 S/UNI MACH48 TYPICAL POWER CONSUMPTION.................... 35 BILL OF MATERIALS..................................................................... 41 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE v PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 1 DEFINITIONS APS ATM CPCI FPGA LVDS POS PRBS S-TCB UL3/PL3 Automatic Protection Switching Asynchronous Transfer Mode Compact PCI. An adapted specification from the Peripheral Component Interconnect (PCI) Specification 2.1 or later. Field Programmable Gate Array Low Voltage Differential Signal Packet Over SONET Pseudo Random Bit Sequence Serial Telecombus UTOPIA Level 3/POS-PHY Level 3 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 2 FEATURES The S/UNI-MACH48 reference design represents only a subset of the MACH48's functional capabilities. The following features are supported in this reference design: * * * * * * * * 777.6 Mbps LVDS Serial Telecombus User selectable between Utopia Level 3 and the POS-PHY Level 3 interface An on board FPGA that allows the user to loopback the UL3/PL3 for testing and evaluation. A CompactPCI interface that allows the user to control and monitor the MACH48 and on board FPGA. The ability to switch between an on-board system clock (77.76 MHz) for standalone testing and an off-board clock for system integration. Selection of either Working or Protect Serial Telecombus (S-TCB) link data. User selectable Time Slot Interchange blocks for input and output. User selectable UL3/PL3 interface clock (100MHz) from on-board (master) or off-board (slave). source PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 3 APPLICATIONS * * Channelized Router/ATM Switch Port Card Multi-service ADMs and Switches PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 4 REFERENCES 1. ATM Forum, ATM User Network Interface Specification, V3.1, September 1994. 2. PMC-1990823, S/UNI MACH48 Data Sheet Issue 2, December 1999. 3. 1030-54000-DTB, PCI 9054 Data Book Version 1.0, November 1998 4. AF-PHY-0136.000, ATM Forum, Utopia 3 Physical Layer Interface, V1.0, November 1999. 5. PICMG 2.0 CompactPCI Specification, R2.1, September 1997. 6. PMC-1991797, CHESS Users Guide, Issue 2, May 2000. 7. PMC-2000299, 777.6 MHz LVDS Serial Telecombus Design Considerations, Issue 1, March 2000. 8. PMC-1980495, POS-PHY Level 3, Issue 4, April 2000. 9. PMC-2000021, CHESS Reference Design Hardware Manual, Dec 2000. 10. Johnson, Howard, "High Speed Digital Design: A Handbook of Black Magic", Prentice Hall, 1993. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 5 APPLICATION EXAMPLES The S/UNI-MACH48 is one component in PMC-Sierra's CHESS (CHannelized Engine for SONET/SDH) family of high speed network devices. The following are but a few examples of how the S/UNI MACH48 reference design can be used. 5.1 Channelized Router/ATM Switch Port Card The S/UNI MACH48 Reference Design can be used to implement a multi-service port card configuration as seen in Figure 1. SONET traffic is transferred via the OC-48 optical interface of the SPECTRA-TBS card. On the ingress, payload is extracted and passed to the TBS where the data is serialized and passed to the S/UNI MACH48. The S/UNI MACH48 will perform cell/packet delineation. On the egress, the S/UNI MACH48 performs cell/packet insertion. The TBS then deserializes the data and transfers it to the SPECTRA for insertion into a SONET frame. The auxiliary and protection data streams can be used for protection switching redundancy. Figure 1 -Router/ATM Switch Port Card SPECTRA-2488 with TBS CARD S/UNI MACH48 CARD UL3/PL3 LVDS x 4 OPTICS SPECTRA 2488 TBS S-TCB AUX PROT PROT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 5.2 Multi-service ADMs and Switches Figure 2 below illustrates a multi-service switch. This example shows only one part of a larger switch. In practice the TSE core card would consist of multiple TSE devices that would comprise a large switch core. Multiple SPECTRA-TBS line cards would also be used to create a protection switching architecture. Figure 2 Multi-Service Switch using S/UNI MACH48 Device SPECTRA-2488 with TBS CARD TSE FABRIC CARD PM5310 TBS PM5372 TSE OC-48 OPTICS PM5315 SPECTRA 2488 S-TCB S-TCB AUX PROT S/UNI MACH48 CARD S-TCB UL3/PL3 UL3/PL3 ATM/IP LAYER PROCESSOR TRAFFIC MANAGER (TM) LCS2 PROT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 6 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 6 BLOCK DIAGRAM Figure 3 - S/UNI MACH48 Reference Design Block Diagram FPGA_TDAT(31..0)/ T_CONTROL FPGA_RDAT(31..0)/ R_CONTROL 8x24 BIT CMOS SWITCHES SWITCH_CONTROL 77.76 MHz Oscillator OJ0REF FP(RJ0FP) SYSCLK RWSEL ICMP OCMP SYSCLK1 SYSCLK2 FPGA CON_RDAT(31..0)/ R_CONTROL uP CONTROL PCI CONTROL SIGNALS DATA BUS ADDRESS BUS CLOCK SWITCH TFCLK RFCLK 100 MHz Oscillator & Driver PROTECTION SERIAL LINKS WORKING SERIAL LINKS SYSCLK1 SYSCLK2 RFCLK_OUT RFCLK_IN CPCI Connector J1 HS-3 Serial LVDS J3 HS-3 UL3/PL3 Receive J4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 TFCLK_OUT TFCLK_IN PLX9054 I/O ACCELERATOR PECLTTL Converter 1.8V REG & HOT SWAP CONTROLLER RWSEL XCMP RJ0FP TJ0FP HS-3 UL3/PL3 Transmit J5 CON_TDAT(31..0)/ T_CONTROL PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7 FUNCTIONAL DESCRIPTION This reference design is a 6U CompactPCI form factor board designed to demonstrate the features of the S/UNI-MACH48 Multi Service Access Device for CHannelized Interfaces. The board consists of a S/UNI MACH48 device, a FPGA for loopback, and a PCI bridge controller to interface with the PCI bus. There are connectors for interfacing to a CPCI backplane and a custom backplane. Figure 4 - Board Layout of S/UNI MACH48 Reference Design 233.35 mm 6U Format 1.8V SWITCHING REGULATOR 5 5 5 5 5 5 5 5 5 FPGA 5 5 5 5 5 5 5 5 5 3 3 3 3 3 3 160 mm HOT SWAP CONTROLLER PI3C16212 PI3C16212 PI3C16212 PI3C16212 PI3C16212 PI3C16212 PI3C16212 PI3C16212 PCI I/O ACCELERATOR J1_1 CPCI Connector UL3/PL3 Receive J7 UL3/PL3 Transmit J6 Serial Telecombus J5 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.1 S/UNI MACH48 7.1.1 777.6 Mbps LVDS Serial Telecombus The S/UNI-MACH48 has 2 sets of 8 serial LVDS data pairs (4 transmit, 4 receive) that operate at 777.6 Mbps. This rate is required for the 8B/10B encoding used to transfer data on each link at OC-12 rates (10/8 x 622.08 Mbps = 777.6 Mbps). One set of data links is the working data stream and the other is used as the protection data stream. The protection data stream is part of the Protection system architecture used RWSEL will select whether the working or protection ingress LVDS streams are processed. During normal operation, RWSEL will be controlled by the host system. However, the RWSEL signal can be modified at any time via the microprocessor interface. This will be explained in more detail below. Figure 5 - S/UNI MACH48 Serial LVDS Layout FPGA RJ0FP TJ0FP RWSEL RWSEL_IN TJ0FP_OUT RJ0FP_IN WORKING LVDS STREAM 50 OHM DIFFERENTIAL PAIRS MATCHED LENGTH PROTECTION LVDS STREAM AMP HS-3 CONNECTOR PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.1.2 Parallel Telecombus Interface The parallel telecombus is not used in the S/UNI MACH48 reference design but its application is illustrated below. The diagram shows a PM5315 SPECTRA2488 interfacing to a S/UNI MACH48 via the parallel telecombus. This is a point to point connection that is clocked at 77.76 MHz. Figure 6 - Typical Parallel Telecombus Interface Typical Parallel Telecombus Connection SYSCLK DDP<4..1> DPL<4..1> DJ0J1<4..1> DD<4..1><7..0> SYSCLK 77.76MHz SYSCLK IDP<4..1> IPL<4..1> IJ0J1<4..1> ID<4..1><7..0> PM5315 SPECTRA-2488 AD<4..1><7..0> ADP<4..1> APL<4..1> AJ0J1<4..1> PM7390 S/UNI-MACH48 OD<4..1><7..0> ODP<4..1> OPL<4..1> OJ0J1<4..1> PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.1.3 Time Slot Interchange The S/UNI MACH48 has the ability to rearrange system side and line side SONET/SDH timeslots. Both the ingress and egress buffer 48 timeslots and rearrange them as desired before outputting them. This feature allows the user to configure timeslot mappings, bypass timeslots, and use predefined mappings for standard Telecombus interfaces. The S/UNI-MACH48 can channelize data streams from STS-48/STM-16 down to STS-1/STM-0/DS3 granularity for a total aggregate bandwidth of 2.488 Gbps (1 STS-48/STM-16 stream). The S/UNI MACH48 reference design makes use of the TSI feature to simplify the PCB layout by re-mapping links in order to avoid crossovers. For a complete list of legal channel mappings, consult the S/UNI MACH48 Data Sheet (Reference 2). PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.1.4 UL3/PL3 Interface The S/UNI MACH48 implements a 32 bit ATM Forum specified UTOPIA Level 3 and POS-PHY Level 3 interface. The S/UNI MACH48 can be set to use either interface protocol. The UL3/PL3 interface can be clocked up to 104MHz. The reference design uses a 100MHz clock that can be selected from either the onboard source or from an off-board source. The line to system interface (RDAT) uses series source termination resistors to damp the driving signal. Figure 7, below, shows a Hyperlynx simulation using the IBIS models for the S/UNI MACH48 and the XC4036XLA. The simulation is based on a 4" long trace with 50 impedance. The value of the terminating resistor is 39 ohms. When not using a series termination, the receiver is subject to overshoot. Designers that do not intend to use termination resistors must ensure that the receiving device can tolerate the expected overshoot. It is recommended that a series source termination be used to reduce overshoot and improve signal integrity. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN Figure 7 - Hyperlynx Simulations on 4" 50 Trace Using S/UNI MACH48 IBIS Model and Xilinx XC4036XLA IBIS Model RDAT signal with no series termination 7.0 volts Overshoot ~ 2 VDC 1 V/div Driver Receiver 0.0 volts 0.0ns 1 nsec/div 10.0ns 7.0 volts RDAT signal with 39 Ohm termination 1 V/div Driver Receiver 0.0 volts 0.0ns 1 nsec/div 10.0ns Simulated 4" 50 Ohm Trace PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2 FPGA A Xilinx XC4036XLA FPGA performs several functions. These include: * * * * * * * * Figure 8 System Clock (77.76MHz) source selection Wire loopback on UTOPIA/POS-PHY Level 3 bus UTOPIA/POS-PHY L3 source/destination select UTOPIA/POS-PHY L3 clock (100MHz) source select Working/Protection Link select Input/Output Connection Memory Page select PCI to MACH control glue logic Reset control - FPGA Logic FPGA UTOPIA/POS-PHY L3 INPUTS UTOPIA/POS-PHY L3 OUTPUTS LOOPBACK ON-BOARD SYSCLK SYSCLK1 SYSCLK2 FP RWSEL_IN XCMP RESET SWITCH LRSTOB READYB L_WRB LADSB LCLK L_INTB LA<12..0> LD<15..0> SYSCLK CONTROL REG SYSCLK_OUT RJ0FP_OUT TJ0FP_OUT RWSEL_OUT ICMP OCMP MACH_RSTB BUS SWITCH PL3 CLK CTRL MACH_INTB MACH_CSB WRB RDB MACH CONTROL REG RESET REG uPROC LOGIC PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.1 SYSCLK Clock Source Selection The FPGA is used to select between an on-board 77.76 MHz source clock and an off-board 77.76 MHz differential clock source. The on board clock is used for S/UNI-MACH48 register access during initial testing and diagnostic loopback mode. SYSCLK is sourced from the TSE fabric card when used in the CHESS reference design Figure 9 - FPGA Clock Source Select Functional Block FPGA 77.76 TTL CLOCK (ONBOARD) 77.76 MHz Differential PECL Clocks From Backplane PECL-TTL CONVERTOR XOR SYSCLK2 Control Register selects between On-board and Off-board Clocks SYSCLK CONTROL REGISTER PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE MUX1 SYSCLK1 MUX2 SYSCLK 15 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.2 UTOPIA/POS-PHY Level 3 Interface The UL3/PL3 interface can be used in two modes on the S/UNI MACH48 reference design. The UL3/PL3 interface can be switched onto the FPGA to accommodate a loopback mode or to the off board HS-3 connectors to interface with other CHESS UL3/PL3 compliant devices In loopback mode, the FPGA will directly route the TXPHY inputs to the RXPHY outputs. This will allow the user to loopback any data input to the S/UNI MACH48 from the LVDS inputs to the LVDS outputs. Figure 10 -Loopback Mode for FPGA/UL3/PL3 Interface LOOPBACK MODE FPGA UL3/PL3 INTERFACE SERIAL LVDS LINKS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.3 UL3/PL3 Bus Timing The bus timing for the loopback interface is show below in Figure 11 and Figure 12. Each figure shows the required setup and hold time for the S/UNI MACH48 and the XC4036XLA. The Tco for the S/UNI MACH48 UL3/PL3 Receive bus is specified in a range from 1.5 to 6 ns. Using a 100 MHz oscillator and calculating the trace delay for the longest and shortest trace with respect to the clock, we get the following waveform relationships below. Figure 11 - UL3/PL3 Bus Timing: Receive at FPGA 0ns 10ns 20ns 30n s mach_rfclk Tco Mach+trace 0 rdat 4.14 ThoFpga TsuFpga 4.14 [3.5 ,] [0.4,] 4.14 <0.23,> <1.3 5,> fpga_rfclk FPGA specification Expected margin PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN Figure 12 shows the UL3/PL3 Transmit bus timing. The setup and hold time required for the S/UNI MACH48 is 2.0 and 0.5 ns, respectively. Additionally, the TCO for the FPGA combined with the board trace lengths give a range from 5.1 to 6.1 ns. As a result both the setup and hold times have a reasonable margin. Figure 12 - UL3/PL3 Bus Timing: Transmit at FPGA 0ns 10ns 20ns 30n s fpga_tfclk Tco+long tdat 0 1.05 TmachHo TmachSu mach_tfclk 1.05 [2,] [0.5 ,] 1.05 <4.52,> <1.55,> MACH48 specification Expected margin A note on FPGA selection: The Xilinx XC4036XLA has the ability to modify the setup and hold times of the receive interface. This ability accomodates the use of bus switches on the UL3/PL3 interface which neccessitate longer trace lengths for layout while allowing the clocks traces to remain relatively short. These long trace lengths combined with a MACH-48 Tco of 1.5 to 6 ns decrease the setup time while increasing the hold time. The XC4036XLA can be configured to have a setup and hold time of 0.4 ns and 3.5 ns, respectively. In a typical application, where the UL3/PL3 bus is connected point to point, the trace lengths will be shorter in relation to the clock trace length, increasing the available setup time while reducing the hold time. In this case, the XC4036XLA can be set to have a setup and hold time of 4.7 and 0, respectively. This setting may not be sufficient to accommodate the full Tco range of the S/UNI MACH48. Alternatively, the Virtex XCV200E or APEX20KE FPGAs have improved setup/hold times and DLL functions on global clock resources that allow more concise clock control. In this figure, trace length variation is ignored across the bus. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN Figure 13 - Timing on UL3/PL3 Receive Bus (VirtexE / APEX20KE) 0ns 10ns 20ns 30n s mach_rfclk TmachCo rdat 0 4.5 TfpgaHo TfpgaSu fpga_rfclk [2,] 4.5 [0,] <1.62,> 4.5 <1.5,> Virtex/APEX setup/hold specification Expected margin PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.4 UL3/PL3 Source/Destination Select The S/UNI-MACH48 reference design allows the user to switch the source and destination of the UL3/PL3 interface. The UL3/PL3 data and control lines can be switched between the FPGA and backplane interfacing connectors. During normal operation the UL3/PL3 interface is switched to the backplane to allow the S/UNI-MACH48 to communicate with other network components When the FPGA is in loopback mode the S/UNI-MACH48 UL3/PL3 transmit and receive are effectively connected to one another, allowing traffic that is received on the serial LVDS interface to be output back onto that interface. This will allow for testing the S/UNI-MACH48 with a TSE fabric card. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN Figure 14 -UTOPIA/POS-PHY INTERFACE SWITCHING FPGA UTOPIA/POS-PHY LEVEL 3 CONTROL & DATA LINES CELL/PACKET LOOPBACK SWITCH CONTROL SWITCH SWITCH AMP HS-3 CONNECTOR UTOPIA/POS RX AMP HS-3 CONNECTOR UTOPIA/POS TX Three control lines determine the UL3/PL3 path. The table below shows the state each line must be in for each function. The FPGA controls these lines. Table 1 Function Loopback Off Board UTOPIA/POS-PHY L3 Switching Truth Table S2 L L S1 L H S0 H L MACH48 FPGA Connector PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.5 Typical UL3/PL3 Bus Layout The S/UNI MACH48 reference design uses high speed bus switches to switch the UL3/PL3 bus between an onboard FPGA and a connector to the backplane. In a typical application, however, this switching functionality is not required and the interface is much simpler. Shorter trace lengths can also be achieved which may allow the elimination of termination resistors. A series source termination may be required for longer trace lengths, depending on how much overshoot the receiving device can tolerate (see Section 7.1.4 for calculations). A point to point interconnect is shown below Figure 15 -Point to point UL3/PL3 interconnect RDAT<31..0> RADR<5..0> RMOD<1..0> INGRESS ATM or IP PROCESSOR RPRTY RSOC/RSOP RSX RENB REOP RERR RCA/RVAL UL3/PL3 INTERFACE SERIAL LVDS LINKS STPA TCA/PTPA TERR TEOP TENB TSX TSOC/TSOP TPRTY TMOD<1..0> TADR<5..0> TDAT<31..0> EGRESS ATM or IP PROCESSOR PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.6 Working/Protection Data Link Selection The S/UNI MACH48 switches between working and protection links depending on the state of the RWSEL input. During normal operation, the state of the RWSEL input is dictated by the system. The system will determine the best data path (either working or protection) to read from. The FPGA allows the user to manually override the RWSEL input from the system for testing purposes. The RWSEL output from the FPGA is inverted due to the re-mapping of the protection and working links as described in section 8.2.4. Figure 16 - Multiple Sources for RWSEL RWSEL (from offboard) RWSEL (to MACH48) 7 WPOVR RWSEL 0 FPGA Control Register PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.7 Connection Memory Page Selection The incoming and outgoing connection memory pages are selected by the ICMP and OCMP pins, respectively. During normal operation, both pins are controlled by the XCMP signal from the TSE fabric card. The ICMP and OCMP can be independently modified through the MACH Control Register. 7.2.8 Microprocessor interface The FPGA also performs glue logic to interface the S/UNI MACH48's generic microprocessor to the PCI9054 bridge device. Figure 17 -FPGA/Microprocessor Interface LD<31..0> LA<31..2> PCI9054 PCI I/O Accelerator READYB LADSB LHOLD LHOLDA LW/RB INTB FPGA FPGA Performs Glue Logic for MACH48 Micro-interface PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE CSB WRB RDB INTB 24 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.2.9 FPGA Register Description Device Reset Register 0x0000 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED MACH_RESETB Default 0 0 0 0 0 0 0 1 The Device Reset Register controls the reset status of each of the devices on the board. MACH_RESETB Writing a `0' to this bit will hold the S/UNI MACH48 in reset. Writing a `1' will take the device out of reset. FPGA Control Register 0x0010 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function NOT USED NOT USED FPEN CMPOVR ICMPSEL OCMPSEL WPOVREN RWSEL Default 0 0 1 0 0 0 0 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN FPEN When the Frame Pulse Enable bit is set, the 8kHz frame pulse generated from off board is passed to the MACH48. When FPEN is 0, this pulse does not pass to the MACH48. CMPOVR The default for CMP is to have these values set by the off board XCMP signal. This occurs when CMPOVR is set to 0. However, when set to 1, both the ICMPSEL and OCMPSEL values become valid and the off board value is ignored. ICMPSEL ICMPSEL will select the Incoming Connection Memory Page. If ICMPSEL is 0, the FPGA will set the ICMP pin on the MACH48 to 0,setting Memory connection Page 0. If ICMPSEL is 1, Memory Connection Page 1 is selected. If CMPOVR is 0, this bit is ignored. OCMPSEL OCMPSEL will select the Outgoing Connection Memory Page in the MACH48. If OCMPSEL is 0, Memory Connection Page 0 will be selected. If OCMPSEL is 1, Memory Connection Page 1 will be selected. If CMPOVR is 0, this bit is ignored. WPOVR The WPOVR (Working/Protect OVeRride) bit controls whether the RWSEL bit is controlled by an off-board source (TSE card) or by the control register. When WPOVR is 0, the RWSEL bit is controlled by the off-board source, which is passed transparently through the FPGA. When WPOVR is 1, RWSEL is controlled by the Control Register. RWSEL The RWSEL bit selects between the Working and Protection Data streams on the MACH48. When RWSEL is 1, the Working data stream is selected. When RWSEL is 0, the Protection data stream is selected. If WPOVREN is set to 0, this bit is ignored. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN SYSCLK Control Register 0x0020 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function NOT USED NOT USED NOT USED NOT USED NOT USED MUX1 MUX2A MUX2B Default 0 0 0 0 0 0 1 1 MUX1 - MUX2B The following truth table will switch the SYSCLK accordingly. Table 2: MUX1 0 0 0 1 Truth Table for SYSCLK Switching MUX2A 0 0 1 X MUX2B 0 1 1 X FUNCTION SYSCLK1 SYSCLK2 ON BOARD SYSCLK1 SYSCLK2 XOR SYSCLK2 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.3 CompactPCI Interface The PM7390 S/UNI MACH48 includes a microprocessor interface to provide read/write access to normal mode registers as described within the S/UNI MACH48 Data Sheet. This design connects a CompactPCI bus to this microprocessor interface. A block diagram of the cPCI interface and bridge is shown below in Figure 18. Figure 18 -CompactPCI Block Diagram. LA<31..2> LD<31..0> CONTROL LA<31..2> LD<31..0> CONTROL AD<31:0> C/BE<3:0> CONTROL CPCI J1 LOCAL BUS PLX 9054 PCI BRIDGE RESET\ PCI BUS EEPROM EECS EESK EEDI/O +12V -12V +5V +3.3V 7.3.1 Interface and Bridge Hardware The PCI9054 is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. The 32 bit multiplexed address/data bus and associated control lines connect directly from the CPCI J1 connector to the PLC PCI9054 bridge device. The bus and control lines are terminated with 10 ohm stub resistance that should be placed close to the J1 connector pins. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN For this reference design the PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. Address lines LA<31...2> provide 32-bit word addressing. The lower two bits of the address lines are used for 16 or 8 bit byte access but are unused in this application. The FPGA implements the local bus glue logic. A serial 93CS66L EEPROM is used for device configuration after reset or upon power-up. The PCI9054 can also be configured by an onboard microprocessor if desired. 7.3.2 Hot Swap Capability In addition to the local and PCI bus interfaces, the cPCI block provides some of the hardware required for hot swap. The hot swap specification outlines a hardware and software solution to allow cPCI boards to be safely inserted or removed from an active CPCI backplane. Note that this block does not provide the minimum Hot Swap requirements for safe insertion and extraction. An additional Hot Swap controller is required to safely power up and power down the board. The cPCI block provides 1V pre-charge voltage to cPCI bus pins to reduce pin bounce during connection or removal. Most cPCI pins are pulled up to 1V with 4 other pins (RST#, ENUM#, INTA#, and REQ#) pre-charged to V(I/O) to provide a stable clock prior to bus contact. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 7.4 Power Supply Figure 19 - Power Supply Board System Block. +5V +3.3V +5V_PCI +3.3V_PCI +12V_PCI -12V_PCI GND BD_SEL# HEALTHY# PCI_RST# Hot Swap Controller LT1643L +12V -12V +5V 1.8V Regulator 1.8V The Power Block provides stable voltage supplies delivered over the CompactPCI backplane from a centralized power supply. Voltage levels of +5V, +3.3V, +12V, -12V and regulated 1.8V are available from this block. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 8 IMPLEMENTATION DESCRIPTION This section details the hardware on the S/UNI-MACH48 reference design and references the schematics in Section 9. 8.1 Sheet 1, Root Drawing This sheet shows the interconnection between the functional blocks of the S/UNI MACH48 reference design. The design is comprised of five functional blocks: the MACH48 Block, FPGA Block, System Interface, CPCI Block and Power Block. 8.2 Sheet 2,3,4,5 MACH48 Block 8.2.1 Sheet 2: Microprocessor Interface This block shows the generic microprocessor interface. Note that A[13] has a 4.7K pull down resistor. This pull down will cause the device to default accesses to the normal mode registers. If A[13] is set high, the device will allow access to test mode registers. JTAG pins are not connected. The DS3 overhead is not used in this application and these pins are connected to a 2x16 pin header. 8.2.2 Sheet 3: UTOPIA/POS-PHY Level 3 Interface This block shows the UTOPIA/POS-PHY Level 3 (UL3/PL3) interface on the S/UNI-MACH48. All lines for this interface are 50 Ohm controlled impedance with series source terminations of 39 ohms. 8.2.3 Sheet 4: Serial Telecombus Interface This block shows both the Parallel and Serial Telecombus interfaces. In this reference design, the parallel telecombus is not used (disabled via register). The serial telecombus operates at 777.6 Mbps, which is synthesized from the 77.76Mhz system clock. It is important that these differential pairs be matched 50 ohm impedance lines with equal trace lengths (within 0.050 inches). The serial telecombus is connected to an AMP HS3 type connector that allows the interface to transmit and receive LVDS signals from a custom backplane. For further information on LVDS design considerations, consult Reference 7. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN Table 3 1 2 3 4 5 6 7 8 9 10- Pinout of S-TCB HS3 Connector A GND GND GND GND GND GND GND GND GND GND B SYSCLK1P RPPROT4 RPPROT3 RPPROT2 RPPROT1 RPWRK4 RPWRK3 RPWRK2 RPWRK1 TJ0FP_OUT C SYSCLK1N RNPROT4 RNPROT3 RNPROT2 RNPROT1 RNWRK4 RNWRK3 RNWRK2 RNWRK1 RJ0FP_IN D SYSCLK2P TPPROT4 TPPROT 3 TPPROT2 TPPROT1 TPWRK4 TPWRK3 TPWRK2 TPWRK1 RWSEL_IN E SYSCLK2N TNPROT4 TNPROT3 TNPROT2 TNPROT1 TNWRK4 TNWRK3 TNWRK2 TNWRK1 XCMP_IN F GND GND GND GND GND GND GND GND GND GND 8.2.4 Port Re-mapping of Serial Telecombus The S/UNI MACH48 Serial Telecombus (S-TCB) pin out locations are organized for direct connection to the TBS device. This direct connection is duplicated for the backplane connector of the CHESS reference design. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN Figure 20 - TBS-MACH48 LVDS Interconnections TBS/MACH48 INTERCONNECT (DIRECT PIN CONNECTIONS) TBS RWRK<1> RWRK<2> RWRK<3> RWRK<4> TWRK<1> TWRK<2> TWRK<3> TWRK<4> RPROT<1> RPROT<2> RPROT<3> RPROT<4> TPROT<1> TPROT<2> TPROT<3> TPROT<4> TWRK<1> TWRK<2> TWRK<3> TWRK<4> RWRK<1> RWRK<2> RWRK<3> RWRK<4> TPROT<1> TPROT<2> TPROT<3> TPROT<4> RPROT<1> RPROT<2> RPROT<3> RPROT<4> PM7390 S/UNI-MACH48 TBS/HS-3 CONNECTOR INTERCONNECT (CHESS BACK PLANE CONNECTION) TBS RWRK<1> RWRK<2> RWRK<3> RWRK<4> TWRK<1> TWRK<2> TWRK<3> TWRK<4> RPROT<1> RPROT<2> RPROT<3> RPROT<4> TPROT<1> TPROT<2> TPROT<3> TPROT<4> S-TCB CONNECTOR In order to create a backplane with generic line card interfaces for the CHESS reference design, it is necessary to route the S/UNI MACH48 S-TCB to match the TBS to connector pin out. This creates difficulty when trying to layout the LVDS links from the S/UNI MACH48, as an increasing number of board layers are required to accommodate the trace crossovers. Using the STS-12 port remapping capability of the S/UNI MACH48 allows the software to re-map the channels. Re-mapping the channels according to Table 4 will simplify PCB routing by eliminating crossovers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE TPROT<4> TPROT<3> TPROT<2> TPROT<1> RPROT<4> RPROT<3> RPROT<2> RPROT<1> TWRK<4> TWRK<3> TWRK<2> TWRK<1> RWRK<4> RWRK<3> RWRK<2> RWRK<1> 33 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN Figure 22 - Routing with Software Re-mapping PHYSICAL ROUTING w/o PORT REMAPPING (DIFFICULT ROUTING) PM7390 S/UNI-MACH48 RPROT<4> RPROT<3> RPROT<2> RPROT<1> TPROT<4> TPROT<3> TPROT<2> TPROT<1> RWRK<4> RWRK<3> RWRK<2> RWRK<1> TWRK<4> TWRK<3> TWRK<2> TWRK<1> NOTE: S-TCB Connector names represent TBS orientation. MACH48 Schematic does not reflect the same name orientation S-TCB CONNECTOR PHYSICAL ROUTING with PORT REMAPPING (SIMPLIFIED ROUTING) PM7390 S/UNI-MACH48 RPROT<4> RPROT<3> RPROT<2> RPROT<1> TPROT<4> TPROT<3> TPROT<2> TPROT<1> RWRK<4> RWRK<3> RWRK<2> RWRK<1> TWRK<4> TWRK<3> TWRK<2> TWRK<1> S-TCB CONNECTOR Table 4 STS-12 Port Remapping for S-TCB HS-3 Off-Board Connector (TBS References) RPROT<4..1> TPROT<4..1> RWRK<4..1> TWRK<4..1> S/UNI MACH48 RWRK<1..4> TWRK<1..4 > RPROT<1..4> TPROT<1..4> PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE TPROT<4> TPROT<3> TPROT<2> TPROT<1> RPROT<4> RPROT<3> RPROT<2> RPROT<1> TWRK<4> TWRK<3> TWRK<2> TWRK<1> RWRK<4> RWRK<3> RWRK<2> RWRK<1> TPROT<4> TPROT<3> TPROT<2> TPROT<1> RPROT<4> RPROT<3> RPROT<2> RPROT<1> TWRK<4> TWRK<3> TWRK<2> TWRK<1> RWRK<4> RWRK<3> RWRK<2> RWRK<1> 34 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN This re-mapping scheme transposes the working data links with the protection data links. While this will not affect the operation of the device, it is useful to maintain the logic of the working and protect links. By inverting the logic of the RWSEL signal, the S/UNI MACH48 will maintain the sense of the link. This logic inversion is done with the FPGA. If the MACH48 is to be installed in a fixed backplane position, then the backplane can be routed to reduce signal crossovers. 8.2.5 Sheet 5:S/UNI MACH48 Power Block The power block shows all of the power and ground connections for the MACH48 device. It is required that the 3.3 VDC I/O be powered before or at the same time as the 1.8 VDC core supply to prevent damage to the ESD protection structures within the MACH48 device. The 3.3VDC AVDH analog power supplies are filtered with an RC network attached to each analog power pin. The 1.8VDC AVDL analog power pins have their own regulator which will provide the required current while maintaining the +/- 5% tolerance. The tolerance on the 3.3 VDC supply is +/- 10%. Table 5 S/UNI MACH48 Typical Power Consumption Current (mA) 210 160 2450 240 3060 Power (mW) 378 528 4410 792 6108 Power Supply AVDL(1.8V) AVDH(3.3V) VDDI total VDDO total Total Consumption Note: VDDO total power is approximately 500 mW without the Parallel telecombus. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 8.3 Sheet 6,7 FPGA Block 8.3.1 Sheet 6: FPGA Block This sheet shows the Xilinx XC4036XLA-8 FPGA. This performs several functions on the S/UNI MACH48 reference design. The connections for the UL3/PL3 interface are optimized for minimum delay when in loopback mode. At power up, the FPGA code is loaded from one of two Xilinx XC1701L SPROMS. A three pin jumper is used to determine which PROM to download code from prior to power up. Alternatively, the FPGA can be programmed directly from the on board header. This requires a Xilinx Xchecker programming cable. 8.3.2 Sheet 7: UL3/PL3 Bus Switching Block This sheet shows the CMOS switches used to switch the UTOPIA/POS-PHY bus between the FPGA and the HS3 Connector. This switch array uses 8 Pericom PI5C16212 high bandwidth, 24 bit bus exchanges switch devices. The switches are controlled by the FPGA through the L_SEL<2..0> bus. The 100MHz UL3/PL3 clock can be switched between on-board and off-board sources. This is done using a QS4A201Q high speed two bit switch which is also controlled by the FPGA through the CLK_SEL<1..0> bus. The 100MHz (100ppm) oscillator and driver is also shown on this sheet. The Pericom PI49FCT3807 clock driver must be B grade or better (>= 100MHz). This clock driver will also provide clocking for other boards connected by the UL3/PL3 backplane if desired. It should be noted that these bus switches are not required in a typical UL3/PL3 configuration. 8.4 Sheet 9 System Interface Block The system interface block shows three AMP HS-3 connectors that are used to interface the Serial Telecombus and the UL3/PL3 receive and transmit. A PECL to TTL converter is also present to convert the off board 77.76MHz differential system clock to TTL levels. 8.5 Sheet 9,10 CompactPCI Block 8.5.1 Sheet 9: I/O Accelerator Block This sheet shows the PCI 9054 I/O Accelerator. This is the bridge chip that allows the PCI bus to communicate with the local microprocessor interface. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN The CPCI_BLOCK shows the PLX 9054 signal and power circuitry connections. The PCI9054 is a 3.3V/5V compliant PCI v2.2 32-bit, 33MHz Bus Master Interface Controller, that provides flexible local bus configurations and Hot Swap capability. The 32 bit multiplexed address/data bus and associated control lines connect directly from the CPCI J1 connector to the PLC PCI9054 interface device. The bus and control lines are terminated with 10 ohm stub resistance that should be placed close to the J1 connector pins. The PCI 9054 operates with a 32-bit non-multiplexed bus (C-mode) on the local bus side. Address lines LA<31...2> provide 32 bit word addressing. The lower two bits of the address lines are used for 16 or 8 bit byte access but are unused in this application. A serial EEPROM is required for device configuration after reset or upon powerup. A NM93CS66 serial EEPROM is used to program the 9054. The Compact PCI specification outlines a number of layout requirements for the CPCI design. These include: * * * * * All 10 ohm stub termination resistors must be placed within 0.6 of the J1 pins, All PCI signal traces must be less than 1.5 (including stub resistor) except P_CLK, P_CLK trace must be 2.5 +/- 0.1, CPCI bus traces impedance is 65 , 39 ohm stub resistor on REQ# should be placed near its source on the PCI9054. 8.5.2 Sheet 11: CompactPCI Connector This sheet shows the CPCI connector J1. An AMP Z-PACKS connector is used per the CPCI Specification (PICMG 2.0 R2.2) 8.6 Sheet 12, Power Supply and Hot Swap Controller Block This sheet shows the power supplies for the board. All CPCI compliant voltages are present as well as a 1.8 V source for driving the MACH 48 logic. The PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN switching regulator is driven by the PCI bus 5 VDC supply. The 3.3 VDC(VDDO, AVDH) supply must be present on the MACH48 before the 1.8 VDC (VDDI, AVDL) supply. To do this, a power supply supervisory circuit is used to control the power supply enable such that if the 3.3 VDC is not present, the 1.8 VDC supply will not turn on. There is also a Hot Swap controller that allows for the removal and replacement of circuit boards into a live PCI slot without damage to on board components. The PWROK_1_8V pin connected to the FPGA is used to indicate when the 1.8V supply is fully powered up. The FPGA will delay any switching until the core voltage is fully powered. The 12VDC and -12VDC supplies are present but not used in this application. For more information on power supply sequencing, See Reference 6, Section 8.3 "Power Sequencing Rules for 1.8V and 3.3V Supplies". PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 9 SCHEMATICS PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H SHEET 2,3,4,5 H MACH48_BLOCK SHEET 10,11 CPCI_BLOCK LD<31..0> LA<31..2> LA<31..2> LD<31..0> LD<31..0> LA<31..2> G LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK PWR_OK RWRK<8..1> TWRK<8..1> RPROT<8..1> TPROT<8..1> G RMOD<1..0> RPRTY RSOC/RSOP RSX RENB REOP RERR RCA/RVAL RADR<5..0> RDAT<31..0> RWRK<8..1> TWRK<8..1> RPROT<8..1> TPROT<8..1> SHEET 6,7,8 SHEET 9 FPGA_BLOCK LD<31..0> LA<31..2> MACH_FP MACH_TJ0FP MACH_FP MACH_TJ0FP MACH_FP MACH_TJ0FP SYSTEM_INTERFACE F LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK F E CON_FP CON_TJ0FP XCMP CON_RWSEL SYSCLK1 SYSCLK2 TMOD<1..0> TPRTY TSOC/TSOP TSX TENB TEOP TERR TCA/PTPA STPA TADR<5..0> TDAT<31..0> MACH_TFCLK MACH_RFCLK MACH_RSTB MACH_CSB MACH_WRB MACH_RDB MACH_INTB MACH_RWSEL MACH_ICMP MACH_OCMP MACH_SYSCLK SYSCLK_TST MACH_OJ0REF CON_FP CON_TJ0FP XCMP CON_RWSEL SYSCLK1 SYSCLK2 XCMP CON_RWSEL SYSCLK1 SYSCLK2 MACH_TFCLK MACH_RFCLK MACH_RSTB MACH_CSB MACH_WRB MACH_RDB MACH_INTB MACH_RWSEL MACH_ICMP MACH_OCMP MACH_SYSCLK SYSCLK_TST MACH_OJ0REF MACH_TFCLK MACH_RFCLK MACH_RSTB MACH_CSB MACH_WRB MACH_RDB MACH_INTB MACH_RWSEL MACH_ICMP MACH_OCMP MACH_SYSCLK SYSCLK_TST MACH_OJ0REF RWRK<8..1> TWRK<8..1> RPROT<8..1> TPROT<8..1> CON_FP CON_TJ0FP LHOLD LHOLDA L_ADSB L_READYB L_WRB L_USERI L_USERO L_RSTOB L_INTB L_CLK PLX_EN PWR_OK E 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB VIO_PCI PLX_EN HEALTHYB BD_SELB VEE_PCI 12V_PCI 3_3V_PCI 5V_PCI VIO_PCI D D RMOD<1..0> RPRTY RSOC/RSOP RSX RENB REOP RERR RCA/RVAL RADR<5..0> RDAT<31..0> RMOD<1..0> RPRTY RSOC/RSOP RSX RENB REOP RERR RCA/RVAL RADR<5..0> RDAT<31..0> CON_RMOD<1..0> CON_RPRTY CON_RSOC/RSOP CON_RSX CON_RENB CON_REOP CON_RERR CON_RCA/RVAL CON_RADR<5..0> CON_RDAT<31..0> CON_RFCLK RSYSCLK CON_RMOD<1..0> CON_RPRTY CON_RSOC/RSOP CON_RSX CON_RENB CON_REOP CON_RERR CON_RCA/RVAL CON_RADR<5..0> CON_RDAT<31..0> CON_RFCLK RSYSCLK CON_RMOD<1..0> CON_RPRTY CON_RSOC/RSOP CON_RSX CON_RENB CON_REOP CON_RERR CON_RCA/RVAL CON_RADR<5..0> CON_RDAT<31..0> CON_RFCLK RSYSCLK SHEET 12 POWER_BLOCK C TMOD<1..0> TPRTY TSOC/TSOP TSX TENB TEOP TERR TCA/PTPA STPA TADR<5..0> TDAT<31..0> TMOD<1..0> TPRTY TSOC/TSOP TSX TENB TEOP TERR TCA/PTPA STPA TADR<5..0> TDAT<31..0> CON_TMOD<1..0> CON_TPRTY CON_TSOC/TSOP CON_TSX CON_TENB CON_TEOP CON_TERR CON_TCA/PTPA CON_STPA CON_TADR<5..0> CON_TDAT<31..0> CON_TFCLK TSYSCLK CON_TMOD<1..0> CON_TPRTY CON_TSOC/TSOP CON_TSX CON_TENB CON_TEOP CON_TERR CON_TCA/PTPA CON_STPA CON_TADR<5..0> CON_TDAT<31..0> CON_TFCLK TSYSCLK CON_TMOD<1..0> CON_TPRTY CON_TSOC/TSOP CON_TSX CON_TENB CON_TEOP CON_TERR CON_TCA/PTPA CON_STPA CON_TADR<5..0> CON_TDAT<31..0> CON_TFCLK TSYSCLK PWR_OK VIO_PCI 5V_PCI 3_3V_PCI 12V_PCI VEE_PCI BD_SELB HEALTHYB C B B DRAWING: TITLE=MACH48_R2_ROOT ABBREV=MACH48_R2_ROOT LAST_MODIFIED=Fri Jan 12 14:41:22 2001 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 2 TITLE: S/UNI MACH 48 REFERENCE DESIGN ROOT DRAWING ENGINEER: RS 8 7 6 5 4 3 2 ISSUE DATE: 00/12/20 REVISION NUMBER: 2 PAGE:1 1 OF 12 A A 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G 3.3 V Y2 4 C3 2 50PPM OSC_EP26 3.3V VCC OUTPUT 3 1 R1 33 0.1UF GND 44.736MHZ T TP14 TS/PD F F 10H4<> 6B10<> LD<31..0>\I 10D4> LA<31..2>\I BGA U7 BGA U7 E 2 1 3 4 2 3 RN35 RN35 RN35 RN35 RN36 RN36 RN36 RN36 33 33 5 8 AP37 AN37 AP39 AP38 A19 33 33 33 33 33 33 7 8 6 5 7 6 AM39 AM38 AM37 AM36 AN39 AN38 MACH48 PM7390 4 OF 6 TOHCH[5] ROHCH[5] TOHCH[4] ROHCH[4] TOHCH[3] ROHCH[3] TOHCH[2] ROHCH[2] TOHCH[1] ROHCH[1] TOHCH[0] ROHCH[0] AH37 AH36 AJ38 AJ37 AK38 AK37 4 RN37 1 RN49 2 RN37 3 RN37 2 RN38 1 RN38 33 33 33 33 33 33 AL37 AK36 AL38 B19 D19 4 RN38 3 RN38 1 RN37 5 8 7 6 7 8 E 3.3 V 3.3 V 4 1 33 33 33 4 RN41 5 6 8 R46 4.7K R45 4.7K MACH48 PM7390 1 OF 6 A[13]/TRS D[15] A[12] D[14] A[11] D[13] A[10] D[12] A[9] D[11] A[8] D[10] A[7] D[9] A[6] D[8] A[5] D[7] D[6] A[4] D[5] A[3] D[4] A[2] D[3] A[1] D[2] A[0] D[1] D[0] B5 C5 B6 C6 A7 B7 D7 B8 C8 D8 A9 B9 C9 B10 C10 A11 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 D TP8 T ALE 4.7K R47 15 14 13 12 11 10 9 8 7 6 5 4 3 2 B11 C11 D11 B12 C12 D12 A13 B13 C13 B14 C14 A15 B15 C15 TOH ROH TOHVAL ROHVAL TOHFP ROHFP REF8K TOHINS DS3TICLK RPOHFP DS3 OVERHEAD 33 5 TP23 T TP30 T 4.7K R55 C18 D17 C17 A18 B18 TCK TDI TDO TMS TRSTB ALE CSB INTB RDB RSTB WRB MICRO/JTAG B16 D15 B17 C16 A17 D16 D 4.7K R29 1.8 V 3.3 V J2 C 6B10> 6B10> 6B10> 6B10< 6B10> MACH_WRB\I MACH_RSTB\I MACH_RDB\I MACH_INTB\I MACH_CSB\I 4.7K R52 4.7K R53 TOHINS TOHFP TOHVAL TOH TOHCH0 TOHCH1 TOHCH2 TOHCH3 TOHCH4 TOHCH5 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 P_1 P_3 P_5 P_7 P_9 P_11 P_13 P_15 P_17 P_19 P_21 P_23 P_25 P_27 P_29 P_31 P_2 P_4 P_6 P_8 P_10 P_12 P_14 P_16 P_18 P_20 P_22 P_24 P_26 P_28 P_30 P_32 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 ROHFP ROHVAL ROH ROHCH0 ROHCH1 ROHCH2 ROHCH3 ROHCH4 ROHCH5 C HEADER 16X2 CONN_MALE B B PMC-Sierra, Inc. A DRAWING ABBREV=MACH48_BLOCK TITLE=MACH48_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:00 2001 DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI MACH48 REFERENCE DESIGN MACH48-MICROPROCESSOR I/F ENGINEER: RS 8 7 6 5 4 3 2 ISSUE DATE: 00/06/27 REVISION NUMBER: 1 PAGE:2 1 OF 12 A 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G TADR<5..0>\I 7G10> 7H10> 7E10< 7C10> TDAT<31..0>\I BGA U7 RADR<5..0>\I MACH48 PM7390 5 OF 6 RDAT<31..0>\I F F E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 5 4 3 2 1 0 B20 C20 B21 C21 A22 B22 C22 D22 B23 C23 D23 A24 B24 C24 B25 C25 A26 B26 C26 D26 B27 C27 D27 A28 B28 C28 B29 C29 A30 B30 C30 D30 C33 D33 A34 B34 C34 D34 3 2 1 4 3 4 1 2 1 3 2 4 2 3 1 4 3 1 4 2 3 2 1 4 2 3 1 4 2 1 3 4 TDAT[31] TDAT[30] TDAT[29] TDAT[28] TDAT[27] TDAT[26] TDAT[25] TDAT[24] TDAT[23] TDAT[22] TDAT[21] TDAT[20] TDAT[19] TDAT[18] TDAT[17] TDAT[16] TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TADR[5] TADR[4] TADR[3] TADR[2] TADR[1] TADR[0] 5 4 3 2 1 0 RDAT[31] RDAT[30] RDAT[29] RDAT[28] RDAT[27] RDAT[26] RDAT[25] RDAT[24] RDAT[23] RDAT[22] RDAT[21] RDAT[20] RDAT[19] RDAT[18] RDAT[17] RDAT[16] RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] RADR[5] RADR[4] RADR[3] RADR[2] RADR[1] RADR[0] 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 E38 E37 E36 F38 F37 G39 G38 G37 G36 H38 H37 H36 J39 J38 J37 K38 K37 L38 L37 L36 M38 M37 M36 N38 N37 N36 P38 P37 T38 T37 T36 U39 Y38 Y37 Y36 AA38 AA37 AC38 RN40 RN40 RN40 RN40 RN1 RN44 RN1 RN1 RN42 RN42 RN42 RN42 RN43 RN43 RN43 RN43 RN44 RN44 RN46 RN44 RN45 RN45 RN45 RN45 RN46 RN46 RN46 RN39 RN47 RN47 RN47 RN47 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 39 6 7 8 5 6 5 8 7 8 6 7 5 7 6 8 5 6 8 5 7 6 7 8 5 7 6 8 5 7 8 6 5 E D TMOD[1] TMOD[0] 1 0 4 RN48 1 RN39 2 RN39 D RMOD[1] RMOD[0] 39 5 39 8 39 7 39 39 39 5 6 6 V37 W38 1 RN48 2 RN48 1 0 C32 D32 39 8 39 7 RN39 RN48 RN1 39.2 39.2 R40 R41 B31 D31 A32 C35 C31 B32 B35 A33 B33 TPRTY RPRTY TSOC/TSOP RSOC/RSOP TSX RSX RENB TENB TEOP REOP TERR RERR TFCLK RFCLK TCA/PTPA RCA/RVAL STPA POS/UL3B RX/TX UTOPIA U38 U36 V39 AC36 U37 3 V38 3 AC37 Y39 4 C19 RMOD<1..0>\I RPRTY\I RSOC/RSOP\I RSX\I RENB\I REOP\I RERR\I MACH_RFCLK\I RCA/RVAL\I 7D10< 7D10< 7D10< 7D10< 7C10> 7D10< 7D10< 7B10> 7D10< C C 3.3 V 4.7K STPA\I 7G10< 7G10< 7B10> 7G10> 7H10> 7G10> 7H10> 7H10> 7H10> 7G10> R42 B MACH_TFCLK\I TERR\I TEOP\I TENB\I TSX\I TSOC/TSOP\I TPRTY\I TMOD<1..0>\I TCA/PTPA\I J3 1 2 3 B DRAWING HEADER3 TITLE=MACH48_BLOCK ABBREV=MACH48_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:03 2001 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI-MACH48 REFERENCE DESIGN MACH48-UTOPIA/POS-PHY LVL3 I/F ENGINEER: RS ISSUE DATE: 00/06/27 REVISION NUMBER: 1 PAGE:3 OF 12 A A 10 9 8 7 6 5 4 3 2 1 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G BGA U7 MACH48 PM7390 2 OF 6 RN59 RN59 RN59 RN59 RN104 RN104 RN104 RN104 1 2 3 4 3 4 1 2 8 7 6 5 6 5 8 7 AN4 AN3 AN2 AN1 AM3 AM2 AL3 AL2 G 9H10< 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K TWRK<8..1>\I ID[1][7] ID[1][6] ID[1][5] ID[1][4] ID[1][3] ID[1][2] ID[1][1] ID[1][0] 9F10< TPROT<8..1>\I OD[1][7] OD[1][6] OD[1][5] OD[1][4] OD[1][3] OD[1][2] OD[1][1] OD[1][0] AJ3 AJ2 AJ1 AH3 AH2 AG3 AG2 AG1 F AA2 AA1 V1 V2 BGA U7 8 7 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 AW33 AC3 M4 M3 N3 N2 P2 P1 R3 R2 V4 V3 Y4 Y3 Y2 Y1 U2 U3 MACH48 PM7390 3 OF 6 TPPROT[4] RPPROT[4] TNPROT[4] RNPROT[4] NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 NET_50 3.3 V 2 1 4 3 6 5 8 7 2 1 4 3 6 5 8 7 RN105 RN105 RN111 RN111 RN111 RN111 RN106 RN106 2 3 4 3 2 1 4 3 7 6 5 6 7 8 5 6 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K AV14 AU14 AV13 AU13 AW12 AV11 AU11 AW10 ID[2][7] ID[2][6] ID[2][5] ID[2][4] ID[2][3] ID[2][2] ID[2][1] ID[2][0] OD[2][7] OD[2][6] OD[2][5] OD[2][4] OD[2][3] OD[2][2] OD[2][1] OD[2][0] AU9 AW8 AV8 AU8 AT8 AW7 AV7 AU7 F 6 5 4 3 2 1 RPPROT[3] RNPROT[3] RPPROT[2] RNPROT[2] RPPROT[1] RNPROT[1] RPWRK[4] RNWRK[4] RPWRK[3] RNWRK[3] RPWRK[2] RNWRK[2] RPWRK[1] RNWRK[1] RWSEL RES TPWRK[1] TNWRK[1] J2 J3 TPPROT[3] TNPROT[3] TPPROT[2] TNPROT[2] TPPROT[1] TNPROT[1] TPWRK[4] TNWRK[4] TPWRK[3] TNWRK[3] TPWRK[2] TNWRK[2] K3 K4 K1 K2 M1 M2 T3 T4 T1 T2 2 3 4 3 2 1 4 3 RN114 RN114 RN107 RN107 RN107 RN107 RN108 RN108 7 6 5 6 7 8 5 6 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K AV22 AU22 AT22 AW21 AV21 AU21 AW20 AV20 ID[3][7] ID[3][6] ID[3][5] ID[3][4] ID[3][3] ID[3][2] ID[3][1] ID[3][0] OD[3][7] OD[3][6] OD[3][5] OD[3][4] OD[3][3] OD[3][2] OD[3][1] OD[3][0] AV18 AU18 AV17 AU17 AT17 AW16 AV16 AU16 8 7 E 6 5 4 3 RN113 RN113 RN109 RN109 RN109 RN110 RN109 RN110 RN113 RN114 RN105 RN112 RN110 RN108 RN106 RN112 3 4 4 2 3 4 1 3 1 1 1 3 1 1 1 2 6 5 5 7 6 5 8 6 8 8 8 6 8 8 8 7 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K AW31 AV31 AU31 AV30 AU30 AW29 AV29 AU29 AT32 AW22 AW14 AP2 AV28 AV19 AU10 AK3 ID[4][7] ID[4][6] ID[4][5] ID[4][4] ID[4][3] ID[4][2] ID[4][1] ID[4][0] IDP[4] IDP[3] IDP[2] IDP[1] IJ0J1[4] IJ0J1[3] IJ0J1[2] IJ0J1[1] OD[4][7] OD[4][6] OD[4][5] OD[4][4] OD[4][3] OD[4][2] OD[4][1] OD[4][0] ODP[4] ODP[3] ODP[2] ODP[1] OJ0J1[4] OJ0J1[3] OJ0J1[2] OJ0J1[1] AW27 AV26 AU26 AW25 AV25 AU25 AT25 AW23 AT28 AW18 AV9 AJ4 AU23 AV15 AU6 AF2 E 2 1 AC4 4.7K R35 603 1% J1 100MIL 1 2 3 4.7K R56 4.7K R57 3.16K R34 TJ0FP RJ0FP SYSCLK SER_EN RESK ATB1 ATB0 SERIAL TELECOMBUS AV33 AV32 AT33 A20 J4 H4 9H10> HEADER3 RWRK<8..1>\I RN113 RN114 RN105 RN112 2 4 4 4 7 5 5 5 4.7K 4.7K 4.7K 4.7K RN110 2 RN108 2 RN106 2 RN112 1 7 4.7K 7 4.7K 7 4.7K 8 4.7K AU32 AT23 AU15 AP3 IPAIS[4] IPAIS[3] IPAIS[2] IPAIS[1] AT29 AU20 AV10 AL1 AU34 OPL[4] OPL[3] OPL[2] OPL[1] IPL[4] IPL[3] IPL[2] IPL[1] ICMP OALARM[4] OALARM[3] OALARM[2] OALARM[1] OCMP OJ0REF PARALLEL TELECOMBUS AV23 AT16 AV6 AF3 D 9G10> RPROT<8..1>\I 6G3> 4.7K MACH_RWSEL\I R2 AU28 AU19 AT10 AK2 AV34 AU33 D 6G3> MACH_SYSCLK\I 6H3> MACH_FP\I 6H3< MACH_TJ0FP\I C 6H3> 6G3> 6H3> C MACH_ICMP\I MACH_OJ0REF\I MACH_OCMP\I B DRAWING ABBREV=MACH48_BLOCK TITLE=MACH48_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:06 2001 B PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 2 TITLE: S/UNI MACH48 REFERENCE DESIGN PARALLEL/SERIAL TELECOMBUS ENGINEER: RS 8 7 6 5 4 3 2 ISSUE DATE: 00/12/20 REVISION NUMBER: 2 PAGE:4 1 OF 12 A A 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H BGA U7 MACH48 PM7390 6 OF 6 L4 R4 W4 AA4 PLACE 0.1UF CAPS NEAR PINS 3.3 V 3.3 V 0.1UF C50 0.1UF C54 0.1UF C58 0.1UF C62 0.1UF C66 0.1UF C70 0.1UF C74 0.1UF C78 0.1UF C82 0.1UF AVDH3 AVDH2 AVDH1 AVDH0 C86 0.1UF G 1.8 VA P3 W2 AB4 AB3 AA3 C90 0.1UF C94 0.1UF C98 0.1UF G C102 0 805 5% AVDL4 AVDL3 AVDL2 AVDL1 AVDL0 0.1UF R36 0.1UF C49 0.1UF C51 0.1UF C55 0.1UF C59 0.1UF C63 0.1UF C67 0.1UF C71 0.1UF C75 0.1UF C79 0.1UF C83 0.1UF C87 0.1UF C91 0.1UF C95 0.1UF C99 0.1UF 0.1UF R30 ANALOG 3.3 VDC C44 C103 0 805 5% C40 F + + + 10UF C111 10UF C107 10UF C125 10UF + + + + C127 10UF C129 10UF C134 10UF C136 10UF R31 0.1UF 0 805 5% C45 3.3 V PLACE TWO 10UF CAPACITORS ON EACH EDGE OF THE MACH48 0.1UF R32 C46 1.8 V E E NOTE: SOLDER BRIDGE IS FOR TEST PURPOSES ONLY 0.1UF C52 0.1UF C56 0.1UF C60 0.1UF C64 0.1UF C68 0.1UF C72 0.1UF C76 0.1UF C80 0.1UF C84 0.1UF C88 0.1UF C92 0.1UF C96 0.1UF 1.8 V C132 + 0 805 5% F 3.3 V 1.8 VA ANALOG 1.8 VDC 1 3 SB1 P<1> P<2> P<3> P<4> 2 4 SOLDERBRIDGE 0.1UF C53 0.1UF C57 0.1UF C61 0.1UF C65 0.1UF C69 0.1UF C73 0.1UF C77 0.1UF C81 0.1UF C85 0.1UF C89 0.1UF C93 0.1UF C97 0.1UF D 3 TO263 3A ADJ U14 LM1085 INPUT OUTPUT 2 C101 C100 4 TAB ADJ/GND 1 100 R37 B2 B3 B4 C2 C3 C4 D2 D3 D4 D6 D10 D14 D21 D25 D29 B36 B37 B38 C36 C37 C38 D36 D37 D38 F36 K36 P36 AA36 AE36 AJ36 AT38 AT37 AT36 AU38 AU37 AU36 AV38 AV37 AV36 AT34 AT30 AT26 AT19 AT15 AT11 AV4 AV3 AV2 AU4 AU3 AU2 AT4 AT3 AT2 AP4 AK4 AF4 VDDO56 VDDO55 VDDO54 VDDO53 VDDO52 VDDO51 VDDO50 VDDO49 VDDO48 VDDO47 VDDO46 VDDO45 VDDO44 VDDO43 VDDO42 VDDO41 VDDO40 VDDO39 VDDO38 VDDO37 VDDO36 VDDO35 VDDO34 VDDO33 VDDO32 VDDO31 VDDO30 VDDO29 VDDO28 VDDO27 VDDO26 VDDO25 VDDO24 VDDO23 VDDO22 VDDO21 VDDO20 VDDO19 VDDO18 VDDO17 VDDO16 VDDO15 VDDO14 VDDO13 VDDO12 VDDO11 VDDO10 VDDO9 VDDO8 VDDO7 VDDO6 VDDO5 VDDO4 VDDO3 VDDO2 VDDO1 VDDO0 + + + + + + 10UF C124 10UF C126 10UF C128 10UF C130 10UF C131 10UF D + + + + 10UF C35 10UF C109 10UF C29 10UF C30 10UF C110 1% 603 + + C133 10UF C135 10UF 44.2 1% 805 R33 VSS75 VSS74 VSS73 VSS72 VSS71 VSS70 VSS69 VSS68 VSS67 VSS66 VSS65 VSS64 VSS63 VSS62 VSS61 VSS60 VSS59 VSS58 VSS57 VSS56 VSS55 VSS54 VSS53 VSS52 VSS51 VSS50 VSS49 VSS48 VSS47 VSS46 VSS45 VSS44 VSS43 VSS42 VSS41 VSS40 VSS39 VSS38 VSS37 VSS36 VSS35 VSS34 VSS33 VSS32 VSS31 VSS30 VSS29 VSS28 VSS27 VSS26 VSS25 VSS24 VSS23 VSS22 VSS21 VSS20 VSS19 VSS18 VSS17 VSS16 VSS15 VSS14 VSS13 VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 VSS0 C153 AW39 AW38 AW37 AW36 AW34 AW32 AW30 AW28 AW26 AW24 AW19 AW17 AW15 AW13 AW11 AW9 AW4 AW3 AW2 AA39 AC39 AE39 AG39 AJ39 AL39 AT39 AU39 AV39 B39 C39 D39 H39 M39 T39 AU1 AP1 AK1 AF1 AD1 AH1 AM1 AT1 AV1 P39 K39 F39 W1 U1 R1 N1 L1 J1 D1 AW1 C1 B1 A39 A38 A37 A36 A31 A29 A27 A25 A23 A21 A16 A14 A12 A10 A8 A6 A4 A3 A2 A1 1.8 V PLACE TWO 10UF CAPACITORS ON EACH EDGE OF THE MACH48 C + C 1.8 VA 1.8 V 3.3 V 0.1UF C36 0.1UF C37 0.1UF C38 0.1UF C43 0.1UF C47 0.1UF C48 TP9 T TP11 T TP15 T TP17 T TP19 T TP25 T B D9 D5 D13 D18 D20 D24 D28 J36 N39 R36 V36 W36 W37 W39 AB36 AG36 AL36 AN36 AP36 AT35 AT31 AT27 AT24 AT21 AT20 AT18 AT14 AT12 AT9 AT7 AT6 AR4 AM4 AL4 AH4 AG4 AD4 C7 TP10 T TP13 T TP16 T TP18 T TP20 T TP26 T PLACE CAPS NEAR POWER PINS VDDI37 VDDI36 VDDI35 VDDI34 VDDI33 VDDI32 VDDI31 VDDI30 VDDI29 VDDI28 VDDI27 VDDI26 VDDI25 VDDI24 VDDI23 VDDI22 VDDI21 VDDI20 VDDI19 VDDI18 VDDI17 VDDI16 VDDI15 VDDI14 VDDI13 VDDI12 VDDI11 VDDI10 VDDI9 VDDI8 VDDI7 VDDI6 VDDI5 VDDI4 VDDI3 VDDI2 VDDI1 VDDI0 POWER B DRAWING ABBREV=MACH48_BLOCK TITLE=MACH48_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:12 2001 PMC-Sierra, Inc. DISTRIBUTE TEST POINTS THROUGHOUT PCB AND LABEL WITH VOLTAGE VALUE DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 2 TITLE: S/UNI MACH48 REFERENCE DESIGN POWER/FILTERING BLOCK ENGINEER: RS 8 7 6 5 4 3 2 ISSUE DATE: 00/12/20 REVISION NUMBER: 2 PAGE:5 1 OF 11 A A 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR 7H3< 5 4 3 2 1 0 FPGA_TADR<5..0> 3.3 V 3.3 V SW1 RIGHT_ANGLE 2 1 4.7K R39 H H 3.3 V 100 100 100 100 100 100 100 100 PBNO 5 6 7 8 5 6 7 8 Y1 1 4 7E3< 5 4 3 2 1 0 FPGA_RADR<5..0> RN57 RN57 RN58 RN58 RN58 RN58 PWR_OK\I MACH_FP\I MACH_TJ0FP\I CON_FP\I CON_TJ0FP\I XCMP\I MACH_ICMP\I MACH_OCMP\I CON_RWSEL\I MACH_RWSEL\I SYSCLK1\I SYSCLK2\I MACH_SYSCLK\I MACH_OJ0REF\I 12D8> 4D10< 4C10> 9F10> 9F10< 9F10> 4C4< 4C4< 9F10> 4D10< 9F10> 9F10> 4D10< 4C4< TRI GND 77.76MHZ 100PPM 3V3 OUT 8 0.1UF 5 C155 3 4 8 7 6 5 RED D2 33 33 33 33 33 33 33 8 RN103 4 A1 RN115 3 A2 RN115 2 A3 RN115 1 A4 RN115 LED SSF-LXH5147 K1 K2 K3 K4 6 5 1 2 3 4 1 7 6 1 2 3 4 2 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 T TP22 PLX_EN\I 10D9< TP5 T T HQFP U11 TP24 CCLK D0 8D8< 8E8> TP6 T TP12 T 3.3 V TP31 T R3 T TP21 1.2K 3.3 V K1 K2 K3 K4 4 A1 RN87 3 A2 RN87 2 A3 RN87 1 A4 RN87 LED SSF-LXH5147 33 7 RN103 TP3 T 33 33 33 33 33 33 GREEN D3 2 3 8 7 6 5 RN49 RN49 RN95 RN95 RN95 RN95 33 R43 G G VCC IO/GCK8/A15 IO/A14 IO IO IO IO IO/A13 IO/A12 IO IO IO IO GND IO IO IO IO VCC IO/A11 IO/A10 GND IO IO IO/A18 IO/A19 IO/A9 IO/A8 VCC GND IO/A7 IO/A6 IO/A20 IO/A21 IO IO GND IO/A5 IO/A4 VCC IO IO IO IO GND IO IO IO IO IO IO IO IO/A3 IO/CS1/A2 IO IO IO/GCK7/A1 IO/A0/WS GND O/TDO F 33 4 TP28 T FPGA_TFCLK1 FPGA_STPA FPGA_TCA/PTPA 1 F 5 RN103 7H3> 7H3> 7H3> 33 8 RN96 7E3> 7E3< 7E3> 7E3> 7H3< 7E3> 7H3< 33 3 33 8 33 7 33 6 33 5 33 8 33 7 33 6 33 5 TP2 T FPGA_RFCLK1 FPGA_RENB FPGA_RCA/RVAL FPGA_RSX FPGA_TSX FPGA_RPRTY FPGA_TPRTY 6 RN103 FPGA_TENB 7H3< 1 RN60 7E3> FPGA_RMOD<1..0> 2 RN60 1 7H3< FPGA_TMOD<1..0> 2 3 4 33 7 RN96 33 6 RN96 33 5 RN96 31 1 2 3 4 1 3 RN60 0 7E3> FPGA_RDAT<15..0> 0 4 RN60 15 E 7H3< FPGA_TDAT<15..0> 15 1 RN54 E 33 8 RN50 30 31 14 FPGA_RSOC/RSOP FPGA_TSOC/TSOP FPGA_REOP FPGA_TEOP FPGA_RERR FPGA_TERR FPGA_RDAT<31..16> FPGA_TDAT<31..16> 7E3> 7H3< 7E3> 7H3< 7E3> 7H3< 7E3> 7H3< 14 2 RN54 13 13 3 RN63 33 7 RN50 29 30 12 12 4 RN63 33 6 RN50 28 29 11 33 5 RN50 27 1 2 3 4 1 2 3 4 1 2 3 4 28 11 3 RN54 33 6 33 5 33 8 33 7 33 6 33 5 33 8 33 7 33 6 33 5 33 8 33 7 XC4036XLA-HQ240 8NS 10 10 4 RN54 33 8 RN51 26 27 9 9 1 RN55 33 7 RN51 25 26 8 33 6 RN51 24 25 8 2 RN55 7 D 33 5 RN51 23 24 D 33 8 RN52 22 23 7 3 RN55 6 6 4 RN55 5 33 7 RN52 21 22 5 1 RN56 4 4 2 RN56 33 6 RN52 20 21 3 3 3 RN56 33 5 RN52 19 20 2 2 4 RN56 33 8 RN53 18 19 1 TP27 T 1 1 RN57 33 7 RN53 17 18 0 TP29 T 33 6 RN53 16 17 0 2 RN57 7D3> FPGA_RFCLK2 FPGA_TFCLK2 33 5 RN53 16 C 2 4 6 4.7K R82 4.7K R83 4.7K R84 3.3 V 100MIL J13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 7H3> GND IO/GCK1/A16 IO/A17 IO IO IO/TDI IO/TCK IO IO IO IO IO IO GND IO/FCLK1 IO IO/TMS IO VCC IO IO GND IO IO IO IO IO IO GND VCC IO IO IO IO IO IO GND IO IO VCC IO IO IO IO/FCLK2 GND IO IO IO IO IO IO IO IO IO IO IO IO/GCK2 O/M1 GND I/M0 VCC CCLK IO/GCK6/DOUT IO/D0/DIN IO IO IO/RCK/RDY/BUSY IO/D1 IO IO IO IO IO IO GND IO IO IO/FCLK4 IO VCC IO IO/D2 GND IO IO IO IO IO/RS IO/D3 GND VCC IO IO/D4 IO IO IO IO GND IO/CS0 IO/D5 VCC IO IO/FCLK3 IO IO GND IO IO IO IO IO IO/D6 IO IO IO IO IO/GCK5 IO/D7 PROGRAM VCC 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 PROG 8E8> C C137 0.1UF C138 0.1UF C139 0.1UF C140 0.1UF C141 0.1UF C142 0.1UF C143 0.1UF C144 0.1UF C145 0.1UF C146 0.1UF C147 0.1UF C148 0.1UF C149 0.1UF C150 0.1UF C151 0.1UF 4.7K R38 7 6 5 4 3 2 1 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 3.3 V VCC I/M2 IO/GCK3 IO/HDC IO IO IO IO/LDC IO IO IO IO IO IO GND IO IO IO IO VCC IO IO GND IO IO IO IO IO IO/INIT VCC GND IO IO IO IO IO IO GND IO IO VCC IO IO IO IO GND IO IO IO IO IO IO IO IO IO IO IO IO/GCK4 GND DONE C152 HEADER 3X2 0.1UF 1 3 5 P_1 P_3 P_5 P_2 P_4 P_6 PLACE 1 DECOUPLING CAP NEXT TO EACH VCC PIN 2 1 0 1 0 B INIT DONE CLK_SEL<1..0> L_SEL<2..0> 8D8< 8C8< 7A10< 7D10< 7H10< B 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 2 DRAWING TITLE=FPGA_BLOCK ABBREV=FPGA_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:37 2001 8 7 6 5 4 3 TITLE: S/UNI MACH48 REFERENCE DESIGN FPGA UTOPIA/POS-PHY I/F ENGINEER: PMC-SIERRA RS 2 ISSUE DATE: 00/12/20 REVISION NUMBER: 2 PAGE:6 1 OF 12 A A 10H4<> 2F9<> 2C9< 2C9< 2C9< 2C9> 2C9< 10D4> 10E2< 10E2< 10E2> 10E2> 10E2< 10F2> 10F2< 10F2> 10F2< 10F2> LD<31..0>\I MACH_RDB\I MACH_WRB\I MACH_CSB\I MACH_INTB\I MACH_RSTB\I LA<31..2>\I L_CLK\I L_INTB\I L_RSTOB\I L_USERO\I L_USERI\I L_WRB\I L_READYB\I L_ADSB\I LHOLDA\I LHOLD\I 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H TDAT<31..0>\I TPRTY\I TEOP\I TSOC/TSOP\I TSX\I 3.3 V 17 17 10 56 1 55 2 10 56 1 55 2 17 FPGA_TDAT<31..0> FPGA_TERR FPGA_TMOD<1..0> FPGA_TCA/PTPA FPGA_STPA FPGA_TADR<5..0> FPGA_TENB FPGA_TPRTY FPGA_TEOP FPGA_TSOC/TSOP FPGA_TSX FPGA_TFCLK1 FPGA_TFCLK2 6E1> 6E10> 6E1> 6E10> 6F1< 6F1< 6H10> 6F1> 6F10> 6E1> 6E1> 6F10> 6F1< 6C1< H 3F4< 3A7< 3B7< 3A7< 3B7< 6B1> L_SEL<2..0> 3.3 V TSSOP U4 S0 S1 S2 VCC VCC S0 S1 S2 3.3 V TSSOP U6 10 56 1 55 2 3.3 V TSSOP U13 17 10 56 1 55 2 TSSOP U2 VCC S0 S1 S2 G 3B7< 3A7< 3B7> 3B7> TERR\I TMOD<1..0>\I TCA/PTPA\I STPA\I 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 19 18 17 16 15 14 13 12 11 10 9 8 31 30 29 28 27 26 25 24 23 22 21 20 31 30 29 28 27 26 25 24 23 22 21 20 7 6 5 4 3 2 1 0 1 0 VCC S0 S1 S2 G 3G4< 3B7< 1 0 TADR<5..0>\I TENB\I 5 4 3 2 1 0 2 4 6 9 11 13 15 18 21 23 25 27 54 521 500 47 45 43 41 39 36 34 32 30 2 4 6 9 11 13 15 18 21 23 25 27 2 4 6 9 11 13 15 18 21 23 25 27 2 4 6 9 11 13 15 18 21 23 25 27 5 4 3 2 1 0 54 52 50 47 45 43 41 39 36 34 32 30 54 52 50 47 45 43 41 39 36 34 32 30 54 52 50 47 45 43 41 39 36 34 32 30 3.3 V R60 4.7K R61 7 6 5 4 3 2 1 0 F VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 3 5 7 10 12 14 16 20 22 24 26 28 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 31 30 29 28 27 26 25 24 23 22 21 20 1A1 1B1 2B1 2A1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8B1 8A1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 3 5 7 10 12 14 16 20 22 24 26 28 53 51 48 46 44 42 40 37 35 33 31 29 3 5 7 10 12 14 16 20 22 24 26 28 3 5 7 10 12 14 16 20 22 24 26 28 53 51 48 46 44 42 40 37 35 33 31 29 53 51 48 46 44 42 40 37 35 33 31 29 53 51 48 46 44 42 40 37 35 33 31 29 1A1 1B1 2B1 2A1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8B1 8A1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 1A1 1B1 2B1 2A1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8B1 8A1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 1A1 1B1 2B1 2A1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8B1 8A1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 F 8 19 38 49 VSS VSS VSS VSS 8 19 38 49 8 19 38 49 8 19 38 49 CON_TDAT<31..0>\I CON_TPRTY\I CON_TEOP\I CON_TSOC/TSOP\I CON_TSX\I CON_TERR\I CON_TMOD<1..0>\I CON_TCA/PTPA\I CON_STPA\I CON_TADR<5..0>\I CON_TENB\I CON_TFCLK\I FPGA_RERR FPGA_RMOD<1..0> FPGA_RCA/RVAL FPGA_RADR<5..0> FPGA_RENB FPGA_RDAT<31..0> FPGA_RPRTY FPGA_REOP FPGA_RSOC/RSOP FPGA_RSX FPGA_RFCLK1 FPGA_RFCLK2 9D10> 9E10> 9E10> 9E10> 9E10> 9E10> 9E10> 9E10< 9E10< 9D10> 9E10> 9E10> 6E1< 6E10< 6F10< 6G10> 6F10> 6E1< 6E10< 6F10< 6E1< 6E1< 6F10< 6F10< 6C10< E E 3F4> 3C4> 3C4> 3C4> 3C4> 6B1> RDAT<31..0>\I RPRTY\I REOP\I RSOC/RSOP\I RSX\I L_SEL<2..0> 3.3 V 17 17 10 56 1 55 2 10 56 1 55 2 17 3.3 V TSSOP U5 S0 S1 S2 VCC VCC S0 S1 S2 3.3 V TSSOP U8 10 56 1 55 2 3.3 V TSSOP U15 D 17 10 56 1 55 2 TSSOP U3 VCC S0 S1 S2 3C4> 3C4> 3B4> 5 4 3 2 1 0 RERR\I RMOD<1..0>\I RCA/RVAL\I 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19 18 17 16 15 14 13 12 11 10 9 8 31 30 29 28 27 26 25 24 23 22 21 20 1 0 VCC S0 S1 S2 D PLACE CAP AT EACH VCC POWER PIN 3.3 V 3F4< 3C4< RADR<5..0>\I RENB\I 3.3 V 1 0 5 4 3 2 1 0 3.3 V 3.3 V RN80 RN83 3.3 V 0.1UF C116 0.1UF C117 0.1UF C118 0.1UF C119 0.1UF C120 0.1UF C121 0.1UF C122 0.1UF 1 2 3 4 RN77 C RN78 RN79 RN82 VSS VSS VSS VSS VSS VSS VSS VSS C123 2 4 6 9 11 13 15 18 21 23 25 27 54 52 1 50 0 47 45 43 41 39 36 34 32 30 2 4 6 9 11 13 15 18 21 23 25 27 2 4 6 9 11 13 15 18 21 23 25 27 2 4 6 9 11 13 15 18 21 23 25 27 54 52 50 47 45 43 41 39 36 34 32 30 54 52 50 47 45 43 41 39 36 34 32 30 54 52 50 47 45 43 41 39 36 34 32 30 31 30 29 28 27 26 25 24 23 22 21 20 83 75 67 5 10 12 4.7K 14 RN76 16 20 22 24 26 28 1 2 3 4 1 2 3 4 1 2 3 4 7 6 5 4 3 2 1 0 C 1A1 1B1 2A1 2B1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8A1 8B1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 83 75 67 5 10 8 12 7 14 6 16 5 20 8 22 7 24 6 26 5 28 53 51 48 46 44 42 40 37 35 33 31 29 53 51 48 46 44 42 40 37 35 33 31 29 5 4 3 2 1 0 1A1 1B1 2A1 2B1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8A1 8B1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 RN81 1 2 3 4 1 2 3 4 1 2 3 4 19 18 17 16 15 14 13 12 11 10 9 8 83 75 67 10 5 12 8 14 7 16 6 20 5 22 8 24 7 26 6 28 5 1A1 1B1 2A1 2B1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8A1 8B1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 53 51 48 46 44 42 40 37 35 33 31 29 RN84 RN85 1 2 3 4 1 2 3 4 1 2 3 4 83 75 67 10 5 12 8 14 7 16 6 20 5 22 8 24 7 26 6 28 5 1A1 1B1 2A1 2B1 3A1 3B1 4A1 4B1 5A1 5B1 6A1 6B1 7A1 7B1 8A1 8B1 9A1 9B1 10A1 10B1 11A1 11B1 12A1 12B1 PI3C16212 1A2 1B2 2A2 2B2 3A2 3B2 4A2 4B2 5A2 5B2 6A2 6B2 7A2 7B2 8A2 8B2 9A2 9B2 10B2 10A2 11A2 11B2 12A2 12B2 53 51 48 46 44 42 40 37 35 33 31 29 31 30 29 28 27 26 25 24 23 22 21 20 VSS VSS VSS VSS 8 19 38 49 8 19 38 49 8 19 38 49 5V 8 19 38 49 VSS VSS VSS VSS 4.7K 4.7K 4.7K 681P U1 24 B CON_RDAT<31..0>\I CON_RPRTY\I CON_RSOC/RSOP\I CON_REOP\I CON_RSX\I CON_RERR\I CON_RMOD<1..0>\I CON_RCA/RVAL\I CON_RADR<5..0>\I CON_RENB\I CON_RFCLK\I 3.3 V QSOP20_2 U23 9B10< 9C10< 9C10< 9C10< 9C10< 9C10< 9C10< 9C10< 9A10> 9C10> 9C10> B DRAWING 3 4 VCC 3B7< MACH_TFCLK\I 3.3 V A0 B0 C0 D0 2 5 7 8 A1 B1 C1 D1 6 9 VCC 4 VCC 8 VCC 15 VCC 20 3C4< MACH_RFCLK\I HCMOS 100.000MHZ 3.3V 100PPM U20 8 ABBREV=FPGA_BLOCK TITLE=FPGA_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:45 2001 VDD OUT 5 33 4 C1 1 11 14 5V A2 B2 0.1UF C2 D2 10 15 C112 0.1UF A GND NC/TS 1 R62 QS4A201Q 17 18 0.1UF 10UF A3 B3 C28 C3 D3 16 19 PMC-Sierra, Inc. 3.3 V RSYSCLK\I TSYSCLK\I 0.1UF C114 0.1UF C115 21 22 C2 A4 B4 C4 D4 20 23 GND S E PI49FCT3807 A 1 0 13 1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 GND GND GND GND GND 3 5 7 9 11 12 14 16 18 19 4 RN61 3 RN61 2 RN61 1 RN61 4 RN62 3 RN62 2 RN62 1 RN62 2 RN63 1 RN63 33 5 33 6 33 7 33 8 33 5 33 6 33 7 33 8 33 7 33 8 9C10< 9D10< 6B1> CLK_SEL<1..0> DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: ISSUE 1 2 6 10 13 17 ISSUE DATE: 00/06/27 TITLE: S/UNI MACH48 REFERENCE DESIGN UTOPIA BUS SWITCHING ENGINEER: PMC-SIERRA RS 8 7 6 5 4 3 2 REVISION NUMBER: 1 PAGE:7 1 OF 12 A 12 PLACE CAPS CLOSE TO QS4A201Q TP7 T TP4 T 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G G F F 3.3 V 3.3 V 0.1UF C32 4.7K R124 4.7K R125 J8 E E 6F1< 6C1< D0 PROG 33 R118 1 2 3 4 5 6 7 8 HEADER8 3.3VD D_GND CLK DONE DIN PROGRAMB INIT DONE 3.3 V 3.3 V 20 4.7K R122 0.1UF 6F1> CCLK VCC 10 6B1> INIT 3.3 V 20 3.3 V 4.7K R123 0.1UF 6B1> DONE 2 J12 VCC CEO GND 14 HEADER3 3 XC1701L-PC20C SOCKET 2 DATA 4 CLK 6 OE 8 CE C TP1 T 10 C34 1 GND D XC1701L-PC20C SOCKET 2 DATA 4 CLK 6 OE 8 CE CEO 14 C33 17 U9 VPP D U12 VPP 17 C B B PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 1 DRAWING TITLE=FPGA_BLOCK ABBREV=FPGA_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:48 2001 TITLE: S/UNI MACH48 REFERENCE DESIGN FPGA PROGRAMMING ENGINEER: PMC-SIERRA RS 8 7 6 5 4 3 2 ISSUE DATE: 00/06/27 REVISION NUMBER: 1 PAGE:8 TRUE 1 OF 12 A A 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR 4G10> 2 4 6 8 7 5 3 1 TWRK<8..1>\I H H 2 4 6 8 7 5 3 1 4D10< RWRK<8..1>\I SER_LVDS FEMALE_RA J5 SER_LVDS FEMALE_RA J5 SER_LVDS FEMALE_RA J5 R50 SOIC8 U10 PECL TTL G 3 4 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 B1 SYSCLK1P B2 RPWRK1 B3 RPWRK2 B4 RPWRK3 B5 RPWRK4 B6 RPROT1 B7 RPROT2 B8 RPROT3 B9 RPROT4 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 SYSCLK1N RNWRK1 RNWRK2 RNWRK3 RNWRK4 RNPROT1 RNPROT2 RNPROT3 RNPROT4 SYSCLK2N E1 TNWRK1 E2 TNWRK2 E3 TNWRK3 E4 TNWRK4 E5 TNPROT1 E6 TNPROT2 E7 TNPROT3 E8 TNPROT4 E9 603 1% 1 2 100 C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10 D1 SYSCLK2P D2 TPWRK1 D3 TPWRK2 D4 TPWRK3 D5 TPWRK4 D6 TPPROT1 D7 TPROT2 D8 TPROT3 D9 TPROT4 D10 Q0 Q1 GND 5 6 7 E10 E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 D0P D0N D1P D1N MC100EPT23 G R48 603 1% 8 100 VCC 0.1UF C108 8 6 4 2 4D10< 8 6 4 2 1 3 5 7 RPROT<8..1>\I 4F10> 56 TPROT<8..1>\I NET_50 NET_50 NET_50 NET_50 R49 56 TP33 T R51 TP32 T 1 3 5 7 3.3 V F 6H3> 6H3< 6H3< 6H3< 6G3< 6G3< CON_TJ0FP\I CON_FP\I CON_RWSEL\I XCMP\I SYSCLK2\I SYSCLK1\I F E 1 7E3< 7E3> 7E3< 7F3< 7E3> 7E3< 7F3< 7F3< 7E3< CON_TFCLK\I CON_TCA/PTPA\I CON_TERR\I CON_TPRTY\I CON_STPA\I CON_TENB\I CON_TEOP\I CON_TSOC/TSOP\I CON_TMOD<1..0>\I UL3/PL3_TX FEMALE_RA J6 UL3/PL3_TX FEMALE_RA J6 E 0 UL3/PL3_TX J6 FEMALE_RA 7F3< AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 CON_TSX\I A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 SER_LVDS FEMALE_RA J5 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 SER_LVDS FEMALE_RA J5 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 SER_LVDS FEMALE_RA J5 D 0 5 10 15 20 25 29 24 19 14 9 4 3 8 13 18 23 28 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 D 2 7 12 17 22 27 31 CON_TDAT<31..0>\I 3 2 1 0 5 7F3< 7E3< AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 0 1 4 30 26 21 16 11 6 1 CON_TADR<5..0>\I TSYSCLK\I 7A4> UL3/PL3_TX FEMALE_RA J6 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 UL3/PL3_TX FEMALE_RA J6 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 UL3/PL3_TX FEMALE_RA J6 C UL3/PL3_RX FEMALE_RA J7 7B3< 7B3< 7B3> 7B3> 7B3> 7B3> 7A4> 7B3> 7B3> CON_RFCLK\I CON_RENB\I CON_RSX\I CON_REOP\I CON_RSOC/RSOP\I CON_RMOD<1..0>\I RSYSCLK\I CON_RERR\I CON_RCA/RVAL\I UL3/PL3_RX FEMALE_RA J7 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 C UL3/PL3_RX J7 FEMALE_RA UL3/PL3_RX FEMALE_RA J7 E1 F1 E2 F2 E3 F3 E4 F4 E5 F5 E6 F6 E7 F7 E8 F8 E9 F9 E10 F10 AMP_HS3_6X10 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 UL3/PL3_RX FEMALE_RA J7 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 UL3/PL3_RX FEMALE_RA J7 7B3> CON_RPRTY\I A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 A8 B8 A9 B9 A10 B10 AMP_HS3_6X10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C1 D1 C2 D2 C3 D3 C4 D4 C5 D5 C6 D6 C7 D7 C8 D8 C9 D9 C10 D10 AMP_HS3_6X10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 B AB1 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AMP_HS3_6X10 CD1 CD2 CD3 CD4 CD5 CD6 CD7 CD8 CD9 CD10 AMP_HS3_6X10 EF1 EF2 EF3 EF4 EF5 EF6 EF7 EF8 EF9 EF10 AMP_HS3_6X10 B 1 6 11 16 21 26 31 30 25 20 15 10 5 0 4 9 14 19 24 29 28 23 18 13 8 3 7C3> 1 2 3 4 CON_RDAT<31..0>\I 7B3< CON_RADR<5..0>\I 5 0 2 7 12 17 22 27 PMC-Sierra, Inc. DRAWING ABBREV=SYSTEM_INTERFACE TITLE=SYSTEM_INTERFACE LAST_MODIFIED=Tue Feb 13 09:51:30 2001 DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI MACH48 REFERENCE DESIGN SYSTEM INTERFACE ENGINEER: RS 8 7 6 5 4 3 2 ISSUE DATE: 00/06/27 REVISION NUMBER: 1 PAGE:9 1 OF 12 A A 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS CPCI BRIDGE ZONE REV DESCRIPTION DATE 3.3 V 3.3 V 4.7K R7_1 APPR H 3.3 V 3.3 V 3.3 V 3.3 V LD<31..0>\I 2F9<> 6B10<> 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 H 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 6 8 7 7 5 6 5 8 4 3 4 1 RES_ARRAY_4 11H8<> 7 6 5 8 6 8 6 7 AD<31..0> LD<31> LD<30> LD<29> LD<28> LD<27> LD<26> LD<25> LD<24> LD<23> LD<22> LD<21> LD<20> LD<19> LD<18> LD<17> LD<16> LD<15> LD<14> LD<13> LD<12> LD<11> LD<10> LD<9> LD<8> LD<7> LD<6> LD<5> LD<4> LD<3> LD<2> LD<1> LD<0> 7 5 8 5 95 96 97 98 100 101 102 103 104 105 106 107 110 111 112 113 114 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 2 3 4 1 3 1 3 2 2 4 1 4 3 1 2 2 4.7K 4.7K 4.7K 4.7K 3.3 V RN2_1 RN2_1 RN2_1 RN1_1 RN1_1 RN5_1 RN3_1 RN3_1 RN1_1 RN3_1 RN2_1 RN1_1 RN4_1 RN3_1 RN5_1 RN4_1 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1 DP<3> DP<2> DP<1> DP<0> 139 138 137 136 162 147 141 133 116 109 99 89 70 62 45 35 28 20 1 PART#PCI9054-AB50PI RN4_1 RN5_1 RN5_1 RN4_1 G G U2_1 BTERM* BIGEND* LHOLDA LHOLD BLAST* 134 163 144 143 148 LHOLDA\I LHOLD\I L_WRB\I L_READYB\I L_ADSB\I 6A10> 6A10< 6A10< F F 6A10> 6A10< 11H8<> C/BE<3..0> 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> 2 3 4 1 2 3 4 3 4 1 2 3 4 1 2 2 3 4 1 2 3 4 1 2 4 1 2 3 4 1 2 3 173 174 175 2 3 4 5 8 9 10 11 12 13 14 15 31 32 33 34 36 37 38 39 40 42 43 46 47 48 49 50 51 7 6 5 8 7 6 5 6 5 8 7 6 5 8 7 7 6 5 8 7 6 5 8 7 5 8 7 6 5 8 7 6 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 10 AD<31> AD<30> AD<29> AD<28> AD<27> AD<26> AD<25> AD<24> AD<23> AD<22> AD<21> AD<20> AD<19> AD<18> AD<17> AD<16> AD<15> AD<14> AD<13> AD<12> AD<11> AD<10> AD<9> AD<8> AD<7> AD<6> AD<5> AD<4> AD<3> AD<2> AD<1> AD<0> RN8_1 RN8_1 RN8_1 RN9_1 RN9_1 RN9_1 RN9_1 RN10_1 RN10_1 RN11_1 RN11_1 RN11_1 RN11_1 RN12_1 RN12_1 RN17_1 RN17_1 RN17_1 RN18_1 RN18_1 RN18_1 RN18_1 RN19_1 RN19_1 RN19_1 RN20_1 RN20_1 RN20_1 RN20_1 RN21_1 RN21_1 RN21_1 ADX31 ADX30 ADX29 ADX28 ADX27 ADX26 ADX25 ADX24 ADX23 ADX22 ADX21 ADX20 ADX19 ADX18 ADX17 ADX16 ADX15 ADX14 ADX13 ADX12 ADX11 ADX10 ADX9 ADX8 ADX7 ADX6 ADX5 ADX4 ADX3 ADX2 ADX1 ADX0 PCI9054 C-MODE LW/R* BREQO READY* LSERR* ADS* 90 149 135 146 145 3 2 1 0 C/BE<3> C/BE<2> C/BE<1> C/BE<0> 1 3 1 3 6 16 30 41 8 6 8 6 10 10 10 10 CBEX3 CBEX2 CBEX1 CBEX0 C/BE<3>* C/BE<2>* C/BE<1>* C/BE<0>* PME* ENUM* PAR DEVSEL* STOP* SERR* PERR* MODE<1> MODE<0> TEST 157 156 155 RN10_1 RN12_1 RN17_1 RN19_1 RN21_1 RN14_1 RN13_1 RN13_1 RN14_1 RN14_1 SERRX PERRX 26 25 11C5< 11C5<> 11F5<> 11C5<> P_ENUMB P_PAR P_DEVSELB P_STOPB 4 4 3 4 3 2 1 4 2 1 2 R16_1 1 171 170 168 8 8 5 7 8 7 6 7 5 5 6 5 10 10 10 10 10 10 10 10 10 10 10 39.2 ENUMX PARX DEVSELX STOPX 167 52 29 22 23 11F5< 11A5<> P_SERRB P_PERRB RN14_1 RN12_1 RN13_1 RN13_1 RN10_1 RN8_1 24 17 21 18 7 172 169 LBE2* LBE3* DMPAF/EOT* WAIT* BREQI CCS* LCLK LEDON/LEDIN LINT* LRESETO* USERI/DACK0/LLOCKI* USERO/DREQ0/LLOCKO* 91 92 153 151 150 160 142 53 154 152 159 158 L_CLK\I L_INTB\I L_RSTOB\I L_USERI\I L_USERO\I 6A10> 6A10> 6A10< 6A10> 6A10< E LOCKX FRAMEX TRDYX IRDYX IDSELX REQX LOCK* FRAME* TRDY* IRDY* IDSEL REQ* RST* GNT* PCLK INTA* LBE0* LBE1* LA<2> LA<3> LA<4> LA<5> LA<6> LA<7> LA<8> LA<9> LA<10> LA<11> LA<12> LA<13> LA<14> LA<15> LA<16> LA<17> LA<18> LA<19> LA<20> LA<21> LA<22> LA<23> LA<24> LA<25> LA<26> LA<27> LA<28> LA<29> LA<30> LA<31> 1 1K 2 1K 3 1K 4 1K 11B5> 11C5> 11G5< P_GNTB P_CLK P_INTAB 10 1 8 5 RN7_1 INTAX 11H7> VIO_PCI\I RSTX DCK U4_1 2 8 7 6 5 B A GND 1.2K R4_1 3 166 165 164 VCC OUT 4 EEDI/O EESK EECS VSS12 VSS11 VSS10 VSS9 VSS8 VSS7 VSS6 VSS5 VSS4 VSS3 VSS2 VSS1 176 161 140 132 115 108 88 69 61 44 27 19 8 7 6 5 1 1K 2 1K 3 1K 4 1K 11B5<> 11E5<> 11B5<> 11D5<> 11E5> 11G5< 11D5> P_LOCKB P_FRAMEB P_TRDYB P_IRDYB P_IDSEL P_REQB P_RSTB 10 LBE0 LBE1 E 3.3 V D + 0.1UF 0.1UF RN6_1 RN6_1 RN6_1 RN6_1 LBE0 94 LBE1 93 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 68 67 66 65 64 63 60 59 58 57 56 55 54 D 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 RN15_1 RN15_1 RN15_1 RN15_1 6F1> PLX_EN\I 1 C16_1 0.1UF C17_1 0.1UF C15_1 0.1UF C13_1 C14_1 0.1UF C19_1 0.1UF C22_1 0.1UF C23_1 10UF C24_1 10UF 3.3 V 3.3 V 10UF + U1_1 NM93CS66LEN C20_1 0.1UF C21_1 4.7K R14_1 PLACE AROUND U2 1 2 3 4 2.2K R13_1 8 7 6 5 VCC PRE PE GND CS SK DI DO PLACE NEAR U1 4.7K R15_1 C C25_1 LA<31..2>\I 2F9< 6B10< + C PRECHARGE D1_1 DL4148 ADJ U3_1 LT1117CST 1V_PRECHG 1 2 2 4 130 R12_1 VOUT VIN TAB ADJ 3 3_3V_LONG 11H7> VIO_LONG 11H7> 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 6 7 8 5 6 7 8 5 7 8 5 6 7 8 5 6 7 7 8 5 6 7 8 5 6 5 6 7 8 5 6 7 6 8 6 8 5 8 7 6 5 7 8 5 7 6 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 10K 0.1UF C4_1 24 R11_1 1 8 5 56 8 R10_1 7 10K 10K 10K 10K 3 2 1 4 3 2 1 4 2 1 4 3 2 1 4 3 2 2 1 4 3 2 1 4 3 4 3 2 1 4 3 2 3 1 3 1 4 1 2 3 4 2 1 4 2 3 1 4 1 RN22_1 RN22_1 RN22_1 RN23_1 RN23_1 RN23_1 RN23_1 RN24_1 RN24_1 RN24_1 RN25_1 RN25_1 RN25_1 RN25_1 RN26_1 RN26_1 RN26_1 RN30_1 RN30_1 RN31_1 RN31_1 RN31_1 RN31_1 RN32_1 RN32_1 RN33_1 RN33_1 RN33_1 RN33_1 RN34_1 RN34_1 RN34_1 RN24_1 RN26_1 RN30_1 RN32_1 RN30_1 RN29_1 RN29_1 RN29_1 RN29_1 RN32_1 RN28_1 RN28_1 RN28_1 RN28_1 RN34_1 RN22_1 RN27_1 RN27_1 2 100K R8_1 B B DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:20 2001 P_GNTB ADX0 ADX1 ADX2 ADX3 ADX4 ADX5 ADX6 ADX7 ADX8 ADX9 ADX10 ADX11 ADX12 ADX13 ADX14 ADX15 ADX16 ADX17 ADX18 ADX19 ADX20 ADX21 ADX22 ADX23 ADX24 ADX25 ADX26 ADX27 ADX28 ADX29 ADX30 ADX31 CBEX0 CBEX1 CBEX2 CBEX3 FRAMEX IRDYX TRDYX DEVSELX STOPX IDSELX LOCKX PARX PERRX SERRX RSTX ENUMX INTAX REQX PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI MACH48 REFERENCE DESIGN CPCI_BLOCK ENGINEER: RS ISSUE DATE: 00/06/27 REVISION NUMBER: 1 PAGE:10 OF 12 A A NOTES: 1. 2. 3. 4. 5. ALL 10 OHM STUBS WITHIN 0.6" ALL PCI SIGNAL TRACES < 1.5" P_CLK TRACE MUST BE 2.5" +/CPCI BUS TRACES ARE 65 OHM. 39 OHM STUB RESISTOR ON REQB OF J1 EXCEPT P_CLK 0.1" PLACED NEAR BRIDGE PIN 10 9 8 7 6 5 4 3 2 1 10 8 7 6 9 5 4 3 2 1 REVISIONS AD<31..0> 10H10<> ZONE REV DESCRIPTION DATE APPR H C/BE<3..0> 10F10<> H 3.3 V 12F8< 12G8< 10C5< 10C3< 10D9< 12F8< 1 2 3 4 4.7K 4.7K 4.7K 4.7K PLACE DECOUPLING CAPS CLOSE TO CONNECTOR VIO_LONG VIO_PCI\I 5V_PCI\I 3_3V_PCI\I VIO_PCI\I 3_3V_PCI\I 5V_PCI\I CPCI J1 + + 3_3V_LONG RN16_1 8 RN16_1 7 RN16_1 6 RN16_1 5 + 0.1UF C10_1 10UF C6_1 0.1UF C12_1 10UF C5_1 0.1UF C9_1 10UF C8_1 0.1UF C11_1 10UF P_INTAB 10E9> 10E9> 10 P_REQB 3 30 26 5% 603 VEE_PCI\I 21 18 R5_1 12V_PCI\I P_DEVSELB 10E9<> 0.1UF 0.1UF C1_1 10UF C3_1 C18_1 10UF P_SERRB 10E9> + 12 F 7 C2_1 + C7_1 G J1_1 + G F A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A1 A2 A3 A4 A5 A6 A7 AD<30> A8 AD<26> A9 C/BE<3> A10 AD<21> A11 AD<18> A15 A16 A17 A18 A19 A20 AD<12> A21 A22 AD<7> A23 A24 AD<1> A25 1 VEE_PCI\I 12E8< 12E8> F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25 F1 F3 F5 F7 F9 F11 F13 F15 F17 F19 F21 F23 F25 HEALTHYB\I 29 P_IDSEL 10E9< 10E9<> 17 P_FRAMEB E 15 E 9 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B1 B2 B3 B4 B5 B6 B7 AD<29> B8 B9 B10 B11 AD<17> B15 B16 B17 B18 B19 AD<15> B20 B21 AD<9> B22 B23 AD<4> B24 B25 4 P_RSTB 10E9< P1_1 STRIP3 3 28 1 2 HOLE_SIZE= 150 MIL MOUNTING HOLE 23 10M D P_IRDYB 10E9<> R2_1 16 STRIP2 ESD STRIP 10M TP2_1 T CHASSIS D 1 R3_1 TP1_1 T CHASSIS STRIP1 CPCI ESD STRIP R1_1 10M 14 8 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C1 C2 C3 C4 C5 C6 C7 AD<28> C8 C9 AD<23> C10 C11 AD<16> C15 C16 C17 C18 C19 AD<14> C20 C21 AD<8> C22 C23 AD<3> C24 C25 3 P_ENUMB 12V_PCI\I 10E9> 12E8< P_CLK 10E9< C 25 C 20 BD_SELB\I P_STOPB P_PAR 12E8< 10E9<> 10E9<> 11 6 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D1 D2 D3 D4 D5 D6 D7 D8 AD<25> D9 D10 AD<20> D11 D15 D16 D17 D18 D19 D20 AD<11> D21 D22 AD<6> D23 D24 AD<0> D25 0 B B P_GNTB 10E9< 31 27 24 22 19 2 P_TRDYB P_LOCKB P_PERRB 1 0 10E9<> 10E9<> 10E9<> DRAWING: TITLE=CPCI_BLOCK ABBREV=CPCI_BLOCK LAST_MODIFIED=Tue Feb 13 09:51:24 2001 13 10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E15 E16 E17 E18 E19 E20 E21 E22 E23 E24 E25 E1 E2 E3 E4 E5 E6 AD<31> E7 AD<27> E8 AD<24> E9 AD<22> E10 AD<19> E11 C/BE<2> E15 E16 E17 E18 C/BE<1> E19 AD<13> E20 AD<10> E21 C/BE<0> E22 AD<5> E23 AD<2> E24 E25 5 2 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI MACH48 REFERENCE DESIGN CPCI CONNECTOR ENGINEER: RS 8 7 6 5 4 3 2 ISSUE DATE: 00/06/27 REVISION NUMBER: 1 PAGE:11 1 OF 12 A A ZPACK5X22A CPCI 10 9 10 8 7 6 9 5 4 3 2 1 REVISIONS ZONE REV DESCRIPTION DATE APPR H H G HOT SWAP CONTROLLER 5V G 3.3 V 11H7> R15_2 8IRF7413 3 2 5 4 1 4 5 1 5V_PCI\I 2 0.01 7 6 8 IRF7413 3 +5V 11H8> R5_2 0.01 10 R8_2 R6_2 220UF C9_2 3_3V_PCI\I 0.01 7 6 +3.3V F R9_2 C8_2 11H7> 100 VIO_PCI\I +12V 10 + R14_2 F 9 10 11 3 13 12 R2_2 R3_2 1.2K 2.0K 2.0K R4_2 GATE 3V_IN 5V_IN 3V_OUT 5V_OUT 11C5> 11F5> 11C5> 6 12V_PCI\I 1 12V_IN VEE_IN ONB FAULTB VEE_OUT 15 12V_OUT 16 12V_OUT VEE_OUT 3V_SENSE BD_SELB\I 5 LTC1643LCGN 5V E GND TIMER R13_2 5V_SENSE VEE_PCI\I 2 0.047UF U2_2 14 +12V R12_2 3.3 V R11_2 E 560 560 150 R10_2 63.4 11F5< 2 HEALTHYB\I 7 PWRGDB 0.1UF D1_2 C5_2 0.1UF C6_2 8 GREEN D1 VEE A1 A2 A3 A4 K1 K2 K3 K4 1 0.01UF 4 C7_2 LED SSF-LXH5147 GND VEE D 6H3< D PWR_OK\I 5V 3.3 V 1.8 V R7_2 4 C + + 220UF R16_2 C1_2 2.2UF C2_2 4.7K 7 8 U1_2 SIE501.8R VIN1 VOUT1 1 VIN2 VOUT2 2 VOUT3 4 3 C + 2.2UF C3_2 220UF 3 MR 1 RESET GND 2 9 10 11 PWROK SENSE TRIM ENABLE GND GND 5 6 C4_2 182 R1_2 MAX812REUS-T 100K U3_2 VCC + B B DRAWING: TITLE=POWER_BLOCK ABBREV=PCIPWRBLOCK LAST_MODIFIED=Tue Feb 13 09:51:26 2001 PMC-Sierra, Inc. DOCUMENT NUMBER: PMC-2000207 DOCUMENT ISSUE NUMBER: 1 TITLE: S/UNI MACH48 REFERENCE DESIGN POWER BLOCK ENGINEER: RS 8 7 6 5 4 3 2 ISSUE DATE: 00/06/27 REVISION NUMBER: 1 PAGE:12 1 OF 12 A A 10 9 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 10 LAYOUT PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN 11 BILL OF MATERIALS Table 6 Bill of Materials Manufacturer PERICOM Ref Des U23 Description IC 3.3V 1:10 CMOS CLOCK DRIVER QSOP20 D GRADE Qty 1 NO. 1 Part Number PI49FCT3807DQ 2 3 SN74AHC1G08DCKR 120673-1 TI AMP U4_1 J5-J7 IC SINGLE 2-INPUT POSITIVE AND GATE 1 Z-PACK 6 ROW HS3 BACKPLANE CONNECTOR, RIGHT ANGLE RECEPTACLE 3 4 5 6 ECU-V1H103KBV ECU-V1H473KBW ECJ-1VB1C104K PANASONIC PANASONIC PANASONIC C7_2 C8_2 C1, C10_1, C11_1, C12_1, C13_1, C14_1, C15_1, C16_1, C17_1, C18_1, C19_1, C1_1, C21_1, C22_1, C23_1, C3, C28, C32-C34, C36-C38, C40, C43C49, C4_1, C50-C59, C5_2, C60-C69, C6_2, C70-C103, C108, C112, C114-C123, C137C152, C155, C9_1 CAP CERAMIC X7R 0603 50V 0.01UF CAP CERAMIC X7R 1206 50V 0.047UF CAP CERAMIC X7R 0603 16V 0.1UF 1 1 118 7 8 GRM42-2X5R106K10 ECS-H1CC106R MURATA PANASONIC C2 C20_1, C24_1, C25_1, C2_1, C3_1, C5_1, C6_1, C7_1, C8_1 CAP CERAMIC X5R 1210 10V 10UF CAP TANCAPC 16V 20% 10UF 1 9 9 ECS-T0JY106R PANASONIC C29, C30, C35, C107, C109-C111, C124C136, C153 CAP TANCAPA 6.3V 20% 10UF 21 10 11 12 13 ECS-H1VC225R ECE-V1AA221P DL4148MS PZC36SAAN PANASONIC PANASONIC MICROSEMI SULLINS ELECTRONICS C2_2, C3_2 C1_2, C4_2, C9_2 D1_1 J1, J3, J12 CAP TANCAPC 35V 20% 2.2UF CAP ELECTRO VA SMD 10V 20% 220UF DIODE RECT 150MA 75V SMT MINIMELF 2 3 1 CONN HEADER STRAIGHT 36POS MALE 3 .1" SINGLE ROW 14 PZC36DAAN SULLINS J2 CONN HEADER 2 ROW 0.1"X0.1" 2X16 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN NO. 15 Part Number PZC36DAAN Manufacturer SULLINS ELECTRONICS Ref Des J13 Description CONN HEADER STRAIGHT 6POS MALE .1" DUAL ROW 3X2 Qty 1 16 17 S1011-36-ND IRF7413 SULLIN INTERNATIONA L RECTIFIER J8 Q1_2, Q2_2 HEADER 8 POS 1 ROW 100 MIL SPACING 1 IC POWER MOSFET 2 18 LM1085IS-ADJ NATIONAL SEMI U14 REGULATOR VARIABLE MICROPOWER LOW DROPOUT ADJUSTABLE 1 19 LT1117CST LINEAR TECHNOLOGIES U3_1 REGULATOR ADJUSTABLE SOT223 800MA OUTPUT 1 20 LTC1643LCGN LINEAR TECHNOLOGY U2_2 IC CPCI HOT SWAP CONTROLLER 1 21 PM7390 PMC-SIERRA U7 MULTI SERVICE ACCESS DEVICE FOR CHANNELIZED INTERFACES 1 22 MAX812REUS-T MAXIM U3_2 IC VOLTAGE MONITOR WITH MANUAL RESET INPUT 2.63V SOT143 1 23 MB3100H-77.76MHZ MMD COMPONENTS Y1 OSC HCMOS/TTL HALF SIZE 8 PIN 77.76MHZ 100PPM 1 24 25 26 MC100EPT23D 614-93-308-31-012 MMD MB3100HH-100.000M HZ MOTOROLA MILL MAX ? U10 U1_1 U20 IC DUAL PECL/TTL TRNSLTR. 3.3V, SOIC8 1 SOCKET FOR PART# NM93CS66LEN 1 27 28 EP2645TTS-44.736M DIGIKEY -- CKN4002-ND ECLIPTEK ? Y2 SW1 OSCILLATOR, 44.736MHZ, 3.3V, 50PPM RIGHT ANGLE PCB MOUNT SPST PUSH BUTTOM 1 1 29 PCI9054-AB50PI PLX TECHNOLOGY U2_1 IC PCI-TO-LOCAL BUS 1 30 PI3C16212 PEROCOM U2-U6, U8, U13, U15 IC 3.3V, HIGH BANDWITH, 24 BIT BUS EXCHANGE SWITCH 8 31 QS4A201Q IDT/QUALITY U1 IC TWO-BY-TWO ANALOG CROSS POINT 1 SWITCH 32 33 34 35 36 ERJ-6GEY0R00V WSL2512-R01-1 ERJ-3GSYJ122V ERJ-3GSYJ100V ERJ-3EKF1000V PANASONIC VISHAY PANASONIC PANASONIC PANASONIC R30-R32, R36 R14_2, R15_2, R5_2 R2_2, R3, R4_1 R5_1, R6_2, R8_2 R37, R48, R50, R9_2 RES 0805 1/10W 5% ZERO OHM RES 2512 1W 1% 0.01 OHM RES 0603 1/16W 5% 1.2K OHM RES 0603 1/16W 5% 10 OHM RES 0603 1/16W 1% 100 OHM 4 3 3 3 4 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN NO. 37 38 39 40 41 42 43 44 45 46 Part Number ERJ-3GSYJ104V ERJ-8GEYJ106V ERJ-3EKF1300V ERJ-3GSYJ151V ERJ-3EKF1820V ERJ-3GSYJ202V ERJ-3GSYJ222V ERJ-6GEYJ240V ERJ-3EKF3161V ERJ-3GSYJ330V Manufacturer PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC PANASONIC Ref Des R16_2, R8_1 R1_1, R2_1, R3_1 R12_1 R10_2 R1_2 R3_2, R4_2 R13_1 R11_1 R34 R1, R40, R41, R43, R62, R118 Description RES 0603 1/16W 5% 100K OHM RES 1206 1/8W 5% 10M OHM RES 0603 1/16W 1% 130 OHM RES 0603 1/16W 5% 150 OHM RES 0603 1/16W 1% 182 OHM RES 0603 1/16W 5% 2.0K OHM RES 0603 1/16W 5% 2.2K OHM RES 0805 1/10W 5% 24 OHM RES 0603 1/16W 1% 3.16K OHM RES 0603 1/16W 5% 33 OHM Qty 2 3 1 1 1 2 1 1 1 6 47 48 ERJ-3EKF39R2V ERJ-3GSYJ472V PANASONIC PANASONIC R16_1 R14_1, R15_1, R2, R29, R35, R38, R39, R42, R45-R47, R52, R53, R55-R57, R60, R61, R7_1, R7_2, R82R84, R122-R125 RES 0603 1/16W 1% 39.2 OHM RES 0603 1/16W 5% 4.7K OHM 1 27 49 50 51 52 53 ERJ-3GSYJ560V ERJ-3GSYJ561V ERJ-3EKF63R4V PANASONIC PANASONIC PANASONIC R10_1, R49, R51 R12_2, R13_2 R11_2 R33 RN10_1, RN11_1, RN12_1, RN13_1, RN14_1, RN17_1, RN18_1, RN19_1, RN20_1, RN21_1, RN7_1, RN8_1, RN9_1 RES 0603 1/16W 5% 56 OHM RES 0603 1/16W 5% 560 OHM RES 0603 1/16W 1% 63.4 OHM ? ? 3 2 1 1 13 DIGI-KEY -- P 54 55 PANASONIC -- EXB-V8V101JV PANASONIC -- EXB-V8V103JV ? ? RN87, RN115 RN22_1, RN23_1, RN24_1, RN25_1, RN26_1, RN27_1, RN28_1, RN29_1, RN30_1, RN31_1, RN32_1, RN33_1, RN34_1 ? ? 2 13 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN NO. 56 57 Part Number PANASONIC -- EXB-V8V102JV PANASONIC -- EXB-V8V330JV Manufacturer ? ? Ref Des RN15_1, RN6_1 RN35-RN58, RN60RN63, RN95, RN96, RN103 Description ? ? Qty 2 31 58 PANASONIC -- EXB-V8V472JV ? RN16_1, RN1_1, RN2_1, RN3_1, RN4_1, RN59, RN5_1, RN76RN85, RN104-RN11 4 ? 28 59 SIE501.8R IPD CONVERTERS U1_2 REGULATOR 5.0V TO 1.8V 6A, 100MV MAX RIPPLE CONVERTER 1 60 61 62 SSF-LXH5147LGD SSF-LXH5147LID N/A LUMEX LUMEX N/A D1, D3 D2 TP1-TP19, TP1_1, TP20-TP29, TP2_1, TP30-TP33 LED QUAD GREEN HORIZONTAL LED QUAD RED HORIZONTAL CONNECTOR HEADER STRAIGHT SINGLE .1" 2 1 35 63 540-99-020-17-400 000 MILL MAX MANUFACTURIN G U9, U12 SOCKET FOR IC XC1701L_PC20C 2 64 65 XC4036XLA-08HQ240 ZM4742A XILINX DIODES INC U11 D1_2 USE FROM APPS_LIB LIBRARY ZENER DIODE 12.0V 5% 1.0W SURFACE MOUNT 1 1 66 352068-1 AMP J1_1 CONNECTOR ZPACK CPCI 2MM HM 110 POS. TYPE A WITH GND SHIELD 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN NOTES PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 PRELIMINARY REFERENCE DESIGN PMC-2000207 ISSUE 2 PM7390 S/UNI MACH48 S/UNI-MACH48 REFERENCE DESIGN CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com Tel: (604) 415-4533 Fax: (604) 415-6206 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 2000 PMC-Sierra, Inc. PMC-2000207 (P1) ref PMC-1990823 (P4) Issue date: June 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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