a
Dual Channel, 12-Bit, 65 MSPS A/D Converter with Analog Input Signal Conditioning AD10265
performance. The AD10265 uses innovative high-density circuit design and laser-trimmed thin-film resistor networks to achieve exceptional matching and performance while still maintaining excellent isolation, and providing for significant board area savings. The AD10265 operates with 5.0 V for the analog signal conditioning with a separate +3.3 V supply for the analog-todigital conversion. Each channel is completely independent allowing operation with independent Encode and Analog inputs. The AD10265 also offers the user a choice of Analog Input Signal ranges to further minimize additional external signal conditioning, while still remaining general-purpose. The AD10265 is packaged in a 68-lead ceramic gull wing package, footprint compatible with the earlier generation AD10242 (12-bit, 40 MSPS). Manufacturing is done on Analog Devices' MIL-38534 Qualified Manufacturers Line (QML) and components are available up to Class-T (-25C to +125C). The AD6640 internal components are manufactured on Analog Devices' high-speed complementary bipolar process (XFCB).
PRODUCT HIGHLIGHTS
FEATURES Dual, 65 MSPS Minimum Sample Rate Channel-Channel Matching, 0.1% Gain Error Channel-Channel Isolation, >80 dB AC-Coupled Signal Conditioning Included Selectable Bipolar Input Voltage Range ( 0.5 V, 1.0 V, 2.0 V) Gain Flatness up to Nyquist: < 0.5 dB 80 dB Spurious-Free Dynamic Range Two's Complement Output Format 3.3 V or 5 V CMOS-Compatible Output Levels 1.05 W Per Channel Industrial and Military Grade APPLICATIONS Phased Array Receivers Communications Receivers FLIR Processing Secure Communications GPS Anti-Jamming Receivers Multichannel, Multimode Receivers PRODUCT DESCRIPTION
The AD10265 is a full channel ADC solution with on-module signal conditioning for improved dynamic performance and fully matched channel-to-channel performance. The module includes two wide dynamic range AD6640 ADCs. Each AD6640 has an AD9631/AD9632 ac-coupled amplifier front end. The AD6640s have on-chip track-and-hold circuitry, and utilize an innovative multipass architecture, to achieve 12-bit, 65 MSPS
1. Guaranteed sample rate of 65 MSPS. 2. Input amplitude options, user configurable. 3. Input signal conditioning included; both channels matched for gain. 4. Fully tested/characterized performance for full channel. 5. Footprint compatible family; 68-lead LCCC.
FUNCTIONAL BLOCK DIAGRAM
AINA3 AINA2 AINA1 AINB3 AINB2 AINB1
AD9632 (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A 9 OUTPUT BUFFERING TIMING AD6640 12 AIN AIN
AD9631
AD9632
AD9631
AIN
AIN
TIMING
ENCODEB ENCODEB
AD10265
AD6640 D11B (MSB) 12 OUTPUT BUFFERING 7 5 D10B D9B D8B D7B
ENCODEA ENCODEA
D9A
D10A
D11A (MSB)
D0B (LSB)
D1B
D2B
D3B
D4B
D5B
D6B
REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2001
AD10265-SPECIFICATIONS
Electrical Characteristics (AV
Parameter RESOLUTION ACCURACY No Missing Codes Offset Error Gain Error1 Gain Error Channel Match Pass Band Ripple to Nyquist ANALOG INPUT (AIN) Input Voltage Range AIN1 AIN2 AIN3 Input Resistance AIN1 AIN2 AIN3 Input Capacitance2 Analog Input Bandwidth High 3 Analog Input Bandwidth Low 3 ENCODE INPUT4, 5 Logic Compatibility Logic "1" Voltage Logic "0" Voltage Logic "1" Current (VINH = 5 V) Logic "0" Current (VINL = 0 V) Input Capacitance SWITCHING PERFORMANCE Maximum Conversion Rate6 Minimum Conversion Rate 6 Aperture Delay (tA) Aperture Delay Matching Aperture Uncertainty (Jitter) ENCODE Pulsewidth High ENCODE Pulsewidth Low Output Delay (tOD) SNR7 Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz SINAD8 Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz Full Full 25C Full Full Full IV IV I VI V IV 12 2, 3 1 2, 3 12
CC
= +5 V; AVEE = -5.0 V; DVCC = +3.3 V; applies to each ADC unless otherwise noted.)
Test Level Mil Subgroup Min AD10265AZ Typ 12 Guaranteed +3.5 0.5 0.8 0.2 0.2 Max Unit Bits
Temp
-10 -1.5 -2.5
+10 +1.5 +2.5 0.5
mV % FS % FS % dB
Full Full Full Full Full Full 25C 25C 25C
V V V IV IV IV IV V V IV IV IV IV IV IV VI IV V V V IV IV IV I II I II I II I II I II I II 12 12 12 12 99 198 396 0
0.5 1.0 2 100 200 400 4.0 160 50 TTL/CMOS 2.0 0 500 -400 12 4, 5, 6 12 65 6.5 400 2.0 0.3 12 12 12 4 5, 6 4 5, 6 4 5, 6 4 5, 6 4 5, 6 4 5, 6 6.5 6.5 7.0 62 60.5 61 60 61 59.5 61 60 61 59.5 61 59 5.0 0.8 800 -200 7.0 101 202 404 7.0
V V V pF MHz kHz
Full Full Full Full 25C Full Full 25C 25C 25C 25C 25C Full 25C Full 25C Full 25C Full 25C Full 25C Full 25C Full
650 -320 4.5
V V A A pF MSPS MSPS ps ns ps rms ns ns ns dB dB dB dB dB dB dB dB dB dB dB dB
9.0 66 66 65 65 63 62 65 64 64 63 62 62
12.5
-2-
REV. A
AD10265
Parameter SPURIOUS-FREE DYNAMIC RANGE Analog Input @ 1.24 MHz @ 17 MHz @ 32 MHz TWO-TONE IMD REJECTION 10 f1, f2 @ -7 dBFS CHANNEL-TO-CHANNEL ISOLATION LINEARITY Differential Nonlinearity (Encode = 20 MHz) Integral Nonlinearity (Encode = 20 MHz) DIGITAL OUTPUTS Logic Compatibility Logic "1" Voltage Logic "0" Voltage Output Coding POWER SUPPLY AVCC Supply Voltage I (AVCC) Current AVEE Supply Voltage I (AVEE) Current DVCC Supply Voltage I (DVCC) Current ICC (Total) Supply Current Power Dissipation (Total) Power Supply Rejection Ratio (PSRR)
11 9
Temp 25C Full 25C Full 25C Full Full 25C
Test Level I II I II V V V IV
Mil Subgroup 4 5, 6 4 5, 6
Min 75 74 71 70
AD10265AZ Typ 80 80 80 79 79 79 77
Max
Unit dBFS dBFS dBFS dBFS dBFS dBFS dBc dB
4, 5, 6 12
66 80
25C Full
IV V
12
-1.0
0.5 1.25
+1.5
LSB LSB
Full Full
I I
1, 2, 3 1, 2, 3
2.8
CMOS DVCC - 0.2 0.2 0.5 Two's Complement +5.0 336 -5.0 66 +3.3 20 422 2.1 0.01
V V
Full Full Full Full Full Full Full Full Full
V V V V V V I I IV
1, 2, 3 1, 2, 3 12
520 2.4 0.02
V mA V mA V mA mA W % FSR/% VS
NOTES 1 Gain tests are performed on A IN1 over specified input voltage range. 2 Input capacitance specifications show only ceramic package capacitance. 3 Full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by FFT analysis) is reduced by 3 dB. 4 ENCODE driven by single-ended source; ENCODE bypassed to ground through 0.01 F capacitor. 5 ENCODE may also be driven differentially in conjunction with ENCODE; see "Encoding the AD10265" for details. 6 Minimum and maximum conversion rates allow for variation in Encode Duty Cycle of 50% 5%. 7 Analog Input signal power at -1 dBFS; signal-to-noise ratio (SNR) is the ratio of signal level to total noise (first 5 harmonics removed). Encode = 65 MSPS. 8 Analog Input signal power at -1 dBFS; signal-to-noise and distortion (SINAD) is the ratio of signal level to total noise + harmonics. Encode = 65 MSPS. 9 Analog Input signal equal -1 dBFS; SFDR is ratio of converter full scale to worst spur. 10 Both input tones at -7 dBFS; two-tone intermodulation distortion (IMD) rejection is the ratio of either tone to the worst third order intermod product. f1 = 17.0 MHz 100 kHz, f2 = 18.0 MHz 100 kHz. 11 Channel-to-channel isolation tested with A channel/50 ohm terminated REV. A
-3-
AD10265
ABSOLUTE MAXIMUM RATINGS 1 Parameter ELECTRICAL VCC Voltage VEE Voltage Analog Input Voltage Analog Input Current Digital Input Voltage (ENCODE) ENCODE, ENCODE Differential Voltage Digital Output Current ENVIRONMENTAL Operating Temperature (Case) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient)
2
Table I. Output Coding Min 0 -7 VEE -10 0 -10 -55 Max +7 0 VCC +10 AVCC 4 +10 +125 175 300 +150 Unit V V V mA V V mA C C C C
MSB
LSB
Base 10 2047 +1 0 -1 2048
Input +FS 0.0 V -FS
0111111111111 0000000000001 0000000000000 1111111111111 1000000000000
EXPLANATION OF TEST LEVELS
Test Level
I. 100% production tested. II. 100% production tested at 25C, and sample tested at specified temperatures. AC testing done on sample basis. III. Sample tested only. IV. Parameter is guaranteed by design and characterization testing. V. Parameter is a typical value only. VI. All devices are 100% production tested at 25C; sample tested at temperature extremes.
-65
NOTES 1 Absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. Functional operability is not necessarily implied. Exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 Typical thermal impedances for "Z" package: JC = 11C/W; JA = 30C/W.
ORDERING GUIDE
Model
Temperature Range -25C to +85C (Case) +25C -25C to +125C (Case) -25C to +125C (Case)
Package Description 68-Lead Ceramic Leaded Chip Carrier Evaluation Board with AD10265AZ 68-Lead Ceramic Leaded Chip Carrier 68-Lead Ceramic Leaded Chip Carrier
Package Option ES-68C ES-68C ES-68C
AD10265AZ AD10265/PCB 5962-9865901 HXA 5962R0151901 TXA
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD10265 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
-4-
REV. A
AD10265
PIN FUNCTION DESCRIPTIONS
Pin No. 1 2, 5, 9-11, 26, 27 3, 4, 12, 15, 16, 34, 35, 55-57 6 7 8 13 14 17-25, 31-33 28 29 30 36-42, 45-49 43, 44, 53, 54, 58-61, 65, 68 50 51 52 62 63 64 66 67
Name SHIELD GNDA NC AINA1 AINA2 AINA3 AVEE AVCC D0A-D11A ENCODEA ENCODEA DVCC D0B-D11B GNDB DVCC ENCODEB ENCODEB AINB1 AINB2 AINB3 AVCC AVEE
Function Internal Ground Shield between channels. A Channel Ground. A and B grounds should be connected as close to the device as possible. No Connect. Pins 15 and 16 are internal test pins: it is recommended to connect them to GND. Analog Input for A side ADC (nominally 0.5 V). Analog Input for A side ADC (nominally 1.0 V). Analog Input for A side ADC (nominally 2.0 V). Analog Negative Supply Voltage (nominally -5.0 V). For A side ADC. Analog Positive Supply Voltage (nominally +5.0 V). For A side ADC. Digital Outputs for ADC A. D0 (LSB). ENCODE is complement of ENCODE. Data conversion initiated on rising edge of ENCODE input. Digital positive supply voltage (nominally 3.3 V) for A side ADC. Digital Outputs for ADC B. D0 (LSB). B Channel Ground. A and B grounds should be connected as close to the device as possible. Digital Positive Supply Voltage (nominally 3.3 V) for B side ADC. Data conversion initiated on rising edge of ENCODE input. ENCODE is complement of ENCODE. Analog Input for B side ADC (nominally 0.5 V). Analog Input for B side ADC (nominally 1.0 V). Analog Input for B side ADC (nominally 2.0 V). Analog Positive Supply Voltage (nominally +5.0 V). For B side ADC. Analog Negative Supply Voltage (nominally -5.0 V). For B side ADC.
PIN CONFIGURATION 68-Lead Ceramic Leaded Chip Carrier
GNDA AINA3 AINA2 AINA1 GNDA NC NC GNDA SHIELD GNDB AVEE AVCC GNDB AINB3 AINB2 AINB1
9 8 7 6 5 4 3 2
1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
GNDA GNDA NC AVEE AVCC NC NC (LSB) D0A D1A D2A D3A D4A D5A D6A D7A D8A GNDA
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
GNDB
PIN 1
AD10265
TOP VIEW (Not to Scale)
GNDB GNDB GNDB NC NC NC GNDB GNDB ENCODEB ENCODEB DVCC D11B (MSB) D10B D9B D8B D7B GNDB
NC = NO CONNECT
REV. A
GNDA ENCODEA ENCODEA DVCC D9A D10A (MSB) D11A NC NC (LSB) D0B D1B D2B D3B D4B D5B D6B GNDB
-5-
AD10265
DEFINITION OF SPECIFICATIONS Analog Bandwidth Output Propagation Delay
The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of ENCODE command and the time when all output data bits are within valid logic levels.
Power Supply Rejection Ratio
The delay between the 50% point of the rising edge of the ENCODE command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The ratio of a change in input offset voltage to a change in power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The sample-to-sample variation in aperture delay.
Differential Nonlinearity
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc.
Signal-to-Noise Ratio (without Harmonics)
The deviation of any code from an ideal 1 LSB step.
Encode Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time that the ENCODE pulse should be left in logic "1" state to achieve rated performance; pulsewidth low is the minimum time ENCODE pulse should be left in low state. At a given clock rate, these specs define an acceptable encode duty cycle.
Harmonic Distortion
The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Spurious-Free Dynamic Range
The ratio of the rms signal amplitude to the rms value of the worst harmonic component.
Integral Nonlinearity
The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale).
Two-Tone Intermodulation Distortion Rejection
The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a "best straight line" determined by a least square curve fit.
Minimum Conversion Rate
The ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dBc.
Two-Tone SFDR
The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit.
Maximum Conversion Rate
The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product. May be reported in dBc (i.e., degrades as signal level is lowered) or in dBFS (always related back to converter full scale).
The encode rate at which parametric testing is performed.
-6-
REV. A
AD10265
N N+1 N+2 N+3 N+4 N+5
TTL CLOCK f 10MHz
ENC ENC
AIN
AINA3
tA
ENCODE
AINA2 AINA1
1/2 AD10265 SHOWN
tOD
DIGITAL OUTPUTS N-2 N-1 N N+1 N+2
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTE: ALL 5V SUPPLY PINS BYPASSED TO GND WITH A 0.1 F CAPACITOR
Figure 1. Timing Diagram
Figure 2. Equivalent Burn-In Circuit
EQUIVALENT CIRCUITS
DVCC
AINA3 AINA2
R4 200 R3 100
CURRENT MIRROR
AINA1
DVCC
Figure 3. Analog Input Stage
VREF
AVCC
D0 - D11
AVCC R1 17k ENCODE R2 8k TIMING CIRCUITS R2 8k R1 17k
AVCC
ENCODE
CURRENT MIRROR
Figure 4. Encode Inputs
Figure 5. Digital Output Stage
REV. A
-7-
AD10265-Typical Performance Characteristics
0
POWER RELATIVE TO FULL SCALE - dB POWER RELATIVE TO FULL SCALE - dB
0 ENCODE = 65.0MSPS AIN = 1.24MHz AIN = -1.004dBFS SNR = 64.88dB SFDR = 78.81dBc -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1024 2048 3072 4096 5120 FREQUENCY - MHz 6144 7168 8192 ENCODE = 65.0MSPS AIN = 17MHz AND 18MHz AIN = -7.067dBFS SFDR = 78dBc
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1024 2048
3072 4096 5120 FREQUENCY - MHz
6144
7168
8192
TPC 1. Single Tone @ 1.24 MHz
TPC 4. Two-Tone FFT @ 17 MHz/18 MHz
0 POWER RELATIVE TO FULL SCALE - dB -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1024 2048 3072 4096 5120 FREQUENCY - MHz 6144 7168 8192 SNR - dB ENCODE = 65.0MSPS AIN = 17MHz AIN = -1dBFS SNR = 63.83dB SFDR = 78.22dBc
66 ENCODE = 65MHz 65 +25 C 64
63 +125 C 62 -55 C 61
60 1.24
17 ANALOG FREQUENCY - MHz
32
TPC 2. Single Tone @ 17 MHz
TPC 5. SNR vs. AIN
0
POWER RELATIVE TO FULL SCALE - dB
90
-10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 0 1024 2048
ENCODE = 65.0MSPS AIN = 32MHz AIN = -1.021dBFS SNR = 64.11dB SFDR = 78.14dBc
SFDR - dBc
80 70 60 50 SFDR - 75dB 40 30 20 10 AIN = 17MHz ENCODE RATE 65MHz SFDR - dBFS SFDR - dBc
3072 4096 5120 FREQUENCY - MHz
6144
7168
8192
0 -70.18
-60.09
-50.18 -39.92 -30.07 -20.02 FUNDAMENTAL - dBFS
-10.1
-1.099
TPC 3. Single Tone @ 32 MHz
TPC 6. Single-Tone SFDR (AIN @ 17 MHz) vs. Power Level
-8-
REV. A
AD10265
90 80 SFDR - dBc
0 -1 -2 -3
LEVEL - dBFS SNR - dB
SNR, WORST SPUR - dB, dBc
70 60 50 40 30 20 10 0 1.24 ENCODE FREQUENCY = 65MHz AIN = -1dBFS
-4 -5 -6 -7 -8 -9 ENCODE RATE = 65MHz ROOM TEMPERATURE
17
32 37 65 80 ANALOG INPUT FREQUENCY - MHz
100
-10 0.02 0.04 0.06 0.08 0.1 0.3 0.5 20 60 FREQUENCY - MHz
90
120 140 160
TPC 7. SNR/Harmonics to AIN > Nyquist MSPS
TPC 8. Gain Flatness vs. Input Frequency
REV. A
-9-
AD10265
THEORY OF OPERATION
Refer to the Functional Block Diagram. The AD10265 employs three monolithic ADI components per channel (AD9631, AD9632, and AD6640), along with multiple passive resistor networks and decoupling capacitors to fully integrate a complete 12-bit analog-to-digital converter. The input signal is first passed through a precision laser-trimmed resistor divider, allowing the user to externally select operation with a full-scale signal of 0.5 V, 1.0 V, or 2.0 V by choosing the proper input terminal for the application. Since the AD6640 implements a true differential analog input, the AD9631/AD9632 have been configured to provide a differential input for the AD6640 ADC through ac-coupling. The ac signal gain of the AD9631/AD9632 can be trimmed to provide a constant differential input to the AD6640. This allows the converter to be used in multiple system applications without the need for external gain circuit normally requiring trim. The AD9631/AD9632 were chosen for their superior ac performance and input drive capabilities, which have limited the ability of many amplifiers to drive high-performance ADCs. As new amplifiers are developed, pin-compatible improvements are planned to incorporate the latest operational amplifier technology.
APPLYING THE AD10265 Encoding the AD10265
ENCODE SOURCE V1 0.01 F Rx
ENCODE ENCODE
5V R1 R2
AD10265
Figure 7. Lower Threshold for Encode
V1 = 5R2 R1Rx to raise logic threshold. R2 + R1+ Rx
AVCC Rx ENCODE SOURCE V1 0.01 F 5V ENCODE ENCODE R1 R2
AD10265
Figure 8. Raise Logic Threshold for Encode
Best performance is obtained by driving the encode pins differentially. However, the AD10265 is also designed to interface with TTL and CMOS logic families. The source used to drive the ENCODE pin(s) must be clean and free from jitter. Sources with excessive jitter will limit SNR and overall performance.
AD10265
TTL OR CMOS SOURCE ENCODE ENCODE 0.01 F
While the single-ended encode will work well for many applications, driving the encode differentially will provide increased performance. Depending on circuit layout and system noise, a 1 dB to 3 dB improvement in SNR can be realized. It is recommended that differential TTL logic be used, however, because most TTL families that support complementary outputs are not delay or slew rate matched. Instead, it is recommended that the encode signal be ac-coupled into the ENCODE and ENCODE pins. The simplest option is shown below. The low jitter TTL signal is coupled with a limiting resistor, typically 100 , to the primary side of an RF transformer (these transformers are inexpensive and readily available; part number in Figure 9 is from MiniCircuits). The secondary side is connected to the ENCODE and ENCODE pins of the converter. Since both encode inputs are self-biased, no additional components are required.
100 TTL T1-1T
Figure 6. Single-Ended TTL/CMOS Encode
The AD10265 encode inputs are connected to a differential input stage (see Figure 4 under Equivalent Circuits). With no input connected to either ENCODE pin, the voltage divider biases the inputs to 1.6 V. For TTL or CMOS usage, the encode source should be connected to ENCODE. ENCODE should be decoupled using a low inductance or microwave chip capacitor to ground. If a logic threshold other than the nominal 1.6 V is required, the following equations show how to use an external resistor, Rx, to raise or lower the trip point (see Figure 4, R1 = 17 k, R2 = 8 k).
V1 = 5R2Rx to lower logic threshold. R1R2 + R1Rx + R2Rx
ENCODE
AD10265
ENCODE
Figure 9. TTL Source--Differential Encode
A clean sine wave may be substituted for a TTL clock. In this case, the matching network is shown below. Select a transformer ratio to match source and load impedances. The input impedance of the AD10265 encode is approximately 11 k differentially. Therefore "R," shown in Figure 10, may be any value that is convenient for available drive power.
SINE SOURCE T1-1T R ENCODE
ENCODE
AD10265
Figure 10. Sine Source--Differential Encode
-10-
REV. A
AD10265
If a low jitter ECL clock is available, another option is to ac-couple a differential ECL signal to the encode input pins as shown below. The capacitors shown here should be chip capacitors, but do not need to be of the low inductance variety.
0.1 F ECL GATE ENCODE 0.1 F ENCODE 510 510
GROUNDING AND DECOUPLING Analog and Digital Grounding
Proper grounding is essential in any high speed, high resolution system. Multilayer printed circuit boards (PCBs) are recommended to provide optimal grounding and power schemes. The use of ground and power planes offers distinct advantages: 1. The minimization of the loop area encompassed by a signal and its return path. 2. The minimization of the impedance associated with ground and power paths. 3. The inherent distributed capacitor formed by the power plane, PCB insulation, and ground plane. These characteristics result in both a reduction of electromagnetic interference (EMI) and an overall improvement in performance. It is important to design a layout that prevents noise from coupling to the input signal. Digital signals should not be run in parallel with input signal traces and should be routed away from the input circuitry. The AD10265 does not distinguish between analog and digital ground pins as the AD10265 should always be treated as an analog component. All ground pins should be connected together directly under the AD10265. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low impedance path and manage the power and ground currents. The ground plane should be removed from the area near the input pins to reduce stray capacitance.
LAYOUT INFORMATION
AD10265
-VS
Figure 11. Differential ECL for Encode
As a final alternative, the ECL gate may be replaced by an ECL comparator. The input to the comparator could then be a logic signal or a sine signal.
AD96687 (1/2)
0.1 F ENCODE 50 510 510 0.1 F ENCODE
AD10265
-VS
Figure 12. ECL Comparator for Encode
USING THE FLEXIBLE INPUT
The AD10265 has been designed with the user's ease of operation in mind. Multiple input configurations have been included on board to allow the user a choice of input signal levels and input impedance. While the standard inputs are 0.5 V, 1.0 V, and 2.0 V, the user can select the input impedance of the AD10265 on any input by using the other inputs as alternate locations for GND or an external resistor. The following chart summarizes the impedance options available at each input location: AIN1 = 100 when AIN2 and AIN3 Are Open. AIN1 = 75 when AIN3 Is Shorted to GND. AIN1 = 50 when AIN2 Is Shorted to GND. AIN2 = 200 when AIN3 Is Open. AIN2 = 100 when AIN3 Is Shorted to GND. AIN2 = 75 when AIN2 to AIN3 Has an External Resistor of AIN2 = 300 , with AIN 3 Shorted to GND. AIN2 = 50 when AIN2 to AIN3 Has an External Resistor of AIN2 = 100 , with AIN3 Shorted to GND. AIN3 = 400 . AIN3 = 100 when AIN3 Has an External Resistor of 133 to GND. AIN3 = 75 when AIN3 Has an External Resistor of 92 to GND. AIN3 = 50 when AIN3 Has an External Resistor of 57 to GND.
The schematic of the evaluation board (Figure 13) represents a typical implementation of the AD10265. The pinout of the AD10265 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design practices. It is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. All capacitors can be standard high quality ceramic chip capacitors. Care should be taken when placing the digital output runs. Because the digital outputs have such a high slew rate, the capacitive loading on the digital outputs should be minimized. Circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. Internal circuitry buffers the outputs of the AD6640 ADC through a resistor network to eliminate the need to externally isolate the device from the receiving gate.
REV. A
-11-
AD10265
J1 AINB3 AGNDB J2 AINB2 AGNDB J22 AINB1 AGNDB J7 AINA3 AGNDA J8 AINA2 AGNDA
AGNDA
JP5 CLKLATCHB2 LATCHB JP1 6 BUFLATB
CLKLATCHB1 JP3 DRBOUT DRAOUT JP4 CLKLATCHA1 JP6 CLKLATCHA2
1 2
U2:A
3
13 12
U2:D
11
4 5
U2:B
74LCX00M
74LCX00M
74LCX00M
1 2
U4:A
3
13 12
U4:D
11
4 5
U4:B
6 JP2
74LCX00M
74LCX00M
74LCX00M
BUFLATA LATCHA
-5.2VAB
47 AT 100MHz L9 47
47 AT 100MHz L8 47
+5VAB
C59 10 F AGNDB
AINA3 AINA2 AINA1
C52 10 F AGNDB
J20 AINA1 C57 0.1 F AGNDA
+5VAB
AINB3 AINB2
68
67 66 65
64 63 62
AGNDA AINA3
AINA2 AINA1 AGNDA NC NC AGNDA
SHIELD AGNDB
AVEE GNDB AINB3
AINB2 AINB1
-5.2VAA L10 C22 10 F AGNDA +5VAA L7 C53 10 F AGNDA 47 47 AT 100MHz 47
36 D0B(LSB) 37 D1B 38 D2B 39 D3B 40 D4B 41 D5B 42 D6B 43 DGNDB
D9A D10A D11A(MSB) NC NC
AVEE D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A
DGNDA ENCAB ENCA DVCC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
GNDB
AVEE
AGNDA AGNDA AGNDA NC AVEE AVEE NC NC D0A(LSB) D1A D2A D3A D4A D5A D6A D7A D8A DGNDA
61
9 8 7 6 5 4 3 2 1
AINB1
U1
AD10265
GNDB GNDB GNDB NC NC NC GNDB GNDB ENCBB ENCB DVCC
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 AGNDB
C61 0.1 F DRBOUT AGNDB ENCBB ENCB DUT 3.3VDB D13B(MSB) C64 0.1 F D12B D11B D10B D9B
L6 47
+3.3VDB
D11B(MSB) D10B D9B D8B D7B GNDB
C58 10 F
DGNDB
ENCAB ENCA
DUT 3.3VDA D11A D12A D13A
D0B D1B D2B
27 28 29 30 31 32 33 34 35
D3B D4B D5B
D6B D7B
DGNDA NC = NO CONNECT L11 +3.3VDA C62 10 F DGNDA 47
D8B
DGNDB
DUT 3.3VDB C63 0.1 F DGNDA C26 0.1 F 9
SPARE GATE 10
DUT 3.3VDA
SPARE GATE 10 9
U2:C
8
C27 0.1 F
U4:C
8
74LCX00M DGNDB DGNDB DGNDA
74LCX00M
DGNDA
Figure 13a. Evaluation Board Schematic
-12-
REV. A
AD10265
+5VAA
U6 2
ADP3330
IN OUT NR SD ERR GND 4
1 8 3 C45 100pF AGNDA
6 +5VAA
J6 ENCODEA AGNDA
C42 0.1 F
JP11 OPEN R140 33k
AGNDA U7 C44 0.1 F VCC Q Q VEE 8 7 6 5 C41 0.47 F R89 100 C49 0.1 F ENCA R94 100 ENCAB
R82 51
AGNDA J18 ENCODEA AGNDA R83 51 JP8 JP7 C40 0.1 F
1 2 3 4
NC D D VBB
AGNDA
MC10EP16D NC = NO CONNECT AGNDA
AGNDA
AGNDA
+5VAA
U8 2
ADP3330
IN OUT NR SD ERR GND 4
1 8 3 C43 100pF AGNDB
6 +5VAA
J16 ENCODEB AGNDB
C37 0.1 F
JP12 OPEN R141 33k
AGNDB U9 C48 0.1 F VCC Q Q VEE 8 7 6 5 C38 0.47 F R95 100 C46 0.1 F ENCBB R97 100 ENCB
R76 51
AGNDB J17 ENCODEB AGNDB R79 51 JP10 JP9 C39 0.1 F
1 2 3 4
NC D D VBB
AGNDB
MC10EP16D NC = NO CONNECT AGNDB
AGNDB
AGNDB
Figure 13b. Evaluation Board Schematic
REV. A
-13-
AD10265
DUT_3.3VDA DUT_3.3VDA DUT_3.3VDA R92 33k JP8 JP7 U10 1 2 3 4 NC D D VBB VCC Q Q VEE 8 7 6 5 DGNDA C47 0.1 F DGNDA R90 100 DGNDA R91 100 1 2 3 4 D0 D0 D1 D1 U11 VCC Q Q GND 8 7 6 5 C51 0.1 F CLKLATCHA1 CLKLATCHA2
MC10EP16D
MC100EPT23 DGNDA DGNDA
DUT_3.3VDB
DUT_3.3VDB DUT_3.3VDB
R93 33k JP10 JP9
U12 1 2 3 4 NC D D VBB VCC Q Q VEE 8 7 6 5 DGNDB C54 0.1 F DGNDB R138 100 DGNDB R96 100 1 2 3 4 D0 D0 D1 D1 U13 VCC Q Q GND 8 7 6 5 C65 0.1 F CLKLATCHB1 CLKLATCHB2
MC10EP16D
MC100EPT23 DGNDB DGNDB
Figure 13c. Evaluation Board Schematic
-14-
REV. A
AD10265
DUT 3.3VDA U21 C13 0.1 F C14 0.1 F C15 0.1 F C20 0.1 F LATCHA DGNDA BANANA JACKS FOR GNDS AND PWRS (LSB) D0A +5VAB +5VAA E1 DGNDA E2 E3 E4 E5 E6 E7 E8 E9 E10 -5.2VAB -5.2VAA AGNDA DGNDB DGNDA D6A D7A D8A D9A D10A D11A D12A (MSB) D13A +3.3VDB R100 0 R99 0 D1A D2A D3A D4A D5A VCC R98 51 25 24 VCC CP2 VCC 42 31 7 16 R114 100 R113 100 R105 100 R104 100 R106 100 R118 51 BUFLATA R103 100 R102 100 R101 100 R109 100 R108 100 R107 100 R110 100 R111 100 MSB 20 LSB 19 18 17 16 15 14 13 12 11 10 9 8 20 19 18 17 16 15 14 13 12 11 10 9 8 21 22 23 24 25 26 27 28 29 30 31 32 33 21 22 23 24 25 26 27 28 29 30 31 32 33 R115 100 R116 100 DUT 3.3VDA R117 100
+3.3VDA
OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND
VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8
O7 O6 O5 O4 O3 O2 O1 O0 GND GND
12 11 9 8 6 5 3 2 21 15
18 GND 4 GND
7 7 6 6 5 5 4 4 3 3 2 2 1 1 J3
34 34 35 35 36 36 37 37 38 38 39 39 40 40
74LCX163743MTD
DGNDA
AGNDB
DGNDA
DUT 3.3VDA U22 C25 0.1 F C21 0.1 F C23 0.1 F C24 0.1 F LATCHB DGNDB E87 E88 E89 E139 E143 E146 E148 E149 E152 E153 E184 E188 E189 E190 E195 E197 E199 E201 E203 E205 E224 E226 E159 E160 E161 E167 E168 E169 E170 E178 E180 E182 E183 E191 E192 E193 E208 E210 E212 E214 E216 E218 E220 E222 E228 E230 E232 E234 DGNDB VCC R119 51 25 24 VCC CP2 VCC
DUT 3.3VDB 42 31 7 R125 100 R127 100
R112 100
R126 100
(LSB) D0B R123 0 R124 D1B 0 D2B D3B D4B D5B DGNDB
E72 E140 E141 E142 E144 E145 E147 E150 E151 E154 E185 E194 E196 E198 E200 E202 E204 E206 E223 E225
DGNDA
AGNDA
E162 E163 E164 E165 E166 E171 E172 E177 E179 E181 E186 E187 E207 E209 E211 E213 E215 E217 E219 E221 E227 E229 E231 E233
D6B D7B D8B D9B D10B D11B D12B (MSB) D13B
OE2 26 I15 27 I14 29 I13 30 I12 32 I11 33 I10 35 I9 36 I8 48 CP1 1 OE1 37 I7 38 I6 40 I5 41 I4 43 I3 44 I2 46 I1 47 I0 28 GND 34 GND 39 GND 45 GND
16 VCC 23 O15 22 O14 20 O13 19 O12 17 O11 16 O10 14 O9 13 O8
R130 100 R129 100 R128 100 R134 100 R137 51 BUFLATB R135 100 R136 100 R131 100 R132 100 R133 100 R120 100 R121 100 R122 100 MSB
20 LSB
20 19 19 18 18 17 17 16 16 15 15 14 14 13 13 12 12 11 11 10 10 9 9 8 8 7 7 6 6 5 5 44 33 2 1 2 1 J4
21 21 22 22 23 23 24 24 25 25 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 33 34 34 35 35 36 36 37 37 38 38 39 39 40 40
O7 O6 O5 O4 O3 O2 O1 O0 GND GND
12 11 9 8 6 5 3 2 21 15 18
GND 4 GND
74LCX163743MTD
DGNDB
AGNDB
DGNDB
Figure 13d. Evaluation Board Schematic
REV. A
-15-
AD10265
EVALUATION BOARD
The AD10265 evaluation board (Figure 14) is designed to provide optimal performance for evaluation of the AD10265 analog-to-digital converter. The board encompasses everything needed to ensure the highest level of performance for evaluating the AD10265.
Power to the analog supply pins is connected via banana jacks. The analog supply powers the crystal oscillator, the associated components and amplifiers, and the analog section of the AD10265. The digital outputs of the AD10265 are powered via Pin 1 of either J1 or J2 found on the digital interface connector with 3.3 V. Contact the factory if additional layout or applications assistance is required.
6.20 0.005
0.00
Figure 14. Evaluation Board Mechanical Layout
5.50 0.005
0.00
-16-
REV. A
AD10265
Bill of Materials List for AD10265 Evaluation Board
Reference Qty Designator 2 2 1 2 10 30 U2, U4 U21, U22 U1 U6, U8 E1-E10 C13-C15, C20, C21, C23-C27, C37, C39, C40, C41, C42, C44, C46, C47, C48, C49, C54-C58, C60, C61, C63, C64, C65 C38, C41 C43, C45 J3, J4 L6-L11 U7, U9, U10, U11 C22, C50, C52, C53, C59, C62 R99, R100, R123, R124 R92, R93, R140, R141 R76, R79, R82, R83, R98, R118, R119, R137 R89, R90, R91, R94, R95, R97, R101-R117, R120-R122, R125-R136, R138 J1, J2, J6-J8, J16-J18, J20, J22 U11, U13 10 F 0.0 33,000 51 47 H 0.1 F Value Description IC, Low-Voltage Quad 2-Input Nand, SOIC-14 IC, 16-Bit Transparent Latch with Three-State Outputs, TSSOP-48 DUT, IC 14-Bit Analog-to-Digital Converter IC, Voltage Regulator 3.3 V, RT-6 Banana Jack, Socket Capacitor, 0.1 F, 20%, 12 V dc, 0805 Manufacturer and Part Number Toshiba/TC74LCX00FN Fairchild/74LCX163743MTD ADI/AD10265AZ Analog Devices/ADP3330ART-3, 3-RLT Johnson Components/08-0740-001 Mena/GRM40X7R104K025BL Component Name 74LCX00M 74LCX163743MTD ADI/AD10465AZ ADP3330 Banana Hole CAP 0805
2 2 2 6 4 6
0.47 F 100 pF
Capacitor, 0.47 F, 5%, 12 V dc, 1206 Capacitor, 100 pF, 10%, 12 V dc, 0805 Connector, 40-pin Header Male St. Inductor, 47 H @ 100 MHz, 20%, IND2 IC, Differential Receiver, SOIC-8 Capacitor, 10 F, 20%, 16 V dc, 1812POL Resistor, 0.0 , 0805 Resistor, 33,000 , 5%, 0.10 Watt, 0805 Resistor, 51 , 5%, 0.10 Watt, 0805
Vitramon/VJ1206U474MFXMB Johansen/500R15N101JV4 Samtec/TSW-120-08-G-D Fair-Rite/2743019447 Motorola/MC10EP16D
CAP 1206 CAP 0805 HD40M IND2 MC10EP16D
Kemet/T491C106M016A57280
POLCAP 1812
4
Panasonic/ERJ-6GEY0R00V Panasonic/ERJ-6GEYJ333V
RES2 0805 RES2 0805
4
8
Panasonic/ERJ-6GEYJ510V
RES2 0805, RES 0805
40
100
Resistor, 100 , 5%, 0.10 Watt, 0805
Panasonic/ERJ-6GEYJ101V
RES2 0805, RES 0805
8
Connector, SMA Female St.
Johnson Components/142-0701-201 SMA
2
IC Op Amp, SOIC-8
Motorola/MC100EPT23
MC100EPT23
REV. A
-17-
AD10265
Figure 15. Top Layer Copper
Figure 16. Second Layer Copper
-18-
REV. A
AD10265
Figure 17. Third Layer Copper
Figure 18. Fourth Layer Copper
REV. A
-19-
AD10265
Figure 19. Fifth Layer Copper
Figure 20. Bottom Layer Copper
-20-
REV. A
AD10265
Figure 21. Bottom Silkscreen
Figure 22. Bottom Assembly
REV. A
-21-
AD10265
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Ceramic Leaded Chip Carrier (ES-68C)
1.180 (29.97) SQ 0.950 (24.13) SQ 0.060 (1.52)
10 PIN 1 9 61 60
0.800 (20.32)
TOP VIEW
(PINS DOWN)
26 27 43
44
0.240 (6.096)
0.050 (1.27)
0.018 (0.457)
-22-
REV. A
-23-
-24-
C00666-0-6/01(A)
PRINTED IN U.S.A.
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