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Data Sheet
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
June 1997
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.1
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Features: Single 5.0-Volt Read and Write Operations CMOS SuperFlash EEPROM Technology Endurance: 250,000 Cycles (typical) Greater than 100 Years Data Retention Memory Organization: 512K x 8/1M x 4 PCMCIA Common Memory 1K x 8/2K x 4 Attribute Memory for User Alterable PCMCIA Attribute Memory Low Power Consumption: Active Current: 15 mA (typical) Standby Current: 5 A (typical) Fast Sector Erase/Byte Program Operation Byte Program Time: 30 s (typical) Sector Erase Time: 60 s (typical) Complete Memory Rewrite: 15 sec (typical) Fast Access Time: 150 and 250 ns Product Description The 28PC040 is organized as a 512K x 8 (bits) common memory array plus a 1K x 8 attribute memory array. The attribute memory can be a ccessed by asserting REG# or issuing an Enable_Attribute command. Either one nibble or two nibbles in a byte can be read in one cycle with internal decoding of CEL#, CEH#, and HB. The 28PC040 must be configured as a pair per 1Mbyte of PCMCIA application memory. Each byte in the PCMCIA memory map consists of two nibbles, one from each 28PC040 in the pair. Each 28PC040 has 4M bits of common memory and 8K bits of attribute memory and is manufa ctured using SST's proprietary, high performance CMOS SuperFlash EEPROM Technology. The split gate cell design and thick oxide tunneling ni jector attain better reliability and manufacturability compared with alternative approaches. The 28PC040 erases and programs with a 5.0 volt only power supply. Figure 1 shows the functional blocks of the 28PC040, and shows the memory map consisting of common memory array and the attribute me mory array. Figure 2 shows the pin assignments for the TSOP package. Pin description and operation modes are described in Tables 1 through 6. Sector Erase Cap ability: 256 Bytes/512 Nibbles per Sector Selectable single Nibble & dual Nibble Access PCMCIA Byte-wide or Word wide selection Latched Address and Data Hardware and Software Data Protection WP Pin Hardware Write Protection 7-Read-Cycle-Sequence Software Data Protection End of Write Detection Toggle Bit Data# Polling TTL I/O Compatibility Packages Available 40-Pin TSOP (10 mm x 14 mm) Device Operation Commands are used to initiate the memory o perations functions of the device. Commands are written to the device using standard microproce ssor write sequences. The device is selected by applying the proper input levels to CS and CS1 0 (see Table 2A). A command is written by assert ing WE# low while keeping CEL# or CEH# low. The address bus is latched on the falling edge of WE#, CEL#, or CEH#, whichever occurs last. The data bus is latched on the rising edge of WE# or CEL#, whichever occurs first. Note, during the software data protection sequence the address are latched on the rising edge of OE# or CEL#, whichever occurs first. Memory Map The 28PC040 consists of two memory arrays: the common memory and the attribute memory. The common memory consists of 1M-nibbles and is used for storing data, program codes and other user files. The total available attribute memory is 2K nibbles. The selection between the common and attribute memory maps is controlled by the REG# pin. When REG# is high, the common memory is active. Alternatively, the attribute memory can be accessed through an E nable_Attribute command, which enables the attribute memory access independent of REG#.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.2
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Two sectors of the attribute memory are used to store the map of nonconforming sectors. Refer to Table 9 for details. A maximum of zero nonco nforming attribute memory sectors and five nonconforming common memory sectors are a llowed when the 28PC040 is shipped. Command Definitions Table 7 contains a command list and a brief summary of the commands. The following is a detailed description of the operations initiated by each command. Sector_Erase Operation The Sector_Erase operation erases all byte within a sector and is initiated by a setup command and an execute command. A sector contains 512 ni bbles. This sector erasability enhances the flexibility and usefulness of the 28PC040, since most applications only need to change a small number of bytes or sectors, not the entire chip. The setup command is performed by writing 22H to the device. To execute the Sector_Erase o peration, the execute command (DDH) must be written to the device. The erase operation begins with the rising edge of the WE# pulse and term inates with the Reset command. The device has an internal timer that will terminate the erase (into the read mode) after TSE if no Reset command has been sent. The end of Erase can be dete rmined using either Data# Polling, Toggle Bit or Successive Reads detection methods. See Figure 9 for timing waveforms. The two-step sequence of setup command fo llowed by an execute command ensures that only memory contents within the addressed sector are erased and other sectors are not inadvertently erased. Erase_Verify The Erase_Verify operation is initiated by writing a single command (AAH). The address bus is latched on the falling edge of WE#, CEL#, or CEH#, whichever occurs last. The Erase_Verify is used only to verify that the device has erased prior to programming. The Erase_Verify uses an internal reference level to provide extra margin compared to normal read levels for "FF" data. This operation automatically resets after reading the byte. Sector_Erase Flowchart Description Fast and reliable erasing of the memory contents within a sector is accomplished by following the algorithmic sector erase flowchart as shown in Figure 20. The Sector_Erase operation will term inate after a maximum of 2 ms, if not interrupted. After the initial 40 s of erase time, a Reset co mmand can be executed to terminate the erase operation followed by an Erase_Verify operation to assure complete erasure. The algorithmic Sector_Erase operation allows for up to seven erase iterations to complete the Sector_Erase. A sector erase iteration is perform by doubling the algorithmic sector erase sector time (T = 40 s ASE , 80 s, 160 s, 320 s, 640 s, 1.28 ms and 2.56 ms). The purpose of the successive erase a ttempts is to optimize the total time required to erase the sector. An additional 150 erase retries at maximum TASE is allowed to ensure erasure. Byte_Program Operation The Byte_Program operation is initiated by writing the setup command (11H). Once the program setup is performed, programming is executed by the next WE# pulse. See Figures 5 and 6 for ti ming waveforms. The address bus is latched on the falling edge of WE#, CEL# or CEH#, whichever occurs last. The data bus is latched on the rising edge of WE#, CEL# or CEH#, whichever occurs first. The rising edge of WE#, CEL# or CEH#, whichever occurs first, begins the program oper a tion. The program operation is terminated automatically by an internal timer. See Figure 18 for the programming flowchart. The two-step sequence of a setup command fo llowed command ensures that only the addressed byte is programmed and other bytes are not ina dvertently programmed. The Byte_Program Flowchart Description Programming data into the 28PC040 is acco mplished by following the Byte_Program flowchart shown in Figure 18. The Byte_Program command sets up the byte for programming. The address bus is latched on the falling edge of WE#, CEL# or CEH#, whichever occurs last. The data bus is latched on the rising edge of WE#, CEL# or CEH#, whichever occurs first and begins the pr o gram operation. The end of program can be
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.3
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
detected using either the Data# Polling or Toggle bit. Reset Operation The Reset command is provided as a means to safely abort the erase or program command s equences. Follow either setup commands (erase or program) with a write of FFH will safely abort the operation. Memory contents will not be altered. After the Reset command, the device returns to the read mode. The Reset command does not enable software data protection. See Figure 7 for timing waveforms. Read The Read operation is initiated by setting CEL#, CEH#, and OE# to logic low and setting WE# to logic high (See Table 3). See Figure 4 for read memory timing diagram. The read operation from the host retrieves data from the array. The device remains enabled for read until another operation mode is accessed. During initial power-up, the device is in the read mode and is software data protected. The device must be unprotected to execute a write command. The read operation of the 28PC040 is controlled by OE# at logic low and either CEL# and/or CEH# at logic low. When CEL# and CEH# are high, the chip is deselected and only standby power will be consumed. OE# is the output control and is used to gate data from the output pins. The data bus is in high impedance state when both CEL# and CEH# are high or OE# is high. Enable_Attribute Operation Attribute memory is access by initiating the E nable_Attribute operation with a single command (88H). Read, Sector_Erase, and Byte Program operations can be performed in the attribute memory. The 1K byte of memory includes the PCMCIA attribute memory information. The REG# pin status has no effect on the operation. To er turn to common memory operations, a Reset command must be issued. The Reset command enables access to the common memory. (See Figure 8) Read_ID operation The Read_ID operation is initiated by writing a single command (99H). A read of address 0000H will output the manufacturer's code (BFH). A read of address 0001H will output the device code (11H). Any other valid command will terminate this operation. Data Protection In order to protect the integrity of nonvolatile data storage, the 28PC040 provides both hardware and software features to prevent inadvertent writes to the device, for example, during system power-up or power-down. Such provisions are d escribed below. Hardware Data Protection The 28PC040 is designed with hardware features to prevent inadvertent writes. This is done in the following ways: 1. Write Inhibit Mode: OE# low, CEL# high, CEH# high, or WE# high will inhibit the write operation. 2. Noise/Glitch Protection: A WE# pulse width of less than 15 ns will not initiate a write c ycle. 3. VCC Power Up/Down Detection: The write o peration is inhibited when V is less than 2.5 CC V. 4. After power-down the device is in the read mode and the device is in the software data protect state. 5. The WP pin at VIH will put the device in the Write Protect mode. Software Data Protection (SDP) The 28PC040 has software methods to further prevent inadvertent writes. In order to perform an erase or program operation, a two-step command sequence consisting of a set-up command fo llowed by an execute command avoids inadvertent erasing and programming of the d evice. The 28PC040 will default to software data prote ction after power up. A sequence of seven consecutive reads at specific addresses will u nprotect the device The address sequence is 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 041AH. The address bus is latched on the rising edge of OE# or CEL#, whichever occurs first. A similar seven read sequence of 1823H, 1820H, 1822H, 0418H, 041BH, 0419H, 040AH will protect
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.4
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
the device. Also refer to Figures 10 and 11 for the 7 read cycle sequence Software Data Protection. The I/O pins can be in any state (i.e., high, low, or tristate). Write Operation Status Detection The 28PC040 provides two software means to detect the completion of a write cycle, in order to optimize the system write cycle time. The end of a write cycle (erase or program) can be detected by three means: 1) monitoring the Data# Polling bit; 2) monitoring the Toggle bit; or by two successive read of the same data. These three detection mechanisms are described below. The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a Data# Polling or Toggle Bit read may be simult a neous with the completion of the write cycle. If this occurs, the system may possibly get an err o neous result, i.e., valid data may appear to conflict with the DQ used. In order to prevent spurious rejection, if an erroneous result occurs, the soft ware routine should include a loop to read the accessed location an additional two (2) times. If both reads are valid, then the device has co mpleted the write cycle, otherwise the rejection is valid. Data# Polling (DQ 3, DQ7) The 28PC040 features Data# Polling to indicate the write operation status. During a write oper a tion, any attempt to read the last byte loaded will receive the complement of the true data on DQ 3 and DQ7. Once the write cycle is completed, DQ 3 for the low nibble and DQ7 for the high nibble will show true data. The device is then ready for the next operation. See Figure 14 for Data Polling timing waveforms. In order for Data# Polling to function correctly, the byte being polled must be erased prior to programming. Toggle Bit (DQ 2, DQ6) An alternative means for determining the write operation status is by monitoring the Toggle Bit, DQ2 for the low nibble and DQ for the high nib6 ble. During a write operation, consecutive attempts to read data from the device will result in DQ2 and DQ6 toggling between logic 0 (low) and logic 1 (high). When the write cycle is completed, the toggling will stop. The device is then ready for the next operation. See Figure 15 for Toggle Bit timing waveforms. Successive Reads An alternative means for determining an end of a write cycle is by reading the same address for two consecutive data matches. Chip select (CS0, CS1) The 28PC040 provides two user selectable chip select pins, CS0 and CS1. By ordering different part number suffix of a device, the device response only to one of the combinations of CS0 and CS1. See Table 2A. Therefore, there is no need of external decoder for up to 4 pairs of d evices. Typically, the CS0 and CS1 are connected to address line A20 and A21. See application note "PCMCIA Memory Cards Made Easy with SST28PC040".
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.5
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
RDY/BSY# RST CS0 CS1 REG# HB WP
4 Sectors Attribute Memory PCMCIA Control Logic (8Kbits)
2048 Sectors Common Memory (4Mbits) X-Decoder
A18-A0
Address buffer & Latches Y-Decoder
CEH# CEL# OE# WE#
Control Logic
I/O Buffers and Data Latches
DQ7 - DQ0
Figure 1:
Functional Block Diagram of SST 28PC040
Pin #1 indicator
RST REG# A11 A9 A8 A13 A14 A17 WE# VCC CEH# A16 A15 A12 A7 A6 A5 A4 A18 RDY/BSY#
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
Standard Pinout Top View
Die up
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
CS1 CS0 OE# A10 CEL# DQ7 DQ3 DQ6 DQ2 DQ5 VSS DQ1 DQ4 DQ0 A0 A1 A2 A3 WP HB
Figure 2:
Standard Pin Assignments for 40-pin TSOP Pac kages.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.6
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Table 1: Symbol A18 -A8 A7-A0 DQ7-DQ0 Pin Description Pin Name Row Address Inputs Column Address Inputs Data Input/Output
CEL#, CEH# Chip Enable
OE# WE# Vcc Vss CS0 - CS1 HB WP
Output Enable Write Enable Power Supply Ground Chip Selects Half-Byte Write Protect
Functions To provide memory addresses. Row addresses define a sector. Selects the byte within the sector. To output data during read cycles and receive input data during write cycles. Data is internally latched during a write cycle. The outputs are in tri-state when OE#, CEL# or CEH# is high. To activate the device when CEL# or CEH# is low.(1) CEL# to enable the low nibble of DQ to DQ3 0 CEH# to enable the high nibble of DQ to DQ7 4 To gate the data output buffers. (1) To control the write operations. (1) To provide 5-volt supply ( 10%)
(1) Preset chip selects used for memory pair select. See Table 2A (1) Selects Odd/Even nibble for chip. (1) To activate write protect state. When WP is high, the device becomes a ROM, acknowledging all read operation, and will ignore all operations attempting to alter memory array data. See Table 7. This open-drain output requires a 1K pull-up resistor (minimum). (2) This pin is low to indicate the chip is busy internally. Any new instruction must be performed only when RDY/BSY# is high. (1) To switch from common memory to attribute memory. There are 1Kbits of attribute memory in the 28PC040 decoded by A9 to A0. REG# can be overridden by the Enable_Attribute command. To reset the device after power-on.(1) RST must be asserted after power-up. After the falling edge of the RST pulse, the 28PC040 will be ready (RDY/BSY#) in ~ 10ms.
RDY/BSY#
Read/Busy
REG#
Attribute Memory
RST
Reset
Note:
(1) (2)
This pin is considered as an input for the purposes of the DC Operation Characteristics Table. This pin is considered as an output for the purposes of the DC Operation Characteristics able. T
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.7
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Operation Modes Selection CEL#, OE# CEH# Read VIL VIL Byte Program VIL VIH Sector Erase VIL VIH Standby VIH X Write Inhibit X VIL Write Inhibit X X Software Chip Erase VIL VIH Product Identification Hardware Mode VIL VIL
Table 2: Mode
WE# VIH VIL VIL X X VIH VIL VIH
DQ DOUT DIN DIN High Z High Z/ DOUT High Z/ DOUT DIN
Address AIN AIN AIN X X X See Table 7
Software Mode SDP Enable & Disable Mode Enable_Attribute Reset Table 2A: Card Decode Table Device Part# Suffix CS1 S00A S01B S10C S11D Note: 0 0 1 1
VIL VIL VIL VIL
VIH VIH VIH VIH
VIL VIL VIL VIL
Manufacturer A18 -A1=VIL, A9=VH, A0=V IL Code (BF) Device Code (11) A18 -A1=VIL, A9=VH, A0=V IH See Table 7 See Table 7 See Table 7 See Table 7
CS0 0 1 0 1
The chip is selected by applying the listed logic levels to CS and CS1. 0 The device part # suffix ind icates the preset state.
Table 3: Main Memory Read Functions Function Mode REG CEH CEL # # # Standby Mode X H H (3) Nibble Access (x4) H H L (3) Nibble Access (x4) H H L Byte Access (x8) (3) H L L Odd Nibble Access(3) H L H Note:
(1) (2) (3)
HB X L H X X
OE# X L L L L
WE# X H H H H
DQ7-4
(1)
DQ3-0
(2)
A18-A0 X AIN AIN AIN AIN
(
High Z High Z High Z Even Nibble High Z Odd Nibble Odd Nibble Even Nibble Odd Nibble High Z
D15 -D8 in Figure 3 D7-D0 in Figure 3 CS1 and CS0 at active state.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.8
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Table 4: Main Memory Write Functions Function Mode REG CEH CEL # # # Standby Mode X H H Nibble Access (x4)(3) H H L Nibble Access (x4) (3) H H L (3) Byte Access (x8) H L L Odd Nibble Access(3) H L H Write Inhibit X X X Notes:
(1) (2) (3)
HB X L H X X X
OE# X H H H H L
WE# X L L L L X
DQ7-4 (1) X X X Odd Nibble Odd Nibble X
DQ3-0 (2) X Even Nibble Odd Nibble Even Nibble X X
A18-A0 X AIN AIN AIN AIN X
D15 -D8 in Figure 3 D7-D0 in Figure 3 CS1 and CS0 at active state.
Table 5: Attribute Memory Read Functions Function Mode REG CEH CEL HB # # # Standby Mode X H H X (4) Nibble Access (x4) L H L L Nibble Access (x4) (4) L H L H Byte Access (x8) (4) L L L X (4) Odd Nibble Access L L H X Note:
(1) (2) (3) (4)
OE# X L L L L
WE # X H H H H
DQ7-4 (1)
DQ3-0 (2)
A9-A0(3) X AIN AIN AIN AIN
High Z High Z High Z Even Nibble High Z Odd Nibble Odd Nibble Even Nibble Odd Nibble High Z
D15 -D8 in Figure 3 D7-D0 in Figure 3 Other addresses are "don't care" CS1 and CS0 at active state
Table 6: Attribute Memory Write Functions Function Mode REG CEH CEL HB # # # Standby Mode X H H X Nibble Access (x4) (4) L H L L (4) Nibble Access (x4) L H L H Byte Access (x8) (4) L L L X Odd Nibble Access(4) L L H X Write Inhibit X X X X Note:
(1) (2) (3) (4)
OE# X H H H H L
WE # X L L L L X
DQ7-4
(1)
DQ3-0
(2)
A9-A0 X AIN AIN AIN AIN X
(3)
X X X Even Nibble X Odd Nibble Odd Nibble Even Nibble Odd Nibble X X X
D15 -D8 in Figure 3 D7-D0 in Figure 3 Other addresses are "don't care" CS1 and CS0 at active state
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.9
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Table 7: Software Command Summary
Required Cycle(s) Sector_Erase(10) Byte_Program(10) Erase_Verify(10) Reset(10) Enable_Attribute(10) Read_ID(10) Software_Data_Protect(10) Software_Data_Unprotect(10) 2 2 2 1 1 3 7 7 Setup Command Cycle Type (1) Addr (2,
3)
Command Su mmary
Data (4) 22H 11H AAH FFH 88H 99H
Execute Command C ycle (1) Type Addr (2, Data (4)
3)
WP (6)
SDP (6)
W W W W W W R R
X X VA(5) X X X (7) (8)
W W R
SA PA X
DDH PD DOUT
R
(9)
(9)
N N Y Y Y Y
N N Y Y Y Y
Notes: 1. Type definition: W = Write, R = Read, X= don't care 2. Addr (Address) definition: SA = Sector Address = A - A8, sector size = 512 nibbles; A - A0 = X for 18 7 this command. 3. Addr (Address) definition: PA = Program Address = A - A0. 18 4. Data definition: PD = Program Data, H = number in hex. 5. Addr (Address) definition: VA = Verify Address = A - A0. 18 6. WP = Hardware Write Protect mode using WP pin, SDP = Software Data Protect mode using 7 Read Cycle Sequence. a) b) Y = the operation can be executed with protection enabled N = the operation cannot be executed with protection enabled
7. Refer to Figure 13 for the 7 Read Cycle sequence for Software_Data_Protect. 8. Refer to Figure 12 for the 7 Read Cycle sequence for Software_Data_Unprotect. 9. Address 0000H retrieves the manufacturer's code of BFH and address 0001H retrieves the device code of 11H. 10. CS1 and CS0 at active state
Table 8: Memory Array Detail Memory Array Sector Select Common Memory Attribute Memory A18 - A8 A9 - A8
Byte Select A7 - A0 A7 - A0
Nibble Select HB HB
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.10
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Table 9:
Attribute Byte Address 200 201 202 203 . . . . 2FE 2FF
Nonconforming Sector Map
D7 X X X X X X X X X X D6 X X X X X X X X X X D5 X X X X X X X X X X D4 X X X X X X X X X X 7F6 7F4 7F2 7F0 7FE 7FC 7FA 7F8 D3 D2 D1 D0 Attribute Byte Address 300 301 302 303 . . . . 3FE 3FF D7 X X X X X X X X X X D6 X X X X X X X X X X D5 X X X X X X X X X X D4 X X X X X X X X X X 7F7 7F5 7F3 7F1 7FF 7FD 7FB 7F9 D3 D2 D1 D0
SNS SUM [3:0] SNS SUM [7:4] 16 1E 14 1C 12 1A 10 18
SNS SUM [3:0] SNS SUM [7:4] 17 1F 15 1D 13 1B 11 19
Note:
The Attribute memory bit is "0" when the corresponding Common memory sector is nonconfor ming. The first 8 sectors of Common memory are always conforming.
Definitions: 1. The SNS sum is the sum of the number of nonconforming sectors and is calculated by summing the "0"s in the remaining bytes of the nonconforming sector map. 2. SNS Sum = Sum of Nonconforming Sector sum. The byte data from these addresses are notni cluded in the sum. a) [3:0] = The lower nibble of the SNS sum. b) [7:4] = The higher nibble of the SNS sum. 3. Only the lower nibble is used in the attribute memory to map the location of the nonconforming sector(s).
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.11
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the po erational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ........................................................................ -55C to +125C Storage Temperature ............................................................................. -65C to +150C D. C. Voltage on Any Pin to Ground Potential ........................................ -0.5V to VCC + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ................... -1.0V to VCC + 1.0V Voltage on A9 Pin to Ground Potential .................................................... -0.5V to 14.0V Package Power Dissipation Capability (Ta = 25C) ................................. 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) ...................... 240C (1) Output Short Circuit Current ................................................................. 100 mA Note:
(1)
Outputs shorted for no more than one second. No more than one output shorted at a time. Table 11: AC Conditions of Test
VCC 5V10% Input Rise/Fall Time...............10 ns Output Load...........................1 TTL Gate and CL = 100 pF See Figures 16 and 17 Ambient Temp 0 C to +70 C
Table 10: Operating Range
Range Commercial
Table 12: DC Operating Characteristics Symbol Parameter Limits Min Max ICC Power Supply Current Read Program and Erase ISB1 ISB2 ILI ILO VIL VIH VIL2 VIH2 VOL VOH VH IH Standby VCC Current (TTL input) Standby VCC Current (CMOS input) Input Leakage Current Output Leakage Current Input Low Voltage,TTL Input High Voltage, TTL Input Low Voltage, CMOS Input High Voltage, CMOS Output Low Voltage Output High Voltage Supervoltage for A9 Supervoltage Current for A 9 25 40 5 20 1 10 0.8 2.0 0.2 VCC-0.2 0.4 2.4 11.6 12.4 200
Units
Test Conditions CE# (L or H) = OE# =VIL, WE# =VIH, all I/Os open Address input = VIL/VIH, at f=1/TRC Min. VCC = VCC Max CE# (L or H) =WE# =VIL, OE# =VIH VCC =VCC Max. CE# =OE# =WE# = VIH, VCC=VCC Max, all Input pins at VIL or VIH CE# = OE# = WE# = VCC -0.3V, VCC=VCC Max, all Input pins at VIL2 or VIH2 VIN = GND to VCC, VCC = VCC Max. VOUT =GND to VCC, VCC = VCC Max. VCC = VCC Max. VCC = VCC Max. VCC = VCC Max. VCC = VCC Max. IOL= 3.2 mA, VCC = VCC Min. IOH = 2.0 mA, VCC = VCC Min. CE#=OE#=VIL,WE#=VIH CE#=OE#=VIL,WE#=VIH , A9 = VH Max.
mA mA mA A A A V V V V V V V A
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.12
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Table 13: Power-up Timings Symbol Parameter (1) TPU-READ Power-up to Read Operation TPU-WRITE (1) Power-up to Write Operation
Maximum 10 10
Units ms ms
Table 14: Capacitance (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition (1) CI/O I/O Pin Capacitance VI/O = 0V CIN (1) Note:
(1)
Maximum 12 pF 6 pF
Input Capacitance
VIN = 0v
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
Table 15: Reliability Characteristics Symbol Parameter Minimum Specification NEND Endurance 100,000 (1) TDR Data Retention 100 VZAP_HBM (1) ESD Susceptibility 1,000 Human Body Model VZAP_MM (1) ESD Susceptibility 200 Machine Model ILTH (1) Latch Up 100 Note:
(1)
Units Cycles Years Volts Volts mA
Test Method MIL-STD-883, Method 1033 MIL-STD-883, Method 1008 MIL-STD-883, Method 3015 JEDEC JEDEC Standard 17
This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
AC Characteristics Table 16: PCMCIA Symbol tCR ta(A) ta(CE) ta(OE) tdis(CE) tdis(OE) ten(CE) ten(OE) tv(A) Read Cycle Timing Parameters IEEE Industry Symbol Symbol Parameter tAVAV TRC Read Cycle time tAVQV TAA Address Access Time tELQV TCE Chip Enable Access Time tGLQV TOE Output Enable Access Time (1) tEHQZ TCLZ CE# Low to Active Output tGHQZ TOLZ(1) OE# Low to Active Output (1) tELQX TCHZ CE# High to High-Z Output tGLQX TOHZ (1) OE# High to High-Z Output (1) tAXQX TOH Output Hold from Address Change 28PC040-150 Min Max 150 150 150 70 0 0 40 40 0 28PC040-250 Min Max 250 250 250 100 0 0 40 40 0
Units ns ns ns ns ns ns ns ns ns
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.13
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Table 17: Erase/Progarm Cycle Timing Parameters PCMCIA IEEE Industrial Symbol tCW tw(WE) tsu(A) th(a) tsu(CE) th(CE) tsu(OE-WE) th(OE-WE) tw(CE) tsu(D-WEH) th(D) Symbol tAVA tWLWH tAVWL tWLAX tELWL tWHEX tGHWL tWGL tWLEH tDVWH tWHDX tWHWL2 Symbol TBP TWP TAS TAH TCS TCH TOES TOEH TCP TDS TDH TSE TRST (1) TEVD TERD TASE tEHEL TCPH tWHWL1 TWPH tRHRL THR (1) tRHBL TRBS (1) TPCP (1) TPCH (1) TPAS (1) TPAH (1) Parameter Byte Program Cycle Time Write Pulse Width (WE#) Address Setup Time Address Hold Time CE# Setup Time CE# Hold Time OE# High Setup Time OE# High Hold Time Write Pulse Width (CE#) Data Setup Time Data Hold Time Sector Erase Cycle Time Reset Command Recovery Time Erase Verify Timing Delay Erase Reset Timing Delay Algorithmic Sector Erase Cycle Time CE# High Pulse Width WE# High Pulse Width Hardware Reset Pulse Width Hardware Reset High to RDY/BSY# Active Protect Chip Enable Pulse Width Protect Chip Enable High Time Protect Address Setup Time Protect Address Hold Time
28PC040150 Min Max 35 80 20 0 0 0 10 10 80 50 10 2 4 .025 4 0.04 50 50 10 10 10 10 0 50
28PC040250 Min Max 35 100 20 0 0 0 10 10 100 50 10 2 4 0.25 4 0.04 50 50 10 10 10 10 0 50
Units s ns ns ns ns ns ns ns ns ns ns ms s s s ms ns ns s s ns ns ns ns
2.56
2.56
Note:
(1)
This parameter is measured only for initial qualification and after the design or process change that could affect this parameter.
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.14
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
CHIP # 0
CHIP # 1
DQ 0-3
DQ 4-7
DQ 0-3
DQ 4-7
PAIR OUTPUT DQ 0-3 DQ 4-7 DQ 8-11 DQ 12-15 Figure 3: Chip Pair Mapping (Nibble Access)
} }
Even Byte
Odd Byte
Table 18: Nibble Access Table Byte Nibble Outputs Even Even Nibble 0-3 Even Odd Nibble 4-7 Odd Even Nibble 8-11 Odd Odd Nibble 12-15
CEL# L L H H
CEH# H H L L
HB L H L H
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.15
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Figure 4:
Read Cycle Timing Diagram
Figure 5:
WE# Controlled Byte Program Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.16
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Figure 6:
CE# Controlled Byte Program Timing Diagram
Figure 7:
Reset Command Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.17
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Figure 8:
Enable_Attribute Timing Diagram
Figure 9:
Sector Erase Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.18
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Figure 10:
Software Data Unprotect Timing Diagram
Figure 11:
Software Data Protect Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.19
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
VCC
VCC min
RST
THR
RDY/BSY#
TPU -READ, TPU -WRITE
Figure 12:
RST and RDY/BSY# waveforms - Power up to Read and Write
VCC
THR RST
RDY/BSY#
TRBS
TPU -READ, TPU -WRITE
Figure 13:
RST and RDY/BSY# waveforms - Hardware Reset
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.20
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Figure 14:
Data# Polling Timing Diagram
Figure 15:
Toggle Bit Timing Diagram
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.21
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
2.4 INPUT
2.0 REFERENCE POINTS 0.8
2.0 OUTPUT 0.8
0.4
AC test inputs are driven at V (2.4 VTTL ) for a logic "1" and VOL (0.4 VTTL ) for a logic "0". MeasureOH ment reference points for inputs and outputs are V (2.0 VTTL ) and VIL (0.8 VTTL ). Inputs rise and fall IH times (10% 90%) are <10 ns.
Figure 16:
AC Input/Output Reference Wav eform
TEST LOAD EXAMPLE
VCC
TO TESTER
RL
HIGH
TO DUT
CL
RL
LOW
Figure 17:
Test Load Example
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.22
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Figure 18:
Byte Program Flowchart
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.23
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Internal Timer
Byte Program/ Sector Erase Initiated
Toggle Bit
Byte Program/ Sector Erase Initiated
Data # Polling
Byte Program Initiated
Wait TBP or TSE
Read byte
Read DQ3,7
Write Completed
Read same byte
No
Is DQ3,7 = true data?
Yes No Does DQ2,6 match ? Write Completed
Yes Write Completed Figure 19: Write Wait Options
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.24
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Figure 20:
Sector_Erase Flowchart
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.25
SST 28PC040 5.0V-only 4 Megabit PCMCIA Interface EEPROM
Product Ordering Information
Device SST28PC040 -
Speed XXX -
Suffix1 XX -
Suffix2 Suffix3 XX XXXX
Card Decode S00A = CS1 low active CS0 low active S01B = CS1 low active CS0 high active S10C = CS1 high active CS0 low active S11D = CS1 high active CS0 high active Package Modifier I = 40 leads Package Type W = TSOP (die up) Operating Temperature C = Commercial = 0 to 70C Minimum Endurance 5 = 100,000 cycles Read Access Speed 250 = 250 ns 150 = 150 ns
Valid combinations SST28PC040-250-5C-WI-S00A SST28PC040-150-5C-WI-S00A SST28PC040-250-5C-WI-S10C SST28PC040-150-5C-WI-S10C Example: SST28PC040-250-5C-WI-S01B SST28PC040-150-5C-WI-S01B SST28PC040-250-5C-WI-S11D SST28PC040-150-5C-WI-S11D
Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine avai lability of new combinations .
(c)1997 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. This specification is subject to change without notice.
14.26

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