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| PRELIMINARY TECHNICAL DATA a SigmaDSPTM Three-Channel, 24-Bit Signal Processing DAC Preliminary Technical Data AD1954 FEATURES 5 V 3-Channel Audio DAC System Accepts Sample Rates up to 48 kHz Seven Biquad Filter Sections per Channel Dual Dynamic Processor with Arbitrary Input/Output Curve and Adjustable Time Constants 0 ms to 6 ms Variable Delay/Channel for Speaker Alignment Stereo Spreading Algorithm for "Phat StereoTM" effect Program RAM Allows Complete New Program Download via SPI Port Parameter RAM Allows Complete Control of More Than 200 Parameters via SPI Port SPI Port Features "Safe-Upload" Mode for Transparent Filter Updates Two Control Registers Allow Complete Control of Modes and Memory Transfers Differential Output for Optimum Performance 112 dB Signal-to-Noise (Not Muted) at 48 kHz Sample Rate (A-Weighted Stereo) 75 dB Stopband Attenuation On-Chip Clickless Volume Control Hardware and Software Controllable Clickless Mute Digital De-emphasis Processing for 32 kHz, 44.1 kHz, 48 kHz Sample Rates Flexible Serial Data Port with Right-Justified, Left-Justified, I2S-Compatible, and DSP Serial Port Modes 44-Lead MQFP or 48-Lead LQFP Plastic Package APPLICATIONS 2.0/2.1 Channel 1 Audio Systems (Two Main Channels Plus Subwoofer) Multimedia Audio Automotive Sound Systems Mini Component Stereo Home Theater Systems (AC-3 Post Processor) Musical Instruments In-Seat Sound Systems (Aircraft, Motor Coaches) PRODUCT OVERVIEW The AD1954 is a complete 26-bit single-chip 3-channel digital audio playback system with built-in DSP functionality for speaker equalization, dual-band compression limiting, delay compensation, and image enhancement. These algorithms can be used to compensate for real-world limitations of speakers, amplifiers, and listening environments, resulting in a dramatic improvement of perceived audio quality. The signal processing used in the AD1954 is comparable to that found in high-end studio equipment. Most of the processing is done in full 48-bit double-precision mode, resulting in very good low-level signal performance and the absence of limit cycles or idle tones. The compressor/limiter uses a sophisticated two-band algorithm often found in high-end broadcast compressors. (continued on page 9) FUNCTIONAL BLOCK DIAGRAM SERIAL DATA OUTPUT 3 3 3 3 MASTER CLOCK OUTPUT AUDIO DATA MUX 26 22 DSP CORE DATA FORMAT: 3.23 (SINGLE PRECISION) 3.45 (DOUBLE PRECISION) DAC - L AD1954 SERIAL DATA INPUTS DAC - R MCLK GENERATOR (256/384/512 fS) ANALOG OUTPUTS MASTER CLOCK INPUTS MCLK MUX DAC - SW AUX SERIAL DATA INPUT SPI DATA OUTPUT SPI INPUT 3 DIGITAL OUT SERIAL CONTROL INTERFACE RAM ROM SigmaDSP and Phat Stereo are trademarks of Analog Devices Inc. REV. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002 PRELIMINARY TECHNICAL DATA AD1954 TABLE OF CONTENTS FEATURES/APPLICATIONS/PRODUCT OVERVIEW . . 1 SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . 7 TYPICAL PERFORMANCE CHARACTERICS . . . . . . . . 8 OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SIGNAL-PROCESSING . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Signal Processing Overview . . . . . . . . . . . . . . . . . . . . . . . 12 Numeric Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 High-pass Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Biquad Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Volume . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Stereo Image Expander . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Main Compressor/Limiter . . . . . . . . . . . . . . . . . . . . . . . . 15 Subwoofer Compressor/Limiter . . . . . . . . . . . . . . . . . . . . 18 De-emphasis Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Using the Sub Re-Injection Paths for Systems with No Subwoofer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Interpolation Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 SPI PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 SPI Address Decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Volume Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Parameter RAM Contents . . . . . . . . . . . . . . . . . . . . . . . . 22 Options for Parameter Updates . . . . . . . . . . . . . . . . . . . . 25 Soft Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Safeload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Summary of RAM modes . . . . . . . . . . . . . . . . . . . . . . . 26 SPI READ/WRITE DATA FORMATS . . . . . . . . . . . . . . . Parameter RAM Read/Write Format (Single Address) . . Parameter RAM Read/Write Format (Burst Mode) . . . . . Program Ram Read/Write Format (Single Address) . . . . Program Ram Read/Write Format (Burst Mode) . . . . . . . Control Register 1 Write Format . . . . . . . . . . . . . . . . . . . Control Register 1 Read Format . . . . . . . . . . . . . . . . . . . Control Register 2 Write Format . . . . . . . . . . . . . . . . . . . Volume Register Write Format . . . . . . . . . . . . . . . . . . . . Data Capture Register (Address and Register Select) Write Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Capture Register (Address and Register Select) Serial Out Write Format . . . . . . . . . . . . . . . . . . . . . . . . Data Capture Read Format . . . . . . . . . . . . . . . . . . . . . . . Safeload Register Write Format . . . . . . . . . . . . . . . . . . . . INITIALIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . Setting the DATA and MCLK input selectors . . . . . . . . . DATA CAPTURE REGISTERS . . . . . . . . . . . . . . . . . . . . SERIAL DATA INPUT PORT . . . . . . . . . . . . . . . . . . . . . Serial Data Input Modes . . . . . . . . . . . . . . . . . . . . . . . . . DIGITAL CONTROL PINS . . . . . . . . . . . . . . . . . . . . . . . Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ANALOG OUTPUT SECTION . . . . . . . . . . . . . . . . . . . . PERFORMANCE PLOTS . . . . . . . . . . . . . . . . . . . . . . . . . APPENDIX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . 27 27 27 27 27 27 27 27 27 28 28 28 28 28 28 28 29 29 31 31 32 32 32 32 33 34 35 -2- REV. PrA PRELIMINARY TECHNICAL DATA AD1954-SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages (AVDD, DVDD) . . . . . . . . . . . . . . . . . . . 5.0 V Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 25C Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.288 MHz Input Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD Input Sample Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 kHz Measurement Bandwidth . . . . . . . . . . . . . . . 20 Hz to 20 kHz Word Width . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 bits Load Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD Load Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TBD Input Voltage HI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 V Input Voltage LO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.8 V ANALOG PERFORMANCE Min RESOLUTION SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Left/Right Output) No Filter (Stereo) With A-Weighted Filter DYNAMIC RANGE (20 Hz to 20 kHz, -60 dB Input) (Left/Right Output) No Filter With A-Weighted Filter TOTAL HARMONIC DISTORTION PLUS NOISE (Left/Right Output) VO = -0.5 dB VO = -20 dB VO = -60 dB OUT-OF-BAND ENERGY (0.5 x fS to 100 kHz) (Left/Right Output) SIGNAL-TO-NOISE RATIO (20 Hz to 20 kHz) (Subwoofer Output) No Filter (Stereo) With A-Weighted Filter DYNAMIC RANGE (20 Hz to 20 kHz, -60 dB Input) (Subwoofer Output) No Filter With A-Weighted Filter TOTAL HARMONIC DISTORTION PLUS NOISE (Subwoofer Output) VO = -0.5 dB VO = -20 dB VO = -60 dB OUT-OF-BAND ENERGY (0.5 x fS to 100 kHz) (Subwoofer Output) ANALOG OUTPUTS Differential Output Range ( Full Scale) Output Capacitance at Each Output Pin CMOUT DC ACCURACY Gain Error Interchannel Gain Mismatch Gain Drift INTERCHANNEL CROSSTALK (EIAJ method) INTERCHANNEL PHASE DEVIATION MUTE ATTENUATION DE-EMPHASIS GAIN ERROR TBD TBD TBD Typ 24 109 112 109 112 -100 -92 -52 Max Unit bits dB dB dB dB dB dB dB -72.5 TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2.50 1.0 0.015 150 -120 0.1 -100 0.1 dB dB dB dB dB dB dB dB dB V p-p pF V % dB ppm/C dB Degrees dB dB NOTES Performance of right and left channels are identical (exclusive of the Interchannel Gain Mismatch and Interchannel Phase Deviation specifications). Specifications subject to change without notice. REV. PrA -3- PRELIMINARY TECHNICAL DATA AD1954 SPECIFICATIONS (continued) DIGITAL I/O Min Input Voltage HI (VIH) Input Voltage LO (VIL) Input Leakage (IIH @ VIH = 2.4 V) Input Leakage (IIL @ VIL = 0.8 V) High Level Output Voltage (VOH) IOH = 1 mA Love Level Output Voltage (VOL) IOL = 1 mA Input Capacitance Specifications subject to change without notice. Typ Max 0.8 10 10 Unit V V A A V V pF 2.4 TBD TBD 20 POWER Min SUPPLIES Voltage, Analog and Digital Analog Current Analog Current, Power-Down Digital Current Digital Current, Power-Down DISSIPATION Operation, Both Supplies Operation, Analog Supplies Operation, Digital Supplies Power-Down, Both Supplies POWER SUPPLY REJECTION RATIO 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 mV p-p Signal at Analog Supply Pins Specifications subject to change without notice. Typ 5 TBD TBD TBD TBD TBD TBD TBD Max 5.5 TBD TBD TBD TBD Unit V mA mA mA mA mW mW mW mW dB dB 4.5 TBD TBD TBD TBD TBD TBD TBD TEMPERATURE RANGE Min Specifications Guaranteed Functionality Guaranteed Storage Specifications subject to change without notice. Typ 25 Max 105 125 Unit C C C -40 -55 DIGITAL TIMING Min tDMP tDMP tDMP tDML tDMH tDBH tDBH tDLS tDLH tDDS tDDH tPDRP MCLK Period (512 fS Mode) MCLK Period (384 fS Mode) MCLK Period (256 fS Mode) MCLK LO Pulsewidth (All Mode) MCLK HI Pulsewidth (All Mode) BCLK LO Pulsewidth BCLK HI Pulsewidth L/RCLK Setup L/RCLK Hold SDATA Setup SDATA Hold PD/RST LO Pulsewidth TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max Unit ns ns ns ns ns ns ns ns ns ns ns ns Specifications subject to change without notice. -4- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 DIGITAL FILTER CHARACTERISTICS Min Passband Ripple Stopband Attenuation Passband Stopband Group Delay Group Delay Variation Typ TBD TBD TBD TBD TBD 0 Max Unit dB dB fS fS sec s REV. PrA -5- PRELIMINARY TECHNICAL DATA AD1954 ABSOLUTE MAXIMUM RATINGS* Package Characteristics (44-Lead MQFP) DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V ODVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V AVDD to AGND6 . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 6 V Digital Inputs . . . . . . . . . . . DGND -0.3 V to DVDD + 0.3 V Analog Inputs . . . . . . . . . . . AGND -0.3 V to AVDD + 0.3 V AGND to DGND . . . . . . . . . . . . . . . . . . . . -0.3 V to + 0.3 V Reference Voltage . . . . . . . . . . . . . . . . . . . . (AVDD + 0.3)/2 V Maximum Junction Temperature . . . . . . . . . . . . . . . . 125C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300C/10 sec *Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Min (Thermal Resistance [Junction-to-Ambient]) JC (Thermal Resistance [Junction-to-Case]) JA Typ Max TBD TBD Unit C/W C/W Package Characteristics (48-Lead LQFP) Min (Thermal Resistance [Junction-to-Ambient]) JC (Thermal Resistance [Junction-to-Case]) JA Typ Max TBD TBD Unit C/W C/W ORDERING GUIDE Model AD1954YS AD1954YSRL AD1954YST AD1954YSTRL Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C Package Description 44-Lead MQFP 44-Lead MQFP 48-Lead LQFP 48-Lead LQFP Package Option S-44 S-44 on 13" Reel ST48 ST48 on 13" Reel PIN CONFIGURATIONS 44-Lead MQFP 48-Lead LQFP SDATAOUT LRCLKOUT MCLKOUT ZEROFLAG LRCLKOUT BCLKOUT SDATAOUT ZEROFLAG FILTERCAP BCLKOUT MCLKOUT COUT DCSOUT OVDD DCSOUT FILTCAP VREF_IN ODVDD 44 43 42 41 40 39 38 37 36 35 34 MCLK2 1 MCLK1 2 MCLK0 3 DEEMP 4 MUTE 5 DVDD 6 SDATA2 7 BCLK2 8 LRCLK2 9 SDATA1 10 BCLK1 11 12 13 14 15 16 17 18 19 20 21 22 LRCKL0 BCLK0 CLATCH RESETB SDATA0 LRCLK1 DGND CDATA AVDD CCLK AGND PIN 1 IDENTIFIER 48 47 46 45 44 43 42 41 40 39 38 37 33 AGND 32 VOUTL- 31 VOUTL+ 30 AVDD NC 1 MCLK2 2 MCLK1 3 MCLK0 4 DEEMP 5 MUTE 6 DVDD 7 SDATA2 8 BCLK2 9 LRCLK2 10 SDATA1 11 BCLK1 12 NC = NO CONNECT VREF_IN NC DGND COUT DGND PIN 1 IDENTIFIER 36 35 34 NC AD1954 TOP VIEW (Not to Scale) 29 AGND 28 AVDD 27 VOUTR+ 26 VOUTR- 25 AGND 24 VOUTS+ 23 VOUTS- AD1954 TOP VIEW (Not to Scale) AGND VOUTL- 33 VOUTL+ 32 AVDD 31 30 29 28 AGND AVDD VOUTR+ VOUTR- 27 AGND VOUTS+ VOUTS- 26 25 13 14 15 16 17 18 19 20 21 22 23 24 LRCLK1 SDATA0 BCLK0 LRCLK0 CLATCH RESETB DGND CDATA CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD1954 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. WARNING! ESD SENSITIVE DEVICE AVDD AGND CCLK NC -6- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 PIN FUNCTION DESCRIPTIONS Pin No. (44-MQFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Pin No. (48-LQFP) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Mnemonic NC MCLK2 MCLK1 MCLK0 DEEMP/ SDATA_AUX MUTE DVDD SDATA2 BCLK2 LRCLK2 SDATA1 BCLK1 DGND LRCLK1 SDATA0 BCLK0 LRCLK0 CDATA CCLK CLATCH RESETB AVDD AGND NC VOUTS- VOUTS+ AGND VOUTR- VOUTR+ AVDD AGND AVDD VOUTL+ VOUTL- AGND NC NC VREF_IN FILTCAP ZEROFLAG SDATAOUT BCLKOUT LRCLKOUT ODVDD DCSOUT COUT MCLKOUT DGND Input/ Output IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN Description No Connect Master Clock Input 2 256/384/512/768 fS Master Clock Input 1 256/384/512/768 fS Master Clock Input 0 256/384/512/768 fS Enables 44.1 kHz De-emphasis Filter (Others available through SPI control.) Mute Signal, initiates volume ramp-down. Digital Supply for DSP Core, 4.5 V - 5.5 V. Serial Data Input 2 Bit Clock 2 Left/Right Clock 2 Serial Data Input 1 Bit Clock 1 Digital Ground Left/Right Clock 1 Serial Data Input 0 Bit Clock 0 Left/Right Clock 0 SPI Data Input SPI Data Bit Clock SPI Data Framing Signal Reset Signal, Active LOW Analog 5 V supply Analog GND No Connect Negative Sub Analog DAC Output Positive Sub Analog DAC output Analog GND Negative Left Analog DAC Output Positive Left Analog DAC Output Analog 5 V Supply Analog GND Analog 5 V Supply Positive Left Analog DAC Output Negative Left Analog DAC Output Analog GND No Connect No Connect Connection for filtered AVDD/2 Connection for Noise Reduction Capacitor Zero Flag Output. Hi when both left and right channels are 0 for 1024 frames Serial Data MUX Output Bit Clock MUX Output Left/Right Clock MUX Output Digital Supply Pin for Output Drivers, 2.5 V - 5.5 V Data Capture Serial Output for Data Capture Registers; use in conjunction with selected LRCLK and BCLK to form a 3-wire output SPI Data Output, Three-stated When Inactive Master Clock Output 512/256 fS (Frequency selected by SPI Register.) Digital Ground OUT OUT OUT OUT OUT OUT 34 35 36 37 38 39 40 41 42 43 44 IN IN OUT OUT OUT OUT OUT OUT OUT REV. PrA -7- PRELIMINARY TECHNICAL DATA AD1954-Typical Performance Characteristics PERFORMANCE PLOTS -0 -2 -4 -6 -8 -10 -12 -14 -16 -18 -20 20 50 100 200 Hz 500 1k 5k 10k The following plots demonstrate the performance achieved on the actual silicon. TPC 1 shows an FFT of a full-scale 1 kHz signal, with a THD + N of -100 dB, which is dominated by a second harmonic. TPC 2 shows an FFT of a -60 dB sine wave, demonstrating the lack of low-level artifacts. TPC 3 shows a frequency response plot with the seven equalization biquads set to an alternating pattern of 6 dB boosts and cuts. TPC 4 shows a "linearity" plot, where the measurement was taken with the same equalization curve used to make TPC 3. When the biquad filters are not in use, the signal passes through the filters with no quantization effects. TPC 4 therefore demonstrates that using double-precision math in the biquad filters has virtually eliminated any quantization artifacts. TPC 5 shows a tone-burst applied to the compressor, with the attack and recovery characteristics plainly visible. The RMS detector was programmed for "normal" RMS time constants; the hold/decay feature was not used for this plot. +0 -20 -40 -60 -80 -100 -120 -140 -160 TPC 3. Frequency Response of EQ Biquad Filters 3.0 2.5 2.0 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 -2.0 -2.5 0 2 4 6 8 10 kHz 12 14 16 18 20 -3.0 -120 -100 -80 -60 dBFS -40 -20 0 TPC 1. FFT of Full-Scale Sine Wave (32 k Points) TPC 4. Lineatiy Plot 0 -20 -40 -60 -80 -100 -120 -140 -160 2.0 1.5 1.0 500m 0 -500m -1.0 -1.5 -2.0 -120 V 0 2 4 6 8 10 kHz 12 14 16 18 20 -100 -80 ms -60 -20 0 TPC 2. FFT of -60 dB Sine Wave (32 k Points) TPC 5. Tone-Burst Response With Compressor Threshold Set to -20 dB -8- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 PRODUCT OVERVIEW (continued from page 1) An extensive SPI port allows click-free parameter updates, along with read-back capability from any point in the algorithm flow. The AD1954 also includes ADI's patented multibit sigma-delta DAC architecture. This architecture provides 112 dB SNR and dynamic range and THD+N of -100 dB. These specifications allow the AD1954 to be used in applications ranging from lowend "boom-boxes" to high-end professional mixing/editing systems. The AD1954 also has a digital output that allows it to be used purely as a DSP. This digital output can also be used to drive an external DAC to extend the number of channels beyond the three that are provided on the chip. FEATURES The AD1954 has a very sophisticated SPI port that supports complete read/write capability of both the program RAM and the parameter RAM. Two control registers are also provided to control the chip serial modes, and various other optional features. Handshaking is included for ease of memory uploads/ downloads. The AD1954 contains four independent data-capture circuits that can be programmed to tap the signal flow of the processor at any point in the DSP algorithm flow. These captured signals can be accessed either through a separate serial-out pin (which can be connected to an external DAC or DSP, for example), or by reading from the data-capture SPI registers. This allows the basic functionality of the AD1954 to be easily extended. The processor core in the AD1954 has been designed from the ground up for straightforward coding of sophisticated compression/ limiting algorithms. The AD1954 contains two independent compressor/limiters with RMS-based amplitude detection and attack/hold/release controls, together with an arbitrary compression curve that is loaded by the user into a lookup table that resides in the parameter RAM. The compressor also features look-ahead compression, which prevents compressor overshoots. The AD1954 has a very flexible serial data input port that allows for glueless interconnection to a variety of ADCs, DSP chips, AES/EBU receivers, and sample rate converters. The AD1954 can be configured in left-justified, I2S, right-justified, or DSP serial port compatible modes. It can support 16, 20, and 24 bits in all modes. The AD1954 accepts serial audio data in MSB first, two's complement format. The part can also be set up in a four channel serial input mode by simultaneously using serial input mux and auxiliary serial input. The AD1954 operates from a single 5 V power supply. It is fabricated on a single monolithic integrated circuit and is housed in a 44-lead MQFP or 48-lead LQFP package for operation over the temperature range -40C to +105C. The AD1954 is comprised of a 26-bit DSP (48-bit with doubleprecision) for interpolation and speaker processing, three multibit sigma-delta modulators, and analog output drive circuitry. Other features include an on-chip parameter RAM using a "safe-upload" feature for transparent and simultaneous updates of filter coefficients. Digital deemphasis filters are also included. On-chip input selectors allow up to three sources of serial data and master clock to be selected. The three-channel configuration is especially useful for 2.1 playback systems that include two satellite speakers and a subwoofer. The default program allows for independent equalization and compression/limiting for the satellite and subwoofer outputs. Figure 1 shows the block diagram of the device. The AD1954 contains a program RAM that is booted from an internal program ROM on power-up. Signal-processing parameters are stored in a 256-location parameter RAM, which is initialized on power-up by an internal boot-ROM. New values are written to the Parameter RAM using the SPI port. The values stored in the parameter RAM control the IIR equalization filters, the dualband compressor/limiter, the delay values, and the settings of the stereo spreading algorithm. ZEROFLAG RESETB MUTE DE-EMPHASIS 3 3 SERIAL DATA I/O GROUP 3 3 AUX SERIAL DATA INPUT MCLK GENERATOR1 (256/384/512 fS IN) 256/512fS OUT CONTROL REGISTERS SPI I/O GROUP 3 SPI PORT TRAP REG. (I2S, SPI) SAFELOAD REGISTERS 3:1 AUDIO DATA MUX1 SERIAL IN1 DATA MEMORY, 52 26 DAC - L 26 22 DSP CORE DATA FORMAT: 3.23 (SINGLE PRECISION) 3.45 (DOUBLE PRECISION) DAC - L DAC -SW2 ANALOG OUTPUTS BIAS MASTER CLOCK I/O GROUP ANALOG BIAS GROUP 3:1 MCLK MUX1 BOOT ROM BOOT ROM PROGRAM RAM 512 35 PROGRAM RAM 256 22 COEFFICIENT ROM 64 22 MEMORY CONTROLLERS SCOUT TRAP DCSOUT NOTES 1CONTROLLED THROUGH SPI CONTROL REGISTERS 2DAC DOES NOT USE DIGITAL INTERPOLATION Figure 1. Block Diagram REV. PrA -9- PRELIMINARY TECHNICAL DATA AD1954 PIN FUNCTIONS All input pins have a logic threshold compatible with TTL input levels, and may therefore be used in systems with 3.3 V logic. All digital output levels are controlled by the ODVDD pin, which may range from 2.7 V to 5.5 V, for compatibility with a wide range of external devices. (See PIN FUNCTION DESCRIPTIONS.) SDATA0, 1, 2--Serial Data Inputs. One of these three inputs is selected by an internal MUX, set by writing to bits <7:6> in Control Register 2. Default is 00, which selects SDATA0. The serial format is selected by writing to bits <3:0> of Control Register 0. See SPI Read/Write Data Formats section for recommendations on how to change input sources without causing a "click" or "pop" noise. LRCLK0, 1, 2--Left/Right Clocks for Framing the Input Data. The active LRCLK input is selected by writing to bits <7:6> in Control Register 2. Default is "00," which selects LRCLKO. The interpretation of the LRCLK changes according to the serial mode, set by writing to Control Register 0. BCLK0, 1, 2--Serial Bit Clocks for Clocking in the Serial Data. The active BCLK input is selected by writing to bits <7:6> in Control Register 2. Default is 00, which selects BCLK0. The interpretation of BCLK changes according to the serial mode, which is set by writing to Control Register 0. LRCLKO, BCLKO, SDATAO--Output of MUX that Selects One of the Three Serial Input Groups. These pins may be used to send the selected serial input signals to other external devices. This output pin is enabled by writing a 1 to Bit 8 of Control Register 2. The default mode is 0, or "OFF." MCLK0, 1, 2--Master Clock Inputs. Active input selected by writing to bits <5:4> of Control Register 2. The default is 00, which selects MCLK0. The master clock frequency must be either 256 x fS, 384 x fS, or 512 x fS, where fS is the input sampling rate. The master clock frequency is programmed by writing to bits <3:2> of Control Register 2. The default is 00, or 512 x fS. See Initialization section for recommendations concerning how to change clock sources without causing an audio "click" or "pop." Note that since the default MCLK source pin is MCKLK0 there must be a clock signal present on this pin on power-up so that the AD1954 can complete its initialization routine. MCLKO--Master Clock Output. The master clock output pin may be programmed to produce either 256 x fS, 512 x fS, or a copy of the selected MCLK input pin. This pin is programmed by writing to bits <1:0> of Control Register 2. The default is 00, which disables the MCLKO pin. CDATA--Serial Data In for the SPI Control Port. See SPI Port section for more information on SPI port timing. COUT--Serial Data Output. This is used for reading back registers and memory locations. It is tri-stated when an SPI read is not active. See SPI Port section for more information on SPI port timing. CCLK--SPI Bit-Rate Clock. This pin either may run continuously, or be gated off in between SPI transactions. See SPI Port section for more information on SPI port timing. CLATCH--SPI Latch Signal. It must go LOW at the beginning of an SPI transaction, and HIGH at the end of a transaction. Each SPI transaction may take a different number of CCLKS to complete, depending on the address and read/write bit that are sent at the beginning of the SPI transaction. Detailed SPI timing information is given in SPI Port section. RESETB--Active-Low Reset Signal. After RESETB goes HIGH, the AD1954 goes through an initialization sequence where the program and parameter RAMs are initialized with the contents of the on-board boot ROMs. All SPI registers are set to 0, and the data RAMs are also zeroed. The initialization is complete after 1024 MCLK cycles. Since the MCLK IN FREQ SELECT (bits <3:2> in Control Register 2) defaults to 512 x fS at power-up, this initialization will proceed at the external MCLK rate, and will take 1024 MCLK cycles to complete, regardless of the absolute frequency of the external MCLK. New values should not be written to the SPI port until the initialization is complete. ZEROFLAG--Zero-Input Indicator. This pin will go HIGH if both serial inputs have been inactive (zero data) for 1024 LRCLK cycles. This pin may be used to drive an external MUTE FET for reduced noise during digital silence. This pin also functions as a test out pin, controlled by the test register at SPI address 511. While most test modes are not useful to the end user, one may be of some use. If the test register is programmed with the number 7 (decimal), the ZEROFLAG output will be switched to the output of the internal pseudo-random noise generator. This noise generator operates at a bit-rate of 128 x fS, and has a repeat time of once per 224 cycles. This mode may be used to generate white noise (or, with appropriate filtering, pink noise) to be used as a test signal for measuring speakers or room acoustics. DCSOUT--Data Capture Serial Out. This pin will output the DSP's internal signals, which can be used by external DACs or other signal-processing devices. The signals that are captured and output on the DCSOUT pin are controlled by writing "Program Counter Trap" numbers to SPI addresses 263 (for the left output) and 264 (for the right output). When the internal Program Counter contents are equal to the "Trap" values written to the SPI port, the selected DSP register is transferred to the DCSOUT parallel-to-serial registers and shifted out on the DCSOUT pin. Table XX shows the Program Counter Trap values and register-select values that should be used to tap various internal points of the algorithm flow. The DCSOUT pin is meant to be used in conjunction with the LRCLK and BCLK signals that are provided to the serial input port. The format of DCSOUT is the same as the format used for the serial port. In other words, if the serial port is running in I2S mode, then the DCSOUT pin, together with the LRCLK0 and BCLK0 pins (assuming input 0 is selected), will form a valid three-wire I2S output. The DCSOUT pin can be used for a variety of purposes. If the DCSOUT pin is used to drive another external DAC, then a 4.1 system is possible using a new program downloaded into the program RAM. REV. PrA -10- PRELIMINARY TECHNICAL DATA AD1954 DEEMP/SDATA_AUX--De-emphasis Input Pin/Auxiliary serial data input. In de-emphasis mode, if this pin is asserted HIGH, then a digital de-emphasis filter will be inserted into the signal flow. The de-emphasis curve is valid only for a sample rate of 44.1 kHz; curves for 32 kHz and 48 kHz may be programmed using the SPI port. This pin can also be used as an auxiliary two-channel serial data input. This function is set by writing a "1" to bit 11 of the Control Register. The same clocks are used for this serial input as are used for the SDATA0, 1, 2 signals. This serial input can only be used in the signal processing flow when using Analog Devices' custom programming tools. The use of de-emphasis is still available while this pin is used as a serial input, but through the software rather than the hardware. MUTE--Mute Output Signal. When this pin is asserted HIGH, a ramp sequence is started that gradually reduces the volume to zero. When deasserted, the volume ramps from zero back to the original volume setting. The ramp speed is timed so that it takes 10 ms to reach zero volume when starting from the default 0 dB volume setting. VOUTL+, VOUTL- --Left-Channel Differential Analog Outputs Full-scale outputs correspond to 1 Vrms on each output pin, or 2 Vrms differential, assuming a VREF input voltage of 2.5 V. The full-scale swing scales directly with VREF. These outputs are capable of driving a load of > 5 k, with a maximum peak current of 1 mA from each pin. An external third-order filter is recommended for filtering out-of-band noise. VOUTR+, VOUTR- --Right Channel Differential Outputs. Output characteristics are the same as for VOUTL+, VOUTL- above. VOUTS+, VOUTS- --SUB Channel Differential Outputs. These outputs are designed to drive loads of 10 k or greater, with a peak current capability of 250 A. This output does not use digital interpolation, as it is intended for low-frequency application. An external third-order filter with a cutoff frequency < 2 kHz is recommended. VREFIN--Analog Reference Voltage Input. The nominal VREFIN input voltage is 2.5 V; the analog gain scales directly with the voltage on this pin. When using the AD1954 to drive a power amplifier, it is recommended that the VREFIN voltage be derived by dividing down and heavily filtering the supply to the power amplifier. This provides a benefit if the compressor/limiter in the AD1954 is used to prevent amplifier clipping. In this case, if the DAC output voltage is scaled to the amplifier power supply, a fixed compressor threshold can be used to protect an amplifier whose supply may vary over a wide range. any AC signal on this pin will cause distortion, and therefore a large decoupling capacitor may be necessary to ensure that the voltage on VREFIN is clean. The input impedance of VREFIN is greater than 1 M. FILTCAP--Filter Cap Point. This pin is used to reduce the noise on an internal biasing point, in order to provide the highest performance. It may not be necessary to connect this pin, depending on the quality of the layout and grounding used in the application circuit. DVDD--Digital VDD for Core. 5 V nominal. ODVDD--Digital VDD for all digital outputs. Variable from 2.7 V to 5.5 V. DGND (2)--Digital Ground. AVDD (2)--Analog VDD. 5 V nominal. For best results, use a separate regulator for AVDD. Bypass capacitors should be placed close to the pins and connected directly to the analog ground plane. AGND--Analog Ground. For best performance, separate non-overlapping analog and digital ground planes should be used. REV. PrA -11- PRELIMINARY TECHNICAL DATA AD1954 L/R DYNAMICS PROCESSOR VOLUME EQ AND CROSSOVER IN LEFT HPF/ DEEMPH HPF/ DEEMPH 7 BIQUAD FILTERS 7 BIQUAD FILTERS CROSSOVER (2 FILTERS) CROSSOVER (2 FILTERS) PHAT STEREO DELAY (0-3.7ms) DELAY (0-3.7ms) DELAY (0-2.3ms) LEVEL DETECT, LOOKUP TABLE DELAY (0-2.3ms) 8 INTERPOLATION DAC OUT LEFT IN RIGHT VOLUME 8 INTERPOLATION DAC OUT RIGHT SUB CHANNEL L/R MIX 1 BIQUAD FILTER VOLUME LEVEL DETECT, LOOKUP TABLE DELAY (0-3.7ms) L/R REINJECTION LEVEL CROSSOVER (3 FILTERS) MONO DAC SUB DYNAMICS PROCESSOR SUBWOOFER LEVEL Figure 2. Signal Processing Flow SIGNAL PROCESSING Signal Processing Overview Figure 2 shows the signal processing flow-graph of the AD1954. The AD1954 is designed to provide all common signal-processing functions commonly used in 2.0 or 2.1 playback systems. A seven-biquad equalizer operates on the stereo input signal. The output of this equalizer is fed to a two-biquad crossover filter for the main channels, and the mono sum of the left and right equalizer outputs is fed to a three-biquad crossover filter for the SUB channel. Each of the three channels has independent delay compensation. There are two high-quality compressor/ limiters available: one operating on the left/right outputs and one operating on the subwoofer channel. The subwoofer output may be blended back into the left/right outputs for 2.0 playback systems. In this configuration, the two independent compressor/ limiters provide two-band compression, which significantly improves the sound quality of compressed audio. In addition, the main channels have a stereo "widening" algorithm that increases the perceived spread of the stereo image. Most of the signal processing functions are coded using full 48-bit double-precision arithmetic. The input wordlength is 24 bits, with two extra "headroom" bits added in the processor to allow internal gains up to 12 dB without clipping (additional gains can be accommodated by scaling down the input signal in the first biquad filter section). Each section of this flow-graph will be explained in detail on the following pages. Numeric Formats The AD1954 uses two different numeric formats; one for the coefficient values (stored in the parameter RAM) and one for the signal data values. The coefficient format is as follows: Coefficient Format Coefficient format: 2.20 Range: -2.0 to +(2.0 - 1 LSB) Examples: 1000000000000000000000 = -2.0 1100000000000000000000 = -1.0 1111111111111111111111 = (1 LSB below 0.0) 0000000000000000000000 = 0.0 0100000000000000000000 = 1.0 0111111111111111111111 = (2.0 - 1 LSB) This format is used because standard biquad filters require coefficients that range between +2.0 and -2.0. It also allows gain to be inserted at various places in the signal path. Internal DSP Signal Data Format Input data format: 1.23 This is sign-extended when written to the data memory of the AD1954. Internal DSP signal data format: 3.23 Range: -4.0 to +(4.0 - 1 LSB) Examples: 10000000000000000000000000 = -4.0 11000000000000000000000000 = -2.0 11100000000000000000000000 = -1.0 11111111111111111111111111 = (1 LSB below 0.0) 00000000000000000000000000 = 0.0 00100000000000000000000000 = 1.0 01000000000000000000000000 = 2.0 01111111111111111111111111 = (4.0 - 1 LSB). It is common in DSP systems to use a standardized method of specifying numeric formats. To better comprehend issues relating to precision and overflow, it is helpful to think in terms of fractional two's complement number systems. Fractional number systems are specified by an A.B format, where A is the number of bits to the left of the decimal point, and B is the number of bits to the right of the decimal point. In a two's complement system, there is also an implied offset of one-half of the binary range; for example, in a two's complement 1.23 system the legal signal range is -1.0 to (+1.0 - 1 LSB). -12- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 2-BIT SIGN EXTENTION 0.75 SIGNAL PROCESSING (3.23 FORMAT) 1.23 3.23 DAC INTERPOLATION FILTERS (3.23 FORMAT) DIGITAL CLIPPER DIGITAL SIGMA-DELTA MODULATORS (1.23 FORMAT) DATA IN SERIAL PORT Figure 3. Numeric Precision and Clipping Structure The sign-extension between the serial port and the DSP core allows for up to 12 dB of gain in the signal path without internal clipping. Gains greater than 12 dB can be accommodated by scaling the input down in the first biquad filter, and scaling the signal back up at the end of the biquad filter section. A digital clipper circuit is used between the output of the DSP core and the input to the DAC sigma-delta modulators, to prevent overloading the DAC circuitry (see Figure 3). Note that there is a gain factor of 0.75 used in the DAC interpolation filters, and therefore signal values of up to 1/0.75 will pass through the DSP without clipping. Since the DAC is designed to produce an analog output of 2 Vrms (differential) with a 0 dB digital input, signals between 0 dB and 1/0.75 (approximately 3 dB) will produce larger analog outputs and result in slightly degraded analog performance. This extra analog range is necessary in order to pass 0 dBFS square waves through the system, as these square waves cause overshoots in the interpolation filters that would otherwise briefly clip the digital DAC circuitry. A separate digital clipper circuit is used in the DSP core to ensure that any accumulator values that exceed the numeric 3.23 format range are clipped when taken from the accumulator. High-Pass Filter Biquad Filters Each of the two input channels has seven second-order biquad sections in the signal path. In addition, the left and right channels have two additional biquad filters that may be used either as crossover filters or as additional equalization filters. The SUB channel has three additional biquad filters, also to be used as equalization and/or crossover filters. In a typical scenario, the first seven biquads would be used for speaker equalization and/ or tone controls, and the remaining filters would be programmed to function as crossover filters. Note that there is a common equalization section used for both the main and SUB channels, followed by crossover filters. This arrangement prevents any interaction from occurring between the crossover filters and the equalization filters. One section of the Biquad IIR filter is shown in Figure 4. This section implements the transfer function: (b0 + b1 x Z H (Z ) = (1 - a1 x Z -1 + b2 x Z -2 -2 -1 - a2 x Z ) ) (2) The high-pass filter is a first-order double-precision design. The purpose of the high-pass filter is to remove "Digital DC" from the input. If this DC were allowed to pass, the detectors used in the compressor/limiter would give an incorrect reading for low signal levels. The high-pass filter is controlled by a single parameter (alpha_HPF), which is programmed by writing to SPI location 180 in 2.20 two's complement format. The following equation can be used to calculate the parameter Alpha_HPF from the -3 dB point of the filter: The coefficients a1, a2, b0, b1, and b2 are all in two's complement 2.20 format with a range from -2 to +2 (minus 1 LSB). The negative sign on the a1 and a2 coefficients is the result of adding both the feed-forward `b' terms as well as the feedback `a' terms. Some digital filter packages automatically produce the correct a1 and a2 coefficients for the topology of Figure 4, while others assume a denominator of the form 1 + a1 x Z-1 + a2 x Z-1. In this case, it may be necessary to invert the a1 and a2 terms for proper operation. The biquad structure shown in Figure 4 is coded using doubleprecision math to avoid limit-cycles from occurring when lowfrequency filters are used. The coefficients are programmed by writing to the appropriate location in the Parameter RAM, through the SPI port (see Table V). There are two possible scenarios for controlling the biquad filters: 1. Dynamic Adjustment (for example, Bass/Treble control or Parametric Equalizer) -2.0 x x HPF _ CUTOFF Alpha _ HPF = 1.0 - EXP (1) fS where EXP is the exponential operator, HPF_CUTOFF is the high-pass cutoff in Hz, and fS is the audio sampling rate. The default value for the -3 dB cutoff of the high-pass filter is 2.75 Hz at a sampling rate of 44.1 kHz. b0 IN b1 Z-1 a1 Z-1 OUT When using dynamic filter adjustment, it is highly recommended that the user employ the "safeload" mechanism to avoid temporary instability when the filters are dynamically updated. This could occur if some, but not all, of the coefficients were updated to new values when the DSP calculates the filter output. The operation of the Safeload registers is detailed in the Options for Parameter Updates section. 2. Setting Static EQ Curve after Power-Up b2 Z-1 a2 Z-1 If many of the biquad filters need to be initialized after powerup (for example, to implement a static speaker-correction curve), the recommended procedure is to set the processor shutdown bit, wait for the volume to ramp down (about 20 ms), and then write directly to the Parameter RAM in Figure 4. Biquad Filter REV. PrA -13- PRELIMINARY TECHNICAL DATA AD1954 "Burst Mode." After the RAM is loaded, the shutdown bit can be de-asserted, causing the volume to ramp back up to the initial value. This entire procedure is click-free, and faster than using the "Safeload" mechanism. The datapaths of the AD1954 contain an extra two bits on top of the 24 bits that are input to the serial port. This allows up to 12 dB of boost without clipping. However, it is important to remember that it is possible to design a filter that has less than 12 dB of gain at the final filter output, but more than 12 dB of gain at the output of one or more intermediate biquad filter sections. For this reason, it is important to cascade the filter sections in the correct order, putting the sections with the largest peak gains at the end of the chain rather than at the beginning. This is standard practice when coding IIR filters, and is covered in basic books on DSP coding. If gains larger than 12 dB cannot be avoided, then the coefficients b0 through b2 of the first biquad section may be scaled down to fit the signal into the 12 dB maximum signal range, and then scaled back up at the end of the filter chain. Volume The algorithm works by increasing the phase shift for lowfrequency signals that are panned left or right in the stereo mix. Since the ear is responsive to inter-aural phase shifts below 1 kHz, this increase in phase shifts results in a widening of the stereo image. Note that signals panned to the center are not processed, resulting in a more natural sound. There are two parameters that control the Phat Stereo algorithm: the "Level" variable, which controls how much out-of-phase information is added to the left and right channels, and the cutoff frequency of the firstorder lowpass filter, which determines the frequency range of the added out-of-phase signals. For best results, the cutoff frequency should be in the range of 500 Hz to 2 kHz. These parameters are controlled by altering the Parameter RAM locations that store the parameters "spread_level" and "alpha_spread." The "spread_level" is a linear number in 2.20 format that multiplies the processed left-right signal before it is added to or subtracted from the main channels. The parameter "alpha_spread" is related to the cutoff frequency of the first-order low-pass filter by the equation: Three separate SPI registers are used to control the volume-- one each for the Left, Right, and Sub channels. These registers are special in that they include automatic digital ramp circuitry for clickless volume adjustment. The volume control word is in 2.20 format, and therefore gains from +2.0 to -2.0 are possible. The default value is 1.0. It takes 1024 audio frames to adjust the volume from 2.0 down to 0; in the normal case where the MAX volume is set to 1.0, it will take 512 audio frames for this ramp to reach zero. Note that a "Mute" command is the same a setting the volume to zero, except that when the part is un-muted, the volume returns to its original value. The volume blocks are placed after the biquad filter sections to maximize the level of the signal that is passed through the filter sections. In a typical situation, the nominal volume setting might be -15 dB, allowing a substantial increase in volume when the user increases the volume. The AD1954 was designed with an analog dynamic range of > 115 dB, so that in the typical situation with the volume set to -15 dB, the signal-to-noise ratio at the output will still exceed 100 dB. Greater output dynamic ranges are possible if the compressor/limiter is used, as the "post-compression gain" parameter can boost the signal back up to a higher level. In this case, the compressor will prevent the output from clipping when the volume is turned up and the input signal is large. Stereo Image Expander -2.0 x x spread _ freq Alpha _ spread = 1.0 - EXP fS where EXP is the exponential operator, spread_freq is the low-pass cutoff in Hz, and fS is the audio sampling rate. Note that the stereo spreading algorithm assumes that frequencies below 1 kHz are present in the main satellite speakers. In some systems, the crossover frequency between the satellite and subwoofer speakers is quite high (> 500 Hz). In this case, the stereo spreading algorithm will not be effective, as the frequencies that contribute to the spreading effect will be coming mostly from the subwoofer, which is a mono source. Delay Each of the three DAC channels has a delay block that allows the user to introduce a delay of up to 165 audio samples. The delay values are programmed by entering the delay (in samples) into the appropriate location of the Parameter RAM. With a 44.1 kHz sample rate, a delay of 165 samples corresponds to a time-delay of 3.74 ms. Since sound travels at approximately 1 foot/ms, this can be used to compensate for speaker placements that are off by as much as 3.74 feet. An additional 100 samples of delay are used in the "look-ahead" portion of the compressor/limiter, but only for the main two channels. This can be used to increase the total delay for the left and right channels to 265 samples, or 6 ms at 44.1 kHz. Main Compressor/Limiter The image-enhancement processing is based on ADI's patented "Phat StereoTM" algorithm. The block diagram is shown below. LEFT IN + - 1 kHz FIRST-ORDER LPF LEVEL - RIGHT IN RIGHT OUT + - LEFT OUT The compressor used in the AD1954 is quite sophisticated, and is comparable in many ways to professional compressor/limiters used in the pro audio and broadcast fields. It uses RMS/peak detection with adjustable attack/hold/release, look-ahead compression, and table-based entry of the input/output curve for complete flexibility. Figure 5. Stereo Image Expander -14- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 The AD1954 uses two compressor/limiters, one in the subwoofer DAC and one in the main left/right DAC. It is well known that having independent compressors operating over different frequency ranges results in a superior perceived sound. With a single-band compressor, loud bass information will modulate the gain of the entire audio signal, resulting in suboptimal maximum perceived loudness as well as gain "pumping" or modulation effects. With independent compressors operating separately on the low and high frequencies, this problem is dramatically reduced. If the AD1954 is being operated in two-channel mode, an extra path is added so that the subwoofer channel can be added back into the main channel. This maintains the advantage of using a 2-band compressor, even in a 2.0 system configuration. Figure 6 shows the traditional basic analog compressor/limiter. It uses a voltage-controlled amplifier to adjust gain, and a feedforward detector path using an RMS detector with adjustable time constants, followed by a non-linear circuit to implement the desired input/output relationship. A simple compressor will have a single threshold above which the gain is reduced. The amount of compression above the threshold is called the compression ratio, and is defined as dB change in input/dB change in output. For example, if the input to a 2:1 compressor is increased by 2 dB, the output will rise by 1 dB for signals above the threshold. A single "hard" threshold results in more audible behavior than a so called "soft-knee" compressor, where the compression is introduced more gradually. In an analog compressor, the soft-knee characteristic is usually made by using diodes in their exponential turn-on region. VCA WITH EXP OUT CONTROL THRESHOLD SLOPE The best analog compressors use RMS detection as the signal amplitude detector. RMS detectors are the only class of detectors that are not sensitive to the phase of the harmonics in a complex signal. The ear also bases its loudness judgment on the overall signal power, and therefore using an RMS detector results in the best audible performance. Compressors that are based on peak detection, while good for preventing clipping, are generally quite poor when it comes to audible performance. RMS detectors have a certain time constant, which determines how rapidly they can respond to transient signals. There is always a tradeoff between speed of response and distortion. Figure 7 shows this trade-off. INPUT WAVEFORM COMPRESSOR ENVELOPE - FAST TIME CONSTANT COMPRESSOR ENVELOPE - SLOW TIME CONSTANT Figure 7. Effect of RMS Time Constant on Distortion FILTER RMS DETECTOR WITH DB OUT COMPRESSION CURVE NONLINEAR CIRCUITS Figure 6. Analog Compressor In the case of a fast-responding RMS detector, the detector envelope will have a signal component in addition to the desired DC component. This signal component (which, for an RMS detector, is at twice the input frequency) will result in harmonic distortion when multiplied by this detector signal. REV. PrA -15- PRELIMINARY TECHNICAL DATA AD1954 The AD1954 uses a "modified RMS" algorithm to improve the relationship between acquisition time and distortion. It uses a peak-riding circuit together with a hold circuit to modify the RMS signal, as shown in Figure 8. This figure shows two envelopes--one with the harmonic distortion, as seen in the previous figure, and the other, flatter envelope is the one produced by the AD1954. One subtlety of the table lookup involves the difference between the RMS value of a sine wave at that of a square wave. If a fullscale square wave is applied to the AD1954, the RMS value of this signal will be 3 dB higher than the RMS value of a 0 dBFS sine wave. Therefore, the top table entry (location 142 for main channel compressor) has been set to correspond to the RMS value of a 0 dBFS square wave. Since we would prefer to calibrate ourselves to sine wave amplitudes, we will refer to this table entry as 3 dB. Therefore, the table will range from +3 dB (location 142) to -96 dB (location 110). The entries in the table are linear gain words in 2.20 format. Figure 10 shows an example of the table entries for a simple above-threshold compressor. INPUT WAVEFORM HOLD TIME, SPIPROGRAMMABLE RELEASE TIME, SPIPROGRAMMABLE OUTPUT LEVEL - dB DESIRED COMPRESSION CURVE Figure 8. Using the Hold and Release Time Feature Using this idea of a "modified RMS" algorithm, the true RMS value is still obtained for all but the lowest-frequency signals, while the distortion due to RMS ripple is reduced. It also allows the user to set the Hold and Release times of the compressor independently. The detector path of the AD1954 is shown in Figure 9. The RMS detector is controlled by three parameters, stored in parameter RAM: the RMS time constant, the hold time, and the release rate. The LOG output of the RMS detector is applied to a lookup table with interpolation. The higher bits of the RMS output form an offset into this table, and the lower bits are used to interpolate between the table entries to form a high-precision gain word. The lookup table resides in the Parameter RAM and is loaded by the user to give the desired curve. The lookup table contains 33 data locations, and the LSB of the address into the lookup table corresponds to a 3 dB change in the amplitude of the detector signal. This gives the user the ability to program an input/output curve over a 99 dB range. For the main compressor, the table resides in locations 110 to 142 in the SPI Parameter RAM. HIGH BITS (1 LSB = 3dB) MODIFIED RMS DETECTOR WITH LOG OUTPUT TIME HOLD RELEASE CONSTANT OUTPUT TO GAIN STAGE INPUT LEVEL - 3dB/TABLE ENTRY 1.0 LINEAR GAIN INPUT LEVEL - 3dB/TABLE ENTRY Figure 10. Example of Table Entry for a Given Compression Curve Note that the maximum gain that can be entered in the table is 2.0 (minus 1 LSB). If more gain is required, the entire compression curve may be shifted upward by using the post-compression gain block following the compressor/limiter. LOOKUP TABLE LOW BITS LINEAR INTERPOLATION Figure 9. Gain Derived from Interpolated Lookup Table -16- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 The AD1954 compressor/limiter also includes a "look-ahead compression" feature. The idea behind look-ahead compression is to prevent compressor overshoots by applying some digital delay to the signal before the gain-control multiplier, but not to the detector path. In this way, the detector can acquire the new amplitude of the input signal before the signal actually reaches the multiplier. A comparison of a tone burst fed to a conventional compressor versus a look-ahead compressor is shown in Figure 11. CONVENTIONAL COMPRESSOR GAIN ficient format used is 2.20, which has a maximum floating-point representation of slightly less than 2.0. This means that the maximum gain that can be achieved in a single instruction is 6 dB. To get more gain, the program in the AD1954 uses a cascade of five multipliers, to achieve up to 30 dB of post-compression gain. To program the compressor/limiter, the following formulas may be used to determine the 22-bit numbers (in 2.20 format) to be entered into the parameter RAM. RMS Time Constant This can be best expressed by entering the time constant in terms of dB/sec "raw" release rate (without the peak-riding circuit). The attack rate is a rather complicated formula that depends on the change in amplitude of the input sine wave. Rms _ tconst _ parameter = 1.0 - 10 LOOK-AHEAD COMPRESSOR GAIN release rate (10.0 x f S ) HOLD TIME Where Rms_tconst_parameter = fractional number to enter into the SPI RAM (after converting to 22-bit 2.20 format) Release_rate = release rate of the raw RMS detector in dB/sec. This must be negative. fS = audio sampling rate. RMS Hold Time rms _ holdtime _ parameter = int( fS x hold _ time) Figure 11. Conventional Compression vs. Look-Ahead Compression In the look-ahead compressor, the gain has already been reduced by the time that the tone-burst signal arrives at the multiplier input. Note that when using a look-ahead compressor, it is important to set the detector hold time to a value that is at least the same as the look-ahead delay time, or else the compressor release will start too soon, resulting in an expanded "tail" of a tone burst signal. The complete flow of the left/right dynamics processor is shown in Figure 12. DELAY SPI-PROGRAMMABLE LOOK-AHEAD DELAY DELAY (L+R) 2 HIGH BITS (1 LSB = 3dB) MODIFIED RMS DETECTOR WITH LOG OUTPUT TIME HOLD RELEASE CONSTANT LOOKUP TABLE LOW BITS POST-COMPRESSION GAIN, SPIPROGRAMMABLE UP TO 30dB Where rms_holdtime_parameter = integer number to enter into the SPI RAM fS = audio sample rate Hold_time = absolute time to wait before starting the release ramp-down of the detector output. int() = integer part of expression RMS Release Rate: RMS _ decay _ parameter = int(rms _ decay / 0.137) Where RMS_decay_parameter = Decimal integer number to enter into the SPI RAM Rms_decay = decay rate in dB/sec int() = integer part of expression Look-ahead Delay LINEAR INTERPOLATION Lookahead _ delay _ parameter = Lookahead _ delay x fS Where Lookahead_delay = predictive compressor delay in absolute time fS = audio sample rate. The maximum lookahead_delay_parameter value is 100. Post-Compression Gain Figure 12. Complete Dynamics Flow, Main Channels Post _ compression _ gain _ parameter = post _ compression _ gain _ linear (1 5) The detector path works from a sum of left and right channels ((L+R)/2). This is the "normal" way that compressors are built, and it counts on the fact that the main instruments in any stereo mix are seldom recorded deliberately out-of-phase, especially in the lower frequencies, which tend to dominate the energy spectrum of real music. The compressor is followed by a block known as "post-compression gain." Most compressors are used to reduce the dynamic range of music by lowering the gain during loud signal passages. This results in an overall loss of volume. This loss can be made up by introducing gain after the compressor. In the AD1954, the coefREV. PrA Where Post_compression gain_linear is the linear post compression gain ^ = raise to the power -17- PRELIMINARY TECHNICAL DATA AD1954 Subwoofer Compressor/Limiter The subwoofer compressor/limiter differs from the left/right compressor in the following ways: 1. The subwoofer compressor operates on a weighted sum of left and right inputs (aa x Left + bb x Right), where aa and bb are both programmable. 2. The detector input has a biquad filter in series with the input in order to implement frequency-dependent compression thresholds. 3. There is no predictive compression, as presumably the input signals are filtered to pass only low frequencies, and therefore transient overshoots are not a problem. The subwoofer compressor signal flow is shown in Figure 13. VIN_SUB = k1 LEFT_IN+K2 RIGHT_IN filter in front of the detector. If one measures the response using a pink-noise generator, the result will look much better, as the detector will settle on only one gain value. The perceptual effect of the swept-sine-wave test is not at all what would be predicted by simply looking at the frequency response curve; it is only the signal-path filters that will affect the perception of frequency response, not the detector-path filters. De-emphasis Filtering The standard for encoding CDs allows the use of a pre-emphasis curve during encoding, which must be compensated for by a de-emphasis curve during playback. The de-emphasis curve is defined as a first-order shelving filter with a single pole at (1/(2 x x 50 s)) followed by a single zero at (1/(2 x x 15 s)). This curve may be accurately modeled using a first-order digital filter. This filter is included in the AD1954; it is not part of the bank of biquad filters, and so does not take away from the number of available filters. Since the specification of the de-emphasis filter is based on an analog filter, the response of the filter should not depend on the incoming sampling rate. However, when the de-emphasis filter is implemented digitally, the response will scale with the sampling rate unless the filter coefficients are altered to suit each possible input sampling rate. For this reason, the AD1954 includes three separate de-emphasis curves; one each for sampling rates of 32 kHz, 44.1 kHz, and 48 kHz. These curves are selected by writing to bits <5:4> of Control Register 1 over the SPI port. Alternatively, the 44.1 kHz curve can be called upon using the DEEMP/SDATA_AUX pin. This pin is included for compatibility with CD decoder chips that have a de-emphasis output pin. Using the Sub Re-Injection Paths for Systems with no Subwoofer HIGH BITS (1 LSB = 3dB) BIQUAD FILTER MODIFIED RMS DETECTOR WITH LOG OUTPUT TIME HOLD RELEASE CONSTANT LOOKUP TABLE LOW BITS POST-COMPRESSION GAIN, SPIPROGRAMMABLE UP TO 30dB LINEAR INTERPOLATION Figure 13. Signal Flow for Subwoofer Compressor The biquad filter before the detector can be used to implement a frequency-dependent compression threshold. For example, assume that the overload point of the woofer is strongly frequency-dependent. In this case, one would have to set the compressor threshold to a value that corresponded to the most sensitive overload frequency of the woofer. If the input signal happened to be mostly in a frequency range where the woofer was not so sensitive to overload, then the compressor would be too pessimistic and the volume of the woofer would be reduced. If, on the other hand, the biquad filter were designed to follow the woofer excursion curve of the speaker, then the volume of the woofer could be maximized under all conditions. This is illustrated in Figure 14. WOOFER EXCURSION BIQUAD RESPONSE Many systems will not use a subwoofer, but would still benefit from two-band compression/limiting. This can be accommodated by using sub reinjection paths in the program flow. These parameters are programmed by entering two numbers (in 2.20 format) into the parameter RAM. Note that if the biquad filters are not properly designed, the frequency response at the crossover point may not be flat. Many crossover filters are designed to be flat in the sense of adding the powers together, but non-flat if the sum is done in voltage mode. The user must take care to design an appropriate set of crossover filters. Interpolation Filters 20 Hz FREQ 200 Hz 20 Hz FREQ 200 Hz Figure 14. Optimizing Woofer Loudness Using the Subwoofer RMS Biquad Filter When using a filter in front of the detector, a confusing sideeffect occurs. If one measures the frequency response by using a swept sine-wave with an amplitude large enough to be above the compressor threshold, the resulting frequency response will not look flat. However, this is not "real" in the sense that, as the sine wave is swept through the system, the gain is being slowly modulated up and down according the response of the biquad The left and right channels have a 128:1 interpolation filter with 75 dB stopband attenuation that precedes the digital sigma-delta modulator. This filter has a group delay of approximately TBD taps. The sub channel does not use an interpolation filter. The reason for this (besides saving valuable MIPs) is that it is expected that the bandwidth of the sub output will be limited to less than 1 kHz. With no interpolation filter, the first "image" will therefore be at 43.1 kHz (which is fS - 1 kHz, for CD audio). The standard external filter used for both the main and sub channels is a third-order, single op amp filter. If the cutoff frequency of the external subwoofer filter is 2 kHz, then there are more than 4 octaves between 2 kHz and the first image at 43.1 kHz. A thirdorder filter will roll off by approximately 18 dB/oct x 4 octaves = 72 dB attenuation. This is approximately the same as the digital attenuation used in the main-channel filters, and so no internal interpolation filter is required to remove the out-of-band images. -18- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 Note that by having interpolation filters in the main channels, but not the subwoofer channel, there is a potential time-delay mismatch between the main and sub channels. The group delay of the digital interpolation filters used in the main left/right channels is about 0.5 ms. This must be compared to the group delay of the external analog filter used in the subwoofer path. If the group delay mismatch causes a frequency response error (when the two signal are "acoustically added"), then the programmable delay feature can be used to put extra delay in either the subwoofer path or the main left/right path. SPI PORT Overview (available for loading the RAMs only), an initial address is given followed by a continuous sequence of data for consecutive RAM locations. The detailed data format diagram for continuousmode operation is given in SPI Read/Write data formats. A sample timing diagram for a single SPI WRITE operation to the parameter RAM is shown in Figure 15. Table I. SPI Word Format Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Data Data Data 00000, Wb/R, adr[9:8] Adr[7:0] The AD1954 has many different control options. Most signalprocessing parameters are controlled by writing new values to the parameter RAM using the SPI port. Other functions such as volume and de-emphasis filtering are programmed by writing to SPI control registers. The SPI port uses a four-wire interface, consisting of CLATCH, CCLK, CDATA and COUT signals. The CLATCH signal goes LOW at the beginning of a transaction and HIGH at the end of a transaction. The CCLK signal latches the serial input data on a LOW-to-HIGH transition. The CDATA signal carries the serial input data, and the COUT signal is the serial output data. The COUT signal remains tri-stated until a READ operation is requested. This allows other SPI-compatible peripherals to share the same readback line. The SPI port is capable of full read/write operation for all of the memories (Parameter and Program) and some of the SPI registers (Control Register 1 and Data Capture registers). The memories may be accessed in both a single-address mode or in burst mode. All SPI transactions follow the same basic format, shown in Table I. The Wb/R bit is LOW for a write, and HIGH for a read operation. The 10-bit address word is decoded into either a location in one of the two memories (Parameter or Program) or one of the SPI registers. The number of Data bytes varies according to the register or memory being accessed. In burst-write mode A sample timing diagram of a single SPI READ operation is shown in Figure 16. The COUT pin goes from tri-state to driven at the beginning of Byte 2. Byte 0 and 1 contain the address and R/W bit, and bytes 2-4 carry the data. The exact format is shown in Tables VIII to XIX. The AD1954 has several mechanisms for updating signalprocessing parameters in real-time without causing loud pops or clicks. In cases where large blocks of data need to be downloaded, the DSP core can be shut down, new data loaded, and then restarted. The shutdown and re-start mechanisms employ a gradual volume ramp to prevent clicks and pops. In cases where only a few parameters need to be changed (for example, a single biquad filter), a "safeload" mechanism is used that allows a block of SPI registers to be transferred to the parameter RAM within a single audio frame while the core is running. The safeload mode uses internal logic to prevent contention between the DSP core and the SPI port. SPI Address Decoding Table II shows the address decoding used in the SPI port. The SPI address space encompasses a set a registers and two RAMs, one for holding signal-processing parameters and one for holding the program instructions. Both of the RAMs are loaded on power-up from on-board "boot" ROMs. CLATCH CCLK CDATA BYTE 0 BYTE 1 BYTE 4 Figure 15. Sample of SPI WRITE Format (Single-Write Mode) CLATCH CCLK CDATA BYTE 0 BYTE 1 XXX COUT HI-Z DATA DATA DATA HI-Z Figure 16. Sample of SPI READ Format (Single-Read Mode) REV. PrA -19- PRELIMINARY TECHNICAL DATA AD1954 Table II. SPI Port Address Decoding SPI Address 0-255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 269-510 511 512-1024 Register Name Parameter RAM SPI Control Register 1 SPI Control Register 2 Volume Left Volume Right Volume Sub Data Capture (SPI Out) #1 Data Capture (SPI Out) #2 Data Capture (Serial Out) Left Data Capture (Serial Out) Right Parameter RAM Safe Load Register 0 Parameter RAM Safe Load Register 1 Parameter RAM Safe Load Register 2 Parameter RAM Safe Load Register 3 Parameter RAM Safe Load Register 4 Unused Test Register Program RAM Read/Write wordlength. Write: 22 Bits Read: 22 Bits Write: 11 Bits Read: 2 Bits Write: 9 Bits Read: N/A Write: 22 Bits Read: N/A Write: 22 Bits Read: N/A Write: 22 Bits Read: N/A Write: 9 Bit Program counter value, 2 Bit Register Address Read: 24 Bits Write: 9 Bit Program Counter Value 2 Bit Register Address Read: 24 Bits Write: 9 Bit Program Counter value, 2 Bit Register Address Read: N/A Write: 9 Bit Program Counter value, 2 Bit Register Address Read: N/A Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data Read: N/A Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data Read: N/A Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data Read: N/A Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data Read: N/A Write: 8 Bit Parameter RAM Address, 22 Bit Parameter Data Read: N/A Write: 8 Bits Read: N/A Write: 35 Bits Read: 35 Bits Control Register 1 Control Register 1 is an 11-bit register that controls serial modes, de-emphasis, mute, power-down, and SPI-to-Memory transfers. Table III documents the contents of this register. Bit <11> controls the functions of the DEEMP/SDATA_AUX pin. The default setting is "0" which corresponds to the de-emphasis function. More information is available in the Pin Functions Section. The wordlength bits are used in right-justified serial modes to determine where the MSB is located relative to the start of the audio frame. The serial mode bits select one of four modes, which are discussed in the Serial Data Input Port section. The de-emphasis bits turn on the internal de-emphasis filter for one of three possible sample rates. The halt program bit is used to initiate a volume ramp-down followed by a shutdown of the DSP core. The user may poll for this operation to complete by reading Bit 1 of Control Register 1. Soft mute is used to initiate a volume ramp-down sequence. If the initial volume was set to 1.0, this operation will take 512 audio frames to complete. When this bit is de-asserted, a "ramp-up" sequence is initiated until the volume returns to its original setting. The initiatesafe-transfer bit will request a data transfer from the SPI "safeload" registers to the parameter RAM. The safeload registers contain address-data pairs, and only those registers that have been written to since the last transfer operation will be uploaded. The user may poll for this operation to complete by reading bit 0 of Control Register 1. Safeload Mechanism section goes into more detail on this feature. The soft power down bit stops the internal clocks to the DSP core, but does not reset the part. The digital power consumption is reduced to a low level when this bit is asserted. Reset can only be asserted using the external reset pin. The Enable-DCSOUT bit is used to turn on the Data Capture Serial Out pin. This pin may be used to send data that is captured using the data-capture feature to external devices such as an additional stereo DAC. The Data Capture Registers section gives more information about the data capture feature. When a read operation is performed on Control Register 1, two bits are returned, as shown in Table IV. -20- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 Table III. Control Register 1 WRITE Definition Table V. Control Register 2 WRITE Definition Register Bits 11 10 9 8 7 6 5:4 Function De-emphasis/Aux. Serial Input Pin Select (1 = Aux. Serial Input) Halt Program (1 = Halt) Initiate safe transfer (1 = transfer) Enable DCSOUT output pin (1 = enable) Soft Mute (1 = start mute sequence) Soft Power down (1 = power down) De-emphasis curve select 00 = none 01 = 44.1 kHz 10 = 32 kHz 11 = 48 kHz Serial In Mode 00 = I2S 01 = Right-Justified 10 = DSP 11 = Left-Justified Wordlength 00 = 24 Bits 01 = 20 Bits 10 = 16 Bits 11 = 16 Bits Register Bits 8 Function Serial Port Output Enable 1 = enabled 0 = disabled Serial Port Input Select 00 = IN0 01 = IN1 10 = IN2 11 = NA MCLK Input Select 00 = MCLK0 01 = MCLK1 10 = MCLK2 11 = NA MCLK In Frequency Select 00 = 512 x fS 01 = 256 x fS 10 = Not Available 11 = 384 x fS MCLK Out Frequency Select 00 Disabled 01 512 x fS 10 256 x fS 11 MCLK_out = MCLK_In (feed-thru) 7:6 5:4 3:2 3:2 1:0 1:0 Control Register 2 Table IV. Control Register 1 READ Definition Register Bits 1 Function DSP core shutdown complete 1 = shutdown complete 0 = not shut down Safe Memory Load Complete 1 = complete (note: cleared after read) 0 = not complete 0 Bit 0 is asserted when all requested safeload registers have been transferred to the parameter RAM. It is cleared after the read operation is complete. Bit 1 is asserted after the requested shutdown of the DSP is completed. When this bit is set, the user is free to write or read any RAM location without causing an audio pop or click. Table V documents the contents of Control Register 2. bits <1:0> set the frequency of the MCLKO pin. If these bits are set to 00, then the MCLKO pin is disabled (default). When set to 01, the MCLKO pin is set to 512 x fS, which is the same as the internal master clock used by the DSP core. When set to 10, this pin is set to 256 x fS, derived by dividing the internal DSP clock by 2. When set to 11, the MCLKO pin mirrors the selected MCLK input pin (it's the output of the MCLK MUX selector). Note that the internal DSP master clock may either be the same as the selected MCLK pin (when MCLK Frequency Select is set to 512 x fS mode) or may be derived from the MCLK pin using internal clock doublers (when MCLK Frequency Select is set to 256 x fS or 384 x fS mode). Bits <3:2> select one of three possible MCLK input frequencies. When set to 00 (default), the MCLK frequency is set to 512 x fS. In this mode, the internal DSP clock and the external MCLK are at the same frequency. When set to 01, the MCLK frequency is set to 256 x fS, and an internal clock doubler is used to generate the DSP clock. When set to 11, the MCLK frequency is set to 384 x fS, and a divide-by-three and two internal clock doublers are used to generate the internal 512 x fS DSP clock. Bits <5:4> select one of three clock input sources using an internal MUX. To avoid click and pop noises when switching MCLK sources, it is recommended that the user put the DSP core in shutdown before switching MCLK sources. Bits <7:6> select one of three serial input sources using an internal MUX. Each source selection includes a separate SDATA, LRCLK and BCLK input. To avoid click and pop noises when switching serial sources, it is recommended that the user put the DSP core in shutdown before writing to these bits. REV. PrA -21- PRELIMINARY TECHNICAL DATA AD1954 Bit 8 is used to enable the three serial output pins. These pins are connected to the output of the serial input MUX, which is set by bits <7:6>. The default is 0 (disabled). Volume Registers The AD1954 contains three 22-bit volume registers, one each for the left, right, and subwoofer channels. These registers are special because when the volume is changed from an initial value to a new value, a linear ramp is used to interpolate between the two values. This feature prevents audible clicks and pops when changing volume. The ramp is set so that it takes 512 audio frames to decrement from a volume of 1.0 (default) down to 0 (muted). The volume registers are formatted in 2.20 two's complement, meaning that 01000000000000000000 is interpreted as 1.0. Negative values can also be written to the volume register, causing an inversion of the signal. Negative values work as expected with the "ramp" feature; to go from +1.0 to -1.0 will take 1024 LRCLKs, and the volume will pass through 0 on the way. Parameter RAM Contents 0 - 255. The low addresses of the RAM are used to control the biquad filters. There are 22 biquad filters in all, and each biquad has five coefficients, resulting in a total memory usage of 110 coefficients. There are also two tables of 33 coefficients each that define the main and sub compressor input/output characteristics. These are loaded with 1.0 on power-up, resulting in no compression. Other RAM entries control other compressor characteristics, as well as delay and spatialization settings. The parameter RAM is initialized on power-up by an on-board boot ROM. The default values (shown in the table) yield no equalization, no compression, no spatialization, no delay, and "normal" detector time constants in the compressor sections. The functionality of the AD1954 on power-up is basically that of a normal audio DAC with no signal-processing capability. The data format of the Parameter RAM is two's complement 2.20 format. This means that the coefficients may range from +2.0 (-1 LSB) to -2.0, with 1.0 represented by the binary word 01000000000000000000. Table VI shows the contents of the parameter RAM. The parameter RAM is 22 bits wide, and occupies SPI addresses Table VI. Parameter RAM Contents Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Function IIR0 Left b0 IIR0 Left b1 IIR0 Left b2 IIR0 Left a1 IIR0 Left a2 IIR1 Left b0 IIR1 Left b1 IIR1 Left b2 IIR1 Left a1 IIR1 Left a2 IIR2 Left b0 IIR2 Left b1 IIR2 Left b2 IIR2 Left a1 IIR2 Left a2 IIR3 Left b0 IIR3 Left b1 IIR3 Left b2 IIR3 Left a1 IIR3 Left a2 IIR4 Left b0 IIR4 Left b1 Default value in fractional 2.20 format 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 -22- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 IIR4 Left b2 IIR4 Left a1 IIR4 Left a2 IIR5 Left b0 IIR5 Left b1 IIR5 Left b2 IIR5 Left a1 IIR5 Left a2 IIR6 Left b0 IIR6 Left b1 IIR6 Left b2 IIR6 Left a1 IIR6 Left a2 IIR0 Right b0 IIR0 Right b1 IIR0 Right b2 IIR0 Right a1 IIR0 Right a2 IIR1 Right b0 IIR1 Right b1 IIR1 Right b2 IIR1 Right a1 IIR1 Right a2 IIR2 Right b0 IIR2 Right b1 IIR2 Right b2 IIR2 Right a1 IIR2 Right a2 IIR3 Right b0 IIR3 Right b1 IIR3 Right b2 IIR3 Right a1 IIR3 Right a2 IIR4 Right b0 IIR4 Right b1 IIR4 Right b2 IIR4 Right a1 IIR4 Right a2 IIR5 Right b0 IIR5 Right b1 IIR5 Right b2 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 REV. PrA -23- PRELIMINARY TECHNICAL DATA AD1954 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 IIR5 Right a1 IIR5 Right a2 IIR6 Right b0 IIR6 Right b1 IIR6 Right b2 IIR6 Right a1 IIR6 Right a2 IIR0 Xover Left b0 IIR0 Xover Left b1 IIR0 Xover Left b2 IIR0 Xover Left a1 IIR0 Xover Left a2 IIR1 Xover Left b0 IIR1 Xover Left b1 IIR1 Xover Left b2 IIR1 Xover Left a1 IIR1 Xover Left a2 IIR0 Xover Right b0 IIR0 Xover Right b1 IIR0 Xover Right b2 IIR0 Xover Right a1 IIR0 Xover Right a2 IIR1 Xover Right b0 IIR1 Xover Right b1 IIR1 Xover Right b2 IIR1 Xover Right a1 IIR1 Xover Right a2 IIR0 Xover Sub b0 IIR0 Xover Sub b1 IIR0 Xover Sub b2 IIR0 Xover Sub a1 IIR0 Xover Sub a2 IIR1 Xover Sub b0 IIR1 Xover Sub b1 IIR1 Xover Sub b2 IIR1 Xover Sub a1 IIR1 Xover Sub a2 IIR2 Xover Sub b0 IIR2 Xover Sub b1 IIR2 Xover Sub b2 IIR2 Xover Sub a1 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 0 1.0 0 0 0 REV. PrA -24- PRELIMINARY TECHNICAL DATA AD1954 104 105 106 107 108 109 110 - 142 143 144 145 - 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 IIR2 Xover Sub a2 IIR Sub RMS b0 IIR Sub RMS b1 IIR Sub RMS b2 IIR Sub RMS a1 IIR Sub RMS a2 Main Compressor Lookup Table base Main Compressor attack/RMS time constant Main Post-Compressor Gain Subwoofer compressor lookup table base Sub Compressor attack/RMS time constant Post-compressor gain (SUB) High-pass filter cutoff frequency Main compressor look-ahead delay Delay Left Delay Right Delay Sub Stereo spreading coefficient Stereo spreading frequency control Subwoofer re-injection to main left Subwoofer re-injection to main right Subwoofer channel input gain from Left IN Subwoofer channel input gain from Right IN Main Detector HOLD time, samples (4095 MAX) Sub Detector HOLD time, samples (4095 MAX) Main detector decay time Sub detector decay time 0 1.0 0 0 0 0 1.0 (all) 5.75 x 10-4 (120 dB/sec) 1.0 1.0 (all) 5.75 x 10-4 (120 dB/sec) 1.0 3.92 x 10-4 0 0 0 0 0 0.112694 0.0 0.0 0.5 0.5 0 0 0.069611 (10000 dB/sec)* 0.069611 (10000 dB/sec)* *The default decay time of the hold/release circuit is set fast enough that the decay is dominated by the time constant of the RMS detector. Options for Parameter Updates The Parameter and Program RAMs can be written and read using one of several methods. 1. Direct read/write. This method allows direct access to the RAMs. Since the RAMs are also being used during real-time DSP operation, a glitch will likely occur at the output. This method is not recommended. 2. Direct read/write after core shutdown. This method avoids the glitch while accessing the internal RAMs by first shutting down the core. This is recommended for transferring large amounts of data, such as initializing the parameter RAM at power-up, or downloading a completely new program. These transfers can be sped up by using "burst mode," where an initial address followed by blocks of data are sent to the RAM. 3. "Safeload" writes, where up to five SPI registers are loaded with address/data intended for the parameter RAM. The data is then transferred to the requested address when the RAM is not busy. This method can be used for dynamic updates while live program material is playing through the AD1954. For example, a complete update of one biquad section can occur in one audio frame, while the RAM is not busy. This method is not available for writing to the Program RAM or control registers. The next section discusses these options in more detail. Soft Shutdown Mechanism When writing large amounts of data to the program or parameter RAM, the processor core should be halted to prevent unpleasant noises from appearing at the audio output. Figure 17 shows a graphical representation of this mechanism's volume envelope. Points A-D are referenced in the following description. Bit 10 in serial Control Register 0 (processor shutdown bit) will shut down the processor core. When the processor shutdown bit is asserted (A), an automatic volume ramp-down sequence (B) lasting from 10 ms - 20 ms will occur, followed by a shutdown REV. PrA -25- PRELIMINARY TECHNICAL DATA AD1954 of the core. This method of shutting down the core prevents pops or clicks from occurring. After the shutdown is complete, Bit 1 in Control Register 1 will be set. The user can either poll for this bit to be set, or just wait for a period longer than 20 ms. Once the core is shut down (C), the parameter or program RAMs may be written or read freely. To ease the transfer of large blocks of sequential data, a "block transfer" mode is supported where a starting address followed by a stream of data is sent to the memory. The address into the memory will be automatically incremented for each new write. This mode is documented in the SPI Data Format section of this datasheet. Once the data has been written, the shutdown bit can be cleared (D). The processor then will initiate a volume "ramp-up" sequence lasting for 10 - 20 ms. Again, this reduces the chance of any pop or click noise from occurring. Safeload Mechanism biquad filter has five coefficients. Once these registers are loaded, the "Initiate Safe Transfer" bit in SPI Control Register 1 is set. Once this bit is set, the processor waits for a period of time in the program sequence where the parameter RAM is not being accessed for at least five consecutive instruction cycles. When the program counter reaches this point, the parameter RAM is written with five new data values, at addresses corresponding to those entered in the safeload registers. When the operation is complete, Bit 0 of Control Register 1 is set. This bit may be polled by the external microprocessor until a 1 is read. This bit will be reset on a read operation. The polling operation is not required; the safeload mechanism guarantees that the transfer will be complete within one audio frame. The Safeload logic automatically sends only those Safeload registers that have been written to since the last Safeload operation. For example, if only two parameters are to be sent, then it is only necessary to write to two of the five Safeload registers. When the Request Safe Transfer bit is asserted, only those two registers will be sent; the other three registers are not sent, and can still hold old or invalid data. The Safeload mechanism is not limited to uploading biquad coefficients; any set of five values in the parameter RAM may be updated in the same way. This allows real-time adjustment of the compressor/limiter, delay, or stereo spreading blocks. Summary of RAM modes Many applications require real-time control of filter characteristics, such as bass/treble controls and parametric or graphic equalization. To prevent instability from occurring, all of the parameters of a particular biquad filter must be updated at the same time; otherwise, the filter could execute for one or two audio frames with a mixture of old and new coefficients. This mix of old and new could cause temporary instability, leading to transients that could take a long time to decay. The method used in the AD1954 to eliminate this problem is to load a set of five registers in the SPI port with the desired parameter RAM address and data. Five registers are used because each Table VII shows the sizes and available modes of the Parameter RAM and the Program RAM. A B C D Figure 17. Recommended Sequences for Complete Parameter of Program RAM Upload Using Shutdown Mechanism Table VII. Read/Write Modes Memory Parameter RAM Program RAM Size 256 x 22 512 x 35 SPI Address Range 0 - 255 512 - 1023 Read YES YES Write YES YES Burst Mode Available YES YES Write Modes Direct Write, Write after core shutdown, "Safeload" write Direct Write, Write after core shutdown -26- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 SPI READ/WRITE DATA FORMATS The read/write formats of the SPI port are designed to be byteoriented. This allows for easy programming of common microcontroller chips. To fit into a byte-oriented format, 0s are appended to the data fields in order To extend the data word to the next multiple of eight bits. For example, 22-bit words written to the SPI parameter RAM are appended with two leading zeroes to reach 24 bits (3 bytes), and 35-bit words written to the program RAM are appended with five zeros to reach 40 bits (5 bytes). These zero-extended data fields are appended to a 2-byte field consisting of a read/write bit and a 10-bit address. The SPI port knows how many data bytes to expect based on the address that is received in the first two bytes. The total number of bytes for a single-location SPI write command can vary from four bytes (for a Control Register write), to seven bytes (for a Program RAM write). Block writes may be used to fill contiguous locations in Program RAM or Parameter RAM. Table VIII. Parameter RAM READ/WRITE Format (Single Address) Byte 0 00000, Wb/R, adr[9:8] Byte 1 adr[7:0] Byte 2 00, param[21:16] Byte 3 param[15:8] Byte 4 param[7:0] Table IX. Parameter RAM Block READ/WRITE Format (Burst Mode) Byte 0 00000, Wb/R, adr[9:8] Byte 1 Byte 2 Byte 3 Byte 4 adr[7:0] 00, param[21:16] param[15:8] param[7:0] ADR Byte 5 Byte 8 Byte 6 Byte 9 Byte 7 Byte 10 ADR+1 ADR+2 Table X. Program RAM READ/WRITE Format (Single Address) Byte 0 Byte 1 Byte 2 00000, prog[34:32] Byte 3 prog[31:24] Byte 4 prog[23:16] Byte 5 prog[15:8] Byte 6 prog[7:0] 00000,Wb/R, adr[9:8] adr[7:0] Table XI. Program RAM Block READ/WRITE Format (Burst Mode) Byte 0 Byte 1 00000, Wb/R, adr[9:8] adr[7:0] Byte 7 Byte 12 Byte 8 Byte 13 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 9 Byte 14 00000, prog[34:32] prog[31:24] prog[23:16] prog[15:8] prog[7:0] Byte 10 Byte 15 Byte 11 Byte 16 ADR ADR+1 ADR+2 Table XII. SPI Control Register 1 WRITE Format Byte 0 00000, Wb/R, adr[9:8] Byte 1 adr[7:0] Byte 2 00000, bit[10:8] Table XIII. SPI Control Register 1 READ Format Byte 3 bit[7:0] Byte 0 00000, Wb/R, adr[9:8] Byte 1 adr[7:0] Table XIV. SPI Control Register 2 WRITE Format Byte 2 000000, bit[1:0] Byte 0 00000, Wb/R, adr[9:8] Byte 1 adr[7:0] Byte 2 00000, bit[10:8] Table XV. SPI Volume Register WRITE Format Byte 3 bit[7:0] Byte 0 000000, adr[9:8] Byte 1 adr[7:0] Byte 2 00, volume[21:16] Byte 3 volume[15:8] Byte 4 volume[7:0] REV. PrA -27- PRELIMINARY TECHNICAL DATA AD1954 Table XVI. Data Capture Register WRITE Format Byte 0 00000, Wb/R, adr[9:8] Byte 1 adr[7:0] Byte 2 00000, progCount[8:6] Byte 3 progCount[5:0], regSel[1:0] NOTES 1. ProgCount[8:0] = value of program counter where trap occurs (see table 6.1). 2. RegSel[1:0] selects one of four registers (see Data Capture Register section). Table XVII. Data_Capture_Serial Out Register (Address and Register Select) WRITE Format Byte 0 00000, Wb/R, adr[9:8] Byte 1 adr[7:0] Byte 2 00000, progCount[8:6] Byte 3 progCount[5:0], regSel[1:0] NOTES 1. ProgCount[8:0] = value of program counter where trap occurs (see table 6.1). 2. RegSel[1:0] selects one of four registers (see Data Capture Register section). Table XVIII. Data Capture READ Format Byte 0 00000, Wb/R, adr[9:8] Byte 1 adr[7:0] Byte 2 00000000 Byte 3 data[23:16] Byte 4 data[15:8] Byte 5 data[7:0] Table XIX. Safeload Register Write Format Byte 0 00000, Wb/R, adr[9:8] INITIALIZATION Power-up Sequence Byte 1 adr[7:0] Byte 2 paramAdr[7:0] Byte 3 00, param[21:16] Setting the Clock Mode Byte 4 param[15:8] Byte 5 param[7:0] The AD1954 has a built in power-up sequence that initializes the contents of all internal RAMs. During this time, the contents of the internal program Boot ROM are copied to the internal Program RAM memory, and likewise the SPI Parameter RAM is filled with values from its associated boot ROM. The data memories are also cleared during this time. The boot sequence lasts for 1024 MCLK cycles and starts on the rising edge of the RESETB pin. Since the boot sequence requires a stable master clock, the user should avoid writing to or reading from the SPI registers during this period of time. Note that the default power-on state of the internal clock mode circuitry is 512 x fS, or about 24 MHz for normal audio sample rates. This mode bypasses all the internal clock doublers, and allows the external master clock to directly operate the DSP core. If the external master clock is 256 x fS or 384 x fS, then the boot sequence will operate at this reduced clock rate and take slightly longer to complete. After the boot sequence has finished, the clock modes may be set via the SPI port. For example, if the external master clock frequency is 256 x fS clock, the boot sequence would take 1024 256 x fS clock cycles to complete, after which an SPI write could occur to put the AD1954 in 256 x fS mode. The default state of the MCLK input selector is MCLK0. Since this input selector is controlled using the SPI port, and the SPI port cannot be written to until the boot sequence is complete, there must be a stable master clock signal present on the MCLK0 pin at start-up. The AD1954 contains two clock doubler circuits that are used to generate an internal 512 x fS clock when the external clock is either 256 x fS or 384 x fS. The clock mode is set by writing to bits 3:2 of Control Register 2. When the clock mode is changed, it is possible that a glitch will occur on the internal MCLK signal. This may cause the processor to inadvertently write an incorrect value into the data RAM, which could cause an audio pop or click sound. To prevent this, it is recommended that the following procedure be followed: 1. Assert the soft power-down bit (Bit 6 in Control Register 1) to stop the internal MCLK. 2. Write the desired clock mode into bits 3:2 of Control Register 2. 3. Wait at least 1 ms while the clock doublers settle. 4. De-assert the soft power-down bit. An alternative procedure is to initiate a "soft shutdown" of the processor core by writing a 1 to the "halt program" bit in Control Register 1. This initiates a volume ramp-down sequence followed by a shutdown of the DSP core. Once the core is shut down (which can be verified by reading bit 1 from Control Register 1, or by waiting at least 20 ms), the new clock mode can be programmed by writing to bits <3:2> of Control Register 2. The DSP core can then be restarted by clearing the "halt program" bit in Control Register 1. -28- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 Setting the Data and MCLK Input Selectors The AD1954 contains input selectors for both the serial data inputs as well as the MCLK input. This allows the AD1954 to select a variety of input and clock sources with no external hardware required. These input selectors are controlled by writing to SPI Control Register 2. When the DATA source or MCLK source is changed by writing to the SPI port, it is possible that a pop or click will occur in the audio. To prevent this noise, the core should be shut down by writing a 1 to the "halt program" bit in Control Register 1. This initiates a volume ramp-down sequence followed by a shutdown of the DSP core. Once the core is shut down (which can be verified by reading bit 1 from Control Register 1, or by waiting at least 20 ms after the halt program command is issued), the new DATA or MCLK source can be programmed by writing to Control Register 2. The DSP core can then be restarted by clearing the "halt-program" bit in Control Register 1. DATA CAPTURE REGISTERS The capture count and register select bits are set by writing to one of the four Data Capture registers at the following SPI addresses: 261: SPI data capture setup register #1 262: SPI data capture setup register #2 263: Data Capture serial out setup register #1 264: Data Capture serial out setup register #2 The format of the captured data varies according to the register select fields. Data captured from the Mult_Out setting is in 1.23 two's complement format, so that a full-scale input signal will produce a full-scale digital output (assuming no processing). If the parameters are set such that the input-to-output gain is more than 0 dB, then the digital output will be clipped. Data captured using the MDI setting is in 3.21 format. A 0 dB digital input will produce a -12 dB digital output, assuming the AD1954 is set for no processing. Data captured using the MCI setting is in 2.20 format. This data is generally a signal gain or filter coefficient, and therefore it does not make sense to talk about the input-to-output gain. A coefficient of 01000000000000000000 corresponds to a gain of 1.0. The data that must be written to set up the data capture is a concatenation of the 9-bit Program Count index with the 2-bit register select field. Refer to Table XX to find the capture count and register select numbers that corresponds to the desired point to be monitored in the signal-processing flow. The SPI capture registers can be accessed by reading from SPI locations 261 (for SPI Capture Register 1) or 262 (for SPI Capture Register 2). The other two data capture registers (datacapture serial-out) automatically transfer their data to the Data Capture Serial Out (DCSOUT) pin. DCSOUT Capture Register 1 is present in the left data slot (as defined by the serial input format) and SCOUT Capture Register 2 is present in the right data slot. The format for writing to the SPI data-capture setup registers is given in the SPI section of this datasheet. dB LEVEL METERS LRCLK EXT DACs BCLK The AD1954 incorporates a feature called "data-capture." Using this feature, any node in the signal processing flow diagram may be sent either to an SPI-readable register, or to a dedicated serial output pin. This allows the basic functionality of the AD1954 to be extended to a larger number of channels, or alternatively it can be used to monitor and display information about signal levels or compressor/limiter activity. The AD1954 contains four independent data capture registers. Two of these registers transfer their data to the data capture serial output (DCSOUT) pin. The serial data format of this pin is the same as the serial data format used for the main digital inputs, and the LRCLK and BCLK signals can therefore be used as frame sync and bit-clock signals. This pin is primarily intended to feed signals to an external DAC or DSP chip to extend the number of channels that the internal DSP can access. The other two registers may be read back over the SPI port, and can be used for a variety of purposes. One example might be to access the dB output of the internal RMS detector, to run a frontpanel signal level display. A sample system is shown in Figure 18. For each of the four data capture registers, a capture count and a register select must be set. The capture count is a number between 0 and 511 that corresponds to the program step number where the capture will occur. The register-select field programs one of four registers in the DSP core that will be transferred to the data-capture register when the program counter equals the capture count. The register select field is decoded as follows: 00: Multiplier Output (Mult_Out) 01: Output of dB conversion block (DB_OUT) 10: Multiplier Data input (MDI) 11: Multiplier Coefficient Input (MCI) DCSOUT 5.1 CHANNEL OUTPUT MICROCONTROLLER AD1954 Figure 18. Typical Application of Data Capture Feature REV. PrA -29- PRELIMINARY TECHNICAL DATA AD1954 Table XX. Data Capture Trap Indexes and Register Select Signal Description HPF Out Left HPF Out Right Deemphasis Out Left Deemphasis Out Right Left Biquad 0 output Left Biquad 1 output Left Biquad 2 output Left Biquad 3 output Left Biquad 4 output Left Biquad 5 output Left Biquad 6 output Right Biquad 0 output Right Biquad 1 output Right Biquad 2 output Right Biquad 3 output Right Biquad 4 output Right Biquad 5 output Right Biquad 6 output Volume Out Left Volume Out Right Volume Out Sub Spatializer Out Left Spatializer Out Right Delay Output Left Delay Output Right Main Compressor RMS Out (dB) Main Compressor Gain Reduction (linear) Look-ahead Delay Output Left Look-ahead Delay Output Right Main Compressor Out Left Main Compressor Out Right Interpolator Input Left (includes SUB Re-Inject) Interpolator Input Right (includes SUB Re-Inject) Sub Channel Filter Input Sub Biquad 0 output Sub Biquad 1 output Program Count Index (9 Bits) 19 245 23 247 38 47 56 65 74 83 92 258 267 276 285 294 315 324 98 95 463 100 96 176 327 131 141 141 154 151 164 177 328 398 406 415 -30- Register Select (2 Bits) Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out DB_OUT MCI MDI MDI Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Numeric Format 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 24-bit positive binary, bit 19 corresponds to a 3 dB change 2.22, 2 LSBs = 0 3.21, 2 LSBs truncated 3.21, 2 LSBs truncated 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped REV. PrA PRELIMINARY TECHNICAL DATA AD1954 Sub Biquad 2 output Sub Biquad 3 output Sub Biquad 4 output Sub Biquad 5 output Sub Biquad 6 output Sub Delay Output Sub RMS Biquad Output Sub RMS Output (dB) Sub Compressor Gain (Linear) Sub Channel Output SERIAL DATA INPUT PORT 424 433 442 451 460 511 471 489 495 511 Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out Mult_out DB_OUT MCI Mult_out 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 1.23, clipped 24-bit positive binary, bit 19 corresponds to a 3 dB change 2.22, 2 LSBs = 0 1.23, clipped The AD1954's flexible serial data input port accepts data in two's complement, MSB-first format. The left channel data field always precedes the right channel data field. The serial mode is set by using mode select bits in the SPI Control Register. In all modes except for the right-justified mode, the serial port will accept an arbitrary number of bits up to a limit of 24 (extra bits will not cause an error, but they will be truncated internally). In the right-justified mode, SPI Control Register bits are used to set the wordlength to 16, 20, or 24 bits. The default on power-up is 24-bit mode. Proper operation of the right-justified mode requires that there be exactly 64 BCLKS per audio frame. Serial Data Input Modes In I2S mode. LRCLK is LO for the left channel, and HI for the right channel. Data is valid on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition but with a single BCLK period delay. The I2S mode can be used to accept any number of bits up to 24. In right-justified mode, LRCLK is HI for the left channel, LO for the right channel. Data is sampled on the rising edge of BCLK. The start of data is delayed from the LRCLK edge by 16, 12, or 8 BCLKS intervals, depending on the selected wordlength. The default wordlength is 24 bits; other wordlengths are set by writing to bits <1:0> of Control Register 1. In right-justified mode, it is assumed that there are 64 BCLKS per frame. Figure 19 shows the serial input modes. For the left-justified mode, LRCLK is HI for the left channel, and LO for the right channel. Data is sampled on the rising edge of BCLK. The MSB is left-justified to an LRCLK transition, with no MSB delay. The left-justified mode can accept any wordlength up to 24 bits. LRCLK BCLK SDATA MSB LEFT CHANNEL LSB MSB RIGHT CHANNEL LSB LEFT JUSTIFIED MODE - 16 TO 24 BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB LSB I2S MODE - 16 TO 24 BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB LSB LEFT CHANNEL RIGHT CHANNEL RIGHT JUSTIFIED MODE - SELECT NUMBER OF BITS PER CHANNEL LRCLK BCLK SDATA MSB LSB MSB LSB DSP MODE - 16 TO 24 BITS PER CHANNEL 1/fS NOTES 1. DSP MODE DOESN'T IDENTIFY CHANNEL 2. LRCLK NORMALLY OPERATES AT fS EXCEPT DSP MODE WHICH IS 2 fS 3. BCLK FREQUENCY IS NORMALLY 64 LRCLK BUT MAY BE OPERATED IN BURST MODE Figure 19. Serial Input Modes REV. PrA -31- PRELIMINARY TECHNICAL DATA AD1954 For the DSP serial port mode, LRCLK must pulse HI for at least one bit clock period before the MSB of the left channel is valid, and LRCLK must pulse HI again for at least one bit clock period before the MSB of the right channel is valid. Data is sampled on the falling edge of BCLK. The DSP serial port mode can be used with any wordlength up to 24 bits. In this mode, it is the responsibility of the DSP to ensure that the left data is transmitted with the first LRCLK pulse, and that synchronism is maintained from that point forward. DIGITAL CONTROL PINS Mute IREF IREF OUT+ VREF IN IREF + DIG_IN BIAS IREF - DIG_IN OUT- The AD1954 offers two methods of muting the analog output. By asserting the MUTE signal HI, the left, right and SUB channel are muted. As an alternative, the user can assert the mute bit in the serial Control Register HI. The AD1954 has been designed to minimize pops and clicks when muting and unmuting the device by automatically ramping the gain up or down. When the device is unmuted, the volume returns to the value set in the volume register. De-emphasis FROM DIGITAL SIGMA-DELTA MODULATOR (DIG_IN) SWITCHED CURRENT SOURCES Figure 20. Internal DAC Analog Architecture The AD1954 has a built-in de-emphasis filter that can be used to decode CDs that have been encoded with the standard "redbook" 50 s/15 s emphasis response curve. This feature may be activated by the pin or by an SPI write to the Control Register. When activating with the pin, only the 44.1 kHz sample-rate curve is available. When using the SPI port, curves for 44.1 kHz, 32 kHz, and 48 kHz are supported. ANALOG OUTPUT SECTION When the AD1954 is used to drive an audio power amplifier, and the compression feature is being used, then the VREF voltage should be derived by dividing down the supply of amplifier. This sets a fixed relationship between the digital signal level (which is the only information available to the digital compressor) and the full-scale output of the amplifier (just prior to the onset of clipping). For example, if the amplifier power supply drops by 10%, then the VREF input to the amplifier will also drop by 10%, which will reduce the analog output signal swing by 10%. The compressor will therefore be effective in preventing clipping regardless of any variation in amplifier supply voltage. Since the VREF input effectively multiplies the signal, care must be taken to ensure that no AC signals appear on this pin. This can be accomplished by using a large decoupling capacitor in the VREF external resistive divider circuit. If the VREF signal is derived by dividing the 5 V analog supply, then the time constant of the divider must effectively filter any noise on the supply. If the VREF signal is derived from an unregulated power-amplifier supply, then the time constant must be longer, as the ripple on the amplifier supply voltage will presumably be greater than in the case of the 5 V supply. Figure 20 shows the block diagram of the analog output section. A series of current sources are controlled by a digital sigma-delta modulator. Depending on the digital code from the modulator, each current source is connected to the summing junction of either a positive I-to-V converter or a negative I-to-V converter. Two extra current sources that "push" instead of "pull" are added to set the mid-scale common-mode voltage. All current sources are derived from the VREF input pin. The gain of the AD1954 is directly proportional to the magnitude of the current sources, and therefore the gain of the AD1954 is proportional to the voltage on the VREF pin. With VREF set to 2.25 V, the gain of the AD1954 is set to provide signal swings of 2 Vrms differential (1 Vrms from each pin). This is the recommended operating condition. -32- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 The AD1954 should be used with an external third-order filter on each output channel. The circuit shown in Figure 21 combines a third-order filter and a single-ended-to-differential converter in the same circuit. The values used in the main channel are for a 100 kHz Bessel filter, and those used in the subwoofer channel (Figure 22) result in a 10 kHz Bessel filter. The lower frequency filter is used on the subwoofer output because there is no digital interpolation filter used in the subwoofer signal-path. When calculating the resistor values for the filter, it is important to take into account the output resistance of the AD1954, which is nominally 60 . For best distortion performance, 1% resistors should be used. The reason for this is that the single-ended performance of the AD1954 is about 80 dB. The degree to which the single-ended distortion cancels in the final output is determined by the common-mode rejection of the external analog filter, which in turn depends on the tolerance of the components used in the filter. The SUB output of the AD1954 has a lower drive strength than the left and right output pins ( 0.25 mA peak versus 0.5 mA peak for the left and right outputs). For this reason, it is best to use higher resistor values in the external SUB filter. For best performance, a large (> 10 f) capacitor should be connected between the FILTCAP pin and analog ground. This pin is connected to an internal node in the bias generator, and by adding an external capacitance to this pin, the thermal noise of the left/right channels is minimized. The SUB channel is not affected by this connection. 3.7k 11k - INPUT 270nF 560nF + INPUT 5.62k 5.62k 1.5k 15nF 150pF 6.8nF 3.01k 27nF 56nF 6.8nF 604 OUT 220nF 2.2nF Figure 21. Recommended External Analog Filter for SUB Channel 3.01k 2.80k - INPUT 1nF NPO 2.7nF NPO + INPUT 806 1.00k 1.50k 549 2.2nF 820pF NPO OUT 270pF NPO 499 Figure 22. Recommended External Analog Filter for MAIN Channels REV. PrA -33- PRELIMINARY TECHNICAL DATA AD1954 APPENDIX Cookbook Formulae for Audio EQ Biquad Coefficients (adapted from Robert Bistro-Johnsons Internet posting) For designing a Parametric EQ, follow the steps below. 1. Given: Frequency Q dB_Gain sample_rate 2. Compute Intermediate Variables A = 10^(dB_Gain/40) omega = 2 x x Frequency/Sample_Rate sn = sin(omega) cs = cos(omega) alpha = sn/(2 x Q) 3. Compute Coefficients b0 = (1 + A x alpha)/(1 + (alpha/A)) b1 = -2 x cs/(1 + (alpha/A)) b2 = (1 - (alpha/A))/(1 + (alpha/A)) a1 = 2 x cs/(1 + (alpha/A)) = -b1 a2 = -(1 - (alpha/A))/(1 + (alpha/A)) 4. The transfer function implemented by the AD1954 is given by: H(Z) = (b0 + b1 x Z-1 + b2 x Z-2)/(1 - a1 x Z-1 - a2 x Z -2) Note the inversion in sign of a1 and a2 relative to the more standard form. This form is used in this document because the AD1954 implements the difference equation using the formula below. Y(n) = a1 x y(n-1) + a2 x y(n-2) + b0 x x(n) + b1 x x(n-1) + b2 x x(n-2) -34- REV. PrA PRELIMINARY TECHNICAL DATA AD1954 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 44-Lead Metric Quad Flat Package (MQFP) 0.530 (13.46) SQ 0.510 (12.95) 0.398 (10.11) SQ 0.390 (9.91) 8 0.8 33 34 23 22 0.096 (2.44) MAX 0.037 (0.94) 0.025 (0.64) SEATING PLANE TOP VIEW (PINS DOWN) 44 12 1 11 0.040 (1.02) 0.032 (0.81) 0.083 (2.11) 0.077 (1.96) 0.040 (1.02) 0.032 (0.81) 0.033 (0.84) 0.029 (0.74) 0.016 (0.41) 0.012 (0.30) NOTE 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. INCH DIMENSIONS ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 48-Lead Thin-Profile Quad Flat Package (LQFP) 0.063 (1.60) MAX 0.030 (0.75) 0.024 (0.60) 0.018 (0.45) 0.354 (9.00) BSC SQ 36 37 25 24 0.039 (1.00) REF SEATING PLANE TOP VIEW (PINS DOWN) VIEW A 48 1 12 13 0.276 (7.00) BSC SQ 0.019 (0.50) 0.011 (0.27) BSC 0.009 (0.22) 0.007 (0.17) 0.057 (1.45) 0.055 (1.40) 0.053 (1.35) 0.008 (0.20) 0.004 (0.09) 7 3.5 0 0.006 (0.15) 0.002 (0.05) VIEW A 0.003 (0.08) MAX ROTATED 90 CCW NOTES 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS. REV. PrA -35- PRELIMINARY TECHNICAL DATA AD1954 -36- REV. PrA PRINTED IN U.S.A. C02760-0-1/02(PrA) |
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