View 4196_967767.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ST486DX2V
66 and 80 MHz clock doubled 486 CPU
PRELIMINARY DATA
IMPROVED 486DX2 PERFORMANCE - Clock doubled core speeds up to 80 MHz - Integrated FPU 10% faster than 80486DX2 - Up to 40 MHz bus speeds for fast local bus systems
INDUSTRY STANDARD 486 COMPATIBILITY - 486DX socket and instruction set compatible - Runs DOS, Windows, OS/2, UNIX - Standard 168-pin PGA - 208-pin QFP The SGS-THOMSON ST486DX2V 3.45 volt CPUs are advanced 486DX/DX2/DX4 compatible processors. These CPUs incorporate an on-chip 8KByte write-back cache and an integrated math coprocessor. The on-chip write-back cache allows up to 15% higher performance by eliminating unnecessary external write cycles. On traditional write-through CPUs, these external write cycles can create bus bottlenecks affecting system wide performance. The integrated floating point unit, improves performance up to 10% over the 80486DX2 at equal internal frequency as measured using Power Meter Whetstone test. BLOCK DIAGRAM
16-byte Instruction Queue Immediate Microcode ROM Control Limit Unit Immediate
ON-CHIP 8-KBYTE WRITE-BACK CACHE - Industry-wide write-back chipset support - Burst-mode write capability - Configurable as write-back or write-through ADVANCED POWER MANAGEMENT - Fast SMI interrupt with separate memory space - Fully static design permits dynamic clock control - Software or hardware initiated low power suspend
- Automatic FPU power-down mode These processors are designed to meet the power management requirements in the newest generation of low-power desktops and notebooks. Power is saved by taking advantage of advanced power management features such as static circuitry, SMM, and automatic FPU power-down. Fast entry and exit of SMM allows frequent use of the SMM feature without noticeable performance degradation. This CPU family maintains compatibility with the installed base of x86 software and provides essential socket compatibility with the 486DX/DX2/DX4.
Decoder Control Sequencer ROM Address
Core Clock Prefetch Data Bus 32 Bus Clock
SMM, Suspend Mode and Clock Control
SUSP# SUSPA# CLK SMI# SMADS#
Branch Control
Execution Pipeline
Execution Unit 3-Input Multiplier Shift Register Adder File Unit Unit Unit Linear Address Bus
Memory Data Bus
Byte Muxes & I/O Regs
8 Write Buffers Data Buffers
D31-D0 32
Cache and Memory Management
Memory Management Unit
Prefetch Unit
8 KByte Instr/Data Cache
FPU Control
Bus Control
Control
Instruction Address Bus Data Address Bus
Address Buffers
A31-A2 BE3#-BE0#
486DX Compatible Bus Interface
1738600
October 1995
This is preliminary information on a new product undergoing evaluation. Details are subject to change without notice.
1/18
ST486DX2V
1.0 PRODUCT OVERVIEW The SGS THOMSON ST486DXTM 3.45 volt microprocessors are advanced 486DX2 microprocessors. The ST486DX2V CPU operates at twice the external bus speed. The CPUs in the ST486DX2 family are high speed 3.45 volt CPUs attaining clock-doubled core speeds of up to 80 MHz. The ST486DX2V 8-KByte cache can be configured to run in traditional write-through mode or in the higher performance write-back mode. Write-back mode eliminates unnecessary external memory write cycles offering up to 15% higher overall performance (80 MHz, PC Bench 9.0) than writethrough mode. The ST486DX2V supports 8, 16 and 32-bit data types and operates in real, virtual 8086 and protected modes. The CPU can access up to 4 GBytes of physical memory using a 32-bit burst mode bus. Floating point instructions are parallel processed using an on-chip math coprocessor. The ST486DX2V CPUs are ideal design solutions for low-powered "Green PC" desktops as well as portable computers. These microprocessors typically draw only 450 A, while the input clock is stopped in suspend mode, due to their static design. System Management Mode (SMM) allows the implementation of transparent system power management or the software emulation of I/O peripheral devices. A list of ST486DX2 3.45 volt parts, including their operating frequency, and package types are listed on page 23 of this document. 1.1 Clock-Doubled CPU Core The clock-doubled ST486DX2 CPU core operates at two times the frequency of the external clock input, while continuing to operate the bus interface at the external clock frequency. This configuration provides high frequency CPU performance without requiring a high speed interface to external memory. The ST486DX2V provides up to 2 times the performance of a 486DX at the same external clock frequency. This level of performance is achieved by doubling the frequency of the input clock and using the resulting signal to drive the CPU core. To further enhance this architecture, the ST486DX2V reduces the performance penalty of slow external memory accesses through use of an on-chip writeback cache and eight write buffers.
The CPU core consists of a five-stage pipeline optimized for minimal instruction cycle times and includes all necessary hardware interlocks to permit successive instruction execution overlap. The execution stage of the pipeline executes simple but frequently used instructions in a single clock cycle and the hardware multiplier executes 16-bit integer multiplications in only three clocks. 1.2 On-Chip Write-Back Cache The ST486DX2V on-chip cache can be configured to run in traditional write-through mode or in a higher performance write-back mode. The writeback cache mode was specifically designed to optimize performance of the CPU core by eliminating bus bottlenecks caused by unnecessary external write cycles. This write-back architecture is especially effective in improving performance of the clock-doubled ST486DX2V CPU. Traditional write-through cache architectures require that all writes to the cache also update external memory simultaneously. These unnecessary write cycles create bottlenecks which result in CPU stalls and adversely impact performance. In contrast, a write-back architecture allows data to be written to the cache without updating external memory. With a write-back cache, external write cycles are only required when a cache miss occurs, a modified line is replaced in the cache, or when an external bus master requires access to data. The ST486DX2V cache is an 8-KByte unified instruction and data cache implemented using a four-way set associative architecture and a least recently used (LRU) replacement algorithm. The cache is designed for optimum performance in write-back mode, however, the cache can be operated in write-through mode. The cache line size is 16 bytes and new lines are only allocated during memory read cycles. Valid status is maintained on a 16-byte cache line basis, but modified or "dirty" status for write-back mode is maintained on a 4-byte (double-word) basis. Therefore, only the double-words that have been modified are written back to external memory when a line is replaced in the cache. The CPU core can access the cache in a single internal clock cycle for both reads and writes. 1.3 FPU Operations Since the FPU is resident within the CPU, the overhead associated with external math coprocessor cycles is eliminated. If the FPU is not in use, the FPU is automatically powered down. This feature reduces overall power consumption.
2/18
ST486DX2V
1.4 System Management Mode System Management Mode (SMM) provides an additional interrupt and a separate address space that can be used for system power management or software transparent emulation of I/O peripherals. SMM is entered using the System Management Interrupt (SMI#) or SMINT instruction. While running in isolated SMM address space, the SMI interrupt routine can execute without interfering with the operating system or application programs. After entering SMM, portions of the CPU state are automatically saved. Program execution begins at the base of SMM address space. The location and size of the SMM memory are programmable within the ST486DX2V. Eight SMM instructions have been added to the 486 instruction set that permit software entry into SMM, as well as saving and restoring the total CPU state when in SMM mode.
ST486DX2V Input & Output Signals.
A31-A2 A20M# AHOLD BOFF# BRDY# BS16#, BS8# CLK EADS# FLUSH# IGNNE# INTR INVAL HOLD KEN# NMI RDY# RESET SMI# SUSP# UP# WM_RST CLKMUL 5 7 4 3 1 1 1 4 3 6 1 - Cache Interface 2 - Coprocessor Interface 3 - Power Management 4 - System Management Mode 5 - Reset Input 6 - VCC Control 7 - Clock Multiplier 1 1 1 1 1 2 2 1 1 ADS# BE3#-BE0# BLAST# BREQ
ST486DX2V CPU
D31-D0 D/C# DP3-DP0 FERR# HITM# HLDA LOCK# M/IO# PCD PCHK# PLOCK# PWT RPLSET(1-0) RPLVAL# SMADS# SUSPA# W/R# VOLDET
1.5 Power Management The ST486DX2V power management features allow for a dramatic improvement in battery life over systems designed with non-static 486 processors. During suspend mode the typical current consumption is less than 1 percent of the full operation current. Suspend mode is entered by either a hardware or a software initiated action. Using the hardware method to initiate suspend mode involves a twopin handshake between the SUSP# and SUSPA# signals. The software can initiate suspend mode through the execution of the HALT instruction. Once in suspend mode, the ST486DX2 power consumption is further reduced by stopping the external clock input. The resulting current draw is typically 450 A. Since the ST486DX2V is static, no internal data is lost when the clock is stopped. 1.6 Signal Summary The ST486DX2V signal set includes ten cache interface signals, two coprocessor interface signals, two power management signals, two system management mode signals, one power supply voltage control signal and one clock multiplier control signal. 1.7 VOLDET The Voldet output signal is used by the system to detect that a low voltage part is in the CPU socket. It is permanently set to a logic 0 level for the low voltage part. 1.8 CLKMUL The CLKMUL input signal must be connect to VSS for proper operation. CLKMUL has an internal pullup. If left unconnected, it will be driven to a logic 1. 1.9 Programable SMM Pin Interface Following power-up or RESET, the ST486DX2V SMM interface pins are disabled. Once enabled, these two pins can either function as defined in the ST 4 8 6D X/ D X2 Da ta bo ok(Or der C od e: DBST486DXST/1) (SMI# and SMADS#) or can be programmed to function with a protocol compatible wit h the 486 SL-enhanced CPUs (SMI#, SMIACT#).
1738001
3/18
ST486DX2V
1.10 SMM Mode Control Bit Configuration register CCR3 bit 3 (SMM_Mode) controls the SMM interface mode. 0=ST mode, 1=SL-compatible mode, and the default state after reset is 0. If the SMI_Lock bit =0, the SMM_Mode may be modified. If the SMI_Lock bit is set, the SMM_Mode bit can no longer be modified. Once the SMI_lock bit is set, the CPU must be reset(RESET pin) in order to modify SMI_Lock and SMM_Mode. 1.11 SMM Pin Definitions The two pins that change function in SL-compatible mode are SMI# and SMADS#. Table 1.1 lists the pin definitions for these two pins. 1.12 SMM Features Not Used in SL-Compatible Mode The SMAC and MMAC functions controlled in Configuration Control Register 1 (CCR1) are disabled when in SL-compatible mode. If the SMI service routine accesses memory outside the defined SMM memory space, SMIACT# remains asserted. Also the SMINT instruction should not be used in SL-compatible mode.
Table 1.1. SMM Pin Definitions
ST MODE SMI#: Bidirectional System management Interrupt pin. Asserted by the system logic to request an SMI interrupt. Sampled by the CPU on each rising clock edge. Causes I/O trap to occur if sampled asserted at least two clocks prior to RDY# sampled asserted for an I/O cycle. Asserted by the CPU during execution of an SMI service routine or in response to SMINT if SMAC is set. SMADS#: SMI Address Strobe output used to indicate that SMIACT#: SMI Active output asserted by the CPU during the current bus cycle is an SMM memory access. execution of an SMI service routine. SL-COMPATIBLE MODE SMI#: System Management Interrupt input pin. Asserted by the system logic to request an SMI interrupt. Sampled by the CPU on each rising clock edge. SMI# is falling edge sensitive and causes an I/O trap to occur if sampled asserted at least three clocks prior to RDY#/BRDY# sampled for any I/O cycle.
4/18
ST486DX2V
2.0 ELECTRICAL SPECIFICATIONS Electrical specifications in this chapter are valid for the clock-doubled ST486DX2V, and the clock-tripled ST486DX4V. The ST486DX4 differs from the ST486DX2 in that the ST486DX4 internal CPU core operates at three times the frequency of the bus interface . 2.1 Electrical Connections 2.1.1 Power and Ground Connections and Decoupling Due to the high frequency of operation of the ST486DX2V, it is necessary to install and test this device using standard high frequency techniques. Th e h ig h clock f re qu enci es use d i n t he ST486DX2V and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VCC and GND pins. 2.1.2 Pull-Up/Pull-Down Resistors Table 2-1 lists the input pins which are internally connected to pull-up and pull-down resistors. The pull-up resistors are connected to VCC and the pull-down resistors are connected to VSS. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted. It is recommended that the ADS#, LOCK# and SMI# output pins be connected to pull-up resistors, as indicated in Table 2-2. The external pull-ups guarantee that the signals remain negated during hold acknowledge states.
2.2 Absolute Maximum Ratings
The following table lists absolute maximum ratings for the ST486DX2V microprocessors. Stresses beyond those listed under Table 2-3 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" Table 2-4 (Page 9) is possible. Exposure to conditions beyond Table 2-3 may (1) reduce device reliability and (2) result in premature failure even when there is no immediately apparent sign of failure. Prolonged exposure to conditions at or near the absolute maximum ratings (Table 2-3) may also result in reduced useful life and reliability. Table 2-1. Pins Connected to Internal Pull-Up and Pull-Down Resistors
SIGNAL A20M# AHOLD BOFF# BS16# BS8# BRDY# EADS# FLUSH# IGNNE# INVAL KEN# RDY# UP# SUSP# WM_RST RESISTOR 20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-up 20-k pull-down
2.1.3 Unused Input Pins
All inputs not used by the system designer and not listed in Table 2-1 (Page 7) should be connected either to ground or to VCC. Connect active-high inputs to ground through a 20 k (10%) pull-down resistor and active-low
Table 2-2. Pins Requiring External Pull-Up Resistors
SIGNAL ADS# LOCK# SMI# EXTERNAL RESISTOR 20-k pull-up 20-k pull-up 20-k pull-up
inputs to VCC through a 20 k (10%) pull-up resistor to prevent possible spurious operation.
Table 2-3. Absolute Maximum Ratings
PARAMETER Case Temperature Storage Temperature Supply Voltage, VCC Voltage On Any Pin Input Clamp Current, IIK Output Clamp Current, IOK ST486DX2V
MIN -65 -65 -0.5 -0.5
MAX +110 +150 4.6 6.0 10 25
UNITS
NOTES Power Applied No Bias With Respect to VSS With Respect to VSS Power Applied Power Applied
C C V V mA mA
5/18
ST486DX2V
2.3 Recommended Operating Conditions Table 2-4 presents the recommended operating conditions for the ST486DX2V device. Table 2-4. Recommended Operating Conditions PARAMETER ST486DX2V
MIN MAX
UNITS
NOTES
TC Case Temperature VCC Supply Voltage VIH High Level Input VIL Low Level Input IOH Output Current (High) IOL Output Current (Low)
0 3.3 2 -0.3
+85 3.6 5.5 0.8 -1 3
C V V
V
Power Applied With Respect to Vss
mA mA
VOH=VOH(MIN) VOL=VOL(MAX)
2.4 DC Characteristics
Table 2-5. DC Characteristics (at Recommended Operating Conditions)
PARAMETER VOL Output Low Voltage IOL = 5 mA VOH Output High Voltage IOH = -1 mA ILI Input Leakage Current For all pins except those listed in Table 2-1. IIH Input Leakage Current For all pins with internal pull-downs. IIL Input Leakage Current For all pins with internal pull-ups ICC Active ICC 2.4 15 ST486DX2V MIN MAX 0.35 UNITS V V A A A 0200 -400 Typical: 560 630 Typical: 14 16 Typical: 0.45 850 950
66 MHz 80 MHz
ICCSM Suspend Mode ICC
mA
66 MHz 80 MHz
ICCSS Standby ICC 0 MHz (Suspended/CLK Stopped) CIN Input Capacitance COUT Output or I/O Capacitance CCLK CLK Capacitance
Notes:
30 34
mA
Note 1, 3
1.1 20 20 20
mA pF pF pF
Note 4 fc = 1 MHz (Note 2) fc = 1 MHz (Note 2) fc = 1 MHz (Note 2)
1. MHz ratings refer to internal clock frequency. 2. Not 100% tested. 3. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static except clock and all outputs unloaded (static IOUT = 0 mA). Specification also valid for UP# = 0. 4. All inputs at 0.4 or VCC - 0.4 (CMOS levels). All inputs held static and all outputs unloaded (static IOUT = 0 mA).
6/18
ST486DX2V
2.5 AC Characteristics Tables 2-6 through 2-9 list the AC characteristics including output delays, input setup requirements, input hold requirements and output float delays. These measurements are based on the measurement points identified in Figure 2-1 and Figure 2-2. The rising clock edge reference level VREF, and other reference levels are shown in Table 2-6 below for the ST486DX2V. Input or output signals must cross these levels during testing. Figure 2-1 shows output delay (A and B) and input setup and hold times (C and D). Input setup and hold times (C and D) are specified minimums, defining the smallest acceptable sampling window a synchronous input signal must be stable for correct operation.
Table 2-6. Drive Level and Measurement Points for Switching Characteristics
SYMBOL VREF VIHD VILD Note: Refer to Figure 2-1. ST486DX2V 1.5 2.3 0 UNITS V V V
Figure 2-1. Drive Level and Measurement Points for Switching Characteristics
Tx V IHD
CLK:
V ILD
V REF
V REF
A B
OUTPUTS:
Valid V Output n REF
MAX Valid Output n+1
MIN
V REF
V IHD INPUTS: V ILD
A - Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - Minimum Input Hold Specification
C
Valid V REF Input
D
V REF
LEGEND:
1709403
7/18
ST486DX2V
Figure 2-2. CLK Timing Measurement Points
T1 T2 V IH(MIN) V REF V IL(MAX)
CLK
T5
T3
T4
1730400
8/18
ST486DX2V
Table 2-7 AC Characteristics for ST486DX2V66 Vcc - 3.0 to 3.6V, Tcase=0 to 85 C, CL=50pF External CLK = 33 MHz (Max.)
SYMBOL T1 T2 T3 T4 T5 T6 T6a T7 T7a T8 T8a T8b T9 T9a T10 T11 T12 T12a T13 T13a T14 T15 T16 T17 T18 T18a T19 T20 T20a T21 T21a T22 T23 PARAMETERS CLK Period CLK High Time CLK Low Time CLK Fall Time CLK Rise Time A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, FERR#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Valid Delay SMADS#, SMI# Valid Delay A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Float Delay SMADS#, SMI# Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay HITM#, RPLSET(1-0), RPLVAL#, SUSPA# Valid Delay BLAST#, PLOCK# Float Delay RPLSET(1-0), RPLVAL# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS# Setup Time INVAL Setup Time EADS# Hold Time INVAL Hold Time BS16#, BS8#, KEN# Setup Time BS16#, BS8#, KEN# Hold Time BRDY#, RDY# Setup Time BRDY#, RDY# Hold Time AHOLD, HOLD Setup Time BOFF# Setup Time AHOLD, BOFF#, HOLD Hold Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Setup Time SMI#, SUSP#, WM_RST Setup Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Hold Time SMI#, SUSP#, WM_RST Hold Time A31-A4, D31-D0, DP3-DP0 Read Setup Time A31-A4, D31-D0, DP3-DP0 Read Hold Time MIN (ns) 30 11 11 MAX (ns) FIGURE 2-2 2-2 2-2 2-2 2-2 2-6 2-6 2-7 2-7 2-5 2-6 2-6 2-7 2-7 2-6 2-7 2-3 2-3 2-3 2-3 2-3 2-3 2-4 2-4 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3, 2-4 2-3, 2-4 Note 1 Note 1 Note 1 Note 1 Note 1 NOTES At 2 V VIL(MAX) 2 V to VIL(MAX) VIL(MAX) to 2 V
3 3 3 3 16 16 20 20 22 20 20 20 20 19 20
3 3 3
3 6 6 3 3 6 3 6 3 6 9 3 6 6 3 3 6 3
Note 1: Not 100% tested.
9/18
ST486DX2V
Table 2-8. AC Characteristics for ST486DX2V80 Vcc - 3.0 to 3.6V, Tcase=0 to 85 C, CL=50pF External CLK = 40 MHz (Max.)
SYMBOL T1 T2 T3 T4 T5 T6 T6a T7 T7a T8 T8a T8b T9 T9a T10 T11 T12 T12a T13 T13a T14 T15 T16 T17 T18 T18a T19 T20 T20a T21 T21a T22 T23 PARAMETERS CLK Period CLK High Time CLK Low Time CLK Fall Time CLK Rise Time A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, FERR#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Valid Delay SMADS#, SMI# Valid Delay A31-A2, ADS#, BE3#-BE0#, BREQ, D/C#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# Float Delay SMADS#, SMI# Float Delay PCHK# Valid Delay BLAST#, PLOCK# Valid Delay HITM#, RPLSET(1-0), RPLVAL#, SUSPA# Valid Delay BLAST#, PLOCK# Float Delay RPLSET(1-0), RPLVAL# Float Delay D31-D0, DP3-DP0 Write Data Valid Delay D31-D0, DP3-DP0 Write Data Float Delay EADS# Setup Time INVAL Setup Time EADS# Hold Time INVAL Hold Time BS16#, BS8#, KEN# Setup Time BS16#, BS8#, KEN# Hold Time BRDY#, RDY# Setup Time BRDY#, RDY# Hold Time AHOLD, HOLD Setup Time BOFF# Setup Time AHOLD, BOFF#, HOLD Hold Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Setup Time SMI#, SUSP#, WM_RST Setup Time A20M#, FLUSH#, IGNNE#, INTR, NMI, RESET Hold Time SMI#, SUSP#, WM_RST Hold Time A31-A4, D31-D0, DP3-DP0 Read Setup Time A31-A4, D31-D0, DP3-DP0 Read Hold Time MIN (ns) 25 9 9 MAX (ns) FIGURE 2-2 2-2 2-2 2-2 2-2 2-6 2-6 2-7 2-7 2-5 2-6 2-6 2-7 2-7 2-6 2-7 2-3 2-3 2-3 2-3 2-3 2-3 2-4 2-4 2-3 2-3 2-3 2-3 2-3 2-3 2-3 2-3,2-4 2-3,2-4 Note 1 Note 1 Note 1 Note 1 Note 1 NOTES At 2 V VIL(MAX) 2 V to VIL(MAX) VIL(MAX) to 2 V
3 3 3 3 14 14 19 19 18 16 16 16 16 17 19
3 3 3
3 6 6 3 3 6 3 6 3 6 8 3 6 6 3 3 6 3
Note 1: Not 100% tested.
10/18
ST486DX2V
Figure 2-3 . Input Setup and Hold Timing
Tx CLK Tx Tx Tx
T12 EADS#
T13
T12A INVAL
T13A
T14 BS8#, BS16#, KEN# T18 AHOLD, HOLD T18A BOFF# T20 A20M#, FLUSH#, INTR, NMI, RESET T20A SMI#, SUSP#, WM_RST
T15
T19
T19
T21
T21A
A31-A4 (CACHE INQUIRY CYCLE)
T22
T23
1724401
11/18
ST486DX2V
Figure 2-4 Input Setup and Hold Timing
T2
Tx
Tx
Tx
CLK T16 BRDY#, RDY# T22 D31-D0, DP3-DP0 (READ) T23 T17
1719303
Figure 2-5. PCHK# Valid Delay Timing
T2 CLK
Tx
Tx
Tx
BRDY#, RDY#
DP3-DP0
T8 PCHK#
D31-D0,
VALID MIN MAX VALID
1719403
12/18
ST486DX2V
Figure 2-6 Output Valid Delay Timing.
Tx CLK A31-A2, ADS#, BE3-BE0#, BREQ, D/C#, HLDA, LOCK#, M/IO#, PCD, PWT, W/R# SMADS#, SMI#
T6 MIN MAX VALID n+1 MAX VALID n+1 MAX VALID n+1 MAX VALID n+1
Tx
Tx
Tx
VALID n T6A MIN
VALID n T8A MIN
BLAST#, PLOCK#
VALID n T8B MIN
HITM#, RPLSET(1-0), RPLVAL#, SUSPA# D31-D0, DP3-DP0 (WRITE)
VALID n
T10
MIN
MAX VALID n+1
1724500
VALID n
Figure 2-7. Output Valid Delay Timing
Tx CLK A31-A2, ADS#, BE3-BE0#, BREQ, D/C#, PWT, PCD, HLDA, LOCK#, M/IO#, W/R#
T7 VALID T7A VALID T9 MIN MAX MIN MAX MIN MAX
Tx
Tx
Tx
SMADS#, SMI#
BLAST#, PLOCK#
VALID T9A MIN MAX
RPLSET(1-0), RPLVAL#
VALID T11 MIN MAX
D31-D0, DP3-DP0 (WRITE)
VALID
1724600
13/18
ST486DX2V
3.0 MECHANICAL SPECIFICATIONS 3.1 168-Pin PGA Package The pin assignments for the ST486DX2V 168-pin PGA package are shown in Figure 3-1. The pins are listed by signal name and pin number in Table 3-1. Figure 3-1. 168-Pin PGA Package Pin Assignments
S
A27
R
A28 A25 Vcc Vss A18 Vcc A15 Vcc Vcc Vcc Vcc A11 A8 Vcc A3
Q
A31 Vss A17 A19 A21 A24 A22 A20 A16 A13 A9 A5 A7 A2
P
D0 A29 A30
N
D2 D1 DP0
M
Vss Vcc D4
L
Vss D6 D7
K
Vss Vcc D14
J
NC D5 D16
H
Vss D3 DP2
G
Vss Vcc D12
F
DP1 D8 D15
E
Vss Vcc D10
D
D9 D13 D17
C
D11 D18 CLK Vcc Vcc
B
D19 D21 Vss Vss Vss D25 Vcc D31 Vcc
A
D20
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
A4 BLAST# PLOCK# Vcc ADS# CLKMUL PCHK# Vss M/IO# W/R# Vcc Vss Vcc Vss Vcc Vss BE1# PCD Vcc Vss Vcc Vss RDY# BE3# Vcc Vss BS8# RESET TDO INTR Vss Vss A10 Vss A6 A26 A23 VOLDET A14 Vss A12 Vss Vss Vss D22 TCK D23 DP3 D24 Vss D29 Vss
1 2 3 4 5 6 7 8 9
WM_RST SMI# UP# Vcc INVAL Vss HITM#
ST486 3.45Volt STANDARD PINOUT 168-Pin PGA (Top View)
D27 D26 D28 D30
10 11 12 13 14 15 16 17
SMADS# RPLSET1
TEST RPLVAL# SUSPA# FERR# RPLSET0 PWT BE0# BE2# BRDY# SUSP# KEN# HOLD A20M# FLUSH# NMI TDI IGNNE#
BREQ HLDA LOCK# D/C#
BOFF# BS16# EADS# AHOLD
S
R
Q
P
N
M
L
K
J
H
G
F
E
D
C
B
A
1738301
14/18
ST486DX2V
Table 3 - 1. ST486DX2V 168-Pin PGA Package Signal Names Sorted by Pin Number
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 Signal Name D20 D22 TCK D23 DP3 D24 VSS D29 VSS INVAL VSS HITM# SUSPA# TDI IGNNE# INTR AHOLD D19 D21 VSS VSS VSS D25 VCC D31 VCC SMI# VCC Pin No. B12 B13 B14 B15 B16 B17 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 D1 D2 D3 D15 D16 Signal Name RPLSET1 RPLVAL# RPLSET0 NMI TD0 EADS# D11 D18 CLK VCC VCC D27 D26 D28 D30 WM_RST UP# SMADS# TEST FERR# FLUSH# RESET BS16# D9 D13 D17 A20M# BS8# Pin No. D17 E1 E2 E3 E15 E16 E17 F1 F2 F3 F15 F16 F17 G1 G2 G3 Signal Name BOFF# VSS VCC D10 HOLD VCC VSS DP1 D8 D15 KEN# RDY# BE3# VSS VCC D12 Pin No. J15 J16 J17 K1 K2 K3 K15 K16 K17 L1 L2 L3 L15 L16 L17 M1 M2 M3 Signal Name BE2# BE1# PCD VSS VCC D14 BE0# VCC VSS VSS D6 D7 PWT VCC VSS VSS VCC D4 Pin No. P2 P3 P15 P16 P17 Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Signal Name A29 A30 HLDA VCC VSS A31 VSS A17 A19 A21 A24 A22 A20 A16 Pin No. R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 Signal Name A15 VCC VCC VCC VCC A11 A8 VCC A3 BLAST# CLKMUL A27 A26 A23 VOLDET A14 VSS A12 VSS VSS VSS VSS VSS A10 VSS A6 A4 ADS#
Q10 A13 Q11 A9
G15 SUSP# G16 VCC G17 VSS H1 H2 H3 H15 H16 H17 J1 J2 J3 VSS D3 DP2 BRDY# VCC VSS NC D5 D16
Q12 A5 Q13 A7 Q14 A2 Q15 BREQ Q16 PLOCK# Q17 PCHK# R1 R2 R3 R4 R5 R6 A28 A25 VCC VSS A18 VCC
M15 D/C# M16 VCC M17 VSS N1 N2 N3 N15 N16 N17 P1 D2 D1 DP0 LOCK# M/IO# W/R# D0
15/18
ST486DX2V
3.2 208 Lead QFP(Quad Flat Package) The pin assignments for the ST486DX2V 208 lead QFP package are shown in Figure 3-2. The pins are listed by signal name and pin number in Table 3-2. Figure 3-2. 208-Lead QFP Package Pin Assignments
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
Vss LOCK# PLOCK# Vcc BLAST# ADS# A2 Vss Vcc Vss Vcc A3 A4 A5 UP# A6 A7 Vcc A8 Vss Vcc A9 A10 Vcc Vss Vcc A11 Vss A12 Vcc A13 A14 Vcc Vss A15 A16 Vcc A17 Vss Vcc TDI TMS A18 A19 A20 Vcc Vcc A21 A22 A23 A24 Vss
Vss Vcc Vss Vcc Vss WM_RST SMADS# Vcc Vss Vcc HITM# RPLSET1 SMI# FERR# SUSPA# TDO Vcc RPLVAL# INVAL IGNNE# SUSP# D31 D30 Vss Vcc D29 D28 Vcc Vss Vcc D27 D26 D25 Vcc D24 Vss Vcc DP3 D23 D22 D21 Vss Vcc RPLSET0 Vss Vcc D20 D19 D18 Vcc D17 Vss
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
Vss Vcc NC PCHK# BRDY# BOFF# BS16# BS8# Vcc Vss CLKMUL RDY# KEN# Vcc Vss HOLD AHOLD TCK Vcc Vcc Vss Vcc Vcc CLK Vcc HLDA W/R# Vss Vcc BREQ BE0# BE1# BE2# BE3# Vcc Vss M/IO# Vcc D/C# PWT PCD Vcc Vss Vcc Vcc EADS# A20M# RESET FLUSH# INTR NMI Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
ST486DX2V 208-Lead PQFP (Top View)
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
Vss Vcc A25 A26 A27 A28 Vcc A29 A30 A31 Vss DP0 D0 D1 D2 D3 D4 Vcc Vss Vcc Vcc Vss Vcc Vcc Vss Vcc D5 D6 Vcc TEST D7 DP1 D8 D9 Vss Vcc Vss D10 D11 D12 D13 Vss Vcc D14 D15 Vcc Vss DP2 D16 Vss Vcc Vss
1738401
16/18
ST486DX2V
Table 3-2. ST486DX2V 208 Lead QFP Package Signal Names Sorted by Pin Number
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 Signal Vss Vcc NC PCHK# BRDY# BOFF# BS16# BS8# Vcc Vss CLKMUL RDY# KEN# Vcc Vss HOLD AHOLD TCK Vcc Vcc Vss Vcc Vcc CLK Vcc HLDA W/R# Vss Vcc BREQ BE0# BE1# BE2# BE3# Vcc Pin 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Vss M/IO# Vcc D/C# PWT PCD Vcc Vss Vcc Vcc EADS# A20M# RESET FLUSH# INTR NMI Vss Vss Vcc Vss Vcc Vss WM_RST SMADS# Vcc Vss Vcc HITM# RPLSET1 SMI# FERR# SUSPA# TDO Vcc RPLVAL# Pin 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 Signal INVAL IGNNE# SUSP# D31 D30 Vss Vcc D29 D28 Vcc Vss Vcc D27 D26 D25 Vcc D24 Vss Vcc DP3 D23 D22 D21 Vss Vcc RPLSET0 Vss Vcc D20 Pin Signal Pin 141 D3 142 D2 143 D1 144 D0 145 DP0 146 Vss 147 A31 148 A30 149 A29 150 Vcc 151 A28 152 A27 153 A26 154 A25 155 Vcc 156 Vss 157 Vss 158 A24 159 A23 160 A22 161 A21 162 Vcc 163 Vcc 164 A20 165 A19 166 A18 167 TMS 168 TDI 169 Vcc 170 Vss 171 A17 172 Vcc 173 A16 174 A15 175 Vss Signal Pin Signal
106 Vcc 107 Vss 108 D16 109 DP2 110 111 112 113 114 115 116 117 118 119 Vss Vcc D15 D14 Vcc Vss D13 D12 D11 D10
176 Vcc 177 A14 178 A13 179 Vcc 180 A12 181 Vss 182 A11 183 Vcc 184 Vss 185 Vcc 186 A10 187 A9 188 Vcc 189 Vss 190 A8 191 Vcc 192 A7 193 A6 194 UP# 195 A5 196 A4 197 A3 198 Vcc 199 Vss 200 Vcc 201 Vss 202 A2 203 ADS# 204 BLAST# 205 Vcc 206 PLOCK# 207 LOCK# 208 Vss
120 Vss 121 Vcc 122 Vss 123 D9 124 D8 125 DP1 126 D7 127 TEST 128 Vcc 129 D6 130 D5 131 Vcc 132 Vss 133 Vcc 134 Vcc 135 Vss 136 Vcc 137 Vcc 138 Vss 139 Vcc 140 D4
100 D19 101 D18 102 Vcc 103 D17 104 Vss 105 Vss
17/18
ST486DX2V
Ordering Information.*
ST SGS-THOMSON Prefix Device Name 486DX Clock ratio 4 = Clock Tripled 2 = Clock Doubled Voltage Dash = 5 volts V= 3.45 volts Speed (internal clock frequency) 66 = 66 MHz 75 = 75 MHz 80 = 80 MHz 10 = 100 MHz 12 = 120 MHz Package Type H = PGA Package L = PQFP Package P = PPGA Package Temperature Range S = 0 to 85o C Case Temp
486DX
4
V
12 H S
1724301
* Please contact your nearest SGS-THOMSON sales office to confirm availability of specific valid combinations and to check on newly released combinations.
SGS-THOMSON is a registered trademark of SGS-THOMSON Microelectronics. ST486DX, ST486DX2, and ST486DX4 are trademarks of SGS-THOMSON Microelectronics. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1995 SGS-THOMSON Microelectronics. All rights reserved. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Korea - Malaysia - Malta - Marocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - United Kingdom - U.S.A.
18/18

▲Up To Search▲

Price & Availability of 4196

	To Download 4196 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .