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M48T59 M48T59Y
64 Kbit (8Kb x8) TIMEKEEPER(R) SRAM
INTEGRATED ULTRA LOW POWER SRAM, REAL TIME CLOCK, POWER-FAIL CONTROL CIRCUIT and BATTERY FREQUENCY TEST OUTPUT for REAL TIME CLOCK AUTOMATIC POWER-FAIL CHIP DESELECT and WRITE PROTECTION WRITE PROTECT VOLTAGES (VPFD = Power-fail Deselect Voltage): - M48T59: 4.5V VPFD 4.75V - M48T59Y: 4.2V VPFD 4.5V SELF-CONTAINED BATTERY and CRYSTAL in the CAPHAT DIP PACKAGE PACKAGING INCLUDES a 28-LEAD SOIC and SNAPHAT(R) TOP (to be Ordered Separately) SOIC PACKAGE PROVIDES DIRECT CONNECTION for a SNAPHAT TOP which CONTAINS the BATTERY and CRYSTAL MICROPROCESSOR POWER-ON RESET (Valid even during battery back-up mode) PROGRAMMABLE ALARM OUTPUT ACTIVE in the BATTERY BACK-UP MODE DESCRIPTION The M48T59/59Y TIMEKEEPER(R) RAM is an 8Kb x8 non-volatile static RAM and real time clock. The monolithic chip is available in two special packages to provide a highly integrated battery backed-up memory and real time clock solution. Table 1. Signal Names
A0-A12 DQ0-DQ7 IRQ/FT RST E G W VCC VSS July 1999 Address Inputs Data Inputs / Outputs Interrupt / Frequency Test Output (Open Drain) Power Fail Reset Output (Open Drain) Chip Enable Output Enable Write Enable Supply Voltage Ground 1/20
SNAPHAT (SH) Battery/Crystal
28
28 1
1
SOH28 (MH)
PCDIP28 (PC) Battery/Crystal CAPHAT
Figure 1. Logic Diagram
VCC
13 A0-A12
8 DQ0-DQ7
W E G
M48T59 M48T59Y IRQ/FT RST
VSS
AI01380C
M48T59, M48T59Y
Figure 2A. DIP Pin Connections
RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 28 1 27 2 26 3 25 4 24 5 23 6 7 M48T59 22 8 M48T59Y 21 20 9 19 10 18 11 17 12 13 16 14 15
AI01381C
Figure 2B. SOIC Pin Connections
VCC W IRQ/FT A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 RST A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 27 2 26 3 25 4 24 5 23 6 22 7 M48T59Y 21 8 20 9 19 10 18 11 17 12 16 13 15 14
AI01382C
VCC W IRQ/FT A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
Table 2. Absolute Maximum Ratings (1)
Symbol TA TSTG TSLD
(2)
Parameter Ambient Operating Temperature Storage Temperature (VCC Off, Oscillator Off) Lead Solder Temperature for 10 seconds Input or Output Voltages Supply Voltage Output Current Power Dissipation Grade 1 Grade 6
Value 0 to 70 -40 to 85 -40 to 85 260 -0.3 to 7 -0.3 to 7 20 1
Unit C C C V V mA W
VIO VCC IO PD
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect reliability. 2. Soldering temperature not to exceed 260C for 10 seconds (total thermal budget not to exceed 150C for longer than 30 seconds).
CAUTION: Negative undershoots below -0.3 volts are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode Deselect Write Read Read Deselect Deselect VSO to VPFD (min) VSO
(2)
VCC 4.75V to 5.5V or 4.5V to 5.5V
E VIH VIL VIL VIL X X
G X X VIL VIH X X
W X VIL VIH VIH X X
DQ0-DQ7 High Z DIN DOUT High Z High Z High Z
Power Standby Active Active Active CMOS Standby Battery Back-up Mode
Notes: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. 2. See Table 7 for details.
2/20
M48T59, M48T59Y
Figure 3. Block Diagram
IRQ/FT
OSCILLATOR AND CLOCK CHAIN 32,768 Hz CRYSTAL POWER
16 x 8 BiPORT SRAM ARRAY
A0-A12
8176 x 8 SRAM ARRAY LITHIUM CELL VOLTAGE SENSE AND SWITCHING CIRCUITRY VPFD
DQ0-DQ7
E W G
VCC
RST
VSS
AI01383D
The M48T59/59Y is a non-volatile pin and function equivalent to any JEDEC standard 8Kb x8 SRAM. It also easily fits into many ROM, EPROM, and EEPROM sockets, providing the non-volatility of PROMs without any requirement for special write timing or limitations on the number of writes that can be performed. The 28 pin 600mil DIP CAPHATTM houses the M48T59/59Y silicon with a quartz crystal and a long life lithium button cell in a single package. The 28 pin 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to prevent reverse insertion. The SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28 lead SOIC, the battery/crystal package (i.e. SNAPHAT) part number is "M4T28-BR12SH1".
Table 4. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 5ns 0 to 3V 1.5V
Note that Output Hi-Z is defined as the point where data is no longer driven.
Figure 4. AC Testing Load Circuit
5V
1.9k DEVICE UNDER TEST 1k
OUT
CL = 100pF or 5pF
CL includes JIG capacitance
AI01030
3/20
M48T59, M48T59Y
Table 5. Capacitance (1, 2) (TA = 25 C, f = 1 MHz )
Symbol CIN CIO
(3)
Parameter Input Capacitance Input / Output Capacitance
Test Condition VIN = 0V VOUT = 0V
Min
Max 10 10
Unit pF pF
Notes: 1. Effective capacitance measured with power supply at 5V. 2. Sampled only, not 100% tested. 3. Outputs deselected.
Table 6. DC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol ILI
(1) (1)
Parameter Input Leakage Current Output Leakage Current Supply Current Supply Current (Standby) TTL Supply Current (Standby) CMOS Input Low Voltage Input High Voltage Output Low Voltage
Test Condition 0V VIN VCC 0V VOUT VCC Outputs open E = VIH E = VCC - 0.2V
Min
Max 1 5 50 3 3
Unit A A mA mA mA V V V V V
ILO
ICC ICC1 ICC2 VIL(2) VIH VOL
-0.3 2.2 IOL = 2.1mA IOL = 10mA IOH = -1mA 2.4
0.8 VCC + 0.3 0.4 0.4
Output Low Voltage (IRQ/FT and RST) (3) Output High Voltage
VOH
Notes: 1. Outputs Deselected. 2. Negative spikes of -1V allowed for up to 10ns once per Cycle. 3. The IRQ/FT and RST pins are Open Drain.
Table 7. Power Down/Up Trip Points DC Characteristics (1) (TA = 0 to 70C)
Symbol VPFD VPFD VSO tDR Parameter Power-fail Deselect Voltage (M48T59) Power-fail Deselect Voltage (M48T59Y) Battery Back-up Switchover Voltage Expected Data Retention Time (at 25 C) Grade 1 Grade 6 7 10 (2) Min 4.5 4.2 Typ 4.6 4.35 3.0 Max 4.75 4.5 Unit V V V YEARS
Notes: 1. All voltages referenced to VSS. 2. Using larger M4T32-BR12SH6 SNAPHAT Top (recommended for industrial temperature - grade 6 device).
DESCRIPTION (cont'd) As Figure 3 shows, the static memory array and the q ua rt z co nt rol led clock o sci lla t or of t h e M48T59/59Y are integrated on one silicon chip. The two circuits are interconnected at the upper eight memory locations to provide user accessible BYTEWIDETM clock information in the bytes with
4/20
addresses 1FF8h-1FFFh. The clock locations contain the year, month, date, day, hour, minute, and second in 24 hour BCD format. Corrections for 28, 29 (leap year), 30, and 31 day months are made automatically. Byte 1FF8h is the clock control register. This byte controls user access to the clock information and also stores the clock calibration setting.
M48T59, M48T59Y
Table 8. Power Down/Up Mode AC Characteristics (TA = 0 to 70C)
Symbol tPD tF (1) tFB
(2)
Parameter E or W at VIH before Power Down VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD(min) to VPFD (max) VCC Rise Time VSO to VPFD (min) VCC Rise Time VPFD (max) to RST High
Min 0 300 10 10 1 40
Max
Unit s s s s s
tR tRB tREC
(3)
200
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 s after VCC passes VPFD (min). 2. VPFD (min) to VSO fall time of less than tFB may cause corruption of RAM data. 3. tREC (min) = 20ms for industrial temperature grade 6 device.
Figure 5. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tF tPD tFB tDR tRB tREC RST tR
INPUTS
RECOGNIZED
DON'T CARE
RECOGNIZED
HIGH-Z OUTPUTS VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01384C
5/20
M48T59, M48T59Y
Table 9. Read Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48T59 / M48T59Y Symbol Parameter Min tAVAV tAVQV (1) tELQV (1) tGLQV
(1)
-70 Max
Unit
Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable Low to Output Transition Output Enable Low to Output Transition Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
70 70 70 35 5 5 25 25 10
ns ns ns ns ns ns ns ns ns
tELQX (2) tGLQX
(2)
tEHQZ (2) tGHQZ tAXQX
(2) (1)
Notes: 1. CL = 100pF (see Figure 4). 2. CL = 5pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV A0-A12 tAVQV tELQV E tELQX tGLQV G tGLQX DQ0-DQ7 VALID
AI01385
VALID tAXQX tEHQZ
tGHQZ
Note: Write Enable (W) = High.
6/20
M48T59, M48T59Y
Table 10. Write Mode AC Characteristics (TA = 0 to 70C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48T59 / M48T59Y Symbol Parameter Min tAVAV tAVWL tAVEL tWLWH tELEH tWHAX tEHAX tDVWH tDVEH tWHDX tEHDX tWLQZ (1, 2) tAVWH tAVE1H tWHQX (1, 2) Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Pulse Width Chip Enable Low to Chip Enable High Write Enable High to Address Transition Chip Enable High to Address Transition Input Valid to Write Enable High Input Valid to Chip Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable Low to Output Hi-Z Address Valid to Write Enable High Address Valid to Chip Enable High Write Enable High to Output Transition 60 60 5 70 0 0 50 55 0 0 30 30 5 5 25 -70 Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
Notes: 1. CL = 5pF (see Figure 4). 2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
DESCRIPTION (cont'd) The eight clock bytes are not the actual clock counters themselves; they are memory locations consisting of BiPORTTM read/write memory cells. The M48T59/59Y includes a clock control circuit which updates the clock bytes with current information once per second. The information can be accessed by the user in the same manner as any other location in the static memory array. The M48T59/59Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors the single 5V supply for an out of tolerance condition. When VCC is out of tolerance, the circuit write protects the SRAM, providing a high degree of data security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below approximately 3V, the control circuitry connects the battery which maintains data and clock operation until valid power returns.
READ MODE The M48T59/59Y is in the Read Mode whenever W (Write Enable) is high and E (Chip Enable) is low. The unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access time (tAVQV) after the last address input signal is stable, providing that the E and G access times are also satisfied. If the E and G access times are not met, valid data will be available after the latter of the Chip Enable Access time (tELQV) or Output Enable Access time (tGLQV). The state of the eight three-state Data I/O signals is controlled by E and G. If the outputs are activated before tAVQV, the data lines will be driven to an indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active, output data will remain valid for Output Data Hold time (tAXQX) but will go indeterminate until the next Address Access.
7/20
M48T59, M48T59Y
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVWH tAVEL E tWLWH tAVWL W tWLQZ tWHDX DQ0-DQ7 DATA INPUT tDVWH
AI01386
tWHAX
tWHQX
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV A0-A12 VALID tAVEH tAVEL E tAVWL W tEHDX DQ0-DQ7 DATA INPUT tDVEH
AI01387B
tELEH
tEHAX
8/20
M48T59, M48T59Y
WRITE MODE The M48T59/59Y is in the Write Mode whenever W and E are low. The start of a write is referenced from the latter occurring falling edge of W or E. A write is terminated by the earlier rising edge of W or E. The addresses must be held valid throughout the cycle. E or W must return high for a minimum of tEHAX from Chip Enable or tWHAX from Write Enable prior to the initiation of another read or write cycle. Data-in must be valid tDVWH prior to the end of write and remain valid for tWHDX afterward. G should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on E and G a low on W will disable the outputs tWLQZ after W falls. DATA RETENTION MODE With valid VCC applied, the M48T59/59Y operates as a conventional BYTEWIDE static RAM. Should the supply voltage decay, the RAM will automatically power-fail deselect, write protecting itself when VCC falls within the VPFD(max), VPFD(min) window. All outputs become high impedance, and all inputs are treated as "don't care." Note: A power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the RAM's content. At voltages below VPFD(min), the user can be assured the memory will be in a write protected state, provided the VCC fall time is not less than tF. The M48T59/59Y may respond to transient noise spikes on VCC that reach into the deselect window
Table 11. Register Map
Address D7 1FFFh 1FFEh 1FFDh 1FFCh 1FFBh 1FFAh 1FF9h 1FF8h 1FF7h 1FF6h 1FF5h 1FF4h 1FF3h 1FF2h 1FF1h 1FF0h 0 0 0 0 0 ST W WDS AFE RPT4 RPT3 RPT2 RPT1 Y WDF R BMB4 Y Y Y D6 D5 D4 Data D3 D2 Year 10 M. 10 Date 0 0 0 Month Date Day Hours Minutes Seconds Calibration BMB2 Y BMB1 Y BMB0 Y RB1 Y RB0 Y D1 D0 Function/Range BCD Format Year Month Date Day Hour Minutes Seconds Control Watchdog Interrupts Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Y Z Unused Flags 01-31 00-23 00-59 00-59 00-99 01-12 01-31 01-07 00-23 00-59 00-59
10 Years 0 0 FT 0 0
10 Hours 10 Minutes 10 Seconds S BMB3 ABE
Al. 10 Date Al. 10 Hours
Alarm Date Alarm Hours Alarm Minutes Alarm Seconds Y Z Y Z Y Z
Alarm 10 Minutes Alarm 10 Seconds Y AF Y Z Y BL
Keys: S = SIGN Bit FT = FREQUENCY TEST Bit R = READ Bit W = WRITE Bit ST = STOP Bit 0 = Must be set to '0' Y = '1' or '0' Z = '0' and are Read only
AF = Alarm Flag BL = Battery Low WDS = Watchdog Steering Bit BMB0-BMB4 = Watchdog Multiplier Bits RB0-RB1 = Watchdog Resolution Bits AFE = Alarm Flag Enable ABE = Alarm in Battery Back-up Mode Enable RPT1-RPT4 = Alarm Repeat Mode Bits WDF = Watchdog Flag
9/20
M48T59, M48T59Y
DATA RETENTION MODE (cont'd) during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended. When VCC drops below VSO, the control circuit switches power to the internal battery which preserves data and powers the clock. The internal button cell will maintain data in the M48T59/59Y for an accumulated period of at least 7 years when VCC is less than VSO. As system power returns and VCC rises above VSO, the battery is disconnected, and the power supply is switched to external VCC. Deselect continues for tREC af te r VCC reaches VPFD(max). For more information on Battery Storage Life refer to the Application Note AN1012. POWER-ON RESET The M48T59/59Y continuously monitors VCC. When VCC falls to the power fail detect trip point, the RST pulls low (open drain) and remains low on power-up for 40ms to 200ms after VCC passes VPFD. A 1k resistor is recommended in order to control the rise time. The reset pulse remains active with VCC at VSS. CLOCK OPERATIONS Reading the Clock Updates to the TIMEKEEPER registers should be halted before clock data is read to prevent reading data in transition. Because the BiPORT TIMEKEEPER cells in the RAM array are only data registers, and not the actual clock counters, updating the registers can be halted without disturbing the clock itself. Figure 9. Clock Calibration Updating is halted when a '1' is written to the READ bit, D6 in the Control register (1FF8h). As long as a '1' remains in that position, updating is halted. After a halt is issued, the registers reflect the count; that is, the day, date, and the time that were current at the moment the halt command was issued. All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an update in progress. Updating is within a second after the bit is reset to a '0'. Setting the Clock Bit D7 of the Control register (1FF8h) is the WRITE bit. Setting the WRITE bit to a '1', like the READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with the correct day, date, and time data in 24 hour BCD format (see Table 12). Resetting the WRITE bit to a '0' then transfers the values of all time registers (1FF9h-1FFFh) to the actual TIMEKEEPER counters and allows normal operation to resume. After the WRITE bit is reset, the next clock update will occur within one second. See the Application Note AN923 "TIMEKEEPER rolling into the 21st century" for information on Century Rollover. Stopping and Starting the Oscillator The oscillator may be stopped at any time. If the device is going to spend a significant amount of time on the shelf, the oscillator can be turned off to minimize current drain on the battery. The STOP bit is the MSB of the seconds register. Setting it to a '1' stops the oscillator. The M48T59/59Y is shipped from STMicroelectronics with the STOP bit set to a '1'. When reset to a '0', the M48T59/59Y oscillator starts within one second.
NORMAL
POSITIVE CALIBRATION
NEGATIVE CALIBRATION
AI00594B
10/20
M48T59, M48T59Y
Calibrating the Clock The M48T59/59Y is driven by a quartz controlled oscillator with a nominal frequency of 32,768 Hz. The devices are tested not to exceed 35 ppm (parts per million) oscillator frequency error at 25C, which equates to about 1.53 minutes per month. With the calibration bits properly set, the accuracy of each M48T59/59Y improves to better than 4 ppm at 25C. The oscillation rate of any crystal changes with temperature (see Figure 10). Most clock chips compensate for crystal frequency and temperature shift error with cumbersome trim capacitors. The M48T59/59Y design, however, employs periodic counter correction. The calibration circuit adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as shown in Figure 9. The number of times pulses are blanked (subtracted, negative calibration) or split (added, positive calibration) depends upon the value loaded into the five bit Calibration byte found in the Control Register. Adding counts speeds the clock up, subtracting counts slows the clock down. The Calibration byte occupies the five lower order bits (D4-D0) in the Control register (1FF8h). These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a Sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs within a 64 minute Figure 10. Crystal Accuracy Across Temperature cycle. The first 62 minutes in the cycle may, once per minute, have one second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a binary 6 is loaded, the first 12 will be affected, and so on. Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator cycles; for every 125,829,120 actual oscillator cycles, that is +4.068 or -2.034 ppm of adjustment per calibration step in the calibration register. Assuming that the oscillator is in fact running at exactly 32,768 Hz, each of the 31 increments in the Calibration byte would represent +10.7 or - 5.35 seconds per month which corresponds to a total range of +5.5 or - 2.75 minutes per month. Two methods are available for ascertaining how much calibration a given M48T59/59Y may require. The first involves simply setting the clock, letting it run for a month and comparing it to a known accurate reference (like WWV broadcasts). While that may seem crude, it allows the designer to give the end user the ability to calibrate his clock as his environment may require, even after the final product is packaged in a non-user serviceable enclosure. All the designer has to do is provide a simple utility that accesses the Calibration byte.
Frequency (ppm) 20 0 -20 -40 -60 -80 -100 -120 -140 -160 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 F = -0.038 ppm (T - T )2 10% 0 F C2 T0 = 25 C
Temperature C
AI00999
11/20
M48T59, M48T59Y
DATA RETENTION MODE (cont'd) The second approach is better suited to a manufacturing environment, and involves the use of the IRQFT pin. The pin will toggle at 512Hz when the Stop bit (D7 of 1FF9h) is '0', the FT bit (D6 of 1FFCh) is '1', the AFE bit (D7 of 1FF6h) is '0', and the Watchdog Steering bit (D7 of 1FF7h) is '1' or the Watchdog Register is reset (1FF7h = 0). Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm oscillator frequency error, requiring a -10 (WR001010) to be loaded into the Calibration Byte for correction. Note that setting or changing the Calibration Byte does not affect the Frequency test output frequency. The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper operation. A 500-10k resistor is recommended in order to control the rise time. The FT bit is cleared on power-up. For more information on calibration, see the Application Note AN934 "TIMEKEEPER Calibration". SETTING ALARM CLOCK Registers 1FF5h-1FF2h contain the alarm settings. The alarm can be configured to go off at a prescribed time on a specific day of the month or repeat every day, hour, minute, or second. It can also be programmed to go off while the M48T59 is in the battery back-up mode of operation to serve as a system wake-up call. RPT1-RPT4 put the alarm in the repeat mode of operation. Table 12 shows the possible configurations. Codes not listed in the table default to the once per second mode to quickly alert the user of an incorrect alarm setting. When the clock information matches the alarm clock settings based on the match criteria defined by RPT1-RPT4, AF (Alarm Flag) is set. If AFE (Alarm Flag Enable) is also set, the alarm condition activates the IRQ/FT pin. The alarm flag and the IRQ/FT output are cleared by a read to the Flags register as shown in Figure 11. The IRQ/FT pin can also be activated in the battery back-up mode. The IRQ/FT will go low if an alarm occurs and both ABE (Alarm in Battery Back-up Mode Enable) and AFE are set. The ABE and AFE bits are reset during power-up, therefore an alarm generated during power-up will only set AF. The user can read the Flag Register at system boot-up to determine if an alarm was generated while the M48T59 was in the deselect mode during powerup. Figure 12 illustrates the back-up mode alarm timing. Table 12. Alarm Repeat Mode
RPT4 1 1 1 1 RPT3 1 1 1 0 RPT2 1 1 0 0 RPT1 1 0 0 0 Alarm Activated Once per Second Once per Minute Once per Hour Once per Day
Figure 11. Interrupt Reset Waveforms
15ns Min A0-A12 ADDRESS 1FF0h
ACTIVE FLAG BIT
IRQ/FT HIGH-Z
AI01388B
12/20
M48T59, M48T59Y
WATCHDOG TIMER The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the eight bit Watchdog Register (Address 1FF7h). The five bits (BMB4-BMB0) store a binary multiplier and the two lower order bits (RB1-RB0) select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The amount of time-out is then determined to be the multiplication of the five bit multiplier value with the resolution. (For example: writing 00001110 in the Watchdog Register = 3 x 1 or 3 seconds). If the processor does not reset the timer within the specified period, the M48T59 sets the WDF (Watchdog Flag) and generates a watchdog interrupt or a microprocessor reset. The most significant bit of the Watchdog Register is the Watchdog Steering Bit. When set to a '0', the watchdog will activate the IRQ/FT pin when timedout. When WDS is set to a '1', the watchdog will output a negative pulse on the RST pin for a duration of 40ms to 200ms. The Watchdog register and the FT bit will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1'. Figure 12. Back-up Mode Alarm Waveforms The watchdog timer resets when the microprocessor performs a re-write of the Watchdog Register. The time-out period then starts over. The watchdog timer is disabled by writing a value of 00000000 to the eight bits in the Watchdog Register. The watchdog function is automatically disabled upon power-up and the Watchdog Register is cleared. If the watchdog function is set to output to the IRQ/FT pin and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. BATTERY LOW WARNING The M48T59 checks it's battery voltage on powerup. The BL (Battery Low) bit (D4 of 1FF0h) will be set on power-up if the battery voltage is less than 2.5V (typical). POWER-ON DEFAULTS Upon application of power to the device, the following register bits are set to a '0' state: WDS; BMB0BMB4; RB0-RB1; AFE; ABE; W; R; FT.
VCC VPFD (max) VPFD (min)
AFE
AF
IRQ/FT HIGH-Z HIGH-Z
AI01389B
13/20
M48T59, M48T59Y
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION ICC transients, including those produced by output switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if capacitors are used to store energy, which stabilizes the VCC bus. The energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1F (as shown in Figure 13) is recommended in order to provide the needed filtering. In addition to transients that are caused by normal SRAM operation, power cycling can generate negative voltage spikes on VCC that drive it to values below VSS by as much as one Volt. These negative spikes can cause data corruption in the SRAM while in battery backup mode. To protect from these voltage spikes, it is recommeded to connect a schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS). Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is recommended for surface mount. Figure 13. Supply Voltage Protection
VCC VCC
0.1F
DEVICE
VSS
AI02169
14/20
M48T59, M48T59Y
ORDERING INFORMATION SCHEME
Example:
M48T59Y
-70 MH
1
TR
Supply Voltage and Write Protect Voltage 59 (1) VCC = 4.75V to 5.5V VPFD = 4.5V to 4.75V 59Y VCC = 4.5V to 5.5V VPFD = 4.2V to 4.5V
Speed -70 70ns PC MH
Package PCDIP28
(2)
Temp. Range 1 6
(3)
Shipping Method for SOIC blank Tubes TR Tape & Reel
0 to 70 C -40 to 85 C
SOH28
Notes: 1. The M48T59 part is offered with the PCDIP28 (i.e. CAPHAT) package only. 2. The SOIC package (SOH28) requires the battery/crystal package (SNAPHAT) which is ordered separately under the part number "M4TXX-BR12SH1" in plastic tube or "M4TXX-BR12SH1TR" in Tape & Reel form. 3. Available in SOIC package only. Caution: Do not place the SNAPHAT battery/crystal package "M4TXX-BR12SH1" in conductive foam since this will drain the lithium button-cell battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
15/20
M48T59, M48T59Y
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
Symb Typ A A1 A2 B B1 C D E e1 e3 eA L N mm Min 8.89 0.38 8.38 0.38 1.14 0.20 39.37 17.83 2.29 29.72 15.24 3.05 28 Max 9.65 0.76 8.89 0.53 1.78 0.31 39.88 18.34 2.79 36.32 16.00 3.81 Typ inches Min 0.350 0.015 0.330 0.015 0.045 0.008 1.550 0.702 0.090 1.170 0.600 0.120 28 Max 0.380 0.030 0.350 0.021 0.070 0.012 1.570 0.722 0.110 1.430 0.630 0.150
A2
A
A1 B1 B e3 D
N
L eA
C
e1
E
1 PCDIP
Drawing is not to scale.
16/20
M48T59, M48T59Y
SOH28 - 28 lead Plastic Small Outline, battery SNAPHAT
Symb Typ A A1 A2 B C D E e eB H L a N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 mm Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ inches Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Drawing is not to scale.
17/20
M48T59, M48T59Y
SH - 4-pin SNAPHAT Housing for 49mAh Battery
Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 mm Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 0.018 0.835 0.560 0.612 0.126 0.080 0.265 0.255 Typ inches Min Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 0.628 0.142 0.090
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Drawing is not to scale.
18/20
M48T59, M48T59Y
SH - 4-pin SNAPHAT Housing for 130mAh Battery
Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 mm Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 0.018 0.835 0.680 0.612 0.126 0.080 0.315 0.285 Typ inches Min Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 0.628 0.142 0.090
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Drawing is not to scale.
19/20
M48T59, M48T59Y
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - All Rights Reserved (R) TIMEKEEPER and SNAPHAT are registered trademarks of STMicroelectronics
TM
CAPHAT, BYTEWIDE and BiPORT are trademarks of STMicroelectronics
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20/20

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