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| HM51W4400B Series 1,048,576-word x 4-bit Dynamic Random Access Memory Description The Hitachi HM51W4400B is a CMOS dynamic RAM organized 1,048,576-word x 4-bit. HM51W4400B has realized higher density, higher performance and various functions by employing 0.8 m CMOS process technology and some new CMOS circuit design technologies. The HM51W4400B offers Fast Page Mode as a high speed access mode. Multiplexed address input permits the HM51W4400B to be packaged in standard 300-mil 26-pin plastic SOJ and standard 300-mil 26-pin plastic TSOP II. Features * Single 3.3 V ( 0.3 V) * High speed Access time: 70 ns/80 ns (max) * Low power dissipation Active mode: 252 mW/216 mW (max) Standby mode: 7.2 mW (max) 0.18 mW (max) (L-version) * Fast page mode capability * 1024 refresh cycles : 16 ms : 128 ms (L-version) * 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * Test function * Battery backup operation (L-version) HM51W4400B Series Ordering Information Type No. HM51W4400BS-7 HM51W4400BS-8 HM51W4400BLS-7 HM51W4400BLS-8 HM51W4400BTT-7 HM51W4400BTT-8 HM51W4400BLTT-7 HM51W4400BLTT-8 Access time 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 70 ns 80 ns 300-mil 26-pin plastic TSOP (TTP-26/20D) Package 300-mil 26-pin plastic SOJ (CP-26/20D) 2 HM51W4400B Series Pin Arrangement HM51W4400BS/BLS Series HM51W4400BTT/BLTT Series I/O1 I/O2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 VSS I/O4 I/O3 CAS OE I/O1 I/O2 WE RAS A9 1 2 3 4 5 26 25 24 23 22 V SS I/O4 I/O3 CAS OE A0 A1 A2 A3 VCC 9 10 11 12 13 18 17 16 15 14 A8 A7 A6 A5 A4 A0 9 18 17 16 15 14 A8 A7 A6 A5 A4 A1 10 A2 11 A3 12 VCC 13 (Top view) (Top view) Pin Description Pin name A0 to A9 A0 to A9 I/O1 to I/O4 RAS CAS WE OE VCC VSS Function Address inputs Refresh address inputs Data-in/Data-out Row address strobe Column address strobe Read/Write enable Output enable Power (+3.3 V typ) Ground 3 4 RAS Row Driver Block Diagram RAS Control Circuit Row Driver 256 k Memory Array Mat 256 k Memory Array Mat I/O1 HM51W4400B Series I/O1 Buffer I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat CAS CAS Control Circuit Row Row Driver Driver Row Row Driver Driver 256 k Memory Array Mat Row Address Buffer I/O2 I/O2 Buffer I/O Bus & Column Decoder Row Driver Row Driver I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat WE WE Control Circuit Row Decoder & Peripheral Circuit Address A0-A9 Row Driver Row Driver 256 k Memory Array Mat 256 k Memory Array Mat I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat I/O3 OE I/O3 Buffer OE Control Circuit I/O Bus & Column Decoder 256 k Memory Array Mat Row Row Driver Driver Row Row Driver Driver 256 k Memory Array Mat Column Address Buffer Row Driver Row Driver I/O4 I/O4 Buffer I/O Bus & Column Decoder I/O Bus & Column Decoder 256 k Memory Array Mat 256 k Memory Array Mat HM51W4400B Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout PT Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 1.0 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 3.0 2.0 -0.3 Typ 0 3.3 -- -- Max 0 3.6 VCC + 0.3 0.8 Unit V V V V 1 1 1 Note DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) HM51W4400B -7 Parameter Operating current Standby current *1, 2 -8 Max 70 2 Min -- -- Max 60 2 Unit Test conditions mA mA RAS, CAS cycling, t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, CAS = VIH WE, OE, Address and Din = VIH or VIL Dout = High-Z Symbol I CC1 I CC2 Min -- -- -- 1 -- 1 mA Standby current *4 (L-version) I CC2 -- 50 -- 50 A 5 HM51W4400B Series DC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V) (cont) HM51W4400B -7 Parameter RAS-only refresh current Standby current *1 *2 -8 Max 70 4 70 60 100 Min -- -- -- -- -- Max 60 4 60 50 100 Unit Test conditions mA mA mA mA A t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min t RC = 125 s t RAS 1 s, WE = VIH, CAS = VIL, OE, Address, Din = VIH or VIL, Dout = High-Z RAS, CAS = VIL, OE, Address, WE and Din = VIH or VIL, Dout = High-Z 0 V Vin 4.6 V 0 V Vout 4.6 V Dout = disable High Iout = -2 mA Low Iout = 2 mA Symbol I CC3 I CC5 I CC6 I CC7 I CC10 Min -- -- -- -- -- CAS-before-RAS refresh current Fast page mode current *1, 3 Battery backup current (standby with CBR refresh) (L-version) Self-refresh current*4 (L-version) Input leakage current Output leakage current Output high voltage Output low voltage *4 I CC11 -- 100 -- 100 A I LI I LO VOH VOL -10 -10 2.4 0 10 10 VCC 0.4 -10 -10 2.4 0 10 10 VCC 0.4 A A V V Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed twice or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. 4. VIH VCC - 0.2 V, 0V VIL 0.2 V. Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V) Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS and CAS = VIH to disable Dout. 6 HM51W4400B Series AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)*1, *14, *15, *16 Test Conditions * * * * Input rise and fall time: 5 ns Input timing reference levels: 0.8 V, 2.0 V Output timing referen,ce levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig) Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters) HM51W4400B -7 Parameter Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS setup time from Din Transition time (rise and fall) Refresh period Refresh period (L-version) Symbol t RC t RP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t ODD t DZO t DZC tT t REF t REF Min 130 50 70 20 0 10 0 15 20 15 20 70 10 20 0 0 3 -- -- Max -- -- -8 Min 150 60 Max -- -- Unit ns ns 19 20 Notes 10000 80 10000 20 -- -- -- -- 50 35 -- -- -- -- -- -- 50 16 128 0 10 0 15 20 15 20 80 10 20 0 0 3 -- -- 10000 ns 10000 ns -- -- -- -- 60 40 -- -- -- -- -- -- 50 16 128 ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms 8 9 7 7 HM51W4400B Series Read Cycle HM51W4400B -7 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Output buffer turn-off time Output buffer turn-off time to OE CAS to Din delay time OE pulse width Symbol t RAC t CAC t AA t OAC t RCS t RCH t RRH t RAL t OFF1 t OFF2 t CDD t OEP Min -- -- -- -- 0 0 0 35 -- -- 20 20 Max 70 20 35 20 -- -- -- -- 20 20 -- -- -8 Min -- -- -- -- 0 0 0 40 -- -- 20 20 Max 80 20 40 20 -- -- -- -- 20 20 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns 6 6 18 18 Notes 2, 3, 17 3, 4, 13, 17 3, 5, 13, 17 3, 17 Write Cycle HM51W4400B -7 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 15 10 20 20 0 15 Max -- -- -- -- -- -- -- -8 Min 0 15 10 20 20 0 15 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 11 11 Notes 10 8 HM51W4400B Series Read-Modify-Write Cycle HM51W4400B -7 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 180 95 45 60 20 Max -- -- -- -- -- -8 Min 200 105 45 65 20 Max -- -- -- -- -- Unit ns ns ns ns ns 10 10 10 Notes Refresh Cycle HM51W4400B -7 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) RAS precharge to CAS hold time CAS precharge time in normal mode Symbol t CSR t CHR t RPC t CPN Min 10 10 10 10 Max -- -- -- -- -8 Min 10 10 10 10 Max -- -- -- -- Unit ns ns ns ns Notes Fast Page Mode Cycle HM51W4400B -7 Parameter Fast page mode cycle time Fast page mode CAS precharge time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol t PC t CP t RASC t ACP t RHCP Min 45 10 -- -- 40 Max -- -- -8 Min 50 10 Max -- -- Unit ns ns 12 3, 13, 17 Notes 100000 -- 40 -- -- 45 100000 ns 45 -- ns ns 9 HM51W4400B Series Fast Page Mode Read-Modify-Write Cycle HM51W4400B -7 Parameter Symbol Min 95 65 Max -- -- -8 Min 100 70 Max -- -- Unit ns ns 10 Notes Fast page mode read-modify-write cycle time t PCM Fast page mode read-modify-write cycle CAS precharge to WE delay time t CPW Test Mode Cycle HM51W4400B -7 Parameter Test mode WE setup time Test mode WE hold time Symbol t WS t WH Min 0 10 Max -- -- -8 Min 0 10 Max -- -- Unit ns ns Notes Counter Test Cycle HM51W4400B -7 Parameter CAS precharge time in counter test cycle Symbol t CPT Min 40 Max -- -8 Min 40 Max -- Unit ns Notes Self Refresh Mode (L-version) HM51W4400BL -7 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol t RASS t RPS t CHS Min 100 130 -50 Max -- -- -- -8 Min 100 150 -50 Max -- -- -- Unit s ns ns Notes 10 HM51W4400B Series Notes: 1. AC measurements assume t T = 5 ns. 2. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 3. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 4. Assumes that tRCD tRCD (max) and tRAD tRAD (max). 5. Assumes that t RCD tRCD (max) and tRAD tRAD (max). 6. t OFF (max) define the time at which the output achieves the open circuit condition and is not referred to output voltage levels. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH and VIL. 8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only, if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only, if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 10. t WCS , t RWD, t CWD, t CPW and t AWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), tCPW tCPW (min) and tAWD tAWD (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 11. These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge in a delayed write or read-modify-write cycle. 12. t RASC defines RAS pulse width in fast page mode cycles. 13. Access time is determined by the longest among t AA , t CAC and t ACP. 14. An initial pause of 100 s is required after power up followed by a minimum of eight initialization cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles is required. 15. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 16. Test mode operation specified in this data sheet is 2-bit test function controlled by control address bits - - - CA0. This test mode operation can be performed by WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will be performed by normal read cycles or by WCBR refresh cycles. When the state of two test bits accord each other, the condition of the output data is high level. When the state of test bits do not accord, the condition of the output data is low level. In order to end this test mode operation, perform a RAS-only refresh cycle or a CASbefore-RAS refresh cycle. 17. In a test mode read cycle, the value of tRAC , t AA , t CAC , t OAC and t ACP is delayed for 2 ns to 5 ns for the specified value. These parameters should be specified in test mode cycles by adding the above value to the specified value in this data sheet. 18. Either t RCH or tRRH must be satisfied 19. t RAS (min) = tRWD (min) + tRWL (min) + tT in read-modify-write cycle. 20. t CAS (min) = tCWD (min) + tCWL (min) + tT in read-modify-write cycle. 21. XXXX H or L (H: V IH (min) Vin VIH (max), L: VIL (min) Vin VIL (max) //////// Invalid Dout 11 HM51W4400B Series Timing Waveforms*21 Read Cycle t RC t RAS RAS tT t RCD t RSH t CAS t CSH t RP t CRP CAS t RAD t ASR t RAH t ASC t RAL t CAH Address Row t RCS Column t RCH WE t CAC t AA Dout t RAC t DZC Din t DZO High-Z t OAC t RRH t OFF1 Dout t OFF2 t CDD t ODD t OEP OE 12 HM51W4400B Series Early Write Cycle t RC t RAS RAS tT t RCD t CSH CAS t RSH t CAS t RP t CRP t ASR t RAH t ASC t CAH Address Row Column t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) ** OE : H or L 13 HM51W4400B Series Delayed Write Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Column t CWL t RWL Address Row t RCS t WP WE t DS t DH Din High-Z Din t DZC t DZO t ODD t OEH Dout Invalid Dout* t OFF2 OE * * Invalid Dout comes out, when OE is low level. 14 HM51W4400B Series Read-Modify-Write Cycle t RWC t RAS t RP RAS tT t RCD t CAS t CRP CAS t RAD t ASR t RAH t ASC tCAH Address Row t RCS Column t CWD t AWD t CWL t RWL t WP WE t RWD t RAC t DZC Din High-Z t AA t CAC t DS t DH Din Dout t OAC Dout t OFF2 t DZO OE t OEP t ODD t OEH 15 HM51W4400B Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP tRPC tCRP CAS t ASR t RAH Address Row Dout High-Z * Refresh address : A0 - A9 (AX0 - AX9) ** WE, Din, OE: H or L 16 HM51W4400B Series CAS-Before-RAS Refresh Cycle t RC t RP RAS t RPC CAS t CPN WE t WS t WH t CPN t CSR tT t CHR t RPC t CRP t RAS t RP Address t OFF1 Dout High-Z *Din, OE: H or L 17 HM51W4400B Series Hidden Refresh Cycle tRC t RAS (Read) t RP t RC t RAS (Refresh) t RC t RP t RAS (Refresh) tRP RAS tT t RSH t RCD CAS t ASC t ASR t RAD t RAH Address Row t RAL t CAH Column t RCH t RRH t RCS WE t RAC Dout t DZC Dout t OFF2 High-Z tDZO t OAC t ODD t CAC t AA t OFF1 t CAS t CHR t CRP t CDD Din OE 18 HM51W4400B Series Fast Page Mode Read Cycle t RASC t RHCP t RP RAS tT t CSH t RCD CAS t ASR t RAD t RAH Address Row tASC t CAH Column t ASC t CAH Column t ASC t CAH Column t RAL t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RCS t RCS WE t DZC t CDD Din High-Z t ODD t CAC t RAC t AA t DZC t CDD High-Z tCAC t AA t ACP t OFF1 Dout t OAC t DZO t OFF2 t OEP Dout t DZO t OEP Dout t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t CAC t AA t ACP t OFF1 t DZO Dout t ODD t OFF2 t OEP t OAC t OFF2 t ODD t OFF1 OE t OAC 19 HM51W4400B Series Fast Page Mode Early Write Cycle t RASC t RP RAS tT t CSH t RCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column Column Column t WCS t WCH t WCS t WCH t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din Din Din Dout High-Z * OE : H or L 20 HM51W4400B Series Fast Page Mode Delayed Write Cycle t RASC t RP RAS tT t CSH tRCD t CAS t CP t PC t CAS t CP t RSH t CAS t CRP CAS t ASR t RAH t ASC t CAH Column t CWL t RCS t WP WE t DH t DS t RCS t DS t DH t RCS t DS Din t DH t ASC t CAH t ASC t CAH Address Row Column t CWL t WP Column t CWL t WP t RWL Din Din Din t OEH Dout t ODD High-Z OE 21 HM51W4400B Series Fast Page Mode Read-Modify-Write Cycle t RASC RAS t RCD tT t CAS CAS t RAD t RAH t ASR t CAH t ASC t ACP t ASC t CAH t CAH t ASC t CP t CAS t PCM t CP t CAS t CRP t RP Address Row Column t AWD t CWD t RWD t CWL t WP t RCS Column t AWD t CWD t CPW t CWL t WP Column t CPW t AWD t RCS t CWD t CWL t RWL t WP t RCS WE t CAC t DS t DH High-Z tAA t RAC tOAC Dout t DZO Dout t OFF2 t DZO t OEH t OAC Dout t OFF2 t OEH t DZC t CAC t DS t DH t ACP t DZC High-Z t CAC t AA t OAC Dout t OFF2 t OEH t DS t DH t DZC Din Din High-Z t AA Din Din t DZO OE t ODD t OEP t OEP t ODD tOEP t ODD 22 HM51W4400B Series Test Mode Cycle *,** Reset Cycle Set Cycle** Test Mode Cycle Normal Mode RAS CAS WE * CBR or RAS-only refresh ** Address, Din, OE: H or L 23 HM51W4400B Series Test Mode Set Cycle WE-and-CAS-Before RAS-Refresh Cycle t RC t RP t RAS t RP RAS tT CAS t CPN t WS t WH WE Address t OFF1 High-Z Dout 24 SP C@ ,, S R P C B @ t CPN *Din, OE: H or L t RPC t CSR t CHR t RPC t CRP HM51W4400B Series CAS-Before-RAS Refresh Counter Check Cycle (Read) t RAS RAS tT t CSR t CHR t CPT t RSH t CAS tCRP t RP CAS t ASC t CAH Address Column t RCH t RRH t WS t WH t RCS WE t DZC t CDD Din t CAC t AA High-Z t OFF1 Dout t DZO t OAC Dout t OFF2 t OEP t ODD OE 25 HM51W4400B Series CAS-Before-RAS Refresh Counter Check Cycle (Write) t RAS RAS tT t CSR t CHR t CPT t RSH t CAS t CRP t RP CAS t ASC t CAH Address Column t WS t WH t WCS t WCH WE t DS t DH Din Din Dout High-Z OE 26 HM51W4400B Series Self Refresh Cycle (L-version) tRP tRASS tRPS RAS tRPC tCPN tCSR tT tCHS tCRP CAS tWS WE tWH tOFF1 Dout High-Z * Address, Din, OE : H or L The low self refresh current is achieved by introducing extremely long internal refresh cycle. Therefore some care needs to be taken on the refresh. 1.Please do not use tRASS timing, 10 s tRASS 100 s. During this period, the device is in transition state from normal operation mode to self refresh mode. If tRASS 100 s, then RAS precharge time should use tRPS instead of tRP. 2.If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of distributed CBR refresh with 15.6 s interval should be executed within 16 ms immediately after exiting from and before entering into the self refresh mode. 3. If you use distributed CBR refresh mode with 15.6 s interval in normal read/write cycle, CBR refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. 4.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode again. 27 HM51W4400B Series Package Dimensions HM51W4400BS/BLS Series (CP-26/20D) 16.90 17.27 Max 22 18 Unit: mm 26 14 7.62 0.13 1 3.50 0.26 5 0.74 1.30 Max 9 13 0.21 2.40 + 0.24 - 8.51 0.13 0.80 6.71 0.28 +0.25 -0.17 0.43 0.10 0.10 1.27 28 HM51W4400B Series HM51W4400BTT/BLTT Series (TTP-26/20D) Unit: mm 17.14 17.54 Max 26 22 18 14 7.62 1 5 1.27 0.42 0.08 0.40 0.06 0.21 1.15 Max 0.17 0.05 0.125 0.04 0.13 0.05 1.20 Max 5.08 0.10 0 - 5 0.50 0.10 M 9 13 0.80 9.22 0.20 Hitachi Code JEDEC Code EIAJ Code Weight TTP-26/20D MO-132AA -- 0.32 g 29 |
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