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| HB526C264EN Series, HB526C464EN Series 1,048,576-word x 64-bit x 2-bank Synchronous Dynamic RAM Module 1,048,576-word x 64-bit x 4-bank Synchronous Dynamic RAM Module ADE-203-629B (Z) Rev. 2.0 Mar. 17, 1997 Description The HB526C264EN, HB526C464EN belong to 8-byte DIMM (Dual In-line Memory Module) family, and have been developed as an optimized main memory solution for 8-byte processor applications. The HB526C264EN is a 1M x 64 x 2-bank Synchronous Dynamic RAM Module, mounted 8 pieces of 16-Mbit SDRAM (HM5216805TT) sealed in TSOP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). The HB526C464EN is a 1M x 64 x 4-bank Synchronous Dynamic RAM Module, mounted 16 pieces of 16-Mbit SDRAM (HM5216805TT) sealed in TSOP package and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). An outline of the HB526C264EN, HB526C464EN are 168-pin socket type package (dual lead out). Therefore, the HB526C264EN, HB526C464EN make high density mounting possible without surface mount technology. The HB526C264EN, HB526C464EN provide common data inputs and outputs. Decoupling capacitors are mounted beside each TSOP on the module board. Features * 168-pin socket type package (dual lead out) Outline: 133.35 mm (Length) x 25.40 mm (Height) x 2.92/4.00 mm (Thickness) Lead pitch: 1.27 mm * 3.3V power supply * Clock frequency: 100 MHz / 83 MHz * JEDEC standard outline unbuffered 8-byte DIMM * LVTTL interface * Data bus width: x 64 (Non parity) bit * 2 Banks can operates simultaneously and independently * Burst read/write operation and burst read/single write operation capability * Programmable burst length: 1/2/4/8/full page HB526C264EN Series, HB526C464EN Series * Programmable burst sequence Sequential/interleave * Full page burst length capability Sequential burst Burst stop capability * Programmable CE latency: 2/3 * 4096 refresh cycles: 64 ms * 2 variations of refresh Auto refresh Self refresh Ordering Information Type No. HB526C264EN-10 HB526C264EN-12 HB526C464EN-10 HB526C464EN-12 Frequency 100 MHz 83 MHz 100 MHz 83 MHz Package Contact pad 168-pin dual lead out socket type Gold 2 HB526C264EN Series, HB526C464EN Series Pin Arrangement 1 pin 10 pin 11 pin 40 pin 41 pin 84 pin 85 pin 94 pin 95 pin 124 pin 125 pin 168 pin Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Pin name VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 NC NC VSS NC NC VDD Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pin name VSS NC S2 DQMB2 DQMB3 NC VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC NC (CKE1)* VSS DQ21 DQ22 DQ23 VSS 1 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Pin name VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 NC NC VSS NC NC VDD Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 Pin name VSS CKE0 NC (S3)*3 DQMB6 DQMB7 NC VDD NC NC NC NC VSS DQ48 DQ49 DQ50 DQ51 VDD DQ52 NC NC NC VSS DQ53 DQ54 DQ55 VSS 3 HB526C264EN Series, HB526C464EN Series Pin Arrangement (cont) Pin No. 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Pin name W DQMB0 DQMB1 S0 NC VSS A0 A2 A4 A6 A8 A10 (AP) NC VDD VDD CK0 Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin name DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC NC SDA SCL VDD Pin No. 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 Pin name CE DQMB4 DQMB5 NC (S1)* RE VSS A1 A3 A5 A7 A9 A11 (BA) NC VDD CK1 NC 2 Pin No. 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 Pin name DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS CK3 NC SA0 SA1 SA2 VDD Notes: 1. NC: HB526C264EN, CKE1: HB526C464EN 2. NC: HB526C264EN, S1: HB526C464EN 3. NC: HB526C264EN, S3: HB526C464EN 4 HB526C264EN Series, HB526C464EN Series Pin Description Pin name A0 to A11 Function Address input Row address Column address DQ0 to DQ63 S0 to S3 RE CE W DQMB0 to DQMB7 CK0 to CK3 (CLK0 to CLK3) CKE0, CKE1 SDA SCL SA0 to SA2 VDD VSS NC Data input/output Chip select input Row enable (RAS) input Column enable (CAS) input Write enable input Byte data mask Clock input Clock enable input Data input/output for serial PD Clock input for serial PD Serial address input Primary positive power supply Ground No connection A0 to A10 A0 to A8 A11 Bank select address 5 HB526C264EN Series, HB526C464EN Series Serial PD Matrix*1 Byte No. Function described 0 1 2 3 4 5 Defines number of bytes written into memory at module mfgr Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comments 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 1 LVTTL CL = 3 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Non parity Normal (15.625 s) Self refresh 2M x 8 128 256 byte SDRAM 11 9 1 2 64 Total number of bytes of SPD memory 0 device Fundamental memory type Number of row addresses on this assembly Number of column addresses on this assembly Number of module banks on this assembly (HB526C264EN) Number of module banks on this assembly (HB526C464EN) 0 0 0 0 0 0 0 0 6 7 8 9 Data width of this assembly Data width continuation Voltage interface standard of this assembly SDRAM cycle time at max (CL = x) -10 (12 ns) -12 (15 ns) 10 11 12 SDRAM access from Clock -10/12 (9 ns) DIMM configuration type Refresh rate/type 13 14 15 SDRAM width, primary DRAM Error checking SDRAM data width Minimum clock delay, back-to-back random column addresses Burst lengths supported Number of banks on each SDRAM device CE number of latencies supported CS number of latency W number of latency 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 CLK 16 17 18 19 20 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 0 1 1 1, 2, 4, 8, full page 2 2, 3 0 0 6 HB526C264EN Series, HB526C464EN Series Byte No. Function described 21 22 23 SDRAM device attributes SDRAM device attributes: General Minimum cycle time (CL = x - 1) -10 (15 ns) -12 (18 ns) 24 Maximum data access from clock (CL = x - 1) -10 (9.5 ns) -12 (10 ns) 25 26 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comments 0 0 1 0 0 0 1 0 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 Non buffer VCC 10% CL = 2 1 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 Minimum clock cycle time (CL = x - 2) 0 Undefined Maximum data access from clock (CL = x - 2) Undefined Minimum row precharge time -10 -12 0 27 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 1 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 30 ns 36 ns 20 ns 24 ns 30 ns 30 ns 60 ns 72 ns 16M byte 28 Minimum row active to row active delay -10 0 -12 0 0 0 0 0 0 0 0 29 Minimum RE to CE delay -10 -12 30 Minimum RE pulse width -10 -12 31 32 to 61 62 63 Module bank density Superset information SPD revision Checksum for bytes 0 to 62 (HB526C264EN) -10 -12 Checksum for bytes 0 to 62 (HB526C464EN) -10 -12 Rev1 0 0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 120 9 0 0 0 1 0 0 1 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 121 10 HITACHI: 07h 64 Manufacturer's JEDEC ID code per JEP - 106E 7 HB526C264EN Series, HB526C464EN Series Byte No. Function described 65 to 71 72 73 74 75 76 77 78 79 Manufacturer's JEDEC ID code per JEP - 106E Manufacturering location Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (HB526C264EN) Manufacturer's part number (HB526C464EN) 80 81 82 83 84 85 86 Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number Manufacturer's part number (-10) Manufacturer's part number (-12) 87 to 90 91 92 93 94 95 to 98 Manufacturer's part number Revision code Revision code Manufacturering date Manufacturering date Assembly serial number Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Comments 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 * * * 3 3 4 0 1 1 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 0 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 0 1 0 1 1 1 1 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 0 0 0 JAPAN (J) H B 5 2 6 C 2 4 6 4 E N -- 1 0 2 Space Initial Space Year code Weak code 99 to 125 Manufacturer specific data 126 127 Intel specification frequency Intel specification CE# *2 0 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 66 MHz CL = 2, 3 Notes: 1. All serial PD data are not protected. 0: Serial data, "driven Low", 1: Serial data, "driven High" 2. All bits of 99 through 125 are defined "1" or "0". 3. Bytes 93 (Manufacturering date - Year code): ex. Year 1996 -> 60h, Year 1997 -> 61h. Bytes 94 (Manufacturering date - Week code): ex. Week 11 -> 0Bh, Week 36 -> 24h. 4. Bytes 95 through 98 are production number. 8 HB526C264EN Series, HB526C464EN Series Block Diagram (HB526C264EN) RE, CE, W S0 CS DQMB0 DQ0 to DQ7 DQM 8 R0 to R7 I/O0 to I/O7 CS DQM 8 R8 to R15 I/O0 to I/O7 CS D0 DQMB4 8 DQ32 to DQ39 R32 to R39 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 D4 DQMB1 DQ8 to DQ15 D1 DQMB5 DQ40 to DQ47 R40 8 to R47 D5 S2 CS DQMB2 DQ16 to DQ23 R16 8 to R23 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 CS D2 DQMB6 8 DQ48 to DQ55 R48 to R55 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 D6 DQMB3 DQ24 to DQ31 R24 8 to R31 D3 DQMB7 DQ56 to DQ63 R56 8 to R63 D7 A0 to A11 CKE0 A0 to A11(D0 to D7) CKE (D0 to D7) CLK (D0, D2) R100, R101 SCL Serial PD SCL SDA SDA U0 A0 A1 A2 CK0, CK1 R102, R103 CLK (D4, D6) CLK (D1, D3) SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D7: HM5216805 U0: 24C02 C0 to C15: 0.33 F R0 to R63, R100 to R105: 10 C200, 201: 10 pF CLK (D5, D7) R104, R105 CK2, CK3 C200, C201 VDD C0 to C15 VSS VDD (D0 to D7) VSS (D0 to D7) 9 HB526C264EN Series, HB526C464EN Series Block Diagram (HB526C464EN) RE, CE, W S0 S1 CS DQMB0 DQ0 to DQ7 R0 8 to R7 DQM I/O0 to I/O7 CS DQM CS CS CS D0 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 D8 DQMB4 DQ32 to DQ39 R32 8 to R39 I/O0 to I/O7 CS DQM DQM D4 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 D12 DQMB1 DQ8 to DQ15 R8 8 to R15 I/O0 to I/O7 D1 D9 DQMB5 DQ40 to DQ47 R40 8 to R47 I/O0 to I/O7 D5 D13 S2 S3 CS DQMB2 DQ16 to DQ23 R16 8 to R23 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 CS CS CS D2 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 D10 DQMB6 DQ48 to DQ55 R48 8 to R55 I/O0 to I/O7 CS DQM DQM D6 DQM I/O0 to I/O7 CS DQM I/O0 to I/O7 D14 DQMB3 DQ24 to DQ31 R24 8 to R31 D3 D11 DQMB7 DQ56 to DQ63 R56 8 to R63 I/O0 to I/O7 D7 D15 A0 to A11 CKE0 VDD R200 CKE1 A0 to A11(D0 to D15) CKE (D0 to D7) SCL Serial PD SCL SDA SDA U0 CKE (D8 to D15) CLK (D0, D2, D8, D10) A0 A1 A2 R100 to R103 SA0 SA1 SA2 Notes : 1. The SDA pull-up resistor is required due to the open-drain/open-collector output. 2. The SCL pull-up resistor is recommended because of the normal SCL line inacitve "high" state. * D0 to D15: HM5216805 U0: 24C02 C0 to C31: 0.33 F R0 to R63, R100 to R107: 10 R200: 10 k CK0, CK1, CK2, CK3 CLK (D4, D6, D12, D14) CLK (D1, D3, D9, D11) R104 to R107 CLK (D5, D7, D13, D15) VDD C0 to C31 VSS VDD (D0 to D15) VSS (D0 to D15) 10 HB526C264EN Series, HB526C464EN Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Note: 1. Respect to V SS . Symbol VT VDD Iout PT Topr Tstg Value -0.5 to +4.6 -0.5 to +4.6 50 8 0 to +65 -55 to +125 Unit V V mA W C C Note 1 1 Recommended DC Operating Conditions (Ta = 0 to +65C) Parameter Supply voltage Symbol VDD VSS Input high voltage Input low voltage VIH VIL Min 3.0 0 2.0 -0.3 Typ 3.3 0 -- -- Max 3.6 0 4.6 0.8 Unit V V V V 1, 2 1, 3 Notes 1 Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns 11 HB526C264EN Series, HB526C464EN Series DC Characteristics (Ta = 0 to 65C, VDD = 3.3 V 0.3 V, V SS = 0 V) (HB526C264EN) HB526C264EN -10 Parameter Operating current Standby current (Bank Disable) Symbol I CC1 I CC2 Min -- -- -- -- Max 800 24 16 320 -12 Min -- -- -- -- Max 680 24 16 280 Unit mA mA mA mA Test conditions Burst length = 1 t RC = min CKE = VIL, t CK = min CKE = VIL CK = VIL or VIH Fixed CKE = VIH, NOP command t CK = min CKE = VIL, t CK = min, DQ = High-Z CKE = VIH, NOP command t CK = min, DQ = High-Z t CK = min, BL = 4 Notes 1, 2, 4 5 6 3 Active standby current (Bank active) I CC3 -- 56 -- 56 mA 1, 2 -- 320 -- 280 mA 1, 2, 3 Burst operating current (CE Latency = 2) (CE Latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 0 800 -- 680 mA 1, 2, 4 1200 -- 680 16 10 10 VDD 0.4 -- -- -10 -10 2.4 0 1000 mA 560 16 10 10 VDD 0.4 mA mA A A V V t RC = min VIH VDD - 0.2 VIL 0.2 V 0 Vin VDD 0 Vout VDD DQ = disable I OH = -2 mA I OL = 2 mA 7 Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CK cycles. 4. Input signal transition is once per one CK cycle. 5. After power down mode, CK operating current. 6. After power down mode, no CK operating current. 7. After self refresh mode set, self refresh current. 12 HB526C264EN Series, HB526C464EN Series DC Characteristics (Ta = 0 to 65C, VDD = 3.3 V 0.3 V, V SS = 0 V) (HB526C464EN) HB526C464EN -10 Parameter Operating current Standby current (Bank Disable) Symbol I CC1 I CC2 Min -- -- -- -- Max -12 Min Max 960 48 32 560 Unit mA mA mA mA Test conditions Burst length = 1 t RC = min CKE = VIL, t CK = min CKE = VIL CK = VIL or VIH Fixed CKE = VIH, NOP command t CK = min CKE = VIL, t CK = min, DQ = High-Z CKE = VIH, NOP command t CK = min, DQ = High-Z t CK = min, BL = 4 Notes 1, 2, 4 5 6 3 1120 -- 48 32 640 -- -- -- Active standby current (Bank active) I CC3 -- 112 -- 112 mA 1, 2 -- 640 -- 560 mA 1, 2, 3 Burst operating current (CE Latency = 2) (CE Latency = 3) Refresh current Self refresh current Input leakage current Output leakage current Output high voltage Output low voltage I CC4 I CC4 I CC5 I CC6 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 0 1080 -- 1480 -- 960 296 10 10 VDD 0.4 -- -- -10 -10 2.4 0 920 mA 1, 2, 4 1240 mA 800 256 10 10 VDD 0.4 mA mA A A V V t RC = min VIH VDD - 0.2 VIL 0.2 V 0 Vin VDD 0 Vout VDD DQ = disable I OH = -2 mA I OL = 2 mA 7 Notes: 1. I CC depends on output load condition when the device is selected. ICC (max) is specified at the output open condition. 2. One bank operation. 3. Input signal transition is once per two CK cycles. 4. Input signal transition is once per one CK cycle. 5. After power down mode, CK operating current. 6. After power down mode, no CK operating current. 7. After self refresh mode set, self refresh current. 13 HB526C264EN Series, HB526C464EN Series Capacitance (Ta = 25C, VDD = 3.3 V 0.3 V) (HB526C264EN) Parameter Input capacitance (Address) Input capacitance (RE, CE, W, CKE) Input capacitance (S, CK) Input capacitance (DQMB) Input/Output capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI/O1 Typ -- -- -- -- -- Max 60 60 40 25 20 Unit pF pF pF pF pF Notes 1, 3 1, 3 1, 3 1, 3 1, 2, 3 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMB = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. Capacitance (Ta = 25C, VDD = 3.3 V 0.3 V) (HB526C464EN) Parameter Input capacitance (Address) Input capacitance (RE, CE, W) Input capacitance (S, CK) Input capacitance (CKE) Input capacitance (DQMB) Input/Output capacitance (DQ) Symbol CI1 CI2 CI3 CI4 CI4 CI/O1 Typ -- -- -- -- -- -- Max 100 100 40 60 30 27 Unit pF pF pF pF pF pF Notes 1, 3 1, 3 1, 3 1, 3 1, 3 1, 2, 3 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQMB = VIH to disable Dout. 3. This parameter is sampled and not 100% tested. 14 HB526C264EN Series, HB526C464EN Series AC Characteristics (Ta = 0 to 65C, VDD = 3.3 V 0.3 V, V SS = 0 V) HB526C264EN/HB526C464EN -10 Parameter System clock cycle time (CE Latency = 2) (CE Latency = 3) CK high pulse width CK low pulse width Access time from CK (CE Latency = 2) (CE Latency = 3) Data-out hold time CK to Data-out low impedance CK to Data-out high impedance Data-in setup time Data in hold time Address setup time Address hold time CKE setup time CKE setup time for power down exit CKE hold time Command setup time Command hold time Ref/Active to Ref/Active command period Active to precharge command period Active to precharge on full page mode Active command to column command (same bank) Precharge to active command period Symbol t CK t CK t CKH t CKL t AC t AC t OH t LZ t HZ t DS t DH t AS t AH t CES t CESP t CEH t CS t CH t RC t RAS t RASC t RCD t RP Min 15 10 3 3 -- -- 3 0 -- 2 1 2 1 2 2 1 2 1 90 60 -- 30 30 15 20 1 -- Max -- -- -- -- 9.5 7.5 -- -- 7 -- -- -- -- -- -- -- -- -- -- 10000 80000 -- -- -- -- 5 64 -12 Min 18 12 4 4 -- -- 3 0 -- 3 1 3 1 3 3 1 3 1 108 72 -- 36 36 18 24 1 -- Max -- -- -- -- 12 9 -- -- 9 -- -- -- -- -- -- -- -- -- -- 10000 80000 -- -- -- -- 5 64 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 1, 2 1, 2, 3 1, 4 1 1 1 1 1, 5 1 1 1 1 1 1 1 1 1 1 1 ns ns ns 1 1 1, 2 Unit ns Notes 1 Write recovery or data-in to precharge lead t DPL time Active (a) to Active (b) command period Transition time (rise to fall) Refresh period t RRD tT t REF 15 HB526C264EN Series, HB526C464EN Series Notes: 1. 2. 3. 4. 5. AC measurement assumes t T = 1 ns. Reference level for timing of input signals is 1.40 V. Access time is measured at 1.40 V. Load condition is C L = 50 pF with current source. t LZ (max) defines the time at which the outputs achieves the low impedance state. t HZ (max) defines the time at which the outputs achieves the high impedance state. t CES defines CKE setup time to CKE rising edge except power down exit command. Test Conditions * Input and output timing reference levels: 1.4 V * Input waveform and output load: See following figures 2.8 V input V SS 80% 20% DQ 50 +1.4 V CL t T tT 16 HB526C264EN Series, HB526C464EN Series Relationship Between Frequency and Minimum Latency HB526C264EN/HB526C464EN Parameter Frequency (MHz) tCK (ns) Active command to column command (same bank) Symbol t RCD -10 100 10 3 9 6 3 2 2 2 5 9 3 -- 1 66 15 2 6 4 2 1 2 2 3 6 3 2 1 33 30 1 3 2 1 1 1 2 2 3 3 2 1 -12 83 12 3 9 6 3 2 2 2 5 9 3 -- 1 55 18 2 6 4 2 1 2 2 3 6 3 2 1 28 36 1 3 2 1 1 1 2 2 3 3 2 1 Notes 1 = [tRAS + tRP] 1 1 1 1 1 2 = [tDPL + tRP] = [tRC] Active command to active command t RC (same bank) Active command to precharge command (same bank) Precharge command to active command (same bank) Write recovery or data-in to precharge command (same bank) t RAS t RP t DPL Active command to active command t RRD (different bank) Self refresh exit time Last data in to active command (Auto precharge, same bank) Self refresh exit to command input Precharge command to high impedance (CE latency = 3) (CE latency = 2) Last data out to active command (auto precharge) (same bank) Last data out to precharge (early precharge) (CE latency = 3) (CE latency = 2) Column command to column command Write command to data in latency DQMB to data in DQMB to data out CKE to CK disable Register set to active command S to command disable Power down exit to command input I SREX I APW I SEC I HZP I HZP I APR I EP I EP I CCD I WCD I DID I DOD I CLE t RSA I CDD I PEC -2 -- 1 0 0 2 1 1 0 1 -2 -1 1 0 0 2 1 1 0 1 -2 -1 1 0 0 2 1 1 0 1 -2 -- 1 0 0 2 1 1 0 1 -2 -1 1 0 0 2 1 1 0 1 -2 -1 1 0 0 2 1 1 0 1 17 HB526C264EN Series, HB526C464EN Series Relationship Between Frequency and Minimum Latency (cont) HB526C264EN/HB526C464EN Parameter Frequency (MHz) tCK (ns) Burst stop to output valid data hold (CE latency = 3) (CE latency = 2) Symbol I BSR I BSR -10 100 10 2 -- 3 -- 0 66 15 2 1 3 2 0 33 30 2 1 3 2 0 -12 83 12 2 -- 3 -- 0 55 18 2 1 3 2 0 28 36 2 1 3 2 0 Notes Burst stop to output high impedance (CE latency = 3) I BSH (CE latency = 2) Burst stop to write data ignore I BSH I BSW Notes: 1. t RCD to tRRD are recommended value. 2. When self refresh exit is executed, CKE should be kept "H" longer than l SREX from exit cycle. 18 HB526C264EN Series, HB526C464EN Series Pin Functions CK0 to CK3 (input pins): CK is the master clock input to this pin. The other input signals are referred at CK rising edge. S0 to S3 (input pins): When S is Low, the command input cycle becomes valid. When S is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. RE, C E, and W (input pins): Although these pin names are the same as those of conventional DRAM modules, they function in a different way. These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. A0 to A10 (input pins): Row address (AX0 to AX10) is determined by A0 to A10 level at the bank active command cycle CK rising edge. Column address (AY0 to AY8) is determined by A0 to A8 level at the read or write command cycle CK rising edge. And this column address becomes burst access start address. A10 defines the precharge mode. When A10 = High at the precharge command cycle, both banks are precharged. But when A10 = Low at the precharge command cycle, only the bank that is selected by A11 (BS) is precharged. A11 (input pin): A11 is a bank select signal (BS). The memory array of the HB526C264EN, HB526C464EN are divided into bank 0 and bank 1, both which contain 2048 row x 512 column x 8 bits. If A11 is Low, bank 0 is selected, and if A11 is High, bank 1 is selected. CKE0, CKE1 (input pins): This pin determines whether or not the next CK is valid. If CKE is High, the next CK rising edge is valid. If CKE is Low, the next CK rising edge is invalid. This pin is used for powerdown and clock suspend modes. DQMB0 to DQMB7 (input pins): Read operation: If DQMB is High, the output buffer becomes High-Z. If the DQMB is Low, the output buffer becomes Low-Z. Write operation: If DQMB is High, the previous data is held (the new data is not written). If DQMB is Low, the data is written. DQ0 to DQ63 (DQ pins): Data is input to and output from these pins. These pins are the same as those of a conventional DRAM module. VDD (power supply pins): 3.3 V is applied. VSS (power supply pins): Ground is connected. 19 HB526C264EN Series, HB526C464EN Series Command Operation Command Truth Table The synchronous DRAM module recognizes the following commands sepcified by the S, R E, C E, W and address pins. Function Ignore command No operation Burst stop in full page Column address and read command Read with auto-precharge Column address and write command Write with auto-precharge Row address strobe and bank act. Precharge select bank Precharge all bank Refresh Mode register set Symbol DESL NOP BST READ READ A WRIT WRIT A ACTV PRE PALL CKE n-1 H H H H H H H H H H n x x x x x x x x x x V x S H L L L L L L L L L L L RE x H H H H H H L L L L L CE x H H L L L L H H H L L W x H L H H L L H L L H L A11 x x x V V V V V V x x V A10 x x x L H L H V L H x V A0 to A9 x x x V V V V V x x x V REF/SELF H MRS H Note: H: VIH. L: VIL. x: V IH or VIL. V: Valid address input Ignore command [DESL]: When this command is set (S is High), the synchronous DRAM module ignore command input at the clock. However, the internal status is held. No operation [NOP]: This command is not an execution command. However, the internal operations continue. Burst stop in full-page [BST]: This command stops a full-page burst operation (burst length = full-page (512)), and is illegal otherwise. Full page burst continues until this command is input. When data input/output is completed for a full-page of data (512), it automatically returns to the start address, and input/output is performed repeatedly. Column address strobe and read command [READ]: This command starts a read operation. In addition, the start address of burst read is determined by the column address (AY0 to AY8) and the bank select address (BS). After the read operation, the output buffer becomes High-Z. Read with auto-precharge [READ A]: This command automatically performs a precharge operation after a burst read with a burst length of 1, 2, 4, or 8. When the burst length is full-page (512), this command is illegal. 20 HB526C264EN Series, HB526C464EN Series Column address strobe and write command [WRIT]: This command starts a write operation. When the burst write mode is selected, the column address (AY0 to AY8) and the bank select address (A11) become the burst write start address. When the single write mode is selected, data is only written to the location specified by the column address (AY0 to AY8) and the bank select address (A11). Write with auto-precharge [WRIT A]: This command automatically performs a precharge operation after a burst write with a length of 1, 2, 4, or 8, or after a single write operation. When the burst length is full-page (512), this command is illegal. Row address strobe and bank activate [ACTV]: This command activates the bank that is selected by A11 (BS) and determines the row address (AX0 to AX10). When A11 is Low, bank 0 is activated. When A11 is High, bank 1 is activated. Precharge selected bank [PRE]: This command starts precharge operation for the bank selected by A11. If A11 is Low, bank 0 is selected. If A11 is High, bank 1 is selected. Precharge all banks [PALL]: This command starts a precharge operation for all banks. Refresh [REF/SELF]: This command starts the refresh operation. There are two types of refresh oepration, the one is auto-refresh, and the other is self-refresh. For details, refer to the CKE truth table section. Mode register set [MRS]: Synchronous DRAM module has a mode register that defines how it operates. The mode register is specified by the address pins (A0 to A11) at the mode register set cycle. For details, refer to the mode register configuration. After power on, the contents of the mode register are undefined, execute the mode register set command to set up the mode register. DQMB Truth Table CKE n-1 H H Function Write enable/output enable Write inhibit/output disable Note: H: VIH. L: VIL. x: V IH or VIL. I DOD is needed. Symbol ENB MASK n x x DQMB L H The HB526C264EN Series, HB526C464EN Series can mask input/output data by means of DQMB During reading, the output buffer is set to Low-Z by setting DQMB to Low, enabling data output. On the other hand, when DQMB is set to High, the output buffer becomes High-Z, disabling data output. During writing, data is written by setting DQMB to Low. When DQMB is set to High, the previous data is held (the new data is not written). Desired data can be masked during burst read or burst write by setting DQMB. For details, refer to the DQMB control section of the HB526C264EN, HB526C464EN operating instructions. 21 HB526C264EN Series, HB526C464EN Series CKE Truth Table CKE n-1 H L L REF SELF H H H H Self-refres Self refresh exit SELFX L L Power down Power down exit L L Note: H: VIH. L: VIL. x: V IH or VIL. S H x x L L L H L H L H RE x x x L L H x H x H x CE x x x L L H x H x H x W x x x H H H x H x H x Current state Active Any Clock suspend Idle Idle Idle Function Clock suspend mode entry Clock suspend Clock suspend mode exit Auto refresh command Self refresh entry Power down entry n L L H H L L L H H H H Address x x x x x x x x x x x Clock suspend mode entry: The synchronous DRAM module enters clock suspend mode from active mode by setting CKE to Low. The clock suspend mode changes depending on the current status (1 clock before) as shown below. ACTIVE clock suspend: This suspend mode ignores inputs after the next clock by internally maintaining the bank active status. READ suspend and READ A suspend: The data being output is held (and continues to be output). WRITE suspend and WRIT A suspend: In this mode, external signals are not accepted. However, the internal state is held. Clock suspend: During clock suspend mode, keep the CKE to Low. Clock suspend mode exit: The synchronous DRAM module exits from clock suspend mode by setting CKE to High during the clock suspend state. IDLE: In this state, all banks are not selected, and completed precharge operation. Auto refresh command [REF]: When this command is input from the IDLE state, the synchronous DRAM module starts auto refresh operation. (The auto refresh is the same as the CBR refresh of conventional DRAM module.) During the auto refresh operation, refresh address and bank select address are generated inside the synchronous DRAM module. For every auto refresh cycle, the internal address counter is updated. Accordingly, 4096 times are required to refresh the entire memory. Before exicuting the auto refresh command, all the banks must be in the IDLE state. In addition, since the precharge for all banks is automatically performed after auto refresh, no precharge command is required after auto refresh. 22 HB526C264EN Series, HB526C464EN Series Self refresh entry [SELF]: When this command is input during the IDLE state, the synchronous DRAM module starts self refresh operation. After the execution of this command, self refresh continues while CKE is Low. Since self refresh is performed internally and automatically, external refresh operations are unnecessary. Power down mode entry: When this command is executed during the IDLE state, the synchronous DRAM module enters power down mode. In power down mode, power consumption is suppressed by cutting off the initial input circuit. Self refresh exit: When this command is executed during self refresh mode, the synchronous DRAM module can exit from self refresh mode. After exiting from self refresh mode, the synchronous DRAM module enters the IDLE state. Power down exit: When this command is executed at the power down mode, the synchronous DRAM module can exit from power down mode. After exiting from power down mode, the synchronous DRAM module enters the IDLE state. Function Truth Table The following table shows the operations that are performed when each command is issued in each mode of the synchronous DRAM module. Current state S Precharge H L L L L L L L L Idle H L L L L L L L L RE x H H H H L L L L x H H H H L L L L CE x H H L L H H L L x H H L L H H L L W x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation Enter IDLE after t RP Enter IDLE after t RP NOP ILLEGAL ILLEGAL ILLEGAL NOP ILLEGA ILLEGAL NOP NOP NOP ILLEGAL ILLEGAL Bank and row active NOP Refresh Mode register set 23 HB526C264EN Series, HB526C464EN Series Current state S Row active H L L L L L L L L Read H L L L L L L L L Read with H auto-precharge L L L L L L L L RE x H H H H L L L L x H H H H L L L L x H H H H L L L L CE x H H L L H H L L x H H L L H H L L x H H L L H H L L W x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation NOP NOP NOP Begin read Begin write Other bank active ILLEGAL on same bank*3 Precharge ILLEGAL ILLEGAL Continue burst to end Continue burst to end Burst stop to full page Continue burst read to CE latency and new read Term burst read/start write Other bank active ILLEGAL on same bank*3 Term burst read and Precharge ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL 24 HB526C264EN Series, HB526C464EN Series Current state S Write H L L L L L L L L Write with H auto-precharge L L L L L L L L Refresh (auto refresh) H L L L L L L L L RE x H H H H L L L L x H H H H L L L L x H H H H L L L L CE x H H L L H H L L x H H L L H H L L x H H L L H H L L W x H L H L H L H L x H L H L H L H L x H L H L H L H L Address x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE x x x BA, CA, A10 BA, CA, A10 BA, RA BA, A10 x MODE Command DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS DESL NOP BST READ/READ A WRIT/WRIT A ACTV PRE, PALL REF, SELF MRS Operation Continue burst to end Continue burst to end Burst stop on full page Term burst and new read Term burst and new write Other bank active ILLEGAL on same bank*3 Term burst write and precharge*2 ILLEGAL ILLEGAL Continue burst to end and precharge Continue burst to end and precharge ILLEGAL ILLEGAL ILLEGAL Other bank active ILLEGAL on same bank*3 ILLEGAL ILLEGAL ILLEGAL Enter IDLE after t RC Enter IDLE after t RC Enter IDLE after t RC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL Notes: 1. H: VIH. L: VIL. x: V IH or VIL. The other combinations are inhibit. 2. An interval of t DPL is required between the final valid data input and the precharge command. 3. If tRRD is not satisfied, this operation is illegal. 25 HB526C264EN Series, HB526C464EN Series From [PRECHARGE] To [DESL], [NOR] or [BST]: When these commands are executed, the synchronous DRAM module enters the IDLE state after tRP has elapsed from the completion of precharge. From [IDLE] To [DESL], [NOP], [BST], [PRE] or [PALL]: These commands result in no operation. To [ACTV]: The bank specified by the address pins and the ROW address is activated. To [REF], [SELF]: The synchronous DRAM module enters refresh mode (auto refresh or self refresh). To [MRS]: The synchronous DRAM module enters the mode register set cycle. From [ROW ACTIVE] To [DESL], [NOP] or [BST]: These commands result in no operation. To [READ], [READ A]: A read oepration starts. (However, an interval of tRCD is requried.) To [WRIT], [WRIT A]: A write operation starts. (However, an interval of tRCD is required.) To [ACTV]: This command makes the other bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands set the synchronous DRAM module to precharge mode. (However, an interval of t RAS is required.) From [READ] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: Data output by the previous read command continues to be output. A f t e r CE latency, the data output resulting from the next command will start. To [WRIT], [WRIT A]: These commands stop a burst read, and start a write cycle. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is requried.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop a burst read, and the synchronous DRAM module enters precharge mode. 26 HB526C264EN Series, HB526C464EN Series From [READ with AUTO PRECHARGE] To [DESL], [NOP]: These commands continue read operations until the burst operation is completed, and the synchronous DRAM module then enters precharge mode. To [ACTV]: This command makes other banks bank active. (However, an interval of tRRD is required.) Attempting to make the currently active bank active results in an illegal command. From [WRITE] To [DESL], [NOP]: These commands continue write operations until the burst operation is completed. To [BST]: This command stops a full-page burst. To [READ], [READ A]: These commands stop a burst and start a read cycle. To [WRIT], [WRIT A]: These commands stop a burst and start the next write cycle. To [ACTV]: This command makes the other bank active. (However, an interval of t RRD is required.) Attempting to make the currently active bank active results in an illegal command. To [PRE], [PALL]: These commands stop burst write and the synchronous DRAM module then enters precharge mode. From [WRITE with AUTO-PRECHARGE] To [DESL], [NOP]: These commands continue write operations until the burst is completed, and the synchronous DRAM module enters precharge mode. To [ACTV]: This command makes the other bank active. (However, an interval of tRC is required.) Attempting to make the currently active bank active results in an illegal command. From [REFRESH] To [DESL], [NOP], [BST]: After an auto-refresh cycle (after t RC ), the synchronous DRAM module automatically enters the IDLE state. 27 HB526C264EN Series, HB526C464EN Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MODE REGISTER SET MRS IDLE REFRESH *1 AUTO REFRESH CKE CKE_ IDLE POWER DOWN ACTIVE CLOCK SUSPEND ACTIVE CKE_ CKE ROW ACTIVE BST (on full page) BST (on full page) WRITE Write WRITE SUSPEND CKE_ WRITE CKE WRITE WITH AP CKE_ WRITEA SUSPEND WRITEA CKE PRECHARGE READ WITH AP WRITE WITH AP READ READ WITH AP WRITE READ Read CKE_ READ CKE READ WITH AP CKE_ READA CKE PRECHARGE READA SUSPEND READ SUSPEND WRITE WITH AP PRECHARGE POWER APPLIED POWER ON PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 28 HB526C264EN Series, HB526C464EN Series Mode Register Configuration The mode register is set by the input to the address pins (A0 to A11) during mode register set cycles. The mode register consists of five sections, each of which is assigned to address pins. A11, A10, A9, A8: (OPCODE): The synchronous DRAM module has two types of write modes. One is the burst write mode, and the other is the single write mode. These bits specify write mode. Burst read and BURST WRITE: Burst write is performed for the specified burst length starting from the column address specified in the write cycle. Burst read and SINGLE WRITE: Data is only written to the column address specified during the write cycle, regardless of the burst length. A7: Keep this bit Low at the mode register set cycle. A6, A5, A4: (LMODE): These pins specify the CE latency. A3: (BT): A burst type is specified. When full-page burst is performed, only "sequential" can be selected. A2, A1, A0: (BL): These pins specify the burst length. A11 A10 A9 A8 A7 0 A6 A5 A4 A3 BT A2 A1 BL A0 OPCODE LMODE A6 A5 A4 CE Latency 0 0 0 0 1 0 0 1 1 X 0 1 0 1 X R -- 2 3 R A3 Burst Type 0 Sequential 1 Interleave A2 A1 A0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Burst Length BT=0 1 2 4 8 R R R F.P. BT=1 1 2 4 8 R R R R A11 A10 0 X X X 0 X X X A9 0 0 1 1 A8 0 1 0 1 Write mode Burst read and burst write R Burst read and SINGLE WRITE R F.P. = Full Page R is Reserved(inhibit) X: 0 or 1 29 HB526C264EN Series, HB526C464EN Series Burst Sequence Burst length = 2 Starting Ad. Addressing(decimal) A0 0 1 Sequence 0, 1, 1, 0, Interleave 0, 1, 1, 0, Burst length = 4 Starting Ad. Addressing(decimal) A1 0 0 1 1 Burst length = 8 Starting Ad. A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Addressing(decimal) Interleave 0, 1, 2, 3, 4, 5, 6, 7, 1, 0, 3, 2, 5, 4, 7, 6, 2, 3, 0, 1, 6, 7, 4, 5, 3, 2, 1, 0, 7, 6, 5, 4, 4, 5, 6, 7, 0, 1, 2, 3, 5, 4, 7, 6, 1, 0, 3, 2, 6, 7, 4, 5, 2, 3, 0, 1, 7, 6, 5, 4, 3, 2, 1, 0, 0, 1, 2, 3, 4, 5, 6, 7, 1, 2, 3, 4, 5, 6, 7, 0, 2, 3, 4, 5, 6, 7, 0, 1, 3, 4, 5, 6, 7, 0, 1, 2, 4, 5, 6, 7, 0, 1, 2, 3, 5, 6, 7, 0, 1, 2, 3, 4, 6, 7, 0, 1, 2, 3, 4, 5, 7, 0, 1, 2, 3, 4, 5, 6, A0 Sequence A0 0 1 0 1 Sequence 0, 1, 2, 3, 1, 2, 3, 0, 2, 3, 0, 1, 3, 0, 1, 2, Interleave 0, 1, 2, 3, 1, 0, 3, 2, 2, 3, 0, 1, 3, 2, 1, 0, 30 HB526C264EN Series, HB526C464EN Series Operation of HB526C264EN Series, HB526C464EN Series Read/Write Operations Bank active: Before executing a read or write operation, the corresponding bank and the row address must be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank active command cycle. An interval of tRCD is requried between the bank active command input and the following read/write command input. Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in the (CE Latency-1) cycle after read command set. HB526C264EN Series, HB526C464EN Series can perform a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (512). The start address for a burst read is specified by the column address (AY0 to AY8) and the bank select address (A11) at the read command set cycle. In a read operation, data output starts after the number of cycles specified by the CE Latency. The CE Latency can be set to 2 or 3. When the burst length is 1, 2, 4, or 8, the Dout buffer automatically becomes High-Z at the next cycle after the successive burst-length data has been output. When the burst length is full-page (512), data is repeatedly output until the burst stop command is input. The CE latency and burst length must be specified at the mode register. CE Latency CK t RCD Command ACTV READ Address Row Column CL = 2 Dout CL = 3 out 0 out 1 out 0 out 2 out 1 out 3 out 2 out 3 CL: CE Latency Burst Length = 4 31 HB526C264EN Series, HB526C464EN Series Burst Length CK t RCD Command Address ACTV READ Row Column BL = 1 BL = 2 Dout out 0 out 0 out 1 out 0 out 1 out 2 out 3 BL = 4 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 BL = 8 out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 out 8 out 255 out 0 out 1 BL = full page BL: Burst Length CE Latency = 2 Write operation: Burst write or single write mode is selected by the OPCODE (A11, A10, A9, A8) of the mode register. Burst write A burst write operation is enabled by setting OPCODE (A9, A8) to (0, 0). A burst write starts in the same cycle as a write command set. (The latency of data input is 0.) The burst length can be set to 1, 2, 4, 8, and full-page, like burst read operations. The write start address is specified by the column address (AY0 to AY8) and the bank select address (A11) at the write command set cycle. CK t RCD Command Address ACTV WRIT Row Column BL = 1 BL = 2 in 0 in 0 in 1 in 1 in 1 in 1 in 2 in 2 in 2 in 3 in 3 in 3 in 4 in 4 in 5 in 5 in 6 in 6 in 7 in 7 in 8 in 255 Din in 0 BL = 4 in 0 BL = 8 in 0 in 0 in 1 BL = full page CE Latency = 2, 3 32 HB526C264EN Series, HB526C464EN Series Single write A single write operation is enabled by setting OPCODE (A9, A8) to (1, 0). In a single write operation, data is olny written to the column address (AY0 to AY8) and the bank select address (A11) specified by the write command set cycle without regard to the burst length setting. (The latency of data input is 0). CK t RCD Command ACTV WRIT Address Din Row Column in 0 CE Latency = 2, 3 Burst Length = 1, 2, 4, 8 full page 33 HB526C264EN Series, HB526C464EN Series Auto Precharge Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, a precharge command need not be executed after each read operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval defined by IAPR is required before execution of the next command. CE latency 3 2 Precharge start cycle 2 cycle before the final data is output 1 cycle before the final data is output CK CL=2 Command READ ACTV out0 out1 out2 out3 lAPR Dout CL=3 Command READ ACTV out0 out1 out2 out3 lAPR Dout Note: Internal auto-precharge starts at the timing indicated by " ". At CLK = 50 MHz (I APR changes depending on the operating frequency.) 34 HB526C264EN Series, HB526C464EN Series Write with auto precharge: In this operation, since precharge is automatically performed after completing a burst write or single write operation, a precharge command need not be executed after each write operation. The command executed for the same bank after the execution of this command must be the bank active (ACTV) command. In addition, an interval of IAPW is requried between the final valid data input and input of the next command. Burst Write (Burst Length = 4) CK Command WRIT ACTV Din in0 in1 in2 in3 lAPW Single Write CK Command WRIT ACTV Din in lAPW 35 HB526C264EN Series, HB526C464EN Series Full-page Burst Stop Burst stop command during burst read: The burst stop (BST) command is used to stop data output during a full-page burst. The BST command sets the output buffer to High-Z and stops the full-page burst read. The timing from command input to the last data changes depending on the CE latency setting. In addition, the BST command is valid only during full-page burst mode, and is invalid with burst lengths 1, 2, 4 and 8. CE latency 2 3 BST to valid data 1 2 BST to high impedance 2 3 CE Latency = 2, Burst Length = full page CK Command Dout out out out out BST out out l BSH = 2 cycle l BSR = 1 cycle CE Latency = 3, Burst Length = full page CK Command BST Dout out out out out out out out l BSR = 2 cycle l BSH = 3 cycle 36 HB526C264EN Series, HB526C464EN Series Burst stop command at burst write: The burst stop command (BST command) is used to stop data input during a full-page burst write. No data is written in the same cycle as the BST command and in subsequent cycles. In addition, the BST command is only valid during full-page burst mode, and is invalid with burst lengths of 1, 2, 4 and 8. And an interval of tDPL is requried between the BST command and the next precharge command. Burst Length = full page CLK Command I/O (input) in in t DPL I BSW = 0 cycle BST PRE/PALL 37 HB526C264EN Series, HB526C464EN Series Command Intervals Read command to Read command interval: Same bank, same ROW address: When another read command is executed at the same ROW address of the same bank as the preceding read command execution, the second read can be performed after an interval of no less than 1 cycle. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (same ROW address in same bank) CK Command Address (A0-A10) BS (A11) READ ACTV READ Row Column A Column B Dout Bank0 Active Column =A Column =B Read Read out A0 out B0 out B1 out B2 out B3 Column =A Column =B Dout Dout CE Latency = 3 Burst Length = 4 Bank0 Same bank, different ROW address: When the ROW address changes on same bank, consecutive read commands cannot be executed; it is necessary to separate the two read commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second read can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. Even when the first command is a burst read that is not yet finished, the data read by the second command will be valid. READ to READ Command Interval (different bank) CK Command Address (A0-A10) BS (A11) ACTV ACTV READ READ Row 0 Row 1 Column A Column B Dout Bank0 Active Bank1 Active Bank0 Bank1 Read Read out A0 out B0 out B1 out B2 out B3 Bank0 Bank1 Dout Dout CE Latency = 3 Burst Length = 4 38 HB526C264EN Series, HB526C464EN Series Write command to Write command interval: Same bank, same ROW address: When another write command is executed at the same ROW address of the same bank as the preceding write command, the second write can be performed after an interval of no less than 1 cycle. In the case of burst writes, the second write command has priority. WRITE toWRITE Command Interval (same ROW address in same bank) CK Command Address (A0-A10) BS (A11) Din Bank0 Active in A0 in B0 in B1 in B2 in B3 ACTV WRIT WRIT Row Column A Column B Column =A Column =B Write Write Burst Write Mode Burst Length = 4 Bank0 Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two write commands with a precharge command and a bank-active command. Different bank: When the bank changes, the second write can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. In the case of burst write, the second write command has priority. WRITE to WRITE Command Interval (different bank) CK Command Address (A0-A10) BS (A11) Din Bank0 Active in A0 in B0 in B1 in B2 in B3 ACTV ACTV WRIT WRIT Row 0 Row 1 Column A Column B Bank1 Bank0 Bank1 Active Write Write Burst Write Mode Burst Length = 4 39 HB526C264EN Series, HB526C464EN Series Read command to Write command interval: Same bank, same ROW address: When the write command is executed at the same ROW address of the same bank as the preceding read command, the write command can be performed after an interval of no less than 1 cycle. However, DQMB must be set High so that the output buffer becomes High-Z before data input. READ to WRITE Command Interval (1) CK Command CL=2 READ WRIT DQMB CL=3 Din in B0 High-Z in B1 in B2 in B3 Dout Burst Length = 4 Burst write READ to WRITE Command Interval (2) CK Command READ WRIT DQMB 2 clock CL=2 High-Z High-Z Dout CL=3 Din Same bank, different ROW address: When the ROW address changes, consecutive write commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bankactive command. Different bank: When the bank changes, the write command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, DQMB must be set High so that the output buffer becomes High-Z before data input. 40 HB526C264EN Series, HB526C464EN Series Write command to Read command interval: Same bank, same ROW address: When the read command is executed at the same ROW address of the same bank as the preceding write command, the read command can be performed after an interval of no less than 1 cycle. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed. WRITE to READ Command Interval (1) CK Command WRIT READ DQMB Din Dout in A0 out B0 Column = A Write CE Latency Column = B Dout out B1 out B2 out B3 Burst Write Mode CE Latency = 2 Burst Length = 4 Bank 0 Column = B Read WRITE to READ Command Interval (2) CK Command WRIT READ DQMB Din Dout in A0 in A1 out B0 out B1 out B2 out B3 Burst Write Mode CE Latency = 2 Burst Length = 4 Bank 0 Column = A Write Column = B Read CE Latency Column = B Dout Same bank, different ROW address: When the ROW address changes, consecutive read commands cannot be executed; it is necessary to separate the two commands with a precharge command and a bank-active command. Different bank: When the bank changes, the read command can be performed after an interval of no less than 1 cycle, provided that the other bank is in the bank-active state. However, in the case of a burst write, data will continue to be written until one cycle before the read command is executed (as in the case of the same bank and the same address). 41 HB526C264EN Series, HB526C464EN Series Read command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the read command that preceded it, the minimum interval between the two commands is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by I HZP, there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by IEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): To output all data CE Latency = 2, Burst Length = 4 CK Command READ PRE/PALL Dout CL=2 out A0 out A1 out A2 out A3 l EP = -1 cycle CE Latency = 3, Burst Length = 4 CK Command READ PRE/PALL Dout CL=3 out A0 out A1 out A2 l EP = -2 cycle out A3 42 HB526C264EN Series, HB526C464EN Series READ to PRECHARGE Command Interval (same bank): To stop output data CE Latency = 2, Burst Length = 1, 2, 4, 8 CK Command READ PRE/PALL Dout out A0 l HZP =2 High-Z CE Latench = 3, Burst Length = 1, 2, 4, 8 CK Command READ PRE/PALL Dout l HZP =3 out A0 High-Z 43 HB526C264EN Series, HB526C464EN Series Write command to Precharge command interval (same bank): When the precharge command is executed for the same bank as the write command that preceded it, the minimum interval between the two commands is 1 cycle. WRITE to PRECHARGE Command Interval (same bank): However, if the burst write operation is unfinished, the input data must be masked by means of DQMB for assurance of the cycle defined by tDPL. WRITE to PRECHARGE Command Interval (same bank) Burst Length = 4 (To stop write operation) CLK Command WRIT PRE/PALL DQM Din t DPL CLK Command WRIT PRE/PALL DQM Din in A0 in A1 t DPL Burst Length = 4 (To write all data) CLK Command WRIT PRE/PALL DQM Din in A0 in A1 in A2 in A3 t DPL 44 HB526C264EN Series, HB526C464EN Series Bank active command interval: Same bank: The interval between the two bank-active commands must be no less than tRC. In the case of different bank-active commands: The interval between the two bank-active commands must be no less than tRRD. Bank active to bank active for same bank CK Command ACTV ACTV Address (A0-A10) BS (A11) ROW ROW t RC Bank 0 Active Bank 0 Active Bank active to bank active for different bank CK ACTV ACTV Command Address (A0-A10) ROW:0 ROW:1 BS (A11) t RRD Bank 0 Active Bank 1 Active 45 HB526C264EN Series, HB526C464EN Series Mode register set to Bank-active command interval: The interval between setting the mode register and executing a bank-active command must be no less than tRSA . CK Command MRS ACTV Address (A0-A11) CODE BS & ROW t RSA Mode Register Set Bank Active 46 HB526C264EN Series, HB526C464EN Series DQMB Control The DQMB mask the lower and upper bytes of the DQ data, respectively. The timing of DQMB is different during reading and writing. Reading: When data is read, the output buffer can be controlled by DQMB. By setting DQMB to Low, the output buffer becomes Low-Z, enabling data output. By setting DQMB to High, the output buffer becomes High-Z, and the corresponding data is not output. However, internal reading operations continue. The latency of DQMB during reading is 2. CK DQMB Dout High-Z out 0 out 1 out 3 lDOD = 2 Latency Writing: Input data can be masked by DQMB. By setting DQMB to Low, data can be written. In addition, when DQMB is set to High, the corresponding data is not written, and the previous data is held. The latency of DQMB during writing is 0. CK , DQMB Din in 0 in 1 in 3 l DID = 0 Latency 47 HB526C264EN Series, HB526C464EN Series Refresh Auto-refresh: All the banks must be precharged before executing an auto-refresh command. Since the autorefresh command updates the interval counter every time it is executed and determines the banks and the ROW addresses to be refreshed, external address specification is not requried. The refresh cycle is 4096 cycles/64 ms. (4096 cycles are required to refresh all the ROW addresses.) The output buffer becomes HighZ after auto-refresh start. In addition, since a precharge has been completed by an internal operation after the auto-refresh, an additional precharge operation by the precharge command is not requried. Self-refresh: After executing a self-refresh command, the self-refresh operation continues while CKE is held Low. During self-refresh operation, all ROW addresses are refreshed by the internal refresh timer. A selfrefresh is terminated by a self-refresh exit command. If you use distributed auto-refresh mode with 15.6 s interval in normal read/write cycle, auto-refresh should be executed within 15.6 s immediately after exiting from and before entering into self refresh mode. If you use address refresh or burst auto-refresh mode in normal read/write cycle, 4096 cycles of distributed auto-refresh with 15.6 s interval should be executed within 64 ms immediately after exiting from and before entering into self refresh mode. Others Power-down mode: The synchronous DRAM module enters power-down mode when CKE goes Low in the IDLE state. In power down mode, power consumption is suppressed by deactivating the input initial circuit. Power down mode continues while CKE is held Low. In addition, by setting CKE to High, the synchronous DRAM module exits from the power down mode, and command input is enabled from the next cycle. In this mode, internal refresh is not performed. Clock suspend mode: By driving CKE to Low during a bank-active or read/write operation, the synchronous DRAM module enters clock suspend mode. During clock suspend mode, external input signals are ignored and the internal state is maintained. When CKE is driven High, the synchronous DRAM module terminates clock suspend mode, and command input is enabled from th enext cycle. For details, refer to the "CKE Truth Table". Power-up sequence: During power-up sequence, the DQMB and the CKE must be set to High. When 200 s has past after power on, all banks must be precharged using the precharge command. After tRP delay, set 8 or more auto refresh commands. And set the mode register set command to initialize the mode register. 48 HB526C264EN Series, HB526C464EN Series Timing Waveforms Read Cycle t CK t CKH t CKL " , , , ! , " , , " ! ! CK t RC VIH CKE t RCD t RAS t RP , , ,,, , , , , , S t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH RE t CS t CH t CS t CH t CS t CH t CS t CH CE t CS t CH t CS t CH t CS t CH t CS t CH W t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH A11 t AS t AH t AS t AH t AS t AH A10 t AS t AH t AS t AH Address t CS t CH DQMB Din t AC t AC t AC Dout t AC Bank 0 Active Bank 0 Read t LZ t OH t OH t OH t HZ Bank 0 Precharge Burst length = 4 Bank0 Access = VIH or VIL 49 HB526C264EN Series, HB526C464EN Series Write Cycle , , ! ! " , " ! t CK t CKH t CKL CK t RC VIH CKE t RCD t RAS t RP t CS t CH t CS t CH t CS t CH t CS t CH S , , RE t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH t CS t CH CE t CS t CH t CS t CH t CS t CH t CS t CH W t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH A11 t AS t AH t AS t AH t AS t AH A10 t AS t AH t AS t AH Address t CS t CH DQMB t DS t DH tDS t DH t DS t DH t DS t DH Din t RWL Dout Bank 0 Active Bank 0 Write Bank 0 Precharge Burst length = 4 Bank0 Access = VIH or VIL 50 HB526C264EN Series, HB526C464EN Series Mode Register Set Cycle , A11(BS) Address DQMB Dout valid code R: b C: b C: b' b b+3 b' b'+1 b'+2 b'+3 , , ,, , , , , , , ,, , , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 CK CKE VIH S RE CE W Din High-Z t RP t RSA t RCD Output mask Precharge If needed Mode Bank 1 register Active Set Bank 1 Read tRCD = 3 CE Latency = 3 Burst Length = 4 = VIH or VIL 51 HB526C264EN Series, HB526C464EN Series Read Cycle/Write Cycle , ,, , , , , , , , , , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK S CKE VIH RE CE W A11(BS) Address DQMB Dout Din R:a C:a R:b C:b C:b' C:b" a a+1 a+2 a+3 b b+1 b+2 b+3 b' Bank 1 Read Read cycle RE-CE delay = 3 CE Latency = 3 Burst Length = 4 = VIH or VIL b'+1 b" b"+1 b"+2 b"+3 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Bank 1 Bank 0 Read Precharge Bank 1 Read Bank 1 Precharge CKE VIH S RE CE W Write cycle RE-CE delay = 3 CE Latency = 3 Burst Length = 4 = VIH or VIL A11(BS) Address DQMB Din R:a C:a R:b C:b C:b' C:b" Dout High-Z a a+1 a+2 a+3 Bank 1 Active b b+1 b+2 b+3 b' Bank 0 Precharge b'+1 b" b"+1 b"+2 b"+3 Bank 0 Active Bank 0 Write Bank 1 Write Bank 1 Write Bank 1 Write Bank 1 Precharge 52 HB526C264EN Series, HB526C464EN Series Read/Single Write Cycle , DQMB Din a b c Dout a a+1 a+3 Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge ,,, , , , ,, , , , , , , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK CKE VIH S RE CE W A11(BS) DQMB Address Din R:a C:a R:b C:a' C:a a Dout a a+1 a+2 a+3 a a+1 a+2 a+3 Bank 0 Precharge Bank 0 Active Bank 0 Read Bank 1 Active Bank 0 Bank 0 Write Read Bank 1 Precharge CKE VIH S RE CE W A11(BS) Address R:a C:a R:b C:a C:b C:c Read/Single write RE-CE delay = 3 CE Latency = 3 Burst Length = 4 = VIH or VIL 53 HB526C264EN Series, HB526C464EN Series Read/Burst Write Cycle 0 CK CKE S RE CE W A11(BS) Address DQMB Din Dout Bank 0 Active 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 R:a C:a R:b C:a a a+1 a+2 a+3 a a+1 a+2 Bank 0 Read Bank 1 Active Clock Suspend a+3 Bank 0 Write Bank 0 Precharge Bank 1 Precharge CKE S RE CE W A11(BS) Address DQMB Din Dout VIH R:a C:a R:b C:a a a+1 a+2 a+3 a a+1 Bank 0 Active Bank 0 Read Bank 1 Active a+3 Bank 0 Write Bank 0 Precharge Read/Burst write RE-CE delay = 3 CE Latency = 4 Burst Length = 4 = VIH or VIL 54 HB526C264EN Series, HB526C464EN Series Full Page Read/Write Cycle * " . 0 & 0- , & " . ' * . 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CK CKE VIH S RE CE W Read cycle RE-CE delay = 3 CE Latency = 3 Burst Length = full page = VIH or VIL A11(BS) Address DQMB Dout R:a C:a R:b a a+1 a+2 a+3 a-2 a-1 a a+1 a+2 a+3 a+4 a+5 Din High-Z Bank 0 Active Bank 0 Read Bank 1 Active Burst stop Bank 1 Precharge CKE VIH S RE CE W Write cycle RE-CE delay = 3 CE Latency = 3 Burst Length = full page = VIH or VIL A11(BS) Address DQMB Dout Din R:a C:a R:b High-Z a a+1 a+2 a+3 a+4 a+5 a+6 a+1 a+2 a+3 a+4 a+5 Bank 0 Active Bank 0 Write Bank 1 Active Burst stop Bank 1 Precharge 55 HB526C264EN Series, HB526C464EN Series Auto Refresh Cycle , -$ , &*, ' & ! - , ' & * $ + , + & t RP t RC tRC Precharge If needed Auto Refresh Auto Refresh Active Bank 0 Read Bank 0 , , ,, , ,, , , , , , , , , , , , ,, , , , , , ,, ,, ,, 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK CKE VIH S RE CE W A11(BS) Address A8=1 R:a C:a DQMB Din Dout High-Z a a+1 Refresh cycle and Read cycle RE-CE delay=2 CE latency=2 Burst length=4 = VIH or VIL Self Refresh Cycle CK l SREX CKE S CKE Low RE CE W A11(BS) Address DQMB A10=1 Din Dout High-Z tRP tRC tRC Precharge command If needed Self refresh entry command Self refresh exit ignore command or No operation Next clock enable Self refresh entry command Auto Next clock refresh enable Self refresh cycle RE-CE delay = 3 CE Latency = 3 Burst Length = 4 = VIH or VIL 56 HB526C264EN Series, HB526C464EN Series Clock Suspend Mode , ,,,, , , ,, , , , , , ,,, t CESP t CEH t CES , 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CK CKE S RE CE W Read cycle RE-CE delay=2 CE latency=2 Burst length=4 = VIH or VIL A11(BS) Address DQMB Dout R:a C:a R:b C:b a a+1 a+2 a+3 b b+1 b+2 b+3 Din High-Z Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank1 Active Read suspend start Read suspend end Bank1 Read Bank0 Precharge Earliest Bank1 Precharge CKE S RE CE W Write cycle RE-CE delay=2 CE latency=2 Burst length=4 = VIH or VIL A11(BS) Address DQMB Dout R:a C:a R:b C:b High-Z Din a a+1 a+2 a+3 b b+1 b+2 b+3 Bank0 Active Active clock suspend start Active clock Bank0 Bank1 supend end Write Active Write suspend start Write suspend end Bank1 Bank0 Write Precharge Earliest Bank1 Precharge 57 HB526C264EN Series, HB526C464EN Series Power Down Mode Precharge command If needed Power down entry Power down mode exit Active Bank 0 , , , , , , , , , ,,, , ,, , , , CK CKE CKE Low S RE CE W A11(BS) Address DQMB Din A10=1 R: a Dout High-Z tRP Power down cycle RE-CE delay=3 CE latency=2 Burst length=4 = VIH or VIL Power Up Sequence 0 1 2 3 4 5 6 7 8 9 10 48 49 50 51 52 53 54 55 CK CKE VIH S RE CE W Address DQMB Din/out VIH Valld code Valld High-Z tRP All banks Auto Refresh Precharge tRC Auto Refresh tRC tRSA Mode register Bank active Set If needed 58 HB526C264EN Series, HB526C464EN Series Physical Outline HB526C264EN Series Unit: mm / inch Front side 133.35 5.250 3.00 0.118 127.35 5.014 2.92 max 0.115 max ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, C B 36.83 1.450 54.61 2.150 A 11.43 0.450 , , , , , , , , , 8.89 0.350 3.00 0.118 1.27 0.10 0.050 0.004 Back side 2 - 3.00 2 - 0.118 4.00 0.157 17.78 0.700 Detail A 2.54 min 0.100 min Detail B 1.27 0.050 0.25 max 0.010 max Detail C 1.00 0.039 3.125 0.125 0.123 0.005 1.00 0.05 0.039 0.002 3.125 0.125 0.123 0.005 6.35 0.250 2.00 0.10 0.079 0.004 6.35 0.250 2.00 0.10 0.079 0.004 25.40 1.000 4.00 min 0.157 min 168 85 59 HB526C264EN Series, HB526C464EN Series HB526C464EN Series Unit: mm / inch Front side 133.35 5.250 3.00 0.118 127.35 5.014 4.00 max 0.115 max ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, C B 36.83 1.450 54.61 2.150 A 11.43 0.450 ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , 8.89 0.350 3.00 0.118 1.27 0.10 0.050 0.004 Back side 2 - 3.00 2 - 0.118 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 168 85 4.00 0.157 17.78 0.700 Detail A 2.54 min 0.100 min Detail B 1.27 0.050 0.25 max 0.010 max Detail C 1.00 0.039 3.125 0.125 0.123 0.005 1.00 0.05 0.039 0.002 60 3.125 0.125 0.123 0.005 6.35 0.250 2.00 0.10 0.079 0.004 6.35 0.250 2.00 0.10 0.079 0.004 25.40 1.000 4.00 min 0.157 min HB526C264EN Series, HB526C464EN Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 61 HB526C264EN Series, HB526C464EN Series Revision Record Rev. 0.0 1.0 Date Contents of Modification Drawn by S. Tsukui T. Sato Approved by K. Tsuneda K. Tsuneda Aug. 20, 1996 Initial issue Feb. 28, 1997 Change of Serial PD matrix AC Characteristics tAC max (CL = 3): 8/9.5 ns to 7.5/9 ns Change of symbol: t RWL to tDPL Change of description for Self-refresh Timing Waveforms: Change of Self-refresh Mar. 17, 1997 Change of Serial PD matrix 2.0 62 |
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