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| R ST9+ FAMILY PROGRAMMING MANUAL PRELIMINARY DATA INTRODUCTION The ST9 8/16 bit microcontroller family introduces a new generation of single-chip architecture. It offers fast program execution, efficient use of memory, sophisticated interrupt handling, input/output (I/O) flexibility and bit-manipulation capabilities, with easy system expansion. Virtually all of the ST9 configuration can be tailored to the needs of the user under program control. This enables the ST9 to serve as an I/O intensive microcontroller, as an intelligent peripheral controller within a larger system, or as a memory intensive microprocessor. Programming of the ST9 is made easy in both high level languages such as C, or directly in assembler language, by the versatility of the 14 addressing modes coupled with the comprehensive instruction set operating on bits, BCD, 8 bit bytes and 16 bit words. The availability of the Register File, giving the programmer multiple 8 and 16 bit accumulators and index pointers, the fast interrupt response time, on-chip DMA and on-chip and external memory access capabilities give the ST9 a high efficiency for real-time control applications. The ST9 has a range of family devices made up from various memory combinations (RAM, ROM/ EPROM, EEPROM), powerful peripherals such as Multifunction Timers, Analog to Digital Converters, Serial Communications Interfaces and a standard Core. The remainder of this section describes in more detail the ST9 features of primary interest to assembly language programmers. Please refer to the ST9 Technical Manual for detailed architectural and configuration information. Note: This Programming Manual follows the syntax of the ST9 Software Tools (TR9 and GAS9, high-level Macro Assembler running under MS-DOS or WindowsTM, SUN-SPARC under SunOS or SolarisTM). Register and bit names follow the recommendations of the symbols.inc file available with tools. November 1997 This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice. 1/298 1 Table of Contents INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . 1 1 SOFTWARE DESCRIPTION . . . . . . . . . . . . 5 1.1 ADDRESSING MODES . . . . . . . . . . . 5 1.2 INSTRUCTION SET . . . . . . . . . . . . . 17 1.3 INSTRUCTION SUMMARY . . . . . . . 24 2 OPCODE MAP . . . . . . . . . . . . . . . . . . . . . 57 3 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . 65 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 ADCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 ADCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 ADCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ADCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 ADCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 ADCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 ADCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 ADDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 ANDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 ANDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 ANDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 ANDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 ANDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ANDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 ANDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 BAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 BCPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 BLD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 BOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 BRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 BSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 BTJF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 BTJT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 BTSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 BXOR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 CALLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 CCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 CPJFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 CPJTI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 CPW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 CPW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 CPW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 CPW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 CPW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 CPW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 CPW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 DA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 DA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 DECW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 DIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 DIVWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 DIVWS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 DJNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 DWJNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 HALT . . . . . . . . . . . . . . . . . . . . . . . . . 298 . . 153 ... INC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 INCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 2/298 1 Table of Contents IRET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 JP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 JPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 JPcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 JRcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 LDPP LDDP . . . . . . . . . . . . . . . . . . . . . . . 168 LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LDW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 LINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 LINKU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 ORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 ORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 ORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 ORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 ORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 ORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 PEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 PEAU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 POPU. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 POPUW . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 POPW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 PUSHU . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 PUSHUW . . . . . . . . . . . . . . . . . . . . . . . . . . 201 PUSHW . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 RCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 RETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 RLC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 RLCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 ROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 ROR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 RRC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 RRCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 SBCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 SBCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 SBCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 SBCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 SBCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 SBCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 SBCW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 SCF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 SDM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 SLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 SLAW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 SPP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 SRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 SRAW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 SRP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 SRP0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 SRP1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 SUBW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 SWAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 TCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 TCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 3/298 1 Table of Contents TCM . . TCM . . TCM . . TCM . . TCM . . TCMW TCMW TCMW TCMW TCMW TCMW TCMW TM . . . TM . . . TM . . . TM . . . TM . . . TM . . . TM . . . TMW . TMW . TMW . TMW . ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ...... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... ....... .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. .. 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 TMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 TMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 TMW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 UNLINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 UNLINKU . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 WFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 XCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 XORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 XORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 XORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 XORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 XORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 XORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 XORW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 298 4/298 1 ST9+ Programming Manual 1 SOFTWARE DESCRIPTION 1.1 ADDRESSING MODES The ST9 offers a wide variety of established and new addressing modes and combinations to facilitate full and rapid access to the address spaces while reducing program length. The available addressing modes are shown in Table 1-1: Single operand arithmetic, logic and shift byte instructions have direct register and indirect register addressing modes. For a full list of the possible combinations for each instruction type, please refer to the ST9 Programming Manual. Table 1. Addressing Modes Operand is In Instruction Addressing Mode Immediate Direct Register File Indirect Indexed Indirect Post-Increment Direct Indirect Indirect Post-Increment Memory Indirect Pre-Decrement Short Indexed Long Indexed Register Indexed Any bit of any working register Any bit in program or data memory Program Memory Direct Indirect Direct Relative Indirect Destination Location Byte Word Byte Word Byte/Word Byte/Word Byte Byte/Word Byte/Word Byte/Word Byte/Word Byte/Word Byte/Word Byte/Word Bit Bit Notation #N #NN r rr (r) N(r) (r)+ NN (rr) (rr)+ -(rr) N(rrx) NN(rrx) rr(rrx) r.b (rr).b NN N (rr) (RR) R RR (R) 5/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Two Operands Arithmetic and Logic Instructions Destination Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Indirect Memory Indirect Memory Indexed Memory Indirect with Post-Increment Memory Indirect with Pre-Decrement Memory Direct Register Direct Memory Direct Memory Indirect Register Direct Register Indirect Memory Indirect Memory Indexed Memory Indirect with Post-Increment Memory Indirect with Pre-Decrement Memory Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Immediate Immediate Immediate Source 6/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Two Operands Load Instructions Destination Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Indirect Register Indexed Memory Indirect Memory Indexed Memory Indirect with Post-Increment Memory Indirect with Pre-Decrement Memory Direct Register Direct Memory Direct Memory Indirect Memory Indexed 1) Register Direct Register Indirect Register Indexed Memory Indirect Memory Indexed Memory Indirect with Post-Increment Memory Indirect with Pre-Decrement Memory Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Register Direct Immediate Immediate Immediate Immediate Source Two Operands Load Instructions2) Destination Register Indirect with Post-Increment Memory Indirect with Post-Increment Memory Indirect with Post-Increment Source Memory Indirect with Post-Increment Register Indirect with Post-Increment Memory Indirect with Post-Increment Notes: 1. Word Instructions Only 2. Load Byte Only 7/298 ST9+ Programming Manual ADDRESSING MODES (Continued) 1.1.1 Register Addressing Modes Immediate Addressing Mode In the Immediate addressing mode, the data is found in the instruction. When using immediate data, a hash-mark (#) is used to distinguish it from an absolute address in memory. Example: ldw RR42,#65535 loads the immediate value 65535 into the register pair R42 & R43. While the example shows decimal data, hexadecimal and binary values may also be used. Example: ldw RR42, #0FFFFh Figure 1. Immediate Register Addressing Mode In the Instruction In a Working Register In an Absolute Register In Memory IMMEDIATE DATA Direct Addressing Mode In the direct addressing mode, a register can be addressed by using its absolute address in the Register File (in decimal, hexadecimal or binary form). Alternatively a register can be addressed directly as a working register; Example: xch R0A2h,r4 exchanges the values in the register RA2h and working register number 4. Figure 2. Direct Register Addressing Mode In the Instruction In a Working Register In an Absolute Register In Memory REGISTER DIRECT REGISTER ADDRESS REGISTER ADDRESS DATA DATA 8/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Indirect Addressing Mode In the Indirect Register Addressing mode, the address of the data does not appear in the instruction but is located in a working register. The address of this register is given in the instruction. The indirect addressing mode is indicated by the use of parentheses. Example: If register 200 contains 178 and working register 11 contains 86 then the instruction ld (r11),R200 loads the value 178 into register 86. Note: the indirect address can only be contained in a working register. Figure 3. Indirect Register Addressing Mode In the Instruction In a Working Register In an Absolute Register In Memory INDIRECT REGISTER REGISTER ADDRESS ADDRESS DATA Indexed Addressing Mode To address a register using the Indexed mode, an offset value is used to add to an index value (which acts as a base or starting value). The offset value is the Immediate value given in the instruction while the index value is given by the contents of the working register. Example: if working register 10 contains 55 then the instruction ld 40(r10),r18 loads register 95 (i.e.55+40) with the contents of working register 18. The Register File never needs an absolute value requiring more than one byte and therefore only requires a short offset and a single register to contain the index. Note: The index value can only be contained in a working register. Figure 4. Indexed Register Addressing Mode INDIRECT REGISTER WITH POST-INCREMENT In the Instruction In a Working Register In an Absolute Register In Memory REGISTER ADDRESS OFFSET ADDRESS + DATA 9/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Register Indirect Post-increment Addressing Mode In this addressing mode, both destination and source addresses are given by the contents of working registers which are then post-incremented. The address of the memory location is contained in a working register pair, and the address of the register is contained into a single working register. Only working registers may be used to contain the addresses, this mode being indicated by both source and destination using parentheses followed by plus sign. Example: if working register 8 contains the value 44, working register pair rr2 contains the value 2000, and register 44 contains the value 56, then by using the instruction ld (rr2)+,(r8)+ the memory location 2000 will be loaded with the value 56. Immediately following this, the contents of r8 is incremented to 45 and the contents of rr2 is incremented to 2001. This addressing mode is useful for moving blocks of data either from Register File to Memory or from Memory to Register File. Figure 5. Register Indirect Post-increment Addressing Mode INDIRECT REGISTER WITH POST-INCREMENT In the Instruction In a Working Register In an Absolute Register In Memory REGISTER ADDRESS ADDRESS DATA +1 ADDRESS HIGH REGISTER ADDRESS ADDRESS LOW DATA +1 Direct Bit Addressing Mode In the direct bit addressing mode, any bit in any working register can be addressed Examples: bset r7.3 This instruction sets the bit 3 of the working register 7. bld r7.3, r12.6 This instruction loads the bit 6 of the working register 12 in bit 3 of working register 7. 10/298 ST9+ Programming Manual ADDRESSING MODES (Continued) 1.1.2 Memory Addressing Modes The memory addressing modes described in this section are available to data and program memory. Thus before addressing the memory, it is necessary to indicate by use of the Set Program/Data Memory instructions, spm and sdm, in which memory the instructions are working. Since each memory space is 64K byte long, a word address is necessary to specify memory locations. Direct Addressing Mode The Memory Direct addressing mode requires the specific location within the memory. This only needs the absolute offset value which can be given in decimal, hex or binary form. Thus the instruction: ld 12345,r9 loads working register 9 data into memory location 12345 In the memory direct mode, it is possible to use an immediate addressing mode for the source operand. Examples: ld 12354,#34 will load the value 34 into the memory location 12354. ldw 12354,#3457 will load the location pair 12354 and 12355 with the value 3457. Figure 6. Memory Direct Addressing Mode In the Instruction In a Working Register In an Absolute Register In Memory DIRECT MEMORY ADDRESS HIGH ADDRESS LOW DATA 11/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Indirect Addressing Mode When using the indirect addressing mode to access memory, the address is contained in a pair of working registers. Example: if the working register pair r8 and r9 contains the value 2000 then the instruction ld (rr8),#34 loads the value 34 into memory location 2000. If the data to be stored is a word then the instruction ldw will automatically interpret the address as a pair of memory locations. So if rr8 contains 2000 then the instruction ldw (rr8),#3 467 loads the memory locations 2000 and 2001 with the value 3467. Figure 7. M emory Indirect Addressing Mode In the Instruction In a Working Register In an Absolute Register In Memory DIRECT MEMORY REGISTER ADDRESS ADDRESS HIGH ADDRESS LOW DATA 12/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Indirect With Post-increment Adressing Mode The indirect with post-increment addressing mode is similar to the memory indirect addressing mode but, in addition, after accessing the data in the currently pointed address, the value in the pointing working register pair is incremented. This mode is indicated by a plus sign following a working register pair in parentheses, e.g. (rr4)+. Example:If the working register pair rr4 (working registers r4 and r5) contains the value 3000 and memory location 3000 contains the value 88, then the instruction ld R50,(rr4)+ loads register 50 with the value 88 and then the value in rr4 to be incremented to 3001. This mode uses only working registers to contain the address. Thus the Indirect with Post-Increment addressing mode is most useful in repeated situations when a number of adjacent items of data are required in succession. The use of this addressing mode saves both time and program memory space since it cuts the usual increment instruction. Figure 8. Memory Indirect Post-Increment Addressing Mode INDIRECT MEMORY WITH POST-INCREMENT In the Instruction REGISTER ADDRESS In a Working Register ADDRESS HIGH ADDRESS LOW In an Absolute Register In Memory DATA +1 13/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Indirect With Pre-decrement Addressing Mode This indirect memory addressing mode has an automatic pre-decrement. The address can only be contained in working registers and the mode is indicated by a minus sign in front of the working registers which are in parentheses, e.g. -(rr6). Example: if the working register pair rr6 contains the value 1111 and location 1110 contains the value 40 then the instruction ld R56,-(rr6) decrements the value in rr6 to 1110 and then loads the value 40 into register 56. This addressing mode allows the ST9 to deal in the reverse order with data previously managed using the indirect post-increment mode without resetting the pointing registers (of the last post-increment). The pre-decrement mode has the same benefits of time and program memory saving as the post-increment mode. Figure 9. Memory Indirect Pre-Decrement Addressing Mode INDIRECT MEMORY WITH PRE-DECREMENT In the Instruction REGISTER ADDRESS In a Working Register ADDRESS HIGH ADDRESS LOW In an Absolute Register -1 In Memory DATA 14/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Indexed Addressing Modes There are three indexed addressing modes, each using an indirect address plus offset format. The index address is given as an indirect address contained in a working register pair, while the offset can be long or short (a word or a byte). The address of the data required is given by the value of the working register pair indicated (the index), plus the value of the given offset. Indexed with an Immediate Short and Long Offset In these indexed modes the offset is a fixed and Immediate value included in the instruction. It may be either a short or long index as required, this immediate value being added to the address given by the working register pair. The short offset is signed-extensed to 16-bits before being added to the register pair. Example: if the working register pair, rr6, contains the value 8000 and memory location 8034 contains the value 254 then the instruction ld R55,34(rr6) loads the value 254 into register 55. Or, as another example, if the working register pair rr2 contains the value 2000 and register 78 contains the value 34 then the instruction. ld 322(rr2),r78 loaded the value 34 into memory location 2322. Figure 10. Memory Indexed with Immediate Short Offset Addressing Mode In the Instruction In a Working Register INDEX HIGH INDEXED MEMORY WITH IMMEDIATE SHORT OFFSET REGISTER ADDRESS OFFSET INDEX LOW In an Absolute Register In Memory + DATA Figure 11. Memory Indexed with Immediate Long Offset Addressing Mode In the Instruction In a Working Register INDEX HIGH REGISTER ADDRESS OFFSET HIGH OFFSET LOW INDEX LOW In an Absolute Register In Memory + DATA INDEXED MEMORY WITH IMMEDIATE LONG OFFSET 15/298 ST9+ Programming Manual ADDRESSING MODES (Continued) Indexed with a Register Offset In this addressing mode, the index is supplied by one pair of working registers and the offset is supplied by a second pair of working registers. The format is rrx(rry), x and y being in the range 0,2,4...12,14. Example: If working register pair rr0 contains the value 2222 and working register pair rr4 contains 3333 while register 45 contains the value 78 then the instruction ld rr4(rr0),R45 loads the value 78 into memory location 5555. Figure 12. Memory Indexed with Register Offset Addressing Mode In the Instruction In a Working Register INDEX HIGH REGISTER ADDRESS REGISTER ADDRESS INDEX LOW OFFSET HIGH OFFSET LOW In an Absolute Register In Memory + DATA INDEXED MEMORY WITH IMMEDIATE LONG OFFSET Indirect Memory Bit Addressing Mode In the indirect memory bit addressing mode, any bit of Program/Data memory location can be addressed with the btset (Bit Test and SET) instruction. Example btset (rr8).3 This instruction sets bit 3 of the memory location addressed by the working registers r8, r9 contents. 16/298 ST9+ Programming Manual 1.2 INSTRUCTION SET The ST9+ instruction set consists of 94 instruction types which can be divided into eight groups: - Load (two operands) - Multiply & Divide (two or three operands) - Arithmetic & logic (two operands) - Boolean (one or two operands) - Arithmetic Logic and Shift (one operand) - Program Control (zero to two operands) - Stack (one or two operands) - Miscellaneous (zero to two operands) The wide range of instructions eases use of the register file and memory, reducing operation times, while the register pointers mechanism allows an unmatched code efficiency and ultrafast context switching. A particularly notable feature is the comprehensive "Any Bit, Any Register" (ABAR) addressing capability of the Boolean instructions. The ST9 can operate with a wide range of data lengths from single bits, 4-bit nibbles which can be in the form of Binary Coded Decimal (BCD) digits, 8-bit bytes, and 16-bit words. The following summary shows the instructions belonging to each group and the number of operands required for each instruction. The source operand is "src", "dst" is the destination operand, and "cc" is a condition code. Table 2. Load Instructions (Two Operands) Mnemonic LD LDW LDPP LDPD LDDP LDDD Operands dst,src dst,src dst,src dst,src dst,src dst,src Load Load Word Load Load Load Load (using (using (using (using CSR) -> (using CSR) DPRx) -> (using CSR) CSR) -> (using DPRx) DPRx) -> (using DPRx) Instruction Table 3. .Arithmetic and Logic Instructions (Two Operands) Mnemonic ADD ADDW ADC ADCW SUB SUBW SBC SBCW AND ANDW OR ORW XOR XORW CP CPW TM TMW TCM TCMW Operands dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src dst,src Add Add Word Add With carry Add Word With Carry Substract Substract Word Substract With Carry Substract Word With Carry Logical AND Logical Word AND Logical OR Logical Word OR Logical Exclusive OR Logical Word Exclusive OR Compare Compare Word Test Under Mask Test Word Under Mask Test Complement Under Mask Test Word Complement Under Mask Instruction 17/298 ST9+ Programming Manual INSTRUCTION SET (Continued) Table 4. Arithmetic Logic and Shift Instructions (One Operand) Mnemonic INC INCW DEC DECW SLA SLAW SRA SRAW RRC RRCW RLC RLCW ROR ROL CLR CPL SWAP DA dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst dst Operands Increment Increment Word Decrement Decrement Word Shift Left Arithmetic Shift Word Left Arithmetic Shift Right Arithmetic Shift Word Right Arithmetic Rotate Right Through Carry Rotate Word Right Through Carry Rotate Left Through Carry Rotate Word Left Through Carry Rotate Right Rotate Left Clear Register Complement Register Swap Nibbles Decimal Adjust Instruction Table 5. Stack Instructions (One or two Operands) Mnemonic PUSH PUSHW PEA POP POPW PUSHU PUSHUW PEAU POPU POPUW LINK UNLINK LINKU UNLINKU src src src dst dst src src src dst dst Frame Pointer, Size (use system stack) Frame Pointer (use system stack) Frame Pointer, Size (use user stack) Frame Pointer (use user stack) Operands Instruction Push on System Stack Push Word on System Stack Push Effective Address on System Stack Pop From System Stack Pop Word from System Stack Push on User Stack Push Word on User Stack Push Effective Address on User Stack Pop From User Stack Pop Word From User Stack Move Stack Pointer upward; support for high-level language Move Stack Pointer backward; support for high-level language Move Stack Pointer upward; support for high-level language Move Stack Pointer backward; support for high-level language Table 6. Multiply and Divide Instructions (Two or three Operands) Mnemonic MUL DIV DIVWS Operands dst,src dst,src dsth,dstl,src Multiply 8x8 Divide 16/8 Divide Word Stepped 32/16 Instruction 18/298 ST9+ Programming Manual INSTRUCTION SET (Continued) Table 7. Boolean Instructions (One or Two Operands) Mnemonic BSET BRES BCPL BTSET BLD BAND BOR BXOR dst dst dst dst dst,src dst,src dst,src dst,src Operands Bit Set Bit Reset Bit Complement Bit Test and Set Bit Load Bit AND Bit OR Bit XOR Instruction Table 8. Program Control Instructions (Zero, One, or Two Operands) Mnemonic RET RETS IRET JRcc JPcc JP JPS CALL CALLS BTJF BTJT DJNZ DWJNZ CPJFI CPJTI dst dst dst dst dst dst 1) src,N src,N dst,N dst,N src1, src2, N src1, src2, N 1) Operands Return from Subroutine Instruction Inter-segment Return to Subroutine Return from Interrupt Jump Relative If Condition is Met Jump if Condition is Met Unconditional Jump Unconditional Inter-segment Jump Unconditional Call Inter-segment Call to Subroutine Bit Test and Jump if False Bit Test and Jump if True Decrement a Working Register and Jump if Non Zero Decrement a Register Pair and Jump if Non Zero Compare and Jump on False. Otherwise Post Increment Compare and Jump on True. Otherwise Post Increment 1) There are two operands for JPS and CALLS: -- the destination segment (1 byte) - the destination address (2 bytes) 19/298 ST9+ Programming Manual INSTRUCTION SET (Continued) Table 9. Miscellaneous (None, One or Two Operands) Mnemonic XCH SRP SRP0 SRP1 SPP EXT EI DI SCF RCF CCF SPM SDM NOP src src src src dst Operands dst,src Exchange Registers Set Register Pointer Long (16 working registers) Set Register Pointer 0 (8 LSB working register) Set Register Pointer 1 (8 MSB working register) Set Page Pointer Sign Extend Enable Interrupts Disable Interrupts Set Carry Flag Reset Carry Flag Complement Carry Flag Select Extended Memory addressing scheme through CSR Register Select Extended Memory addressing scheme through DPRx Registers No Operation Stop Program Execution and Wait for the next Enabled Interrupt. If a DMA request is present, the CPU executes the DMA service routine and then automatically returns to the WFI Stop Program Execution Until Next System Reset Instruction WFI HALT 20/298 ST9+ Programming Manual INSTRUCTION SET (Continued) 1.2.1 ST9 Processor Flags An important feature of a single chip microcomputer is the ability to test data and make the appropriate action based on the results. In order to provide this facility, FLAGR (register 231) in the register file is used as a flag register. Six bits of this register are used as the following flags: Bit 7: C - Carry Bit 6: Z - Zero Bit 5: S - Sign Bit 4: V - Overflow Bit 3: D - Decimal Adjust Bit 2: H - Half Carry Bit 1 is reserved for emulation, and should be always written as 0. Bit 0 selects extended memory addressing scheme through CSR or DPRx registers. The Flag Register is further described in the Architecture Chapter. 1.2.2 Condition Codes Flags C, Z, S, and OV control the operation of the "conditional" Jump instructions. The next table shows the condition codes and the flag settings. Note : Some of the Status flags are used to indicate more than one condition e.g. Zero and Equal. In such cases the condition code is the same for both conditions. Table 10. Condition Codes Table Mnemonic code F T C NC Z NZ PL MI OV NOV EQ NE GE LT GT LE UGE ULT UGT ULE Meaning Always False Always True Carry Not carry Zero Not Zero Plus Minus Overflow No Overflow Equal Not Equal Greater Than or Equal Less Than Greater Than Less Than or Equal Unsigned Greater Than or Equal Unsigned Less Than Unsigned Greater Than Unsigned Less Than or Equal Flag setting ____ ____ C=1 C=0 Z=1 Z=0 S=0 S=1 V=1 V=0 Z=1 Z=0 (S xor V)=0 (S xor V)=1 (Z or(S xor V))=0 (Z or(S xor V))=1 C=0 C=1 (C=0 and Z=0)=1 (C or Z)=1 Hex. value 0 8 7 F 6 E D 5 4 C 6 E 9 1 A 2 F 7 B 3 Binary value 0000 1000 0111 1111 0110 1110 1101 0101 0100 1100 0110 1110 1001 0001 1010 0010 1111 0111 1011 0011 21/298 ST9+ Programming Manual INSTRUCTION SET (Continued) 1.2.3 Notation Operands and status flags are represented by a notational shorthand in the detailed instruction description (see programming manual). The notation for operands (condition codes and address modes) and the actual operands they represent are as follows: Table 11. Notation (Part 1) Notation cc #N #NN r R rr RR (r) (R) (r)+ N(rx) N NN (rr) (rr)+ -(rr) N(rrx) Significance Condition Code Immediate Byte Immediate Word Working Register Direct Register Direct Working Register Pair Direct Register Pair Indirect Working Register Indirect register Indirect working register post increment Indexed register Memory relative Short Address Direct Memory Long Address Indirect Pair of Working Register Pointers Indirect Pair of Working Register Pointers with Post Increment Indirect Pair of Working Register Pointers with Pre Decrement Indexed Pair of Working Register Pointers with Short Offset (rrn) (rrn)+ -(rrn) N(rrx) # data # data rn Rn rrn RRn (rn) (Rn) (rn)+ N(rx) where data is a byte expression where data is a word expression where n=0-15 where n=0-255, except 208-223 where n is an even number in the range 0-14. (n=0,2,4,6....14) where n is an even number in the range 0-254. (n=0,2,4,6....254) except 208-222 where n=0-15 where n=0-255 where n=0-15 where x=0-15; N=0-255 (one byte) Program label or expression in the range +127/-128 starting from the address of the next instruction Program label or expression in the range 0-65535 in memory area Where n is an even number in the range 0-14.(n=0,2,4,6....14) where n is an even number in the range 0-14.(n=0,2,4,6....14) where n is an even number in the range 0-14.(n=0,2,4,6....14) where x is an even number in the range 0-14.(x=0,2,4,6....14) and N is a signed one byte expression between +127/-128 Actual Operand/Range 22/298 ST9+ Programming Manual INSTRUCTION SET (Continued) Table 12. Notation (Part 2) Notation Significance Indexed Pair of Working Register Pointers with Long Offset Indexed Pair of Register Pointers with Short Offset Indexed Pair of Register Pointers with Long Offset Indexed Pair of Working Registers with a Pair of Working Registers used as Offset Bit pointer in a direct working register Bit pointer in a Memory Location using a Pair of Indirect Working Registers as Address Pointer Indirect pair of Register Pointer Actual Operand/Range where x is an even number in the range 0-14.(x=0,2,4,6....14) and NN is word expression in the range between 0 and 65535 where x is an even number in the range 0-254.(x=0,2,4,6...254) and N is a one byte signed expression in the range +127/-128 where x is an even number in the range 0-254.(x=0,2,4,6....14) and NN is word expression in the range between 0 and 65535 where n and x are two even numbers in the range 0-14. (n,x=0,2,4,6....14) n=0.15 b is a number between 0-7; 0 is LSB, 7 is MSB where n is an even number in the range 0-14.(n=0,2,4,6....14) b is a number between 0-7; 0 is LSB, 7 is MSB where n is an even number in the range 0-255.(n=0,2,4,6....254) NN(rrx) NN(rrx) N(RRx) N(RRx) NN(RRx) NN(RRx) rr(rrx) rrn(rrx) r.b rn.b (rr).b (rrn).b (RR) (RRn) Table 13. Symbols Symbol dst src OPC XTN ofs ofd r.b SSP USP PC CC C Z S V D CIC btd Meaning Destination Operand Source Operand Operation Code Operation Code Extension Source Offset Destination Offset Bit and Working Register System Stack Pointer User Stack Pointer Program Counter Condition Code Carry Flag Zero Flag Sign Flag Overflow Flag Decimal Adjust Flag Central Interrupt Control Register Source Bit of Working Register Assignment of Result 23/298 ST9+ Programming Manual 1.3 INSTRUCTION SUMMARY The following tables summarize the operation for each of the instructions which are listed with their corresponding mnemonic codes, addressing modes, byte counts, timing information, and affected flags. GENERAL NOTES: FLAGS STATUS: - ^ : affected - - : not affected - 0 : reset to zero - 1 : set to one - ? : undefined Note: for detailed information on the instruction set refer to the ST9+ programming manual. - dst: destination operand - src: source operand - SSP: system stack pointer - USP: user stack pointer - PC: program counter - cc: condition code - C: carry flag - CPR: code page register - Z: zero flag - S: sign flag - V: overflow flag - D: decimal adjust flag - CIC: central interrupt control register - DP : selects extended memory addressing scheme through CSR or DPRx registers. TIMING INFORMATION: The number of clock cycles given is valid when no wait states are added to memory accesses. In order to facilitate the evaluation of timings when wait states are added to memory access, two additional columns are given: P and D. P gives the number of accesses to program memory for instruction fetch: if wait states are added when accessing the memory containing the code, the number of these wait states, multiplied by the value of column P, must be added to the instruction duration. The same applies to column D, which gives the number of accesses needed for operands; these are typically in data memory, unless (except for stack operations, which are always performed with data memory) bit 0 of the FLAGS register is 0 (e.g. after executing the SPM instruction). 24/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 12 12 14 14 12 14 14 16 16 14 14 14 6 6 10 16 14 14 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ADC : Addition of two bytes with carry ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC ADC r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 3 3 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C rr<-rr+1 dst<-dst+src+C rr<-rr+1 rr<-rr-1 dst<-dst+src+C rr<-rr-1 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C rr<-rr+1 dst<-dst+src+C rr<-rr+1 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C rr<-rr-1 dst<-dst+src+C rr<-rr-1 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C ^^^^0^ ^^^^0^ ^^^^0^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 ^ ^ ^ ^ ^ ^^^^0^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 ^ ^ ^ ^ ^ ^ ^ ^^^^0^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 ^ ^ ^ ^ ^ ^ 25/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 12 14 14 14 16 16 14 14 14 14 14 10 10 16 18 18 18 18 18 18 20 20 18 18 18 10 10 18 22 20 22 20 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ADCW : Add word with carry ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW ADCW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 4 4 4 4 4 4 4 4 4 4 4 4 0 0 4 4 4 4 6 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C rr<-rr+2 dst<-dst+src+C rr<-rr+2 rr<-rr-2 dst<-dst+src+C rr<-rr-2 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C rr<-rr+2 dst<-dst+src+C rr<-rr+2 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C rr<-rr-2 dst<-dst+src+C rr<-rr-2 dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C dst<-dst+src+C ^^^^?? ^^^^?? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? 26/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 12 12 14 14 12 14 14 16 16 14 14 14 6 6 10 16 14 14 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ADD : Addition of two bytes without carry ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD ADD r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 3 3 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src rr<-rr+1 dst<-dst+src rr<-rr+1 rr<-rr-1 dst<-dst+src rr<-rr-1 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src rr<-rr+1 dst<-dst+src rr<-rr+1 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src rr<-rr-1 dst<-dst+src rr<-rr-1 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src ^^^^0^ ^^^^0^ ^^^^0^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 ^ ^ ^ ^ ^ ^^^^0^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 ^ ^ ^ ^ ^ ^ ^ ^^^^0^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 ^ ^ ^ ^ ^ ^ 27/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 12 14 14 14 16 16 14 14 14 14 14 10 10 16 18 18 18 18 18 18 20 20 18 18 18 10 10 18 22 20 22 20 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ADDW : Add words without carry ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW ADDW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 4 4 4 4 4 4 4 4 4 4 4 4 0 0 4 4 4 4 6 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src rr<-rr+2 dst<-dst+src rr<-rr+2 rr<-rr-2 dst<-dst+src rr<-rr-2 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src rr<-rr+2 dst<-dst+src rr<-rr+2 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src rr<-rr-2 dst<-dst+src rr<-rr-2 dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src dst<-dst+src ^^^^?? ^^^^?? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? 28/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 12 12 14 14 12 14 14 16 16 14 14 14 6 6 10 16 14 14 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - AND : Logical AND between two bytes AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND AND r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 3 3 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src rr<-rr+1 dst<-dst AND src rr<-rr+1 rr<-rr-1 dst<-dst AND src rr<-rr-1 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src rr<-rr+1 dst<-dst AND src rr<-rr+1 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src rr<-rr-1 dst<-dst AND src rr<-rr-1 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src -^ ^ 0 - -^ ^ 0 - -^ ^ 0 - ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^ ^ 0 - ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^ ^ 0 - ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 - 29/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 12 14 14 14 16 16 14 14 14 14 14 10 10 16 18 18 18 18 18 18 20 20 18 18 18 10 10 18 22 20 22 20 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - ANDW : Logical AND between two words ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW ANDW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 4 4 4 4 4 4 4 4 4 4 4 4 0 0 4 4 4 4 6 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src rr<-rr+2 dst<-dst AND src rr<-rr+2 rr<-rr-2 dst<-dst AND src rr<-rr-2 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src rr<-rr+2 dst<-dst AND src rr<-rr+2 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src rr<-rr-2 dst<-dst AND src rr<-rr-2 dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src dst<-dst AND src - ^ ^ 0 -- ^ ^ 0 -- ^ ^ 0 -^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - - ^ ^ 0 -^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - - ^ ^ 0 -^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - 30/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 10 10 4 10 10 10 10 4 4 6/10 6/10 10 10 8 14 P D BAND : Bit AND BAND BAND BCPL BLD BLD BOR BOR BRES BSET BTJF BTJT BXOR BXOR BTSET BTSET r.b r.b r.b r.b r.b r.b r.b r.b r.b r.b r.b r.b r.b r.b (rr).b N N r.b r.!b r.b r.!b r.b r.!b r.b r.!b 3 3 2 3 3 3 3 2 2 3 3 3 3 2 2 3 3 2 3 3 3 3 2 2 3/4 3/4 3 3 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 dst bit<-dst bit AND src bit dst bit<-dst bit AND complemented src bit dst bit<-dst bit complemented dst bit<-src bit dst bit<-src bit complemented dst bit<-dst bit OR src bit dst bit<-dst bit OR complemented src bit dst bit<- 0 dst bit<- 1 If test bit is 0, PC<-PC+N If test bit is 1, PC<-PC+N dst bit<-dst bit XOR src bit dst bit<-dst bit XOR complemented src bit If test bit = 0, test bit <-1,Z<-1 If test bit = 0, test bit <-1,Z<-1 ------------------------------------------------------------------^^0- -^^0- Operation Flags CZSVDH BCPL : Bit Complement BLD : Bit Load BOR : Bit OR BRES : Bit Reset BSET : Bit Set BTJF, BTJT : Bit test and jump BXOR : Bit Exclusive OR BTSET : Bit Test and Set 31/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles P D Operation Flags CZSVDH ---------------- CALL : Call a subroutine CALL CALL CALL NN (rr) (RR) 3 2 2 12 12 12 3 3 3 2(1) 2(1) 2(1) SSP<-SSP-2,(SSP)< PC, PC<-dst SSP<-SSP-2,(SSP)< PC, PC<-dst SSP<-SSP-2,(SSP)< PC, PC<-dst CALLS : Call a subroutine in another segment CALLS CALLS CALLS N,NN (r),(rr) (R), (rr) 3 2 2 16 16 16 4 3 3 3(1) 3(1) 3(1) SSP<-SSP-3, (SSP+1)<- PC, (SSP)<-CSR, CSR<-N, PC<-NN SSP<-SSP-3, (SSP+1)<- PC, (SSP)<-CSR, CSR<-r, PC<-rr SSP<-SSP-3, (SSP+1)<- PC, (SSP)<-CSR, CSR<-R, PC<-rr C <- C complemented dst<-0 dst<-0 dst<-0 dst<-0 ---------------- CCF : Complement Carry Flag CCF CLR CLR CLR CLR r R (r) (R) 1 2 2 2 2 4 4 4 4 4 1 2 2 2 2 0 0 0 0 0 ^- - - - CLR : Clear register Note 1. No data memory accesses are performed if the system stack is kept in the Register File. 32/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 10 10 12 12 10 12 12 14 14 12 12 12 6 6 8 14 12 12 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ - CP : Compare bytes CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP CP r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 2 2 dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src,rr<-rr+1 dst-src,rr<-rr+1 rr<-rr-1,dst-src rr<-rr-1,dst-src dst-src dst-src dst-src dst-src dst-src,rr<-rr+1 dst-src,rr<-rr+1 dst-src dst-src dst-src dst-src dst-src dst-src rr<-rr-1,dst-src rr<-rr-1,dst-src dst-src dst-src dst-src dst-src dst-src dst-src If compare not verified jump otherwise post-increment If compare verified jump otherwise post-increment dst<- NOT dst<- NOT dst<- NOT dst<- NOT dst dst dst dst CPJFI, CPJTI : Compare with post-increment CPJFI (rr), r N 3 14/16 3 1 ------ CPJTI (rr), r N 3 14/16 3 1 ------ CPL : Complement Register CPL CPL CPL CPL r R (r) (R) 2 2 2 2 4 4 4 4 2 2 2 2 0 0 0 0 ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 - 33/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 14 14 14 14 16 16 14 14 14 14 14 10 10 14 14 14 14 16 14 14 16 16 14 14 14 10 10 14 20 16 18 16 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ - CPW : Compare word CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW CPW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 2 2 4 dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src rr<-rr+2 dst-src rr<-rr+2 rr<-rr-2 dst-src rr<-rr-2 dst-src dst-src dst-src dst-src dst-src dst-src rr<-rr+2 dst-src rr<-rr+2 dst-src dst-src dst-src dst-src dst-src dst-src rr<-rr-2 dst-src rr<-rr-2 dst-src dst-src dst-src dst-src dst-src dst-src dst-src dst-src ^^^^ ^^^^ ^^^^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ---- ^^^^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ -- ^^^^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ -- 34/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 4 6 6 4 4 4 4 6 6 2 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ????^ ^ ^ ^ - DA : Decimal adjust DA DA DA DA DEC DEC DEC DEC DECW DECW DI r R (r) (R) r R (r) (R) rr RR 2 2 2 2 2 2 2 2 2 2 1 2 2 2 2 2 2 2 2 2 2 1 0 0 0 0 0 0 0 0 0 0 0 dst<- DA dst<- DA dst<- DA dst<- DA dst dst dst dst DEC : Decrement dst<- dst-1 dst<- dst-1 dst<- dst-1 dst<- dst-1 dst<-dst-1 dst<-dst-1 Bit 4 of the CIC Register is set to 0 dst / src <- dst high=remainder 16/8 <- dst low=result DECW : Decrement Word -^^^--^^^------- DI : Disable Interrupts DIV : Divide 16 by 8 DIV rr r 2 26/14 2/4 0/2 note 1 DIVWS : Divide Word Stepped 32 by 16 DIVWS rrhigh rrlow rr 3 26 3 0 32/16 note 1 DJNZ : Decrement a working register and Jump if Non Zero DJNZ r N 2 6 2/3(3) 0 r <- r-1, If r=0 then PC<-PC+N note 2 DWJNZ : Decrement a register pair and Jump if Non Zero DWJNZ DWJNZ rr RR N N 3 3 8 8 3/4(3) 3/4(3) 0 0 rr<-rr-1, If rr=0 then PC<-PC+N RR<-RR-1,If RR=0 then PC<-PC+N note 2 Note 1. Refer to the ST9+ Programming Manual for detailed information. Note 2. Registers in groups E and F are not allowed, either directly or as working registers. Note 3. Additional fetch when the jump is taken. 35/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 2 6 6 inf. P D Operation Flags CZSVDH --------------------- EI : Enable Interrupts EI EXT EXT HALT rr RR 1 2 2 2 1 2 2 2 0 0 0 0 Bit 4 of the CICR register is set to 1 r(7) --> r(n) n=8-15 R(7) --> R(n) n=8-15 Stops all internal clocks until next system reset if not in Watchdog Mode dst INC : Increment INC INC INC INC INCW INCW r R (r) (R) rr RR 2 2 2 2 2 2 4 4 4 4 6 6 2 2 2 2 2 2 0 0 0 0 0 0 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ - INCW : Increment Word dst<-dst+1 dst<-dst+1 FLAGS<-(SSP),SSP<-SSP+1, [CSR<-(SSP),SSP JP : Jump to a Routine JP JP JP JPcc NN (rr) (RR) NN 3 2 2 3 8 8 8 6/8 3 3 3 3 0 0 0 0 --------------------- JPS : Jump to a routine in another segment JPS JPS JPS N,NN (r),(rr) (R), (rr) 3 2 2 10 10 10 4 3 3 0 0 0 ---------------- JRcc : Conditional Relative Jump to a Routine JRcc N 2 6 2/3(3) 0 IF cc(condition code)is true, PC<-PC+dst ------ Note 1. All flags are restored to original setting (before interrupt occured). Note 2. Performed only if register file is not used. Note 3. Additional fetch when the jump is taken. 36/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 4 4 6 6 8 8 10 6 12 12 14 14 12 12 12 12 12 4 6 8 10 12 12 10 6 12 12 14 14 12 12 12 4 6 8 14 10 10 12 12 14 14 14 14 P D Operation Flags CZSVDH - LD : Load byte instructions LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LD LDPP LDDP LDPD LDDD r R r R r R r R r r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rx) N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) (r)+ (rr)+ (rr)+ (rr)+ (rr)+ (rr)+ r R R r (r) (r) (rr) (rr) NN N(rx) N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r r R r R r r R #N #N #N #N (rr) (rr) (rr)+ (r)+ (rr)+ (rr)+ (rr)+ (rr)+ 2 3 2 2 2 3 2 3 4 3 4 4 5 5 3 3 3 3 3 2 3 2 3 3 3 4 3 4 4 5 5 3 3 3 2 3 3 5 3 3 2 2 2 2 2 2 2 3 2 2 2 3 2 3 4 3 4 4 5 5 3 3 3 3 3 2 3 2 3 3 3 4 3 4 4 5 5 3 3 3 2 3 3 5 3 3 2 2 4 3 3 2 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 1 1 0 0 1 1 2 2 1 1 0 1 1 2 dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src,rr<-rr+1 dst<-src,rr<-rr+1 rr<-rr-1,dst<-src rr<-rr-1,dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src,rr<-rr+1 dst<-src,rr<-rr+1 dst-src dst-src dst-src dst-src dst-src dst-src dst-src rr<-rr-1,dst<-src rr<-rr-1,dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src, rr<-rr+1,r<-r+1 dst<-src, rr<-rr+1,r<-r+1 dst<-src (1),rr<-rr+1 dst<-src (2),rr<-rr+1 dst<-src (3),rr<-rr+1 dst<-src (4),rr<-rr+1 LDPP,LDDP,LDPD, LDDD : Load from / to program / data memory Note Note Note Note 1. dst using CSR, src using CSR. 2. dst using DPRx, src using CSR. 3. dst using CSR, src using DPRx. 4. dst using DPRx, src using DPRx. 37/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 6 6 6 6 8 8 10 10 12 8 14 14 16 16 14 14 14 14 14 6 6 12 12 14 14 14 10 14 14 16 16 14 14 14 8 8 14 18 20 18 16 P D Operation Flags CZSVDH - LDW : Load word instructions LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW LDW rr RR rr RR rr RR rr RR rr rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rx) N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) N(rrx) NN(rrx) NN (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rx) N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 3 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 3 4 4 5 5 3 3 3 4 4 4 5 6 6 2 2 3 3 3 3 3 2 3 4 3 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 3 4 4 5 5 3 3 3 4 4 4 5 6 6 2 0 0 0 0 0 0 2 2 2 0 2 2 2 2 2 2 2 2 2 0 0 2 2 2 2 2 0 2 2 2 2 2 2 2 0 0 2 2 2 2 4 dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-ssc dst<-src dst<-src dst<-src dst<-src dst<-src,rr<-rr+2 dst<-src,rr<-rr+2 rr<-rr-2,dst<-src rr<-rr-2,dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src,rr<-rr+2 dst<-src,rr<-rr+2 dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src rr<-rr-2,dst<-src rr<-rr-2,dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src dst<-src 38/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 12/16 P D Operation Flags CZSVDH ---- LINK : create stack frame in system stack LINK RR #N 3 3 2/0 SSP<-SSP-1[2], (SSP)<-R[R], R[R]<-SSP, SSP<-SSP-N " " LINK rr #N 3 12/16 3 2/0 - - ---- LINKU : create stack frame in system stack LINKU RR #N 3 12/16 3 2/0 USP<-USP-1[2], (USP)<-R[R], R[R]<-USP, USP<-USP-N " " ---- LINKU rr #N 3 12/16 3 2/0 - - ---- MUL : Multiply MUL rr r 2 22 2 0 dst <- dst x src, 8 x 8 multiply No Operation note 1 NOP : No operation NOP 1 2 1 0 ---- Note 1. Refer to ST9 programming manual for detailed information. Note 2. The value inside [ ] is valid for external memory stack 39/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 12 12 14 14 12 14 14 16 16 14 14 14 6 6 10 16 14 14 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - OR : Logical OR between 2 bytes OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR OR r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 3 3 dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src, rr<-rr+1 dst<-dst OR src, rr<-rr+1 rr<-rr-1, dst<-dst OR src rr<-rr-1, dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src, rr<-rr+1 dst<-dst OR src, rr<-rr+1 dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src rr<-rr-1, dst<-dst OR src rr<-rr-1, dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src 40/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 12 14 14 14 16 16 14 14 14 14 14 10 10 16 18 18 18 18 18 18 20 20 18 18 18 10 10 18 22 20 22 20 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - ORW : Logical OR between two words ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW ORW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 4 4 4 4 4 4 4 4 4 4 4 4 0 0 4 4 4 4 6 dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src rr<-rr+2 dst<-dst OR src rr<-rr+2 rr<-rr-2 dst<-dst OR src rr<-rr-2 dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src rr<-rr+2 dst<-dst OR src rr<-rr+2 dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src rr<-rr-2 dst<-dst OR src rr<-rr-2 dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src dst<-dst OR src -^^0--^^0--^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - 41/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. PEA PEA PEA PEA PEAU PEAU PEAU PEAU POP POP POP POP POPU POPU POPU POPU POPUW POPUW POPW POPW PUSH PUSH PUSH PUSH PUSH PUSHU PUSHU PUSHU PUSHU PUSHU PUSHUW PUSHUW PUSHUW PUSHW PUSHW PUSHW r R (r) (R) r R (r) (R) rr RR rr RR dst Clock P D Operation cycles PEA : Push effective address on system stack 2/0(1) 4 20 4 N(rrx) SSP<-SSP-2, (SSP)<-rrx+N 5 22 5 NN(rrx) SSP<-SSP-2, (SSP)<-rrx+NN 2/0(1) 4 20 4 N(RRx) SSP<-SSP-2, (SSP)<-RRx+N 2/0(1) 5 22 5 NN(RRx) SSP<-SSP-2, (SSP)<-RRx+NN 2/0(1) PEAU : Push effective address on user stack USP<-USP-2, (USP)<-rrx+N 2/0(1) 4 20 4 N(rrx) USP<-USP-2, (USP)<-rrx+NN (1) 5 22 5 NN(rrx) 2/0 USP<-USP-2, (USP)<-RRx+N (1) 4 20 4 N(RRx) 2/0 USP<-USP-2, (USP)<(1) 5 22 5 NN(RRx) 2/0 RRx+NN POP : Pop system stack 1/0(1/0) dst<-(SSP), SSP<-SSP+1 2 8 2 2 8 2 1/0(1/0) dst<-(SSP), SSP<-SSP+1 2 8 2 1/0(1/0) dst<-(SSP), SSP<-SSP+1 2 8 2 1/0(1/0 dst<-(SSP), SSP<-SSP+1 POPU : Pop user stack 1/0(1/0) dst<-(USP), USP<-USP+1 2 8 2 2 8 2 1/0(1/0) dst<-(USP), USP<-USP+1 2 8 2 1/0(1/0) dst<-(USP), USP<-USP+1 2 8 2 1/0(1/0) dst<-(USP), USP<-USP+1 POPUW : Pop word from user stack 2 10 2 2/0(1/0) dst<-(USP), USP<-USP+2 2 10 2 2/0(1/0) dst<-(USP), USP<-USP+2 POPW : Pop word from system stack 2 10 2 2/0(1/0) dst<-(SSP), SSP<-SSP+2 2 10 2 2/0(1/0) dst<-(SSP), SSP<-SSP+2 PUSH : Push system stack 1/0(1/0) SSP<-SSP-1, (SSP)<-src 2 8 2 r 1/0(1/0) SSP<-SSP-1, (SSP)<-src 2 8 2 R 1/0(1/0) SSP<-SSP-1, (SSP)<-src 2 8 2 (r) 1/0(1/0) SSP<-SSP-1, (SSP)<-src 2 8 2 (R) 3 12 3 #N 1/0(1/0) SSP<-SSP-1, (SSP)<-src src Bytes r R (r) (R) #N rr RR #NN rr RR #NN PUSHU : Push user stack 1/0(1/0) USP<-USP-1, (USP)<-src 2 8 2 1/0(1/0) USP<-USP-1, (USP)<-src 2 8 2 1/0(1/0) USP<-USP-1, (USP)<-src 2 8 2 1/0(1/0) USP<-USP-1, (USP)<-src 2 8 2 3 12 3 1/0(1/0) USP<-USP-1, (USP)<-src PUSHUW : Push word on user stack 2 8/10 3/2(2) USP<-USP-2, (USP)<-src 2/0(1) 2 8/10 USP<-USP-2, (USP)<-src 3/2(2) 2/0(1) 4 16 USP<-USP-2, (USP)<-src 4 2/0(1) PUSHW : Push Word on System Stack 2 8/10 3/2(2) SSP<-SSP-2, (SSP)<-src 2/0(1) (2) 2 8/10 SSP<-SSP-2, (SSP)<-src 3/2 2/0(1) 4 16 SSP<-SSP-2, (SSP)<-src 4 2/0(1) Flags CZSVDH - --------------------- ------------------------------- Note 1. No data memory accesses are done if the stack is kept in the Register File. Note 2. Additional fetch when the stack is kept in Memory. 42/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 8/10 P D Operation Flags CZSVDH 0---------- RCF : Reset carry flag RCF RET 1 1 1 2 0 2(1) C <- 0 PC <- (SSP), SSP <- SSP+2 CSR<-(SSP), PC <- (SSP+1), SSP <- SSP+3 dst(0)<-C, C<-dst(7) dst(n+1)<-dst(n) n=0-6 " " " " " " RET : Return from subroutine RETS : Return from subroutine in another segment RETS 2 12/14 2 3(1) ------ RLC : Rotate left through carry RLC RLC RLC RLC RLCW RLCW ROL ROL ROL ROL ROR ROR ROR ROR RRC RRC RRC RRC RRCW RRCW r R (r) (R) rr RR r R (r) (R) r R (r) (R) r R (r) (R) rr RR 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 4 6 6 8 8 4 4 6 6 4 4 6 6 4 4 6 6 8 8 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ^^^^-^^^^-^^^^-^^^^-- RLCW : Rotate word left through carry dst(0)<-C, C<-dst(15) dst(n+1)<-dst(n) n=0-14 " " C<-dst(7), dst(0)<-dst(7) dst(n+1)<-dst(n) n=0-6 " " " " " " ^?^ ^ - ^ ?^ ^ - - ROL : Rotate left ^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-^^^^-- ROR : Rotate right C<-dst(0), dst(7)<-dst(0) dst(n)<-dst(n+1) n=0-6 " " " " " " RRC : Rotate right through carry dst(7)<-C, C<-dst(0) dst(n)<-dst(n+1) n=0-6 " " " " " " RRCW : Rotate word right through carry dst(15)<-C, C<-dst(0) dst(n)<-dst(n+1) n=0-14 " " Note 1. No data memory accesses are done if the stack is kept in the Register File. 43/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 12 12 14 14 12 14 14 16 16 14 14 14 6 6 10 16 14 14 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SBC : Subtraction of 2 bytes with carry SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC SBC r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 3 3 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C rr<-rr+1 dst<-dst-src-C rr<-rr+1 rr<-rr-1 dst<-dst-src-C rr<-rr-1 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C rr<-rr+1 dst<-dst-src-C rr<-rr+1 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C rr<-rr-1 dst<-dst-src-C rr<-rr-1 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C ^ ^ ^1^ ^ ^ ^1^ ^ ^ ^1^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 ^ ^ ^ ^ ^ ^ ^ ^1^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 1 1 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^1^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 1 ^ ^ ^ ^ ^ ^ 44/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 12 14 14 14 16 16 14 14 14 14 14 10 10 16 18 18 18 18 18 18 20 20 18 18 18 10 10 18 22 20 22 20 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SBCW : Subtraction of word with carry SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW SBCW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 4 4 4 4 4 4 4 4 4 4 4 4 0 0 4 4 4 4 6 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C rr<-rr+2 dst<-dst+src+C rr<-rr+2 rr<-rr-2 dst<-dst-src-C rr<-rr-2 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C rr<-rr+2 dst<-dst-src-C rr<-rr+2 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C rr<-rr-2 dst<-dst-src-C rr<-rr-2 dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C dst<-dst-src-C ^^^^?? ^^^^?? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^^^^?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? 45/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 P D Operation Flags CZSVDH 1----- SCF : Set carry flag SCF 1 1 0 C <- 1 Set Data Memory DP<-1 Note 1 dst C<-dst(7), dst (0)<-0 dst(n+1)<-dst(n)n=0-6 " " " " SDM : Set data memory SDM 1 4 1 0 ------ SLA : Shift left arithmetic r SLA R (rr) 2 3 3 4 6 14 2 3 3 0 0 3 ^ ^ ^ ^ 0^ ^ ^ ^ ^ 0^ ^ ^ ^ ^ 0^ SLAW : Shift word left arithmetic rr SLAW RR (rr) 2 3 2 8 8 20 2 3 2 0 0 6 C<-dst(15), dst (0)<-0 dst(n+1)<-dst(n)n=1-14 " " " " ^ ^ ^ ^ ?? ^ ^ ^ ^?? ^ ^ ^ ^?? SPM : Set program memory SPM 1 4 1 0 Set Program Memory DP<-0 Note 2 Set Page Pointer dst(7)<-dst(7), C<-dst(0) dst(n)<-dst(n+1)n=0-6 " " " " " " dst(15)<-dst(15), C<-dst(0) dst(n)<-dst(n+1)n=0-14 " " ------ SPP : Set page pointer SPP SRA SRA SRA SRA SRAW SRAW r R (r) (R) rr RR #N 2 2 2 2 2 2 2 4 4 4 6 6 8 8 2 2 2 2 2 2 2 0 0 0 0 0 0 0 -----^ ^ ^ 0-^ ^ ^0-^ ^ ^0-^ ^ ^ 0 - -^ ^ ?^ 0 - ^ ?^ 0 - SRA : Shift right arithmetic SRAW : Shift word right arithmetic Note 1. Following this instruction, all addressing modes referring to address spaces will use DPRx registers. Note 2. Following this instruction, all addressing modes referring to address spaces will use CSR register, except for the following instructions which operate with DPRx registers independently of the setting of the DP flag :CALLS, RETS, LINK/LINKU, UNLINK/UNLINKU, PUSH(W)/PUSHU(W), POP(W)/POPU(W), PEA/PEAU, and CALL, RET, IRET and interrupt execution (assuming the Stack Pointers are not pointing to the Register File). 46/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 4 4 P D Operation Flags CZSVDH ---------------- SRP : Set register pointer SRP SRP0 SRP1 #N #N #N 2 2 2 2 2 2 0 0 0 Set Register Pointer Set Register Pointer 0 Set Register Pointer 1 SRP0 : Set register pointer 0 SRP1 : Set register pointer 1 47/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 12 12 14 14 12 14 14 16 16 14 14 14 6 6 10 16 14 14 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ SUB : Subtraction of 2 bytes without carry SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB SUB r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 3 3 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src rr<-rr+1 dst<-dst-src rr<-rr+1 rr<-rr-1 dst<-dst-src rr<-rr-1 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src rr<-rr+1 dst<-dst-src rr<-rr+1 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src rr<-rr-1 dst<-dst-src rr<-rr-1 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src ^ ^ ^ ^1^ ^ ^ ^ ^1^ ^ ^ ^ ^1^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 ^ ^ ^ ^ ^ ^ ^ ^ ^1^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 1 1 ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^1^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 1 1 1 1 1 1 ^ ^ ^ ^ ^ ^ 48/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 12 14 14 14 16 16 14 14 14 14 14 10 10 16 18 18 18 18 18 18 20 20 18 18 18 10 10 18 22 20 22 20 8 8 8 8 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? SUBW : Subtraction of words SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SUBW SWAP SWAP SWAP SWAP rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) r R (r) (R) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 2 2 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 2 2 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 4 4 4 4 4 4 4 4 4 4 4 4 0 0 4 4 4 4 6 0 0 0 0 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src rr<-rr+2 dst<-dst-src rr<-rr+2 rr<-rr-2 dst<-dst-src rr<-rr-2 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src rr<-rr+2 dst<-dst-src rr<-rr+2 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src rr<-rr-2 dst<-dst-src rr<-rr-2 dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst<-dst-src dst(0-3)<--->dst(4-7) dst(0-3)<--->dst(4-7) dst(0-3)<--->dst(4-7) dst(0-3)<--->dst(4-7) ^ ^ ^ ^ ?? ^ ^ ^ ^ ?? ^ ^ ^ ^ ?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ^ ^ ^ ^ ?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ^ ^ ^ ^ ?? ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? - SWAP : Swap nibbles ?^ ?^ ?^ ?^ 49/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 10 10 12 12 10 12 12 14 14 12 12 12 6 6 8 14 12 12 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - TCM : Test and complement byte under mask TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM TCM r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 2 2 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src rr<-rr+1 NOT dst AND src rr<-rr+1 rr<-rr-1 NOT dst AND src rr<-rr-1 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src rr<-rr+1 dst<-dst AND src rr<-rr+1 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src rr<-rr-1 NOT dst AND src rr<-rr-1 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src -^^0--^^0--^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 - 50/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 14 14 14 14 16 16 14 14 14 14 14 10 10 14 14 14 14 16 14 14 16 16 14 14 14 10 10 14 20 16 18 16 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - TCMW : Test and complement word under mask TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW TCMW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 2 2 4 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src rr<-rr+2 NOT dst AND src rr<-rr+2 rr<-rr-2 NOT dst AND src rr<-rr-2 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src rr<-rr+2 NOT dst AND src rr<-rr+2 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src rr<-rr-2 NOT dst AND src rr<-rr-2 NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src NOT dst AND src -^^0--^^0--^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - 51/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 10 10 12 12 10 12 12 14 14 12 12 12 6 6 8 14 12 12 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - TM : Test byte under mask TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM TM r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 2 2 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src rr<-rr+1 dst AND -src rr<-rr+1 rr<-rr-1 dst AND src rr<-rr-1 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src rr<-rr+1 dst AND src rr<-rr+1 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src rr<-rr-1 dst AND src rr<-rr-1 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src -^^0--^^0--^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 - 52/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 14 14 14 14 16 16 14 14 14 14 14 10 10 14 14 14 14 16 14 14 16 16 14 14 14 10 10 14 20 16 18 16 P D Operation Flags CZSVDH -^^0 ^^0^^0^^0^^0^^0^^0^^0^^0^^0^^0^^0^^0^^0^^0-- TMW : Test word under mask TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW TMW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 2 2 4 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src rr<-rr+2 dst AND src rr<-rr+2 rr<-rr-2 dst AND src rr<-rr-2 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src rr<-rr+2 dst AND src rr<-rr+2 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src rr<-rr-2 dst AND src rr<-rr-2 dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src dst AND src - -^^0--^^0--^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - 53/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 6/10 P D Operation Flags CZSVDH ------ UNLINK: remove stack frame from sysyem stack UNLINK RR 2 2 2/0 SSP<-RR, RR<-(SSP), SSP<-SSP+1[2] " " USP<-RR, RR<-(USP), USP<-USP+1[2] " " wait for interrupt UNLINK UNLINKU rr RR 2 2 6/10 6/10 2 2 2/0 2/0 ----------- UNLINKU: remove stack frame from user stack UNLINKU WFI rr 2 2 6/10 4+... 2 2 2/0 0 ----------- WFI : Wait for Interrupt Note. The value inside [ ] is valid for external memory stack 54/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 6 6 6 6 4 6 6 6 6 6 8 8 10 12 12 14 14 12 12 12 12 12 6 6 12 12 14 14 12 14 14 16 16 14 14 14 6 6 10 16 14 14 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - XCH : Exchange Register XCH XCH XCH XCH XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR XOR r R r R r R r R r R r R r r R r R r r R r R (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) r R (rr) NN (rr) (RR) r R R r r R R r (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) r R r R r R r r R r R r r R #N #N #N #N (rr) (rr) 3 3 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 3 3 3 3 2 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 3 3 3 3 3 3 3 3 4 4 4 5 5 3 3 3 3 3 3 5 3 3 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 2 2 3 3 dst <-> src dst <-> src dst <-> src dst <-> src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src rr<-r+1 dst<-dst XOR src rr<-rr+1 rr<-rr-1 dst<-dst XOR src rr<-rr-1 dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src rr<-rr+1 dst<-dst XOR src rr<-rr+1 dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src rr<-rr-1 dst<-dst XOR src rr<-rr-1 dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src XOR : Logical exclusive OR -^^0--^^0--^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 - 55/298 ST9+ Programming Manual INSTRUCTION SUMMARY (Continued) Mnemo. dst src Bytes Clock cycles 8 8 8 8 10 10 12 12 14 14 14 16 16 14 14 14 14 14 10 10 16 18 18 18 18 18 18 20 20 18 18 18 10 10 18 22 20 22 20 P D Operation Flags CZSVDH ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - XORW : Logical exclusive OR between words XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW XORW rr RR rr RR rr RR rr RR rr rr RR rr RR rr rr RR rr RR (r) (r) (rr) (rr) (rr)+ (rr)+ NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) -(rr) -(rr) rr RR (rr) NN N(rrx) NN(rrx) (rr) rr RR RR rr (r) (r) (rr) (rr) NN N(rrx) N(rrx) NN(rrx) NN(rrx) rr(rrx) (rr)+ (rr)+ -(rr) -(rr) rr RR rr RR rr RR rr rr RR rr RR rr rr RR #NN #NN #NN #NN #NN #NN (rr) 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 2 3 3 3 3 3 2 3 4 4 4 5 5 3 3 3 3 3 3 3 2 3 3 3 4 4 4 5 5 3 3 3 4 4 4 6 5 6 2 0 0 0 0 0 0 2 2 2 2 2 2 2 2 2 2 2 2 0 0 4 4 4 4 4 4 4 4 4 4 4 4 0 0 4 4 4 4 6 dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src rr<-rr+2 dst<-dst XOR src rr<-rr+2 rr<-rr-2 dst<-dst XOR src rr<-rr-2 dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src rr<-rr+2 dst<-dst XOR src rr<-rr+2 dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src rr<-rr-2 dst<-dst XOR src rr<-rr-2 dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src dst<-dst XOR src -^^0--^^0--^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - -^^0-^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ 0 0 0 0 0 0 0 - 56/298 ST9+ Programming Manual 2 OPCODE MAP R, Rd, Rs: general registers (8 bits), if the first 4 bits are Dh then the last 4 bits specify a working register. rr,rrd,rrs: working register pair (3 bits), a single bit (0 or 1) follows. RR,RRd,RRs: general register pair (7 bits), if the first 4 bits are Dh then the last 3 bits specify a working register; a single bit (0 or 1) follows. bd,bs: destination and source bit numbers (3 bits followed by a 0 or 1), associated to rd and rs for r.b bit addressing modes. N: 8-bit quantity. NN: 16-bit quantity (divided in Nh & Nl) nnnnnn: 6-bit segment number. wwwww: 5-bit register window number (for SRP...) pppppp: 6-bit register page number (for SPP). K: ALU parametrization, 4 bits (corresponding instruction is ALD or ALDW, value of K gives instruction to be substituted for "ALD": K= ALD= 0 OR 1 AND 2 SBC 3 ADC 4 ADD 5 SUB 6 XOR 8 CP 9 CP A TM F LD Table 14. Opcode Map OPCODE 00 01 02 03 04 05 06 06 07 07 08 09 0A 0B 0C 0D 0E 0E 0E 0E 0F 0F 0F 10 11 12 13 14 BYTE1 BYTE2 BYTE3 BYTE4 BYTE5 OPCODE MNEMONIC EI SCF OR OR OR OR ALDW ALDW ORW ORW LD LD DJNZ JR LD JP ORW ORW ORW ORW BOR BOR BSET DI RCF AND AND AND ADDRESSING MODE rd,rs rd,rs Rs Rd K,rr1 K,rr0 RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 bd1,rd bd1,rd bd0,rd Rd N Nd Nhd RRd0 Nhs Nhs Nld Nls Nls Nhs Nls Nl bs0,rs bs1,rs rd,rs rd,(rs) Rd,Rs Rd,#N Nd(rr),#NNs NNd(rr),#NNs RRd,RRs RRd,#NN r0,Rs Rd,r0 r0,N F,N r0,#N F,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) rd.b,rs.b rd.b,!rs.b rd.b rd,rs rd,rs Rs Rd rd,rs rd,(rs) Rd,Rs 57/298 ST9+ Programming Manual OPCODE 15 16 17 17 18 19 1A 1B 1C 1D 1E 1E 1E 1E 1F 1F 1F 20 21 22 23 24 25 26 26 27 27 28 29 2A 2B 2C 2D 2E 2E 2E 2E 2F 2F 30 31 32 33 34 35 36 36 BYTE1 Rd Rs RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 bd1,rd bd1,rd bd0,rd Rd Rd rd,rs rd,rs Rs Rd K,rr1 K,rr0 RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 RR0 K,0001 Rd Rd rd,rs rd,rs Rs Rd RR0 K,0001 BYTE2 N Rd RRd0 Nhs BYTE3 BYTE4 BYTE5 Nls Nl bs0,rs bs1,rs Rd N N N RRd0 Nhs R N Nls R Nl Ns Ndh Ndl Rd N Nsh Nsl Ndh Ndl OPCODE MNEMONIC AND XCH ANDW ANDW LD LD DJNZ JR LD JP ANDW ANDW ANDW ANDW BAND BAND BRES POPU POPU SBC SBC SBC SBC ALD ALD SBCW SBCW LD LD DJNZ JR LD JP SBCW SBCW SBCW SBCW SRAW ALD PUSHU PUSHU ADC ADC ADC ADC RRCW ALDW ADDRESSING MODE Rd,#N Rs,Rd RRd,RRs RRd,#NN r1,Rs Rd,r1 r1,N LT,N r1,#N LT,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) rd.b,rs.b rd.b,rs.b rd.b Rd (Rd) rd,rs rd,(rs) Rd,Rs Rd,#N N(rr),R NN(rr),R RRd,RRs RRd,#NN r2,Rs Rd,r2 r2,N LE,N r2,#N LE,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) RR NNd,#Ns Rd (Rd) rd,rs rd,(rs) Rd,Rs Rd,#N RR NNd,#NNs 58/298 ST9+ Programming Manual OPCODE 37 37 38 39 3A 3B 3C 3D 3E 3E 3E 3E 3F 3F 40 41 42 43 44 45 46 47 47 48 49 4A 4B 4C 4D 4E 4E 4E 4E 4F 50 51 52 53 54 55 56 57 57 58 59 5A 5B BYTE1 RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 01nnnnnn 11nnnnnn Rd Rd rd,rs rd,rs Rs Rd RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 rrd0,rs Rd Rd rd,rs rd,rs Rs Rd RRs0 RRs0 RRd1 Rs Rd N N BYTE2 RRd0 Nhs BYTE3 BYTE4 BYTE5 Nls Nl Nh Nh Nl Nl Rd N RRd0 Nhs Nls Nl Rd N rrh0,rrl0 RRd0 Nhs Nls OPCODE MNEMONIC ADCW ADCW LD LD DJNZ JR LD JP ADCW ADCW ADCW ADCW CALLS JPS DEC DEC ADD ADD ADD ADD RET ADDW ADDW LD LD DJNZ JR LD JP ADDW ADDW ADDW ADDW MUL INC INC SUB SUB SUB SUB DIVWS SUBW SUBW LD LD DJNZ JR ADDRESSING MODE RRd,RRs RRd,#NN r3,Rs Rd,r3 r3,N ULE,N r3,#N ULE,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) nnnnnn,NN nnnnnn,NN Rd (Rd) rd,rs rd,(rs) Rd,Rs Rd,#N RRd,RRs RRd,#NN r4,Rs Rd,r4 r4,N OV,N r4,#N OV,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) rrd,rs Rd (Rd) rd,rs rd,(rs) Rd,Rs Rd,#N rrh,rrl,RRs RRd,RRs RRd,#NN r5,Rs Rd,r5 r5,N MI,N 59/298 ST9+ Programming Manual OPCODE 5C 5D 5E 5E 5E 5E 5F 60 60 60 60 61 62 63 64 65 66 67 67 68 69 6A 6B 6C 6D 6E 6E 6E 6E 6F 6F 6F 70 71 72 72 73 73 73 74 74 75 75 76 77 78 79 BYTE1 N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 rrd0,rs rrs1,rrx0 rrd1,rrx1 rrs0,rrx0 rrd0,rrx1 rd,rs rd,rs Rs Rd Rs RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 bd1,rd bd1,rd bd0,rd Rd Rd K,rrs1 K,rrd0 K,rrs0 0100,rr1 1100,rr1 RRd1 RRs0 RRd0 RRd1 Rd Rd Rs Rd BYTE2 BYTE3 BYTE4 BYTE5 Nl K,rd K,rs K,rrde K,rrse Rd N RRd0 Nhs Nls Nl bs0,rs bs1,rs Rd Rs RRd0 R R OPCODE MNEMONIC LD JP SUBW SUBW SUBW SUBW DIV ALD ALD ALDW ALDW CCF XOR XOR XOR XOR PUSH XORW XORW LD LD DJNZ JR LD JP XORW XORW XORW XORW BXOR BXOR BCPL DA DA ALD ALD ALD CALLS JPS CALL PUSHW POPW UNLINK POP POP LD LD ADDRESSING MODE r5,#N MI,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) rrd,rs rd,rrs(rrx) rrd(rrx),rs rrd,rrs(rrx) rrd(rrx),rrs rd,rs rd,(rs) Rd,Rs Rd,#N Rs RRd,RRs RRd,#NN r6,Rs Rd,r6 r6,N EQ,N r6,#N EQ,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) rd.bd,rs.bs rd.bd, rs.bs rd.bd Rd (Rd) Rd,(rrs) (rrd),Rs (RRd),(rrs) (R),(rr) (R),(rr) (RRd) RRs RRd RRd Rd (Rd) r7,Rs Rd,r7 60/298 ST9+ Programming Manual OPCODE 7A 7B 7C 7D 7E 7F 7F 80 81 82 83 84 85 86 86 86 86 87 87 88 89 8A 8B 8C 8D 8E 8E 8E 8E 8F 8F 8F 8F 8F 8F 8F 8F 8F 90 91 92 93 94 95 96 97 97 BYTE1 N N N Nh K,rrs0 K,rrx1 K,rrx0 Rd Rd rd,rs rd,rs Rs Rd K,rrx1 K,rrx1 K,rrx0 K,rrx0 RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 RRd0 F1 F3 C1 C3 01 01 03 03 Rd Rd rd,rs rd,rs Rs Rd RRs0 RRs0 RRd1 BYTE2 BYTE3 BYTE4 BYTE5 Nl RRd0 N Nh Rd Nl Rd Rd N N N Nh Nh RRd0 Nhs RRs1 RRd0 Nl Nl Nls RRs1 RRd0 Nl N N Nh Nh RRx0 RRx1 RRx0 RRx1 Nl Nl N Nl N Nl Nh Nh Rd N K,rd RRd0 Nhs Nls OPCODE MNEMONIC DJNZ JR LD JP ALDW ALD ALD CPL CPL CP CP CP CP ALDW ALDW ALDW ALDW CPW CPW LD LD DJNZ JR LD JP CPW CPW CPW CPW RLCW PUSH PUSHU PUSH PUSHU PEA PEA PEAU PEAU CLR CLR CP CP CP CP ALDW CPW CPW ADDRESSING MODE r7,N UL,N r7,#N UL,NN RRd,(rrs) Rd,N(rrx) Rd,NN(rrx) Rd (Rd) rd,rs rd,(rs) Rd,Rs Rd,#N N(rrx),RRs RRd,N(rrx) NN(rrx),RRs RRd,NN(rrx) RRd,RRs RRd,#NN r8,Rs Rd,r8 r8,N T,N r8,#N T,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) RRd N N NN NN N(RRx) NN(RRx) N(RRx) NN(RRx) Rd (Rd) rd,rs rd,(rs) Rd,Rs Rd,#N (rd),RRs RRd,RRs RRd,#NN 61/298 ST9+ Programming Manual OPCODE 98 99 9A 9B 9C 9D 9E 9E 9E 9E 9F 9F A0 A1 A2 A3 A4 A5 A6 A7 A7 A8 A9 AA AB AC AD AE AE AE AE AF AF B0 B1 B2 B3 B4 B4 B5 B5 B6 B6 B7 B7 B8 B9 BYTE1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 rrs0,rd rrs1,rd Rd Rd rd,rs rd,rs Rs Rd K,rs RRs0 RRd1 Rs Rd N N N Nh rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 b0,rd b1,rd Rd Rd rs,rx rd,rx K,rrs1 K,rrd0 rd,rrs0 rs,rrd1 RR0 RR1 RR0 RR1 Rs Rd BYTE2 BYTE3 BYTE4 BYTE5 Nl N N Rd N RRd0 RRd0 Nhs Nls Nl N N N N Rd Rs N OPCODE MNEMONIC LD LD DJNZ JR LD JP CPW CPW CPW CPW CPJF CPJT ROL ROL TM TM TM TM ALDW TMW TMW LD LD DJNZ JR LD JP TMW TMW TMW TMW BTJT BTJF RLC RLC LD LD ALD ALD LD LD PUSHUW LINKU POPUW UNLINKU LD LD ADDRESSING MODE r9,Rs Rd,r9 r9,N GE,N r9,#N GE,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) rd,(rrs),N rd,(rrs),N Rd (Rd) rd,rs rd,(rs) Rd,Rs Rd,#N RRd,(rs) RRd,RRs RRd,#NN r10,Rs Rd,r10 r10,N GT,N r10,#N GT,NN rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) b.rd,N b.rd,N Rd (Rd) N(rx),rs rd,N(rx) Rd,(rrs)+ (rrd)+,Rs rd,(rrs) (rrd),rs RR RR,#N RR RR r11,Rs Rd,r11 62/298 ST9+ Programming Manual OPCODE BA BB BC BD BE BE BF BF C0 C1 C2 C2 C3 C3 C4 C5 C6 C6 C7 C7 C7 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D4 D5 D5 D6 D6 D6 D6 D7 D7 D8 D9 DA BYTE1 N N N Nh K,rrd1 K,rrd0 RRd0 01 Rd Rd K,rrs1 K,rrd0 K,rrs1 K,rrd0 K,rd K,rs RR0 RR1 wwwww000 wwwww100 wwwww101 pppppp10 Rs Rd N N N Nh RRd0 Rd Rd Nh RR0 RR1 K,rrs1 K,rrd0 rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 rd,rrs1 rs,rrd0 Rs Rd N BYTE2 BYTE3 BYTE4 BYTE5 Nl RRs0 Nh Nh Nl Nl Rd Rs RRd RRs Nh Nh N Nl Nl Nl Nl N RRd0 RRs0 OPCODE MNEMONIC DJNZ JR LD JP ALDW ALDW LDW HALT ROR ROR ALD ALD ALDW ALDW ALD ALD DWJNZ EXT SRP SRP0 SRP1 SPP LD LD DJNZ JR LD JP ETRAP DECW RRC RRC CALL IRET JP LINK ALDW ALDW LDPP LDDP LDPD LDDD LD LD LD LD DJNZ ADDRESSING MODE r11,N UGT,N r11,#N UGT,NN (rr),RR (rr),#NN RRd,#NN Rd (Rd) Rd,-(rrs) -(rrd),Rs RRd,-(rrs) -(rrd),RRs NN,rs RR,N RR wwwww wwwww wwwww pppppp r12,Rs Rd,r12 r12,N NOV,N r12,#N NOV,NN RRd Rd (Rd) NN (RR) RR,#N RRd,(rrd)+ (rrd)+,RRs (rrd)+,(rrs)+ (rrd)+,(rrs)+ (rrd)+,(rrs)+ (rrd)+,(rrs)+ (rd)+,(rrs)+ (rrd)+,(rs)+ r13,Rs Rd,r13 r13,N 63/298 ST9+ Programming Manual OPCODE DB DC DD DE DE DF E0 E1 E2 E2 E3 E3 E3 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EF EF F0 F1 F2 F2 F2 F3 F4 F5 F6 F6 F7 F8 F9 FA FB FC FD FE FF BYTE1 N N Nh rrs1,rx rrd0,rx RRd0 Rd Rd K,rrd0 K,rrs1 rrd0,rrs0 rrd1,rrs0 rrd0,rrs1 rrd1,rrs1 rd,rs rd,rs Rs K,rs Rs Rd N N N Nh RRs0 01 31 Rd Rd bs1,rs bs1,rs bd0,rd K,rrd0 Rs Rd bd0,rr0 01 Rs Rs Rd N N N Nh BYTE2 BYTE3 BYTE4 BYTE5 Nl N N Nh Nh Nl Nl K,rd Rd Nl RRd0 bd0,rd bd1,rd N Rd N Nl OPCODE MNEMONIC JR LD JP LDW LDW INCW SRA SRA ALDW ALDW LDW LDW LDW LDW LD LD ALD ALD LD LD DJNZ JR LD JP SPM LDW WFI ERET SWAP SWAP BLD BLD BTSET ALD LD LD BTSET RETS PUSH LD LD DJNZ JR LD JP SDM NOP ADDRESSING MODE PL,N r13,#N PL,NN N(rx),rrs rrd,N(rx) RRd Rd (Rd) rrd,NN NN,rrs rrd,rrs (rrd),rrs rrd,(rrs) (rrd),(rrs) rd,(rs) (rd),rs (rd),Rs Rd,(rs) r14,Rs Rd,r14 r14,N NE,N r14,#N NE,NN RRd,RRs Rd (Rd) rd.bd,rs.bs rd.bd,rs.bs rd.bd (rrd),#N Rd,Rs Rd,#N (rr).bd (Rs) r15,Rs Rd,r15 r15,N NC,N r15,#N NC,NN 64/298 INSTRUCTIONS ST9+ Programming Manual ADC Add with carry (byte) Register, Register ADC dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycle 4 6 6 6 6 6 6 6 OPC (HEX) 32 33 34 34 34 E6 E6 E7 OPC XTN 3 3 3 ADC [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Addr Mode dst src r r r (r) R R r R R r (r) R (r) r R (r) OPERATION: dst dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source and destination byte can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. EXAMPLE: Instruction ADC r8,R64 HEX 34 40 D8 Binary 0011 0100 0100 0000 1101 1000 If the carry flag is set, working register 8 contains 35 (decimal) and register 64 contains 22 (decimal), after this instruction working register 8 will contain 58. 66/298 1 ST9+ Programming Manual ADC Add with carry (byte) Register, Memory ADC dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 3 3 3 3 3 3 3 3 3 3 3 3 ADC [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The destination byte is held in the destination register. The source byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src + C rr rr + 1 The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are incremented after the ADC has been carried out. OPERATION c: rr rr - 1 dst dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are decremented before the ADC is carried out. 67/298 1 ST9+ Programming Manual ADC Add with carry (byte) Register, Memory ADC dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. ADC EXAMPLE: Instruction ADC r8,(rr4)+ HEX B4 35 D8 Binary 1011 0100 0011 0101 1101 1000 If the carry flag is reset, working register 8 contains 11 (decimal), working register pair 4 contains 4200 (decimal) and memory location 4200 contains 11 (decimal), after this instruction working register 8 will contain 22 and working register pair 4 will contain 4201 68/298 1 ST9+ Programming Manual ADC Add with carry (byte) Memory, Register ADC dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 12 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 3 3 3 3 3 3 3 3 3 3 3 3 ADC [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r Oper a a b b c c a a a a a a OPERATION a: dst dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source byte is held in the source register. The destination byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src + C rr rr + 1 The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source byte is in the source register, the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the ADC has been carried out. OPERATION c: rr rr - 1 dst dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source byte is in the source register, the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the ADC is carried out. 69/298 1 ST9+ Programming Manual ADC Add with carry (byte) Memory, Register ADC dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. ADC . EXAMPLE: Instruction ADC 4028,r8 HEX C5 38 0F BC Binary 1100 0101 0011 1000 0000 1111 1011 1100 If the carry flag is set, memory location 4028 contains 200 (decimal) and working register 8 contains 32 (decimal), after this instruction memory location 4028 will contain 233. 70/298 1 ST9+ Programming Manual ADC Add with carry (byte) Memory, Memory ADC dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 14 14 OPC (HEX) 73 73 OPC XTN 3 3 ADC Address dst (RR) (rr)* Mode src (rr) (rr) OPERATION: dst dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. EXAMPLE: Instruction ADC (rr4),(rr8) HEX 73 38 D4 Binary 0111 0011 0011 1000 1101 0100 If the carry flag is set, working register pair 4 contains 2800 (decimal), memory location 2800 contains 46 (decimal), working register pair 8 contains 4200 (decimal) and memory location 4200 contains 45 (decimal), after this instruction memory location 2800 will contain 92. 71/298 1 ST9+ Programming Manual ADC Add with carry (byte) All, Immediate ADC dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 10 16 OPC (HEX) 35 35 F3 2F OPC XTN 3 31 ADC [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: dst dst + src + C The source byte, along with the carry flag, is added to the destination byte and the result is stored in the destination byte. The source byte is the immediate value in the operand, the destination byte can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. EXAMPLE: Instruction ADC (rr8),#32 HEX F3 38 20 Binary 1111 0011 0010 1000 0010 0000 If the carry flag is set, working register pair 8 contains 4028 (decimal) and memory location 4028 contains 74 (decimal), after this instruction memory location 4028 will contain 107. 72/298 1 ST9+ Programming Manual ADCW ADCW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 3E 37 37 37 96 96 A6 A6 ADCW Add With Carry (Word) - Register, Register OPC XTN 3 3 3 3 [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address Mode dst src rr rr RR RR rr RR RR rr (r) RR (r) rr RR (r) rr (r) OPERATION: dst dst + src + C The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source and destination word can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction ADCW (r8),RR64 HEX 96 40 38 Binary 1001 0110 0100 0000 0011 1000 If the carry flag is zero, register pair 64 contains 1102 (decimal), working register 8 contains 200 (decimal), and register pair 200 contains 2550 (decimal), after this instruction register pair 200 will hold 3652. 73/298 1 ST9+ Programming Manual ADCW ADCW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 3E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 3 3 3 3 3 3 3 3 3 3 3 ADCW Add With Carry (Word) - Register, Memory [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst + src + C The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src + C rr rr + 2 The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the ADD has been carried out. OPERATION c: rr rr - 2 dst dst + src + C The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are decremented before the ADD is carried out. 74/298 1 ST9+ Programming Manual ADCW ADCW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. ADCW Add With Carry (Word) - Register, Memory EXAMPLE: Instruction ADCW RR64,-(rr4) HEX C3 35 40 Binary 1100 0011 0011 0101 0100 0000 If the carry flag is set, working register pair 4 contains 1184 (decimal), register pair 64 contains 5000 (decimal) and memory location 1182 contains 1100 (decimal), after this instruction working register pair 64 will contain 6101 and register pair 4 will contain 1182. 75/298 1 ST9+ Programming Manual ADCW ADCW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 16 18 18 18 18 18 18 18 18 22 20 20 OPC (HEX) 3E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 3 3 3 3 3 3 3 3 3 3 3 ADCW Add With Carry (Word) - Memory, Register [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst dst + src + C The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source word is held in the source register. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src + C rr rr + 2 The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the ADD has been carried out. OPERATION c: rr rr - 2 dst dst + src + C The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the ADD is carried out. 76/298 1 ST9+ Programming Manual ADCW ADCW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. ADCW Add With Carry (Word) - Memory, Register EXAMPLE: Instruction ADCW (rr4)+,RR64 HEX D5 34 40 Binary 1101 0101 0011 0100 0100 0000 If the carry flag is set, register pair 64 contains 1250 (decimal), working register pair 4 contains 1064 (decimal), and memory location 1064 contains 1750, after this instruction is carried out memory pair 1064 will contain 3001 and working register pair 4 will contain 1066. 77/298 1 ST9+ Programming Manual ADCW ADCW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 20 OPC (HEX) 3E ADCW Add With Carry (Word) - Memory, Memory OPC XTN - Address Mode dst src (rr) (rr) OPERATION: dst dst + src + C The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction ADCW (rr4),(rr6) HEX 3E 57 Binary 0011 1110 0101 0111 If the carry flag is set, working register pair 6 contains 1002 (decimal), memory pair 1002 contains 2300 (decimal), working register pair 4 contains 1060 (decimal) and memory pair 1060 contains 2700 (decimal), after this instruction memory pair 1060 will contain 5001. 78/298 1 ST9+ Programming Manual ADCW ADCW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ [XTN dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 18 20 22 22 OPC (HEX) 37 37 BE 06 06 36 ADCW Add With Carry (Word) - All, Immediate OPC XTN 3 3 3 31 |dst,0] Address Mode dst src RR #NN rr #NN (rr) #NN N(rr) NN(rr) NN #NN #NN #NN [XTN |dst,1] [ src l ] [XTN |dst,0] [ src h ] [ XTN ] [ dst h ] OPERATION: dst dst + src + C The source word, along with the carry flag, is added to the destination word and the result is stored in the destination word. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction ADCW RR64,#4268 HEX 37 41 10 AC Binary 0011 0111 0100 0001 0001 0000 1010 1100 If the carry flag is zero and register pair 64 contains 2000 (decimal), after this instruction has been carried out register pair 64 will contain the decimal value 6268. 79/298 1 ST9+ Programming Manual ADD Add (byte) Register, Register ADD dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 42 43 44 44 44 E6 E6 E7 OPC XTN 4 4 4 ADD [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address Mode dst src r r r (r) R R r R R r (r) R (r) r R (r) OPERATION: dst dst + src The source byte is added to the destination byte and the result is stored in the destination byte. The source and destination byte can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. EXAMPLE: Instruction ADD (r8),R255 HEX E6 FF 48 Binary 1110 0110 1111 1111 0100 1000 If working register 8 contains 28 (decimal), register 28 contains 43 (decimal) and register 255 contains 21 (decimal) after this instruction register 28 will contain 64. 80/298 1 ST9+ Programming Manual ADD Add (byte) Register, Memory ADD dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 4 4 4 4 4 4 4 4 4 4 4 4 ADD [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst + src The source byte is added to the destination byte and the result is stored in the destination byte. The destination byte is held in the destination register. The source byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src rr rr + 1 The source byte is added to the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are incremented after the ADD has been carried out. OPERATION c: rr rr - 1 dst dst + src The source byte is added to the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are decremented before the ADD is carried out. 81/298 1 ST9+ Programming Manual ADD Add (byte) Register, Memory ADD dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. ADD EXAMPLE: Instruction ADD R32,-(rr4) HEX C2 45 20 Binary 1100 0010 0100 0101 0010 0000 If register 32 contains 207 (decimal), working register pair 4 contains 4200 (decimal) and memory location 4199 contains 27 (decimal), after this instruction register 32 will contain 234 and working register pair 4 will contain 4199. 82/298 1 ST9+ Programming Manual ADD Add (byte) Memory, Register ADD dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 12 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 4 4 4 4 4 4 4 4 4 4 4 4 ADD [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r Oper a a b b c c a a a a a a OPERATION a: dst dst + src The source byte is added to the destination byte and the result is stored in the destination byte. The source byte is held in the source register. The destination byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src rr rr + 1 The source byte is added to the destination byte and the result is stored in the destination byte. The source byte is in the source register, the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the ADD has been carried out. OPERATION c: rr rr - 1 dst dst + src The source byte is added to the destination byte and the result is stored in the destination byte. The source byte is in the source register, the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the ADD is carried out. 83/298 1 ST9+ Programming Manual ADD Add (byte) Memory, Register ADD dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. ADD EXAMPLE: Instruction ADD 6(rr8),R255 HEX 26 49 06 FF Binary 0010 0110 0100 1001 0000 0110 1111 1111 If working register pair 8 contains 4028 (decimal), memory location 4034 contains 110 (decimal) and register 255 contains 100 (decimal), after this instruction memory location 4034 will contain 210. 84/298 1 ST9+ Programming Manual ADD Add (byte) Memory, Memory ADD dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 14 14 OPC (HEX) 73 73 OPC XTN 4 4 ADD Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION: dst dst + src The source byte is added to the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. EXAMPLE: Instruction ADD (rr4),(rr8) HEX 73 48 D4 Binary 0111 0011 0100 1000 1101 0100 If working register pair 4 contains 2800 (decimal) and memory location 2800 contains 46 (decimal), working register pair 8 contains 4200 (decimal) and memory location 4200 contains 45 (decimal), after this instruction memory location 2800 will contain 91. 85/298 1 ST9+ Programming Manual ADD Add (byte) All, Immediate ADD dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 10 16 OPC (HEX) 45 45 F3 2F OPC XTN 4 41 ADD [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: dst dst + src The source byte is added to the destination byte and the result is stored in the destination byte. The source byte is the immediate value in the operand, the destination byte can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. EXAMPLE: Instruction ADD (rr8),#32 HEX F3 48 20 Binary 1111 0011 0100 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 74 (decimal), after this instruction memory location 4028 will contain 106. 86/298 1 ST9+ Programming Manual ADDW Add (Word) - Register, Register ADDW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 4E 47 47 47 96 96 A6 A6 ADDW OPC XTN 4 4 4 4 [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address Mode dst src rr rr RR RR rr RR RR rr (r) RR (r) rr RR (r) rr (r) OPERATION: dst dst + src The source word is added to the destination word and the result is stored in the destination word. The source and destination words, held in register pairs, can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction ADDW RR64,(r8) HEX A6 48 40 Binary 1010 0110 0100 1000 0100 0000 If working register 8 contains 124, register pair 124 contains 1300 (decimal) and register pair 64 contains 800 (decimal) after this instruction register pair 64 will contain 2100. 87/298 1 ST9+ Programming Manual ADDW Add (Word) - Register, Memory ADDW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 4E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 4 4 4 4 4 4 4 4 4 4 4 ADDW [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst + src The source word is added to the destination word and the result is stored in the destination word. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src rr rr + 2 The source word is added to the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the ADD has been carried out. OPERATION c: rr rr - 2 dst dst + src The source word is added to the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are decremented before the ADD is carried out. 88/298 1 ST9+ Programming Manual ADDW Add (Word) - Register, Memory ADDW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. ADDW EXAMPLE: Instruction ADDW RR64,(rr8) HEX 7E 48 40 Binary 0111 1110 0100 1000 0100 0000 If working register pair 8 contains 1240 (decimal), memory pair 1240 contains 3000 (decimal) and register pair 64 contains 1000 (decimal), after this instruction working register pair 64 will contain 4000. 89/298 1 ST9+ Programming Manual ADDW Add (Word) - Memory, Register ADDW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 16 18 18 18 18 18 18 18 18 18 20 20 OPC (HEX) 4E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 4 4 4 4 4 4 4 4 4 4 4 ADDW [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst dst + src The source word is added to the destination word and the result is stored in the destination word. The source word is held in the source register. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst + src rr rr + 2 The source word is added to the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the ADD has been carried out. OPERATION c: rr rr - 2 dst dst + src The source word is added to the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the ADD is carried out. 90/298 1 ST9+ Programming Manual ADDW Add (Word) - Memory, Register ADDW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. ADDW EXAMPLE: Instruction ADDW (rr4)+,RR64 HEX D5 44 40 Binary 1101 0101 0100 0100 0100 0000 If register pair 64 contains 1250 (decimal), working register pair 4 contains 1064 (decimal), and memory pair 1064 contains 1750, after this instruction is carried out memory pair 1064 will contain 3000 and working register pair 4 will contain 1066. 91/298 1 ST9+ Programming Manual ADDW Add (Word) - Memory, Memory ADDW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 20 OPC (HEX) 4E ADDW OPC XTN - Address Mode dst src (rr) (rr) OPERATION: dst dst + src The source word is added to the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction ADDW (rr4),(rr6) HEX 4E 57 Binary 0100 1110 0101 0111 If working register pair 6 contains 1002 (decimal), memory pair 1002 contains 2300 (decimal), working register pair 4 contains 1060 (decimal) and memory pair 1060 contains 2700 (decimal), after this instruction memory pair 1060 will contain 5000. 92/298 1 ST9+ Programming Manual ADDW Add (Word) - All, Immediate ADDW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 18 20 22 22 OPC (HEX) 47 47 BE 06 06 36 ADDW OPC XTN 4 4 4 41 [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address dst RR rr (rr) N(rr) NN(rr) NN Mode src #NN #NN #NN #NN #NN #NN OPERATION: dst dst + src The source word is added to the destination word and the result is stored in the destination word. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Set if carry from MSB of result, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction ADDW RR64,#4268 HEX 47 41 10 AC Binary 0100 0111 0100 0001 0001 0000 1010 1100 If register pair 64 contains 2000 (decimal), after this instruction has been carried out register pair 64 will contain the decimal value 6268. 93/298 1 ST9+ Programming Manual AND AND (byte) Register, Register AND dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 12 13 14 14 14 E6 E6 E7 OPC XTN 1 1 1 AND [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address dst r r R r R (r) (r) R Mode src r (r) R R r R r (r) OPERATION: dst dst AND src The contents of the source are ANDed with the destination byte and the results stored in the destination byte. The contents of the source are not affected. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction AND r8,R64 HEX 14 40 D8 Binary 0001 0100 0100 0000 1101 1000 If working register 8 contains 11001100 and register 64 contains 10000101, after this instruction working register 8 will contain 10000100. 94/298 1 ST9+ Programming Manual AND AND (byte) Register, Memory AND dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 1 1 1 1 1 1 1 1 1 1 1 1 AND [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst AND src The source byte is ANDed with the destination byte and the result stored in the destination byte. The destination register is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: dst dst AND src rr rr + 1 The contents of the memory location addressed by the source register pair are ANDed with the contents of the directly addressed destination register the result stored in the destination byte. The contents of the source register pair are incremented after the AND has been carried out. OPERATION c: rr rr - 1 dst dst AND src The contents of the source register pair are decremented and then the contents of the memory location addressed by the source register pair are ANDed with the contents of the directly addressed destination register. The result is stored in the destination byte. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. 95/298 1 ST9+ Programming Manual AND AND (byte) Register, Memory AND dst,src (Cont'd) EXAMPLE: Instruction AND r8,4028 HEX C4 18 0F BC Binary AND 1100 0100 0001 1000 0000 1111 1011 1100 If working register 8 contains 11001100 and memory location 4028 contains 10000101, after this instruction working register 8 will contain 10000100. 96/298 1 ST9+ Programming Manual AND AND (byte) Memory, Register AND dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 12 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 1 1 1 1 1 1 1 1 1 1 1 1 AND [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r Oper a a b b c c a a a a a a OPERATION a: dst dst AND src The source byte is ANDed with the destination byte and the result stored in the destination byte. The source registers are addressed directly, the memory location are addressed either directly, indirectly or by indexing. OPERATION b: dst dst AND src rr rr + 1 The contents of the memory location addressed by the destination register pair (destination byte) are ANDed with the contents of the directly addressed source register the result stored in the destination byte. The contents of the destination register pair are incremented after the AND has been carried out. OPERATION c: rr rr - 1 dst dst AND src The contents of the destination register pair are decremented and then the contents of the memory location addressed by the destination register pair (destination byte) are ANDed with the contents of the directly addressed source register. The result is stored in the destination byte. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. 97/298 1 ST9+ Programming Manual AND AND (byte) Memory, Register AND dst,src (Cont'd) EXAMPLE: Instruction AND 4028,r8 HEX C5 18 0F BC Binary AND 1100 0101 0001 1000 0000 1111 1011 1100 If working register 8 contains 11001100 and memory location 4028 contains 10000101, after this instruction memory location 4028 will contain 10000100. 98/298 1 ST9+ Programming Manual AND AND (byte) Memory, Memory AND dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 14 14 OPC (HEX) 73 73 OPC XTN 1 1 AND Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION: dst dst AND src The contents of the memory location addressed by the source register pair are ANDed with the content of the memory location addressed by the destination register pair. The source and destination addresses are for the word high order byte. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero Unaffected. Unaffected. EXAMPLE: Instruction AND (rr4),(rr8) HEX 73 18 D4 Binary 0111 0011 0001 1000 1101 0100 If working register pair 4 contains 2800 (decimal), memory location 2800 contains 11001100, working register pair 8 contains 4200 (decimal) and memory location 4200 contains 11000011, after this instruction memory location 2800 will contain 11000000. 99/298 1 ST9+ Programming Manual AND AND (byte) All, Immediate AND dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 10 16 OPC (HEX) 15 15 F3 2F OPC XTN 1 11 AND [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: dst dst AND src The value #N is ANDed with the content of the destination register or memory location (destination byte) and stored in the destination byte. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction AND (rr8),#32 HEX F3 18 20 Binary 1111 0011 0001 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 11101100, after this instruction memory location 4028 will contain 00100000. 100/298 1 ST9+ Programming Manual ANDW AND (Word) - Register, Register ANDW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 1E 17 17 17 96 96 A6 A6 ANDW OPC XTN 1 1 1 1 [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address dst rr RR rr RR (r) (r) RR rr Mode src rr RR RR rr RR rr (r) (r) OPERATION: dst dst AND src The source word is ANDed with the destination word. The result is left in the destination. The source and destination words can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Undefined. Undefined. EXAMPLE: Instruction ANDW RR32,RR64 HEX 17 40 20 Binary 0001 0111 0100 0000 0010 0000 If register pair 64 contains 11001100/11001100B and register pair 32 contains 10101010/10101010B, after this instruction register pair 32 will contain 10001000/ 10001000B. 101/298 1 ST9+ Programming Manual ANDW AND (Word) - Register, Memory ANDW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 1E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 1 1 1 1 1 1 1 1 1 1 1 ANDW [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst AND src The source word is ANDed with the destination word. The result is left in the destination word. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. The contents of the source are not affected. OPERATION b: dst dst AND src rr rr + 2 The source word is ANDed with the destination word. The result is left in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the AND has been carried out. OPERATION c: rr rr - 2 dst dst AND src The source word is ANDed with the destination word. The result is left in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are decremented before the AND is carried out. 102/298 1 ST9+ Programming Manual ANDW AND (Word) - Register, Memory ANDW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Undefined. Undefined. ANDW EXAMPLE: Instruction ANDW RR64,(rr4)+ HEX D5 15 40 Binary 1101 0101 0001 0101 0100 0000 If working register pair 4 contains 1184 (decimal), register pair 64 contains 10101010/ 10101010B and memory pair 1184 contains 11001100/11001100B, after this instruction register pair 64 will contain 10001000/10001000B and register pair 4 will contain 1186. 103/298 1 ST9+ Programming Manual ANDW AND (Word) - Memory, Register ANDW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 16 18 18 18 18 18 18 18 18 18 20 20 OPC (HEX) 1E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 1 1 1 1 1 1 1 1 1 1 1 ANDW [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,1] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst dst AND src The source word is ANDed with the destination word. The result is stored in the destination word. The source word is held in the source register pair. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst AND src rr rr + 2 The source word is ANDed with the destination word. The result is stored in the destination word. The source word is in the source register pair, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair pair are incremented after the AND has been carried out. OPERATION c: rr rr - 2 dst dst AND src The source word is ANDed with the destination word. The result is stored in the destination word. The source word is in the source register pair , the destination word is in the memory pair addressed by the destination register pair. The contents of the destination register pair pair are decremented before the AND is carried out. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Undefined. Undefined. 104/298 1 ST9+ Programming Manual ANDW AND (Word) - Memory, Register ANDW dst,src (Cont'd) EXAMPLE: Instruction ANDW (rr8),RR64 HEX BE 19 40 ANDW Binary 1011 1110 0001 1001 0100 0000 If register pair 64 contains 11001100/11001100B, working register pair 8 contains 2000 (decimal) and memory pair 2000 contains 10101010/10101010B, after this instruction memory pair 2000 will hold 10001000/10001000B. 105/298 1 ST9+ Programming Manual ANDW AND (Word) - Memory, Memory ANDW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 20 OPC (HEX) 1E ANDW OPC XTN - Address Mode dst src (rr) (rr) OPERATION: dst dst AND src The source word is ANDed with the destination word. The result is stored in the destination word. The source word is in the memory pair addressed by the source register pair, the destination word is in the memory pair addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Undefined. Undefined. EXAMPLE: Instruction ANDW (rr4),(rr6) HEX 1E 57 Binary 0001 1110 0101 0111 If working register pair 6 contains register 1002 (decimal), memory pair 1002 contains 11001100/11001100B, working register pair 4 contains 1060 (decimal), and memory pair 1060 contains 10101010/10101010B, after this instruction memory pair 1060 will contain 10001000/10001000B. 106/298 1 ST9+ Programming Manual ANDW AND (Word) - All, Immediate ANDW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 18 20 22 22 OPC (HEX) 17 17 BE 06 06 36 ANDW OPC XTN 1 1 1 11 [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address dst RR rr (rr) N(rr) NN(rr) NN Mode src #NN #NN #NN #NN #NN #NN OPERATION: dst dst AND src The source word is ANDed with the destination word. The result is stored in the destination word. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Undefined. Undefined. EXAMPLE: Instruction ANDW RR64,#52428 HEX 17 41 CC CC Binary 0001 0111 0100 0001 1100 1100 1100 1100 If register pair 64 contains 10101010/10101010B, after this instruction has been carried out register pair 64 will contain 10001000/10001000B. 107/298 1 ST9+ Programming Manual BAND Bit AND BAND dst.b,src.b INSTRUCTION FORMAT: [ [ OPC OPC ] ] [btd,1| dst ] [btd,1| dst ] [bts,1| src ] [bts,0| src ] No. Bytes 3 3 No. Cycl 10 10 OPC (HEX) 1F 1F OPC XTN - BAND Addr Mode dst src r.b r.b r.b r.!b Oper a b OPERATION a: dst bit dst bit AND src bit The selected bit in the source working register is ANDed with the selected bit of the destination working register and the result left in the destination bit. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. OPERATION b: dst bit dst bit AND NOT src bit The complement of the selected bit in the source working register is ANDed with the selected bit of the destination working register and the result left in the destination bit. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction BAND r4.5,r8.2 HEX 1F B4 58 Binary 0001 1111 1011 0100 0101 1000 If bit 2 of working register 8 is 0 and bit 5 of working register 4 is 1, after this instruction bit 5 of working register 4 will be 0. NOTE: A bit AND can use the same or different nibbles of the same register as both source and destination. 108/298 1 ST9+ Programming Manual BCPL Bit Complement BCPL dst.b INSTRUCTION FORMAT: [ OPC ] [btd,0| dst ] No. Bytes 2 No. Cycl 4 OPC (HEX) 6F OPC XTN - BCPL Address Mode dst src r.b - OPERATION: dst bit NOT dst bit The selected bit in the destination working register is set to its own complement. All other bits in the destination register remain unaffected. The destination is directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction BCPL r4.5 HEX 6F A4 Binary 0110 1111 1010 0100 If bit 5 of working register 4 was 1, after this instruction it will be 0. 109/298 1 ST9+ Programming Manual BLD Bit Load BLD dst.b,src.b INSTRUCTION FORMAT: [ [ OPC OPC ] ] [bts,1| src ] [bts,1| src ] [btd,0| dst ] [btd,1| dst ] No. Bytes 3 3 No. Cycl 10 10 OPC (HEX) F2 F2 OPC XTN - BLD Addr Mode dst src r.b r.b r.b r.!b Oper a b OPERATION a: dst bit src bit The selected bit in the source working register is loaded into the selected bit of the destination working register. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. OPERATION b: dst bit NOT src bit The complement of the selected bit in the source working register is loaded into the selected bit of the destination working register. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction BLD r4.5,r8.!2 HEX F2 58 B4 Binary 1111 0010 0101 1000 1011 0100 If bit 2 of working register 8 is 1, after this instruction bit 5 of working register 4 will be 0. NOTE: A bit load can use the same or different nibbles of the same register as both source and destination. 110/298 1 ST9+ Programming Manual BOR Bit OR BOR dst.b,src.b INSTRUCTION FORMAT: [ [ OPC OPC ] ] [btd,1| dst ] [btd,1| dst ] [bts,0| src ] [bts,1| src ] No. Bytes 3 3 No. Cycl 10 10 OPC (HEX) 0F 0F OPC XTN - BOR Addr Mode dst src r.b r.b r.b r.!b Oper a b OPERATION a: dst bit dst bit OR src bit The selected bit in the source working register is ORed with the selected bit of the destination register and the result left in the destination bit. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. OPERATION b: dst bit dst bit OR NOT src bit The complement of the selected bit in the source working register is ORed with the selected bit of the destination working register and the result left in the destination bit. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction BOR r4.5,r8.2 HEX 0F B4 48 Binary 0000 1111 1011 0100 0100 1000 If bit 2 of working register 8 is 1 and bit 5 of working register 4 is 0, after this instruction bit 5 of working register 4 will be 1. NOTE: A bit OR can use the same or different nibbles of the same register as both source and destination. 111/298 1 ST9+ Programming Manual BRES Bit Reset BRES dst.b INSTRUCTION FORMAT: [ OPC ] [btd,0| dst ] No. Bytes 2 No. Cycl 4 OPC (HEX) 1F OPC XTN - BRES Address Mode dst src r.b - OPERATION: dst bit 0 The selected bit in the destination working register is reset to 0. All other bits in the destination register remain unaffected. The destination is directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction BRES r4.5 HEX 1F A4 Binary 0001 1111 1010 0100 After this instruction bit 5 of working register 4 will be 0. 112/298 1 ST9+ Programming Manual BSET Bit Set BSET dst.b INSTRUCTION FORMAT: [ OPC ] [btd,0| dst ] No. Bytes 2 No. Cycl 4 OPC (HEX) 0F OPC XTN - BSET Address Mode dst src r.b - OPERATION: dst bit 1 The selected bit in the destination working register is set to 1. All other bits in the destination register remain unaffected. The destination is directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction BSET r4.5 HEX 0F A4 Binary 0000 1111 1010 0100 After this instruction bit 5 of working register 4 will be 1. 113/298 1 ST9+ Programming Manual BTJF Bit Test And Jump If False BTJF dst,src INSTRUCTION FORMAT: No. Bytes [ N ] 3 No.Cycl No Jmp Jmp 6 10 OPC (HEX) AF BTJF Addr Mode dst src r.b PC offs. N [ OPC ] [btd,1| dst ] OPERATION: If tested bit is zero then PC PC + N where -128 N 127 The specified bit in the destination working register is tested and if it is found to be equal to zero, the source value N is added to the program counter and control passes to the statement whose address is now in the PC. If the tested bit is one, the instruction following BTJF is executed. N is a relative value in the range +127/-128. FLAGS: No flags affected. EXAMPLE: Instruction BTJF r10.2,-40 HEX AF 5A D8 Binary 1010 1111 0101 1010 1101 1000 If bit 2 of working register 10 is zero and the program counter holds 200, after this instruction the program counter will jump to address 160. 114/298 1 ST9+ Programming Manual BTJT Bit Test And Jump If True BTJT dst,src INSTRUCTION FORMAT: No. Bytes [ N ] 3 No.Cycl No Jmp Jmp 6 10 OPC (HEX) AF BTJT Addr Mode dst src r.b PC offs. N [ OPC ] [btd,0| dst ] OPERATION: If tested bit is one then PC PC + N where -128 N 127 The specified bit in the destination working register is tested and if it is found to be equal to one, the source value N is added to the program counter and control passes to the statement whose address is now in the PC. If the tested bit is zero the instruction following BTJT is executed. N is a relative value in the range +127/-128. FLAGS: No flags affected. EXAMPLE: Instruction BTJT r10.2,+40 HEX AF 4A 28 Binary 1010 1111 0100 1010 0010 1000 If bit 2 of working register 10 is a one and the program counter holds 200, after this instruction the program counter will jump to address 240. 115/298 1 ST9+ Programming Manual BTSET Bit Test and Set BTSET dst.b INSTRUCTION FORMAT: [ [ OPC OPC ] ] [btd,0| dst ] [btd,0| dst,0 ] No. Bytes 2 2 No. Cycl 8 14 OPC (HEX) F2 F6 OPC XTN - BTSET Addr Mode dst src r.b (rr).b - Oper OPERATION: If dst.b = 0 then dst.b 1 The selected bit in the destination is tested; if zero it is set to one and the zero flag set. The destination is addressed either by working register direct or memory indirect. FLAGS: C: Z: S: V: D: H: Unaffected. Set if bit was zero, otherwise cleared. Set if bit 7 is tested and was set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction BTSET r4.5 HEX F2 A4 Binary 1111 0010 1010 0100 If bit 5 of working register 4 is 0, after this instruction it is set to 1 and the zero flag is also set to 1. 116/298 1 ST9+ Programming Manual BXOR Bit XOR BXOR dst.b,src.b INSTRUCTION FORMAT: [ [ OPC OPC ] ] [btd,1| dst ] [btd,1| dst ] [bts,0| src ] [bts,1| src ] No. Bytes 3 3 No. Cycl 10 10 OPC (HEX) 6F 6F OPC XTN - BXOR Addr Mode dst src r.b r.b r.b r.!b Oper a b OPERATION a: dst bit dst bit XOR src bit The selected bit in the source working register is XORed with the selected bit of the destination register and the result left in the destination bit. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. OPERATION b: dst bit dst bit XOR NOT src bit The complement of the selected bit in the source working register is XORed with the selected bit of the destination working register and the result left in the destination bit. All other bits in the destination register remain unaffected. Both source and destination are directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction BXOR r4.5,r8.2 HEX 6F B4 48 Binary 0110 1111 1011 0100 0100 1000 If bit 2 of working register 8 is 1 and bit 5 of working register 4 is 0, after this instruction bit 5 of working register 4 will be 1. NOTE: A bit XOR can use the same or different nibbles of the same register as both source and destination. 117/298 1 ST9+ Programming Manual CALL Unconditional Call Subroutine CALL dst INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ [ dst,1 dst h ] ] [ dst l ] No. Bytes 2 2 3 No. Cycl 12 12 12 OPC (HEX) 74 74 D2 OPC XTN - CALL Address Mode dst src (RR) (rr)* NN - OPERATION: SSP SSP - 2 (SSP) PC PC dst The current contents of the program counter (PC) are pushed onto the top of the system stack. (The program counter value used is the address of the first instruction byte following the CALL instruction). The specified destination address is then loaded into the PC and points to the first instruction of the CALL procedure. In direct memory addressing mode the destination is in the memory location addressed by the absolute value in the operand. In the indirect memory addressing mode the destination is in the memory location addressed by the contents of the destination register pair. FLAGS: No flags affected. EXAMPLE: Instruction CALL 3521H HEX D2 35 21 Binary 1101 0010 0011 0101 0010 0001 If the content of the program counter is 1A47 (hex) and the content of the system stack pointer is 3002 (hex) the above instruction will cause the stack pointer to be decremented to 3000 (hex), 1A4A (the address following the instruction) is stored in external data memory 3000 (hex) and 3001 (hex), and the program counter is loaded with 3521 (hex). The program counter now points to the address of the first statement in the procedure to be executed. 118/298 1 ST9+ Programming Manual CALLS Unconditional Far Call Subroutine CALLS seg, dst INSTRUCTION FORMAT: [ [ OPC OPC ][ ] [ seg ] [ dst,1 dst h ] [ ][ seg dst l ] ] No. Bytes 4 3 3 No. Cycl 16 16 16 OPC (HEX) 3F 73 73 CALLS Address Mode dst seg 01xx xxxx NN N (rr) (R) (rr) (r) OPC XTN OPERATION: SSP SSP - 1 (SSP) CSR SSP SSP - 2 (SSP) PC CSR seg PC dst This instruction uses a different stack frame, saving both the PC and the CSR on the stack. The current contents of the CSR and program counter (PC) are pushed onto the top of the system stack. (The program counter value used is the address of the first instruction byte following the CALLS instruction). The specified destination address is then loaded into the CSR and PC and points to the first instruction of the CALLS procedure. In direct memory addressing mode the destination is in the memory location addressed by the absolute value in the operands. In the indirect memory addressing mode the destination is in the memory location addressed by the contents of the destination registers. FLAGS: No flags affected. 119/298 1 ST9+ Programming Manual EXAMPLE: Instruction CALLS 12H, 3521H HEX 3F 52 35 21 Binary 0011 1111 0101 0010 0011 0101 0010 0001 If the content of the PC is 1A47 (hex), the content of CSR is 6 and the content of the system stack pointer is 3003 (hex) the above instruction will cause the stack pointer to be decremented to 3000 (hex), 1A4B (the address following the instruction) is stored in external data memory 3000 (hex) and 3001 (hex), the value 6 (CSR) is stored in 3002 (hex), CSR and PC are loaded with 12, 3521 (hex). The program counter now points to the address of the first statement in the procedure to be executed. Stack PCL PCH CSR 3003h 120/298 1 ST9+ Programming Manual CCF Complement Carry Flag CCF INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 4 OPC (HEX) 61 OPC XTN - CCF Address Mode dst src - OPERATION: C NOT C The carry flag is complemented; if C=1 it is changed to C=0 and vice-versa. FLAGS: C: Complemented. No other flags affected. EXAMPLE: Instruction CCF HEX 61 Binary 0110 0001 If the carry flag is set to one, after this instruction it will be reset to zero. 121/298 1 ST9+ Programming Manual CLR Clear Register CLR dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 4 4 OPC (HEX) 90 90 91 91 OPC XTN - CLR Address Mode dst src R r (R) (r) - OPERATION: dst 0 The contents of destination register, directly or indirectly addressed, is cleared to zero. FLAGS: No flags affected. EXAMPLE: Instruction CLR (R32) HEX 91 20 Binary 1001 0001 0010 0000 If register 32 holds 142, after this instruction register 142 will contain 0. 122/298 1 ST9+ Programming Manual CP Compare (byte) Register, Register CP dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 92 93 94 94 94 E6 E6 E7 OPC XTN 9 9 9 CP [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address Mode dst src r r r (r) R R r R R r (r) R (r) r R (r) OPERATION: dst - src The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source and destination byte can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB, otherwise set indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. EXAMPLE: Instruction CP (r8),R255 HEX E6 FF 98 Binary 1110 0110 1111 1111 1001 1000 If working register 8 contains 28 (decimal), register 28 contains 11001100 and register 255 contains 10000101, after this instruction: Z, C , S and V flags will be reset to zero. 123/298 1 ST9+ Programming Manual CP Compare (byte) Register, Memory CP dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 9 9 9 9 9 9 9 9 9 9 9 9 Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) CP Oper a a b b c c a a a a a a [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] OPERATION a: dst - src The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected The destination byte remains unaffected. The destination byte is held in the destination register. The source byte can be addressed directly, indirectly or by indexing. OPERATION b: dst - src rr rr + 1 The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are incremented after the CP has been carried out. OPERATION c: rr rr - 1 dst - src The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are decremented before the CP is carried out. 124/298 1 ST9+ Programming Manual CP Compare (byte) Register, Memory CP dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB, otherwise set indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. CP EXAMPLE: Instruction CP R32,-(rr4) HEX C2 95 20 Binary 1100 0010 1001 0101 0010 0000 If register 32 contains 11001100, working register pair 4 contains 4200 (decimal) and memory location 4199 contains 11001100, after this instruction, C, S, V flags will be reset to zero, the zero flag will be set to one and working register pair 4 will contain 4199. 125/298 1 ST9+ Programming Manual CP Compare (byte) Memory, Register CP dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 10 10 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 9 9 9 9 9 9 9 9 9 9 9 9 Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r CP Oper a a b b c c a a a a a a [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] OPERATION a: dst - src The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source byte is held in the source register. The destination byte can be addressed directly, indirectly or by indexing. OPERATION b: dst - src rr rr + 1 The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source byte is in the source register, the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the CP has been carried out. OPERATION c: rr rr - 1 dst - src The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source byte is in the source register , the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the CP is carried out. 126/298 1 ST9+ Programming Manual CP Compare (byte) Memory, Register CP dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB, otherwise set indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. CP EXAMPLE: Instruction CP 4028,R8 HEX C5 98 0F BC Binary 1100 0101 1001 1000 0000 1111 1011 1100 If memory location 4028 contains 11001100 and working register 8 contains 10000101, after this instruction the zero flag will be reset to zero. 127/298 1 ST9+ Programming Manual CP Compare (byte) Memory, Memory CP dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 12 12 OPC (HEX) 73 73 OPC XTN 9 9 CP Address dst (RR) (rr)* Mode src (rr) (rr) OPERATION: dst - src The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source byte is in the memory location addressed by the source register pair, the destination byte is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB, otherwise set indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. EXAMPLE: Instruction CP (rr4),(rr8) HEX 73 98 D4 Binary 0111 0011 1001 1000 1101 0100 If working register pair 4 contains 2800 (decimal), memory location 2800 contains 11001100, working register pair 8 contains 4200 (decimal) and memory location 4200 contains 11001100, after this instruction the zero flag will be set to one. 128/298 1 ST9+ Programming Manual CP Compare (byte) All, Immediate CP dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 8 14 OPC (HEX) 95 95 F3 2F OPC XTN 9 91 CP [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: dst - src The source byte is compared with (subtracted from) the destination byte and C, Z, S and V flags are affected. The destination byte remains unaffected. The source byte is the immediate value in the operand, the destination byte can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB, otherwise set indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. EXAMPLE: Instruction CP (rr8),#32 HEX F3 28 20 Binary 1111 0011 0010 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 11101100, after this instruction the zero flag will be reset to zero. 129/298 1 ST9+ Programming Manual CPJFI CPJFI dst,src,N INSTRUCTION FORMAT: No. Bytes [ PC Offset ] 3 No.Cycl No Jmp Jmp 14 16 OPC (HEX) 9F CPJFI Compare And Jump If False Otherwise Post-Increment Addr Mode dst r src (rr) PC offs. N [ OPC ] [src,0| dst ] OPERATION: If compare not verified jump, otherwise increment source register pair. The source operand is compared to (subtracted from) the destination operand. If the result is different from zero the offset N (where N is in the range -128/+127) is added to the program counter and control passes to the statement whose address is now in the PC, otherwise the source pointer is incremented by one and the instruction following the CPJFI is executed. FLAGS: No flags affected. EXAMPLE: Instruction CPJFI r2,(rr14),+100 HEX 9F E2 64 Binary 1001 1111 1110 0010 0110 0100 If the current value of the program counter is 340 (decimal) and working register 2 contains 11001100B, working register pair 14 contains 3000 (decimal) and memory location 3000 holds 10000100B the program counter will now point at program location 440 (decimal). NOTE : The source value must exist within the destination area (or limit checks must be included). 130/298 1 ST9+ Programming Manual CPJTI CPJTI dst,src,N INSTRUCTION FORMAT: No. Bytes [ PC Offset ] 3 No.Cycl No Jmp Jmp 14 16 OPC (HEX) 9F CPJTI Compare And Jump If True Otherwise Post-Increment Addr Mode dst r src (rr) PC offs. N [ OPC ] [src,1| dst ] OPERATION: If compare verified jump, otherwise increment source registers pair. The source operand is compared to (subtracted from) the destination operand. If the result is zero the offset N (where N is in the range -128/+127) is added to the program counter and control passes to the statement whose address is now in the PC, otherwise the source pointer is incremented by one and the instruction following the CPJTI is executed. FLAGS: No flags affected. EXAMPLE: Instruction CPJTI r2,(rr14),+100 HEX 9F F2 64 Binary 1001 1111 1111 0010 0110 0100 If the current value of the program counter is 340 (decimal) and working register 2 contains 11001100B, working register pair 14 contains 3000 (decimal) and memory location 3000 holds 11001100B the program counter will now point at program location 440 (decimal). NOTE : The source value must exist within the destination area (or limit checks must be included). 131/298 1 ST9+ Programming Manual CPL Complement Register CPL dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 4 4 OPC (HEX) 80 80 81 81 OPC XTN - CPL Address Mode dst src R r (R) (r) - OPERATION: dst NOT dst The contents of the destination register, directly or indirectly addressed, are one complemented (1 becomes 0 and 0 becomes 1). FLAGS: C: Z: S: V: D: H: Unaffected. Set if result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction CPL (R32) HEX 81 20 Binary 1000 0001 0010 0000 If register 32 contains 142 and register 142 holds 10101010B, after this instruction the contents of register 142 become 01010101B. 132/298 1 ST9+ Programming Manual CPW Compare (Word) - Register, Register CPW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 9E 97 97 97 96 96 A6 A6 OPC XTN 9 9 9 9 CPW [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address Mode dst src rr rr RR RR rr RR RR rr (r) RR (r) rr RR (r) rr (r) OPERATION: dst - src The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The source and destination word can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. EXAMPLE: Instruction CPW (r8),RR64 HEX 96 40 98 Binary 1001 0110 0100 0000 1001 1000 If register pair 64 contains 11001100/11001100B, working register 8 contains 200 (decimal) and register pair 200 contains 01001000/01001000B, after this instruction the zero flag will be reset. 133/298 1 ST9+ Programming Manual CPW Compare (Word) - Register, Memory CPW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 14 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 9E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 9 9 9 9 9 9 9 9 9 9 9 CPW [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst - src The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. OPERATION b: dst - src rr rr + 2 The source word is compared with (subtracted from) the destination word and appropriate flags set. The destination remains unaltered. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the compare has been carried out. OPERATION c: rr rr - 2 dst dst - src The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are decremented before the compare is carried out. 134/298 1 ST9+ Programming Manual CPW Compare (Word) - Register, Memory CPW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. CPW EXAMPLE: Instruction CPW RR64,-(rr4) HEX C3 95 40 Binary 1100 0011 1001 0101 0100 0000 If working register pair 4 contains 1184 (decimal), register pair 64 contains 11001100/ 11001100B and memory pair 1182 contains 11001100/11001100B, after this instruction has been carried out the zero flag will be set and register pair 4 will contain 1182. 135/298 1 ST9+ Programming Manual CPW Compare (Word) - Memory, Register CPW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 14 14 14 14 14 14 14 14 14 16 16 16 OPC (HEX) 9E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 9 9 9 9 9 9 9 9 9 9 9 CPW [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst - src The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The source word is held in the source register. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst - src rr rr + 2 The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the compare has been carried out. OPERATION c: rr rr - 2 dst - src The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The source word is in the source register , the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the compare is carried out. 136/298 1 ST9+ Programming Manual CPW Compare (Word) - Memory, Register CPW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. CPW EXAMPLE: Instruction CPW (rr4)+,RR64 HEX D5 94 40 Binary 1101 0101 1001 0100 0100 0000 If register pair 64 contains 11001100/11001100B, working register pair 4 contains 1064 (decimal) and memory pair 1064 contains 01001000/01001000B, after this instruction has been carried out the zero flag will be reset and working register pair 4 will contain 1066. 137/298 1 ST9+ Programming Manual CPW Compare (Word) - Memory, Memory CPW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 16 OPC (HEX) 9E OPC XTN - CPW Address Mode dst src (rr) (rr) OPERATION: dst - src The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The source word is in the memory location addressed by the source register pair, the destination word is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. EXAMPLE: Instruction CPW (rr4),(rr6) HEX 9E 57 Binary 1001 1110 0101 0111 If working register pair 6 contains 1002 (decimal), memory pair 1002 contains 11001100/11001100B, working register pair 4 contains 1060 (decimal) and memory pair 1060 contains 11001100/11001100B, after this instruction the zero flag will be set. 138/298 1 ST9+ Programming Manual CPW Compare (word) - All, Immediate CPW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 14 16 18 20 OPC (HEX) 97 97 BE 06 06 36 OPC XTN 9 9 9 91 CPW [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address Mode dst src RR #NN rr #NN (rr) #NN N(rr) NN(rr) NN #NN #NN #NN OPERATION: dst - src The source word is compared with (subtracted from) the destination word and the appropriate flags set. The destination remains unaltered. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. EXAMPLE: Instruction CPW RR64,#52428 HEX 97 41 CC CC Binary 1001 0111 0100 0001 1100 1100 1100 1100 If register pair 64 contains 01001000/01001000B, after this instruction has been carried out the zero flag will be reset to zero. 139/298 1 ST9+ Programming Manual DA Decimal Adjust DA dst INSTRUCTION FORMAT: [ OPC ] [ src ] No. Bytes 2 2 2 2 No. Cycl 4 4 6 6 OPC (HEX) 70 70 71 71 OPC XTN - DA Address Mode dst src R r (R) (r) - OPERATION: dst DA dst After an addition (ADD, ADC) or subtraction (SUB, SBC), this instruction adds a number, determined by the binary result of the previous arithmetic operation, in order to convert the contents of the destination register into two 4-bit BCD digits. The following table indicates the operation performed: Instruction Carry before DA 0 0 0 Bits 4-7 value (Hex) 0-9 0-8 0-9 A-F 9-F A-F 0-2 0-2 0-9 0-8 7-F 6-F H Flag before DA 0 0 1 0 0 1 0 0 0 1 0 1 Bits 0-3 value (Hex) 0-9 A-F 0-3 0-9 A-F 0-3 0-9 A-F 0-9 6-F 0-9 6-F Number added to byte 00 06 06 60 66 66 60 66 00 FA A0 9A Carry after DA 0 0 0 1 1 1 1 1 0 0 1 1 ADD ADC 0 0 0 1 1 0 SUB SBC 0 1 1 140/298 1 ST9+ Programming Manual DA Decimal Adjust DA dst (Cont'd) FLAGS: C: Z: S: V: D: H: Set if carry from MSB, otherwise cleared.(see table above) Set if result is zero, otherwise cleared. Set if result bit 7 is set, otherwise clered. Undefined. Unaffected. Unaffected. DA EXAMPLE: Instruction DA R32 HEX 70 20 Binary 0111 0000 0010 0000 If addition is performed using the BCD values 15 and 27, the result should be 42. The sum is incorrect, however, in the destination location when using standard binary arithmetic. 0001 0010 0011 0101 0111 1100 =3C H 0011 0000 0100 1100 0110 0010 =42H The DA statement adjusts this result so that the correct BCD representation is obtained. 141/298 1 ST9+ Programming Manual DEC Decrement Register DEC dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 4 4 OPC (HEX) 40 40 41 41 OPC XTN - DEC Address Mode dst src R r (R) (r) - OPERATION: dst dst - 1 The content of destination register, directly or indirectly addressed, is decremented by 1. FLAGS: C: Z: S: V: D: H: Unaffected. Set if result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Unaffected. Unaffected. EXAMPLE: Instruction DEC (r2) HEX 41 D2 Binary 0100 0001 1101 0010 If working register 2 holds 122 and register 122 contains 100 (decimal), after this instruction is executed register 122 will contain 99. 142/298 1 ST9+ Programming Manual DECW Decrement Word Register DECW dst INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] No. Bytes 2 2 No. Cycl 6 6 OPC (HEX) CF CF DECW OPC XTN - Address Mode dst src RR rr - OPERATION: dst dst - 1 The destination register content is decremented by 1. FLAGS: C: Z: S: V: D: H: Unaffected. Set if result is zero, otherwise cleared. Set if result is negative, otherwise cleared. Set if arithmetic overflow occurred, otherwise cleared. Unaffected. Unaffected. EXAMPLE: Instruction DECW rr2 HEX CF D2 Binary 1100 1111 1101 0010 If working register pair 2 holds 2000 (decimal), after this instruction is executed it will contain 1999 (decimal). 143/298 1 ST9+ Programming Manual DI Disable Interrupts DI INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 2 OPC (HEX) 10 OPC XTN - DI Address Mode dst src - OPERATION: CIC.4 0 Bit 4 of the Central Interrupt Control register (R230) is reset to zero. All interrupts except NMI are then disabled. FLAGS: No flags affected. EXAMPLE: Instruction DI HEX 10 Binary 0001 0000 After this instruction all interrupts (except NMI) are disabled. NOTE: The NMI (Not Maskable Interrupt) can be disabled only with a general chip reset. 144/298 1 ST9+ Programming Manual DIV Divide (16/8) DIV dst,src INSTRUCTION FORMAT: [ OPC ] [dst,0| src ] No. Bytes 2 No. Cycl 26/14 OPC (HEX) 5F OPC XTN - DIV Address Mode dst src rr r OPERATION: dst/src:dst (low) - result dst (high) - remainder The contents of the destination register pair are divided by the contents of the source register. The result is left in the destination register low byte and the remainder in the destination register high byte. This operation takes 26 clock cycles. If the dividend high byte is greater than the divider, this operation takes 14 clock cycles. Input Output rr_dst r_src rr_dst high rr_dst low = dividend = divisor = remainder = result The src byte holds the unmodified divisor. FLAGS: C: Z: S: V: D: H: Set to one if divide performed correctly, reset in case of overflow. Set if result is zero, otherwise reset. Set if reminder is zero, otherwise reset. Undefined. Always set to one. Undefined. EXAMPLE: Instruction DIV rr8,r6 HEX 5F 86 Binary 0101 1111 1000 0110 If working register 6 contains 30 (decimal) and working register pair 8 contains 500 (decimal), after this instruction working register 9 will contain 16 (decimal) and working register 8 will contain 20 (decimal). 145/298 1 ST9+ Programming Manual DIV Divide (16/8) DIV dst,src (Cont'd) NOTE 1: DIV If the dividend high is greater than or equal to the divisor the instruction is not carried out, the carry flag is reset to zero (D flag is always set to one), all other flags are undefined. This control takes 20 clock cycles and both destination and source register remain unmodified. If the divisor is zero, a trap is generated simulating a subroutine call. The current Program Counter is saved on the system stack and then the PC is set to the contents of memory locations 0002 and 0003 of the Program memory which contains the Divide-by-zero trap vector. This procedure takes 38 clock cycles. Location 0002 Interrupt Vector Pointer High Location 0003 Interrupt Vector Pointer Low The "divide by zero attempted" subroutine should be written by the user. NOTE 2: Warning: The subroutine must be terminated by RET (not IRET). 146/298 1 ST9+ Programming Manual DIVWS Divide Word Stepped (32/16) DIVWS dsth, dstl, src INSTRUCTION FORMAT: [ OPC ] [ src,0 ] [dsh,0|dsl,0] No. Bytes 3 3 No. Cycl 26 26 OPC (HEX) 56 56 OPC XTN - DIVWS Address Mode dsh dsl src rr rr RR rr rr rr OPERATION: When executed 16 times and then followed by a RLCW on the destination low working register pair, this instruction carries out a 32 bit by 16 bit divide and leaves the result in the destination low working register pair and the remainder in the destination high working register pair. No automatic controls are carried out on the relationship between divisor and dividend before this instruction is carried out, nor is the divisor checked for zero, these should be supplied by the user. FLAGS: All undefined. EXAMPLE: Instruction DIVWS rr6,rr8,RR10 HEX 56 0A 68 Binary 0101 0110 0000 1010 0110 1000 Working register pair 6 will contain the 16 high order bits of the dividend, working register pair 8 will contain the 16 low order bits of the dividend and register pair 10 will contain the 16 bit divisor. After this instruction working register pair 8 will contain the result and working register pair 6 the remainder. See subroutine example. NOTE: A typical example of a subroutine using the DIVWS instruction is shown below. 147/298 1 ST9+ Programming Manual DIVWS Divide Word Stepped (32/16) DIVWS dsth, dstl, src (Cont'd) DIVSTEP SUBROUTINE EXAMPLE DIVWS This subroutine first checks that divisor is greater than the dividend high byte and that the divisor is greater than zero before carrying out the division. d_len = r0 dvsr = RR10 dvd_hi = rr6 dvd_low = rr8 ; ;inputs: RR10 = 16 bit divisor ; rr6 = 32 bit dividend high ; rr8 = 32 bit dividend low ;outputs: RR10 = unmodified divisor ; rr6 = remainder ; rr8 = result ; DIVSTEP: cpw dvd_hi,dvsr ;check dividend higher than divisor jrug Out ;if not leave subroutine cpw dvsr,#0000h ;check divisor zero jrnz Defloop ;if true start divide Out: ret Defloop: pushu d_len ;set 16 bit step divide loop ld d_len,#16 Loop: divws dvd_hi,dvd_low,dvsr ;carry out divws djnz d_len,Loop ;16 times rlcw dvd_low popu d_len ret 148/298 1 ST9+ Programming Manual DJNZ Decrement And Jump If Not Zero DJNZ dst,N INSTRUCTION FORMAT: [ dst | OPC ] [ PC Offset ] No. Bytes 2 No. Cycl 6 OPC (HEX) A OPC XTN Addr Mode dst src r - DJNZ PC offs. N OPERATION: dst dst - 1 If dst not equal to 0 then PC PC + N The destination working register being used as a counter is decremented. If the contents of the register are not zero after decrementing, the offset N (where N is in the range -128/+127) is added to the program counter. The original value of the program counter is taken to be the address of the instruction byte following the DJNZ instruction. When the working register counter reaches zero, control falls through to the statement following the DJNZ statement. FLAGS: EXAMPLE: No flags affected. DJNZ is typically used to control a "loop" of instructions. In the following example 12 bytes are moved from one area in the register file to another one. The steps involved are: ;load 12 into the counter (working register 6) ;set up the loop to perform the moves ;end the loop with djnz pointer1 = oldbuf-1 pointer2 = newbuf-1 ld ld ld djnz r6,#12 ;load counter r9,pointer1(r6 ;move one byte to pointer2(r6),r9;new location r6,Loop ;decrement and loop until ;counter = 0 Loop: NOTE : Due to the ST9 architecture, the DJNZ instruction cannot be used with registers in group E or F accessed through working registers pointing to such groups, as the result of this test is undefined. 149/298 1 ST9+ Programming Manual DWJNZ DWJNZ dst,N INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] [ PC Offset ] No. Bytes 3 3 No. Cycl 8 8 OPC (HEX) 16 16 OPC XTN C6 C6 DWJNZ Decrement Word And Jump If Not Zero Addr Mode dst src RR rr - PC offs. N N OPERATION: dst dst - 1 If dst not equal to 0 then PC PC + N The destination register being used as a counter is decremented. If the contents of the register are not zero after decrementing, the offset N (where N is in the range -128/ +127) is added to the program counter. The original value of the program counter is taken to be the address of the instruction byte following the DWJNZ instruction. When the register counter reaches zero, control falls through to the statement following the DWJNZ statement. FLAGS: EXAMPLE: No flags affected. DWJNZ is typically used to control a "loop" of instructions. In the following example 300 bytes are moved from one area in the register file to another. The steps involved are: ;load 300 into the counter (working register pair 6) ;set up the loop to perform the moves ;end the loop with dwjnz pointer1 = oldbuf-1 pointer2 = newbuf-1 ld rr6,#300 ;load counter Loop: ld r9, pointer1(rr6) ;move one to byte ld pointer2(rr6),r9 ;new location dwjnz rr6,Loop ;decrement and loop until ;counter = 0 NOTE : Due to the ST9 architecture, the DWJNZ instruction cannot be used with registers in group E or F accessed through working registers pointing to such groups, as the result of this test is undefined. 150/298 1 ST9+ Programming Manual EI Enable Global Interrupts EI INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 2 OPC (HEX) 00 OPC XTN - EI Address Mode dst src - OPERATION: CIC.4 1 Bit 4 of the Central Interrupt Control register (R230) is set to one. All interrupts except NMI are then enabled. FLAGS: No flag affected. EXAMPLE: Instruction EI HEX 00 Binary 0000 0000 After this instruction all interrupts (except NMI) are enabled. NOTE: The NMI (Not Maskable Interrupt) must be separately enabled (see Technical Manual). 151/298 1 ST9+ Programming Manual EXT Sign Extend EXT dst INSTRUCTION FORMAT: [ OPC ] [ dst,1 ] No. Bytes 2 2 No. Cycl 6 6 OPC (HEX) C6 C6 OPC XTN - EXT Address Mode dst src RR rr - OPERATION: dst(n) MSB dst(7) LSB; where n=8,..,15 This instruction extends to the MSB register the sign bit (bit 7) of the LSB register. If bit 7 of the LSB is 1, all bits of the MSB register will be set to 1, if bit 7 of the LSB is 0, all bits of the MSB are reset. The destination is directly addressed. FLAGS: No flags affected. EXAMPLE: Instruction EXT RR10 HEX C6 0B Binary 1100 0110 0000 1011 If bit 7 of register R11 is 1, after this instruction all bits in register R10 will be 1. 152/298 1 ST9+ Programming Manual HALT Halt HALT INSTRUCTION FORMAT: [ OPC ] [ XTN ] No. Bytes 2 No. Cycl inf. OPC (HEX) BF OPC XTN 01 HALT Address Mode dst src - OPERATION: FLAGS: Stops program execution until next system reset. No flags Affected. EXAMPLE: Instruction HALT HEX BF 01 Binary 1011 1111 0000 0001 When the program encounters this instruction it is halted until a reset is executed. 153/298 1 ST9+ Programming Manual INC Increment Register INC dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 4 4 OPC (HEX) 50 50 51 51 OPC XTN - INC Address Mode dst src R r (R) (r) - OPERATION: dst dst + 1 The content of the destination register, directly or indirectly addressed, is incremented by 1. FLAGS: C: Z: S: V: D: H: Unaffected. Set if result is zero, otherwise cleared. Set if result is negative, otherwise cleared. Set if arithmetic overflow occurred, otherwise cleared. Unaffected. Unaffected. EXAMPLE: Instruction INC (R32) HEX 51 20 Binary 0101 0001 0010 0000 If register 32 holds 142 and register 142 contains 95 (decimal), after this instruction register 142 will contain 96. 154/298 1 ST9+ Programming Manual INCW Register Increment Word INCW dst INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] No. Bytes 2 2 No. Cycl 6 6 OPC (HEX) DF DF OPC XTN - INCW Address Mode dst src RR rr - OPERATION: dst dst + 1 The destination register pair content is incremented by 1. FLAGS: C: Z: S: V: D: H: Unaffected. Set if result is zero, otherwise cleared. Set if result is negative, otherwise cleared. Set if arithmetic overflow occurred, otherwise cleared. Unaffected. Unaffected. EXAMPLE: Instruction INCW RR32 HEX DF 20 Binary 1101 1111 0010 0000 If register pair 32 contains 4000 (decimal) after this instruction it will contain 4001 (decimal). 155/298 1 ST9+ Programming Manual IRET Interrupt Return IRET INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 12/14/16 OPC (HEX) D3 OPC XTN - IRET Address Mode dst src - OPERATION: EMR2.EMCSV = 0 (ISR used): FLAGS (SSP) SSP SSP + 1 PC (SSP) SSP SSP + 2 CICR.4 1 EMR2.EMCSV = 1 (CSR used): FLAGS (SSP) SSP SSP + 1 CSR (SSP) SSP SSP + 1 PC (SSP) SSP SSP + 2 CICR.4 1 Issued at the end of an interrupt service routine, this instruction restores the flag register and the program counter. It also re-enables any interrupts that are potentially enabled. This instruction has a different operation if bit ENCSR of EMR2 is set. When bit ENCSR of register EMR2 is set, CSR is also pushed in the case of an interrupt, and is restored when IRET is executed. FLAGS: All flags are restored to original setting (before interrupt occurred). EXAMPLE: Instruction IRET HEX D3 Binary 1101 0011 This instruction causes the program to resume execution exactly at the point it left when an interrupt service routine was initiated. All flags are set to the status they had when the interrupt service routine was started. EMR2.EMCSV = 0 (ISR used): EMR2.EMCSV = 1 (CSR used): 2002h PCL PCH FLAGS 2000h PCL PCH CSR FLAGS 2002h 2000h 156/298 1 ST9+ Programming Manual JP Unconditional Jump JP dst INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ [ dst,0 dst h ] ] [ dst l ] No. Bytes 2 2 3 No. Cycl 8 8 8 OPC (HEX) D4 D4 8D OPC XTN - JP Address Mode dst src (RR) (rr)* NN - OPERATION: PC dst The unconditional jump simply replaces the contents of the program counter with the destination contents. Control then passes to the statement addressed by the program counter. The destination operand can be in a directly or indirectly addressed program memory location. FLAGS: No flags affected. EXAMPLE: Instruction JP 1024 HEX 8D 04 00 Binary 1000 1101 0000 0100 0000 0000 The instruction replaces the content of the program counter with 1024 (decimal) and transfers program control to that location. 157/298 1 ST9+ Programming Manual JPS Unconditional Far Jump JPS seg, dst INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ [ dst,1 seg ] [ ] [ dst h seg ][ ] dst l ] No. Bytes 3 3 4 No. Cycl 10 10 10 OPC (HEX) 73 73 3F OPC XTN C0 C0 C0 JPS Address Mode dst seg (rr) (r) (rr) (R) NN N OPERATION: CSR src PC dst The unconditional inter segment jump simply replaces the contents of the CSR and program counter with the destination contents. Control then passes to the statement addressed by the program counter. The destination operand can be in a directly or indirectly addressed program memory location. FLAGS: No flags affected. EXAMPLE: Instruction JPS 0,1024 HEX 3F C0 04 00 Binary 0011 1111 1100 0000 0000 0100 0000 0000 The instruction replaces the content of the program counter with 1024 (decimal) and transfers program control to that location. 158/298 1 ST9+ Programming Manual JPcc Conditional Jump JPcc dst INSTRUCTION FORMAT: [ cc | OPC ] [ dst h ] [ dst l ] No. Bytes 3 No. Cycl 6/8 OPC (HEX) D OPC XTN - JPcc Address Mode dst src NN - OPERATION: If cc is true, PC dst The conditional jump transfers program control to the designated location if the condition code specified by "cc" is true. The destination operand is a directly addressed program memory location. FLAGS: No flags affected. EXAMPLE: Instruction JPEQ 1024 HEX 6D 04 00 Binary 0110 1101 0000 0100 0000 0000 If the result of the last mathematic or logic operation left the zero flag set, then the program counter is loaded with 1024 (decimal) and control is transferred to that location. 159/298 1 ST9+ Programming Manual JRcc Conditional Jump Relative JRcc dst INSTRUCTION FORMAT: No. Bytes ] 2 No. Cycl No Jmp Jmp 6 6 OPC (HEX) B OPC XTN - JRcc Addr Mode dst N src - [ cc | OPC ] [ dst OPERATION: If cc is true, PC PC + dst The conditional jump adds the immediate data to the program counter and control is transferred to the new location if the condition code specified by "cc" is true. The range of the relative address is +127/-128, and the original value of the program counter is taken to be the address of the first instruction byte following the JRcc statement. FLAGS: No flags affected. EXAMPLE: Instruction JREQ 24 HEX 6B 18 Binary 0110 1011 0001 1000 If the result of the last mathematic or logic operation left the zero flag set then the program counter is loaded with the present value plus 24 and control is transferred to that location. 160/298 1 ST9+ Programming Manual LD Load (byte) Register, Register LD dst,src INSTRUCTION FORMAT: [ dst | OPC ] [ src | OPC ] [ OPC ] [ [ [ [ [ OPC OPC OPC OPC OPC ] ] ] ] ] [ src ] No. Bytes 2 2 2 3 2 3 3 3 3 3 No. Cycl 4 6 4 4 6 6 6 6 6 6 OPC (HEX) 8 8 9 E6 E4 E6 E7 B2 B3 F4 OPC XTN F F F - LD [ dst ] [ dst | src ] [ src ] [ XTN | src ] [ src | dst ] [ dst | src ] [ src ] [ XTN | dst [ dst [ ofd [ ofs [ dst ] ] ] ] ] Address Mode dst src r R r r R r (r) r r (r) (r) R R (r) N(r) r r N(r) R R OPERATION: dst src The contents of the source are loaded into the destination. The contents of the source are not affected. The source and destination can both be addressed directly, indirectly or by indexing. FLAGS: No flags affected. EXAMPLE: Instruction LD r8,72(r5) HEX B3 85 48 Binary 1011 0011 1000 0101 0100 1000 If register 5 contains 183 (decimal) and register 255 (i.e. 183+72) contains 131 (decimal), after this instruction working register 8 will contain 131. 161/298 1 ST9+ Programming Manual LD Load (byte) Register, Memory LD dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [ dst |src,0] ] [ dst |src,1] ] [ XTN |src,1] [ No. Bytes 2 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 12 12 12 12 12 8 12 12 12 10 14 14 OPC (HEX) B5 D7 B4 B4 C2 C2 72 60 7F 7F C4 7F 7F OPC XTN F F F F F F F F F F F Addr Mode dst src r (rr) (r)+ (rr)+ R (rr)+ r (rr)+ R -(rr) r -(rr) R (rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) LD Oper a d b b c c a a a a a a a dst ] [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] OPERATION a: dst src The destination register will be loaded with the contents of the memory location addressed either directly, indirectly or by indexing. OPERATION b: dst src rr rr + 1 The contents of the memory location addressed by the source register pair are loaded into the directly addressed destination register. The contents of the source register pair are incremented after the load has been carried out. OPERATION c: rr rr - 1 dst src The contents of the source register pair are decremented and then the contents of the memory location addressed by the source register pair are loaded into the directly addressed destination register. OPERATION d: dst src rr+1 rr rr + 1 The contents of the memory location addressed by the source register pair are loaded into the register addressed by the destination register. The source and destination register are incremented after the load has been carried out. 162/298 1 ST9+ Programming Manual LD Load (byte) Register, Memory LD dst,src (Cont'd) FLAGS: No flags affected. LD EXAMPLE: Instruction LD (r4)+,(rr6)+ HEX D7 47 Binary 1101 0111 0100 0111 If working register 4 contains 100 (decimal), working register pair 6 contains 1242 (decimal) and memory location 1242 contains 132, after this instruction register 100 will contain 132, working register 4 will contain 101 and working register 6 will contain 1243. 163/298 1 ST9+ Programming Manual LD Load (byte) Memory, Register LD dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [ src |dst,0] ] [ src |dst,1] ] [ XTN |dst,0] [ No. Bytes 2 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 8 12 12 12 12 10 12 12 12 10 14 14 OPC (HEX) D7 B5 B4 B4 C2 C2 72 60 26 26 C5 26 26 OPC XTN F F F F F F F F F F F Addr Mode dst src (rr)+ (r)+ (rr) (r) (rr)+ R (rr)+ r -(rr) R -(rr) r (rr) R rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r LD Oper d a b b c c a a a a a a a src ] [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] OPERATION a: dst src The data in the source register is loaded into the memory location addressed either directly, indirectly or by indexing. OPERATION b: dst src rr rr + 1 The memory location addressed by the destination register pair is loaded with the contents of the directly addressed source register. The contents of the destination register pair are incremented after the load has been carried out. OPERATION c: rr rr - 1 dst src The contents of the destination register pair are decremented and then the memory location addressed by the the destination register pair is loaded with the contents of the directly addressed source register. OPERATION d: dst src rr+1 rr rr + 1 The memory location addressed by the destination register pair is loaded with the contents of the register addressed by the source register. The source and destination register are incremented after the load has been carried out. 164/298 1 ST9+ Programming Manual LD Load (byte) Memory, Register LD dst,src (Cont'd) FLAGS: No flags affected. LD EXAMPLE: Instruction LD (rr4)+,(r6)+ HEX D7 64 Binary 1101 0111 0110 0100 If working register pair 4 contains 1000 (decimal), working register 6 contains 242 (decimal) and register 242 contains 132, after this instruction memory location 1000 will contain 132, working register pair 4 will contain 1001 and working register 6 will contain 243. 165/298 1 ST9+ Programming Manual LD Load (Byte) Memory, Memory LD dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 10 10 OPC (HEX) 73 73 OPC XTN F F LD Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION: dst src The contents of the memory location addressed by the source register pair are loaded into the memory location addressed by the destination register pair. FLAGS: No flags affected. EXAMPLE: Instruction LD (rr4),(rr6) HEX 73 F6 D4 Binary 0111 0011 1111 0110 1101 0100 If working register pair 4 contains 1000 (decimal), working register pair 6 contains 1242 (decimal) and memory location 1242 contains 132, after this instruction memory location 1000 will contain 132. 166/298 1 ST9+ Programming Manual LD Load (Byte) All, Immediate LD dst,src INSTRUCTION FORMAT: [ dst | OPC [ OPC [ OPC [ OPC [ dst h ] ] ] ] ] [ src ] [ dst ] [ XTN |dst,0] [ XTN ] [ dst l ] No. Bytes [ [ [ src src src ] ] ] 2 3 3 5 No. Cycl 4 6 8 14 OPC (HEX) C F5 F3 2F OPC XTN F F1 LD Address Mode dst src r #N R #N (rr) #N NN #N OPERATION: dst src The value #N is loaded into the destination register or memory location. FLAGS: No flags affected. EXAMPLE: Instruction LD r8,#242 HEX 8C F2 Binary 1000 1100 1111 0010 After this instruction has been carried out working register 8 contains the decimal value 242. 167/298 1 ST9+ Programming Manual LDPP LDDP LDPD LDDD Load (Byte) Data/Program Memory, Data/Program Memory LDPP dst,src LDDP dst,src LDPD dst,src LDDD dst,src No. Bytes 2 2 2 2 No. Cycl 14 14 14 14 OPC (HEX) D6 D6 D6 D6 OPC XTN Address Mode dst src (rr)+ (rr)+ (rr)+ (rr)+ (rr)+ (rr)+ (rr)+ (rr)+ INSTRUCTION FORMAT: LDPP: LDDP: LDPD: LDDD: [ [ [ [ OPC OPC OPC OPC ] ] ] ] [dst,0|src,0] [dst,1|src,0] [dst,0|src,1] [dst,1|src,1] OPERATION: dst src rrd rrd + 1 rrs rrs + 1 The data in the indirectly addressed memory source byte is loaded into the indirectly addressed memory destination byte. The contents of the working register pairs used to address both source and destination are incremented after the instruction has been carried out. Source and destination can be both in the data memory, both in the program memory or one can be in the data memory while the other is in the program memory. FLAGS: No flags affected. EXAMPLE: Instruction LDDD (rr8)+,(rr12)+ HEX D6 9D Binary 1101 0110 1001 1101 If working register pair 8 contains 1131 (decimal), working register pair 12 contains 2400 (decimal) and the memory location 2400 contains 100 (decimal), after this instruction memory location 1131 will contain 100, working register pair 8 will contain 1132 and working register pair 12 will contain 2401. 168/298 1 ST9+ Programming Manual LDW Load (Word) Register, Register LDW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ OPC OPC OPC OPC OPC OPC ] ] ] ] ] ] [dst,0|src,0] [ src,0 ] [ XTN | src ] [src,1| dst ] [dst,0| src ] [ src,0 ] No. Bytes [ XTN | dst ] [ [ [ [ dst,0 ofd ofs dst,0 ] ] ] ] 2 3 3 3 3 3 3 3 3 3 No. Cycl 6 6 6 8 8 10 8 6 6 6 OPC (HEX) E3 96 96 A6 A6 DE DE EF EF EF OPC XTN F F F F - LDW Address Mode dst src rr rr (r) RR (r) rr RR (r) rr (r) N(r) rr rr N(r) RR RR rr RR RR rr OPERATION: dst src The contents of the source are loaded into the destination. The contents of the source are not affected. The source and destination can be addressed directly, indirectly or by indexing. FLAGS: No flags affected. EXAMPLE: Instruction LDW rr8,RR254 HEX EF FE D8 Binary 1110 1111 1111 1110 1101 1000 If register pair 254 contains 3F C1 (hex), after this instruction the working register pair 8 will contains 3F C1 (hex). 169/298 1 ST9+ Programming Manual LDW Load (Word) Register, Memory LDW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] [dst,0|src,1] ] [ XTN |src,1] [ No. Bytes dst,0 ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 10 14 14 14 14 10 14 14 14 12 16 16 OPC (HEX) E3 D5 D5 C3 C3 7E 60 86 86 E2 86 86 OPC XTN F F F F F F F F F F F LDW [ [ [ [ [ [ [ [ OPC OPC OPC dst,0 OPC src l OPC ofs l ] [ XTN |src,0] [ dst,0 ] ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) RR (rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a b b c c a a a a a a a OPERATION a: dst src In the destination register pair will be loaded the contents of the memory location addressed either directly, indirectly or by indexing. OPERATION b: dst src rr rr + 2 The word in the memory pair addressed by the source register pair is loaded into the destination register pair The source address is for the word high order byte. The contents of the source register pair are incremented by two after the load has been carried out. OPERATION c: rr rr - 2 dst src The contents of the source register pair are decremented twice and then the word in the memory pair addressed by the source register pair is loaded into the destination register pair. The source address is for the word high order byte. FLAGS: No flags affected. EXAMPLE: Instruction LD rr8,(rr4)+ HEX D5 F5 D8 Binary 1101 0101 1111 0101 1101 1000 If working register 4 contains 2400 (decimal) and memory pair 2400 contains 56 ED (Hex), after this instruction working register pair 8 will contain 56 ED and working register pair 4 will contain 2402. 170/298 1 ST9+ Programming Manual LDW Load (Word) Memory, Register LDW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] [dst,1|src,0] ] [ XTN |dst,0] [ No. Bytes src,0 ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 14 14 14 14 12 14 14 14 14 16 16 OPC (HEX) E3 D5 D5 C3 C3 BE 60 86 86 E2 86 86 OPC XTN F F F F F F F F F F F LDW [ [ [ [ [ [ [ [ OPC OPC OPC src,1 OPC dst l OPC ofd l ] [ XTN |dst,1] [ src,0 ] ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |src,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr (rr) RR rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a b b c c a a a a a a a OPERATION a: dst src The contents of the source register pair are loaded into the memory pair addressed either directly, indirectly or by indexing. The destination address is for the word high order byte. OPERATION b: dst src rr rr + 2 The contents of the source register pair are loaded into the memory pair addressed by the contents of the destination register pair. The destination address is for the word high order byte. The contents of the destination register pair are incremented twice after the load has been carried out. OPERATION c: rr rr - 2 dst src The contents of the destination register pair are decremented twice and then the contents of the source register pair are loaded into the memory pair addressed by the contents of the destination register pair. The destination address is for the word high order byte. 171/298 1 ST9+ Programming Manual LDW Load (Word) Memory, Register LDW dst,src (Cont'd) FLAGS: No flags affected. LDW EXAMPLE: Instruction LDW (rr4)+,RR64 HEX D5 F4 40 Binary 1101 0101 1111 0100 0100 0000 If working register pair 4 contains 1024 (decimal) and register pair 64 contains 8F E3 (Hex), after this instruction memory pair 1024 will contain 8F E3 and register pair 4 will contain 1026. 172/298 1 ST9+ Programming Manual LDW Load (Word) Memory, Memory LDW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 16 OPC (HEX) E3 OPC XTN - LDW Address Mode dst src (rr) (rr) OPERATION: dst src The contents of the memory pair addressed by the source register pair are loaded into the memory pair addressed by the destination register pair. The source and destination addresses are for the word high order byte. FLAGS: No flags affected. EXAMPLE: Instruction LDW (rr4),(rr6) HEX E3 57 Binary 1110 0011 0101 0111 If working register pair 4 contains 1024 (decimal), working register pair 6 contains 2042 (decimal) and memory pair 2042 contains CB ED (Hex), after this instruction memory pair 1024 will contain CB ED. 173/298 1 ST9+ Programming Manual LDW Load (Word) All, Immediate LDW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,0 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 8 8 14 18 20 18 OPC (HEX) BF BF BE 06 06 36 OPC XTN F F F F1 LDW [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address dst RR rr (rr) N(rr) NN(rr) NN Mode src #NN #NN #NN #NN #NN #NN OPERATION: dst src The value #NN is loaded into the destination register pair or memory pair. FLAGS: No flags affected. EXAMPLE: Instruction LDW RR100,#4268 HEX BF 64 10 AC Binary 1011 1111 0110 0100 0001 0000 1010 1100 After this instruction has been carried out register pair 100 contains the decimal value 4268 (10 AC Hex.). 174/298 1 ST9+ Programming Manual LINK Link code LINK INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst,1 ] [ src ] [ XTN |dst,1] [ src ] No. Bytes 3 3 No. Cycl 16/12 16/12 OPC (HEX) D4 D4 OPC XTN D LINK Address Mode dst src RR #N rr #N OPERATION: Stack in memory (16 cycles) SSP = SSP - 2 (SSP) = RR RR = SSP SSP = SSP - N Stack in the register file (12 cycles) SSP(low) = SSP(low) - 1 (SSP(low)) = RR(low) RR(low) = SSP(low) SSP(low) = SSP(low) - N SSP(high) = undefined In C functions, the compiler needs to push variables in the system stack and to keep the return address location of the function inside the stack. Therefore, a frame pointer is used, and 2 pieces of code named prologue and epilogue need to be added at the beginning and at the end of the function. The "Link" instruction is used to reduce the code overhead generated by the compiler inside the function. FLAGS: EXAMPLES: No flags affected. LINK RR4, #3. Stack in memory (16 cycles) SSP Stack in the register file (12 cycles) SSP RR4(high) RR4(low) RR4_new RR4(low) RR4_new After the instruction, RR4 points to the location where previous RR4 has been stored. 175/298 1 ST9+ Programming Manual LINKU Link code LINKU INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ XTN |dst,1] [ src ] [ dst,1 ] [ src ] No. Bytes 3 3 No. Cycl 16/12 16/12 OPC (HEX) B6 B6 LINKU OPC XTN D - Address Mode dst src rr #N RR #N OPERATION: Stack in memory(16 cycles) USP = USP - 2 (USP) = RR RR = USP USP = USP - N Stack in the register file (12 cycles) USP(low) = USP(low) - 1 (USP(low)) = RR(low) RR(low) = USP(low) USP(low) = USP(low) - N USP(high) = undefined In C functions, the compiler needs to push variables in the user stack and to keep the return address location of the function inside the stack. Therefore, a frame pointer is used, and 2 pieces of code named prologue and epilogue need to be added at the beginning and at the end of the function. The "Linku" instruction is used to reduce the code overhead generated by the compiler inside the function. FLAGS: EXAMPLES: No flags affected. LINKU RR4, #3. Stack in memory (16 cycles) USP Stack in the register file (12 cycles) USP RR4(high) RR4(low) RR4_new RR4(low) RR4_new After the instruction, RR4 points to the location where previous RR4 has been stored. 176/298 1 ST9+ Programming Manual MUL Multiply (8x8) MUL dst,src INSTRUCTION FORMAT: [ OPC ] [dst,0| src ] No. Bytes 2 No. Cycl 22 OPC (HEX) 4F OPC XTN - MUL Address Mode dst src rr r OPERATION: dst dst(low) * src The contents of the source register are multiplied by the low order byte of the destination register pair. The 16 bit result is left in the destination register pair. Input rr dst high (even address) = don't care rr dst low (odd address) = first operand rr src = second operand Output rr dst high= MSB of the result rr dst low = LSB of the result The src byte holds the unmodified second operand. FLAGS: C: Z: S: V: D: H: Contains a copy of result bit 0. Set if result MSB is zero, otherwise cleared. Contains a copy of result bit 15. Set if result LSB is zero, otherwise reset. Always reset to zero. Undefined. EXAMPLE: Instruction MUL rr6,r8 HEX 4F 68 Binary 0100 1111 0110 1000 If working register 7 contains 35 and working register 8 contains 220, after this instruction working register pair 6 will contain 7700 (decimal), i.e. working register 6 will contain 1E (Hex) and register 7 will contain 14 (Hex). 177/298 1 ST9+ Programming Manual NOP No Operation NOP INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 2 OPC (HEX) FF OPC XTN - NOP Address Mode dst src - OPERATION: No Operation is carried out. This instruction is often used in timing or delay loops. FLAGS:No flags affected. 178/298 1 ST9+ Programming Manual OR OR (byte) Register, Register OR dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 02 03 04 04 04 E6 E6 E7 OPC XTN 0 0 0 OR [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address Mode dst src r r r (r) R R r R R r (r) R (r) r R (r) OPERATION: dst dst OR src The contents of the source are ORed with the destination byte and the results stored in the destination byte. The contents of the source are not affected. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction OR r8,R64 HEX 04 40 D8 Binary 0000 0100 0100 0000 1101 1000 If working register 8 contains 11001100 and register 64 contains 10000101, after this instruction working register 8 will contain 11001101. 179/298 1 ST9+ Programming Manual OR OR (byte) Register, Memory OR dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 0 0 0 0 0 0 0 0 0 0 0 0 OR [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst OR src The source byte is ORed with the destination byte and the result stored in the destination byte. The destination register is addressed directly, the memory location (source byte) addressed either directly, indirectly or by indexing. OPERATION b: dst dst OR src rr rr + 1 The contents of the memory location addressed by the source register pair are ORed with the contents of the directly addressed destination register. The result is stored in the destination register. The contents of the source register pair are incremented after the OR has been carried out. OPERATION c: rr rr - 1 dst dst OR src The contents of the source register pair are decremented and then the contents of the memory location addressed by the source register pair are ORed with the contents of the directly addressed destination register. The result is stored in the destination register. 180/298 1 ST9+ Programming Manual OR OR (byte) Register, Memory OR dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. OR EXAMPLE: Instruction OR r8,4028 HEX C4 08 0F BC Binary 1100 0100 0000 1000 0000 1111 1011 1100 If working register 8 contains 11001100 and memory location 4028 contains 10000101, after this instruction working register 8 will contain 11001101. 181/298 1 ST9+ Programming Manual OR OR (byte) Memory, Register OR dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 12 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 0 0 0 0 0 0 0 0 0 0 0 0 Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r OR Oper a a b b c c a a a a a a [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] OPERATION a: dst dst OR src The source byte is ORed with the destination byte and the result stored in the destination byte. The source registers are addressed directly, the memory location are addressed either directly, indirectly or by indexing. OPERATION b: dst dst OR src rr rr + 1 The contents of the memory location addressed by the destination register pair (destination byte) are ORed with the contents of the directly addressed source register. The result is stored in the destination byte. The contents of the destination register pair are incremented after the OR has been carried out. OPERATION c: rr rr - 1 dst dst OR src The contents of the destination register pair are decremented and then the contents of the memory location addressed by the destination register pair (destination byte) are ORed with the contents of the directly addressed source register. The result is stored in the destination byte. 182/298 1 ST9+ Programming Manual OR OR (byte) Memory, Register OR dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. OR EXAMPLE: Instruction OR 4028,r8 HEX C5 08 0F BC Binary 1100 0101 0000 1000 0000 1111 1011 1100 If working register 8 contains 11001100 and memory location 4028 contains 10000101, after this instruction memory location 4028 will contain 11001101. 183/298 1 ST9+ Programming Manual OR OR (byte) Memory, Memory OR dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 14 14 OPC (HEX) 73 73 OPC XTN 0 0 OR Address dst (RR) (rr) Mode src (rr) (rr) OPERATION: dst dst OR src The contents of the memory location addressed by the source register pair are ORed with the content of the memory location addressed by the destination register pair. The source and destination addresses are for the word high order byte. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction OR (rr4),(rr8) HEX 73 08 D4 Binary 0111 0011 0000 1000 1101 0100 If working register pair 4 contains 2800 (decimal), memory location 2800 contains 11001100, working register pair 8 contains 4200 (decimal) and memory location 4200 contains 00001100, after this instruction memory location 2800 will contain 11001100. 184/298 1 ST9+ Programming Manual OR OR (byte) All, Immediate OR dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 10 16 OPC (HEX) 05 05 F3 2F OPC XTN 0 01 OR [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: dst dst OR src The value #N is ORed with the content of the destination register or memory location. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction OR (rr8),#32 HEX F3 18 20 Binary 1111 0011 0001 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 11101101, after this instruction memory location 4028 will contain 11101101. 185/298 1 ST9+ Programming Manual ORW OR (Word) - Register, Register ORW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 0E 07 07 07 96 96 A6 A6 OPC XTN 0 0 0 0 ORW [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address dst rr RR rr RR (r) (r) RR rr Mode src rr RR RR rr RR rr (r) (r) OPERATION: dst dst OR src The source word is ORed with the destination word and the result is stored in the destination word. The source and destination word can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction ORW (r8),RR64 HEX 96 40 08 Binary 1001 0110 0100 0000 0000 1000 If register pair 64 contains 11001100/11001100B, working register 8 contains 200 (decimal) and register pair 200 contains 10101010/10101010B, after this instruction register pair 200 will hold 11101110/11101110B. 186/298 1 ST9+ Programming Manual ORW OR (Word) - Register, Memory ORW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 0E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 0 0 0 0 0 0 0 0 0 0 0 ORW [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst OR src The source word is ORed with the destination word and the result is stored in the destination word. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst OR src rr rr + 2 The source word is ORed with the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the OR has been carried out. OPERATION c: rr rr - 2 dst dst OR src The source word is ORed with the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are decremented before the OR is carried out. 187/298 1 ST9+ Programming Manual ORW OR (Word) - Register, Memory ORW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. ORW EXAMPLE: Instruction ORW RR64,-(rr4) HEX C3 05 40 Binary 1100 0011 0000 0101 0100 0000 If working register pair 4 contains 1184 (decimal), register pair 64 contains 10101010/ 10101010B and memory pair 1182 contains 11001100/11001100B, after this instruction register pair 64 will contain 11101110/11101110B and register pair 4 will contain 1182. 188/298 1 ST9+ Programming Manual ORW OR (Word) - Memory, Register ORW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 16 18 18 18 18 18 18 18 18 18 20 20 OPC (HEX) 0E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 0 0 0 0 0 0 0 0 0 0 0 ORW [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst dst OR src The source word is ORed with the destination word and the result is stored in the destination word. The source word is held in the source register. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst OR src rr rr + 2 The source word is ORed with the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the OR has been carried out. OPERATION c: rr rr - 2 dst dst OR src The source word is ORed with the destination word and the result is stored in the destination word. The source word is in the source register , the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the OR is carried out. 189/298 1 ST9+ Programming Manual ORW OR (Word) - Memory, Register ORW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. ORW EXAMPLE: Instruction ORW (rr4)+,RR64 HEX D5 04 40 Binary 1101 0101 0000 0100 0100 0000 If register pair 64 contains 11001100/1101100B, working register pair 4 contains 1064 (decimal) and memory pair 1064 contains 10101010/10101010B, after this instruction has been carried out memory pair 1064 will contain 11101110/ 11101110B and working register pair 4 will contain 1066. 190/298 1 ST9+ Programming Manual ORW OR (Word) - Memory, Memory ORW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 20 OPC (HEX) 0E OPC XTN - ORW Address Mode dst src (rr) (rr) OPERATION: dst dst OR src The source word is ORed with the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction ORW (rr4),(rr6) HEX 0E 57 Binary 0000 1110 0101 0111 If working register pair 6 contains 1002 (decimal), memory pair 1002 contains 11001100/11001100B, working register pair 4 contains 1060 (decimal) and memory pair 1060 contains 10101010/10101010B, after this instruction memory pair 1060 will contain 11101110/11101110B. 191/298 1 ST9+ Programming Manual ORW OR (Word) - All, Immediate ORW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 18 20 22 22 OPC (HEX) 07 07 BE 06 06 36 OPC XTN 0 0 0 01 ORW [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address dst RR rr (rr) N(rr) NN(rr) NN Mode src #NN #NN #NN #NN #NN #NN OPERATION: dst dst OR src The source word is ORed with the destination word and the result is stored in the destination word. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction ORW RR64,#52428 HEX 07 41 CC CC Binary 0000 0111 0100 0001 1100 1100 1100 1100 If register pair 64 contains 10101010/10101010B, after this instruction has been carried out register pair 64 will contain 11101110/11101110B. 192/298 1 ST9+ Programming Manual PEA Push Effective Address on System Stack PEA src INSTRUCTION FORMAT: [ [ [ [ OPC ofs OPC ofs l ] ] ] ] [ [ [ XTN XTN ofs h ] ] ] [ [ src,0 src,1 ] ] No. Bytes 4 4 5 5 No. Cycl 20 20 22 22 OPC (HEX) 8F 8F 8F 8F OPC XTN 01 01 01 01 PEA Address Mode dst src N(RR) N(rr)* NN(R R) NN(rr) * OPERATION: SSP SSP - 2 (SSP) RR + "a" (Where "a" is the immediate value N or NN) The present value of the SSP is decremented by 2 and the content of the source register pair summed with the offset is pushed onto the system stack. FLAGS: No flag affected. EXAMPLE: Instruction PEA 16(RR32) HEX 8F 01 20 10 Binary 1000 1111 0000 0001 0010 0000 0001 0000 The content of register pair RR32 is 1024, to this value is added the immediate value 16 and the result is pushed into the stack location pointed by the pre-decremented system stack pointer. 193/298 1 ST9+ Programming Manual PEAU PEAU src INSTRUCTION FORMAT: [ [ [ [ OPC ofs OPC ofs l ] ] ] ] [ [ [ XTN XTN ofs h ] ] ] [ [ src,0 src,1 ] ] No. Bytes 4 4 5 5 No. Cycl 20 20 22 22 OPC (HEX) 8F 8F 8F 8F OPC XTN 03 03 03 03 PEAU Push Effective Address on User Stack Address Mode dst src N(RR) N(rr)* NN(R R) NN(rr) * OPERATION: USP USP - 2 (USP) RR + "a" (Where "a" is the immediate value N or NN) The present value of the USP is decremented by 2 and the contents of the source register pair summed with the offset is pushed into the user stack. FLAGS: No flags affected. EXAMPLE: Instruction PEAU 16(RR32) HEX 8F 03 20 10 Binary 1000 1111 0000 0011 0010 0000 0001 0000 The content of register pair RR32 is 1024, to this value is added the immediate value 16 and the result is pushed into the stack location pointed by the pre-decremented user stack pointer. 194/298 1 ST9+ Programming Manual POP Pop Byte from System Stack POP dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 8 8 8 8 OPC (HEX) 76 76 77 77 OPC XTN - POP Address Mode dst src R r (R) (r) - OPERATION: dst (SSP) SSP SSP + 1 The contents of the system stack addressed by the system stack pointer are loaded into the destination location and then the system stack pointer is incremented automatically by one. FLAGS: No flags affected EXAMPLE: Instruction POP (r2) HEX 77 D2 Binary 0111 0111 1101 0010 If the system stack pointer contains 2000 (decimal), working register 2 contains 52 (decimal) and system stack location 2000 contains 124 (decimal), after this instruction register 52 will contain 124 and the system stack pointer will contain 2001. 195/298 1 ST9+ Programming Manual POPU Pop Byte from User Stack POPU dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 8 8 8 8 OPC (HEX) 20 20 21 21 OPC XTN - POPU Address Mode dst src R r (R) (r) - OPERATION: dst (USP) USP USP + 1 The contents of the user stack addressed by the user stack pointer are loaded into the destination location and then the user stack pointer is increment automatically by one. FLAGS: No flags affected. EXAMPLE: Instruction POPU (r2) HEX 21 D2 Binary 0010 0001 1101 0010 If the user stack pointer contains 2000 (decimal), working register 2 contains 52 (decimal) and user stack location 2000 contains 124 (decimal), after this instruction register 52 will contain 124 and the user stack pointer will contain 2001. 196/298 1 ST9+ Programming Manual POPUW Pop Word from User Stack POPUW dst INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] No. Bytes 2 2 No. Cycl 10 10 OPC (HEX) B7 B7 POPUW OPC XTN - Address Mode dst src RR rr - OPERATION: dst (USP) USP USP + 2 The contents of the user stack addressed by the user stack pointer are loaded into the destination register pair and the user stack pointer is automatically increment by two. FLAGS: No flags affected. EXAMPLE: Instruction POPUW rr2 HEX B7 D2 Binary 1011 0111 1101 0010 If the user stack pointer contains 2000 (decimal), user stack location 2000 contains 11 (hex) and user stack location 2001 contains 24 (hex), after this instruction working register 2 will contain 11 (hex), working register 3 will contain 24 (hex) and the user stack pointer will contain 2002. 197/298 1 ST9+ Programming Manual POPW Pop Word from System Stack POPW dst INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] No. Bytes 2 2 No. Cycl 10 10 OPC (HEX) 75 75 POPW OPC XTN - Address Mode dst src RR rr - OPERATION: dst (SSP) SSP SSP + 2 The contents of the system stack pointer are loaded into the destination register pair and the system stack pointer is automatically incremented by two. FLAGS: No flags affected. EXAMPLE: Instruction POPW rr2 HEX 75 D2 Binary 0111 0101 1101 0010 If the system stack pointer contains 2000 (decimal), system stack location 2000 contains 11 (hex), system stack location 2001 contains 24 (hex), after this instruction working register 2 will contain 11 (hex), working register 3 will contain 24 (hex) and the system stack pointer will contain 2002. 198/298 1 ST9+ Programming Manual PUSH Push Byte on System Stack PUSH src INSTRUCTION FORMAT: [ OPC ] [ src ] No. Bytes 2 2 2 2 3 No. Cycl 8 8 8 8 12 OPC (HEX) 66 66 F7 F7 8F OPC XTN F1 PUSH [ OPC ] [ XTN ] [ src ] Address Mode dst src R r (R) (r) #N OPERATION: SSP SSP - 1 (SSP) src The system stack pointer is decremented automatically by one and then the operand loaded into the location addressed by the decremented system stack pointer. FLAGS: No flags affected. EXAMPLE: Instruction PUSH (R32) HEX F7 20 Binary 1111 0111 0010 0000 If the system stack pointer contains 2000 (decimal), register 32 contains 100 and register 100 contains 60 (decimal), after this instruction system stack pointer location 1999 will contain 60. 199/298 1 ST9+ Programming Manual PUSHU Push Byte on User Stack PUSHU src INSTRUCTION FORMAT: [ OPC ] [ src ] No. Bytes 2 2 2 2 3 No. Cycl 8 8 8 8 12 OPC (HEX) 30 30 31 31 8F PUSHU OPC XTN F3 [ OPC ] [ XTN ] [ src ] Address dst - Mode src R r (R) (r) #N OPERATION: USP USP - 1 (USP) src The user stack pointer is decremented automatically by one and then the contents of the source operand loaded into the location addressed by the decremented user stack pointer. FLAGS: No flags affected. EXAMPLE: Instruction PUSHU #20 HEX 8F F3 14 Binary 1000 1111 1111 0011 0001 0100 If the user stack pointer contains 2000 (decimal), after this instruction user stack pointer location 1999 will contain 20. 200/298 1 ST9+ Programming Manual PUSHUW Push Word on User Stack PUSHUW src INSTRUCTION FORMAT: [ [ [ OPC OPC src l ] ] ] [ [ src,0 XTN ] ] [ src h ] No. Bytes 2 2 4 No. Cycl 8/10 8/10 16 PUSHUW OPC (HEX) B6 B6 8F OPC XTN C3 Address Mode dst src RR rr #NN OPERATION: USP USP - 2 (USP) src The user stack pointer is automatically decremented by two and then the contents of the source operand is loaded into the user stack. FLAGS: No flags affected. EXAMPLE: Instruction PUSHUW RR32 HEX B6 20 Binary 1011 0110 0010 0000 If the stack pointer contains 2000 (decimal) and register pair 32 contains 6000 (hex), after this instruction the user stack pointer will contain 1998, user stack location 1999 will contain 00 (hex) and user stack location 1998 will contain 60 (hex). NOTE: See also PEAUW instruction. 201/298 1 ST9+ Programming Manual PUSHW Push Word on System Stack PUSHW src INSTRUCTION FORMAT: [ [ [ OPC OPC src l ] ] ] [ [ src,0 XTN ] ] [ src h ] No. Bytes 2 2 4 No. Cycl 8/10 8/10 16 OPC (HEX) 74 74 8F PUSHW OPC XTN C1 Address Mode dst src RR rr #NN OPERATION: SSP SSP - 2 (SSP) src The system stack pointer is automatically decremented by two and then the contents of the source register pair is loaded into the system stack. FLAGS: No flag affected. EXAMPLE: Instruction PUSHW RR32 HEX 74 20 Binary 0111 0100 0010 0000 If the system stack pointer contains 2000 (decimal) and register pair 32 contains 6000 (hex), aftert this instruction the system stack pointer will contain 1998, system stack location 1999 will contain 00 (hex) and system stack location 1998 will contain 60 (hex). NOTE: See also PEAW instruction. 202/298 1 ST9+ Programming Manual RCF Reset Carry Flag RCF INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 4 OPC (HEX) 11 OPC XTN - RCF Addr Mode dst src - OPERATION: C0 The carry flag is reset to zero, regardless of its previous content. FLAGS: C: reset to zero. No other flags affected. EXAMPLE: Instruction RCF HEX 11 Binary 0001 0001 Regardless of its prior condition, after this instruction the carry flag will be reset to zero. 203/298 1 ST9+ Programming Manual RET Return From Subroutine RET INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 8/10 OPC (HEX) 46 OPC XTN - RET Addr Mode dst src - OPERATION: PC (SSP) SSP SSP + 2 This instruction is normally used to return to the previously executed procedure at the end of procedure entered by a CALL statement. The contents of the location addressed by the system stack pointer are popped into the program counter. The next statement executed is that addressed by the new content of the PC. FLAGS: EXAMPLE : No flags affected. If the program counter contains 35B4 (hex), the system stack pointer contains 2000 (hex), external data memory location 2000 (hex) contains 18 (hex), and location 2001 (hex) contains 85 (hex), then the instruction: RET leaves the value 2002 (hex) in the system stack pointer and 1885 (hex), the addressed of the next instruction, in the program counter. Stack 2002h PCL PCH 2000h 204/298 1 ST9+ Programming Manual RETS Return From Far Subroutine RETS INSTRUCTION FORMAT: [ OPC ] No. Bytes 2 No. Cycl 12/10* OPC (HEX) F6 OPC XTN 01 RETS Addr Mode dst src - * depends if stack is in memory/register file PC (SSP) SSP SSP+2 CSR (SSP) SSP SSP+1 This instruction is normally used to return to the previously executed procedure at the end of procedure entered by a CALLS statement. The contents of the location addressed by the system stack pointer are popped into the CSR and PC registers. The next statement executed is that addressed by the new content of the PC. FLAGS: EXAMPLE : No flags affected. If the program counter contains 35B4 (hex), the system stack pointer contains 2000 (hex), external data memory 2000 (hex) contains 18 (hex), and data memory pair 2001 (hex) contains 85A1 (hex), after the instruction CSR contains 18 (hex), PC points to instruction address 85A1 (hex) and the system stack pointer contains 2003 (hex). OPERATION: Stack PCL PCH CSR 3003h 205/298 1 ST9+ Programming Manual RLC Rotate Left Through Carry RLC dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 6 6 OPC (HEX) B0 B0 B1 B1 OPC XTN - RLC Addr Mode dst src R r (R) (r) - OPERATION: dst(0) C C dst(7) dst(n+1) dst(n) Where n=0-6 The contents of the destination register are shifted one place to the left with bit 7 shifted into the carry flag and the carry flag shifted into bit 0. The destination register can be directly or indirectly addressed. b7 C b0 FLAGS: C: Set if carry from MSB (bit 7 was 1). Z: Set if the result is zero, otherwise cleared. S: Set if the result bit 7 is set, otherwise cleared. V: Set if result bit 7 is changed, otherwise cleared. D: Unaffected. H: Unaffected. EXAMPLE: Instruction RLC (r2) HEX B1 D2 Binary 1011 0001 1101 0010 If the carry flag is zero, working register 2 contains 155 (decimal) and register 155 contains 11001100B, after this instruction register 155 will contain 10011000B and the carry flag will be set to 1. 206/298 1 ST9+ Programming Manual RLCW Rotate Left Through Carry Word RLCW dst INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] No. Bytes 2 2 No. Cycl 8 8 OPC (HEX) 8F 8F RLCW OPC XTN - Addr Mode dst src RR rr - OPERATION: dst(0) C C dst(15) dst(n+1) dst(n) where n=0-14 The contents of the destination register pair are shifted one place to the left with bit 15 shifted into the carry flag and the carry flag shifted into bit 0. b15 C b0 FLAGS: C: Set if carry from MSB bit 15 was 1. Z: Undefined. S: Set if the result bit 15 is set, otherwise cleared. V: Set if result bit 15 is changed, otherwise cleared. D: Unaffected. H: Unaffected. EXAMPLE: Instruction RLCW rr2 HEX 8F D2 Binary 1000 1111 1101 0010 If the carry flag is zero, and working register pair 2 contains 11001100/11001100B, after this instruction it will 10011001/10011000B and the carry flag will be set to 1. 207/298 1 ST9+ Programming Manual ROL Rotate Left Byte ROL dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 6 6 OPC (HEX) A0 A0 A1 A1 OPC XTN - ROL Addr Mode dst src R r (R) (r) - OPERATION: C dst(7) dst(0) dst(7) dst(n+1) dst(n) Where n=0-6 The contents of the destination register are shifted one place to the left with bit 7 shifted into bit 1 and into the carry flag. The destination register can be directly or indirectly addressed. b7 C b0 FLAGS: C: Set if carry from MSB (bit 7 was 1). Z: Set if the result is zero, otherwise cleared. S: Set if the result bit 7 is set, otherwise cleared. V: Set if result bit 7 is changed, otherwise cleared. D: Unaffected. H: Unaffected. EXAMPLE: Instruction ROL (r2) HEX A1 D2 Binary 1010 0001 1101 0010 If working register 2 contains 146 (decimal) and register 146 contains 11001100B, after this instruction register 146 will contain 10011001B and the carry flag will be set to 1. 208/298 1 ST9+ Programming Manual ROR Rotate Right Byte ROR dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 6 6 OPC (HEX) C0 C0 C1 C1 OPC XTN - ROR Addr Mode dst src R r (R) (r) - OPERATION: C dst(0) dst(7) dst(0) dst(n) dst(n+1) Where n=0-6 The contents of the destination register are shifted one place to the right with bit 0 shifted into bit 7 and into the carry flag. The destination register can be directly or indirectly addressed. b7 b0 C FLAGS: C: Set if carry from LSB (bit 0 was 1). Z: Set if the result is zero, otherwise cleared. S: Set if the result bit 7 is set, otherwise cleared. V: Set if result bit 7 is changed, otherwise cleared. D: Unaffected. H: Unaffected. EXAMPLE: Instruction ROR R32 HEX C0 20 Binary 1100 0000 0010 0000 If the carry flag is set to one and register 32 contains 11001100B, after this instruction register 32 will contain 01100110B and the carry flag will be reset to zero. 209/298 1 ST9+ Programming Manual RRC Rotate Right Through Carry Byte RRC dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 6 6 OPC (HEX) D0 D0 D1 D1 OPC XTN - RRC Addr Mode dst src R r (R) (r) - OPERATION: dst(7) C C dst(0) dst(n) dst(n+1) Where n=0-6 The contents of the destination register are shifted one place to the right with bit 0 shifted into the carry flag and the carry flag shifted into bit 7. The destination register can be directly or indirectly addressed. b7 b0 C FLAGS: C: Set if carry from LSB (bit 0 was 1). Z: Set if the result is zero, otherwise cleared. S: Set if the result bit 7 is set, otherwise cleared. V: Set if result bit 7 is changed, otherwise cleared. D: Unaffected. H: Unaffected. EXAMPLE: Instruction RRC (R32) HEX D1 20 Binary 1101 0001 0010 0000 If the carry flag is zero, register 32 contains 155 and register 155 contains 00110011B, after this instruction register 155 will contain 00011001B and the carry flag will be set to 1. 210/298 1 ST9+ Programming Manual RRCW Rotate Right Through Carry Word RRCW dst INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] No. Bytes 2 2 No. Cycl 8 8 OPC (HEX) 36 36 RRCW OPC XTN - Addr Mode dst src RR rr - OPERATION: dst(15) C C dst(0) dst(n) dst(n+1) where n=0-14 The contents of the destination register pair are shifted one place to the right with bit 0 shifted into the carry flag and the carry flag shifted into bit 15. FLAGS: C: Set if carry from LSB (bit 0 was 1). b15 b0 C Z: Undefined. S: Set if the result bit 15 is set, otherwise cleared. V: Set if result bit 15 is changed, cleared otherwise. D: Unaffected. H: Unaffected. EXAMPLE: Instruction RRCW R32 HEX 36 20 Binary 0011 0110 0010 0000 If the carry flag is set and register 32 pair contains 11001100/11001100B, after this instruction register 32 will contain 11100110/01100110B and the zero flag will be reset to 0. 211/298 1 ST9+ Programming Manual SBC SBC dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 22 23 24 24 24 E6 E6 E7 OPC XTN 2 2 SBC Subtract with carry (byte) Register, Register [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address dst r r R r R (r) (r) R Mode src r (r) R R r R r (r) OPERATION: dst dst - src - C The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The source and destination byte can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SBC r8,(r4) HEX 23 84 Binary 0010 0011 1000 0100 If the carry flag is reset, working register 8 contains 100 (decimal), working register 4 contains 200 (decimal) and register 200 contains 25 (decimal), after this instruction working register 8 will contain 75. 212/298 1 ST9+ Programming Manual SBC SBC dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 2 2 2 2 2 2 2 2 2 2 2 2 SBC Subtract with carry (byte) Register, Memory [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst - src - C The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The destination byte is held in the destination register. The source byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src - C rr rr + 1 The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are incremented after the SBC has been carried out. OPERATION c: rr rr - 1 dst dst - src - C The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are decremented before the SBC is carried out. 213/298 1 ST9+ Programming Manual SBC SBC dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SBC Subtract with carry (byte) Register, Memory Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SBC r8,6(rr4) HEX 7F 25 06 D4 Binary 0111 1111 0010 0101 0000 0110 1101 1000 If the carry flag is set, working register 8 contains 110 (decimal), working register pair 4 contain 4200 (decimal) and memory address 4204 (decimal) contains 10 (decimal), after this instruction working register 8 contains 99 (decimal). 214/298 1 ST9+ Programming Manual SBC SBC dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 12 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 2 2 2 2 2 2 2 2 2 2 2 2 SBC Subtract with carry (byte) Memory, Register [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r Oper a a b b c c a a a a a a OPERATION a: dst dst - src - C The source byte, along with the carry, is subtracted from destination byte and the result is stored in the destination byte. The source byte is held in the source register. The destination byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src - C rr rr + 1 The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the source register, the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the SBC has been carried out. OPERATION c: rr rr - 1 dst dst - src - C The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the source register , the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the SBC is carried out. 215/298 1 ST9+ Programming Manual SBC SBC dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SBC Subtract with carry (byte) Memory, Register Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SBC (rr8)+,R255 HEX B4 28 FF Binary 1011 0100 0010 1000 1111 1111 If the carry flag is set, working register pair 8 contains 4028 (decimal) memory location 4028 contains 110 (decimal) and register 255 contains 101 (decimal), after this instruction memory location 4028 will contain 8 and working register pair 8 will contain 4029. 216/298 1 ST9+ Programming Manual SBC SBC dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 14 14 OPC (HEX) 73 73 OPC XTN 2 2 SBC Subtract with carry (byte) Memory, Memory Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION: dst dst - src - C The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SBC (rr4),(rr8) HEX 73 28 D4 Binary 0111 0011 0010 1000 1101 0100 If the carry flag is set, working register pair 4 contains 2800 (decimal), memory location 2800 contains 46 (decimal), working register pair 8 contains 4200 (deciamal) and memory location 4200 contains 45 (decimal), after this instruction memory location 2800 will contain 0. 217/298 1 ST9+ Programming Manual SBC Subtract with carry (byte) All, Immediate SBC dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 10 16 OPC (HEX) 25 25 F3 2F OPC XTN 2 21 SBC [ XTN |dst,0] [ XTN ] [ dst l ] Address dst R r (rr) NN Mode src #N #N #N #N OPERATION: dst dst - src - C The source byte, along with the carry, is subtracted from the destination byte and the result is stored in the destination byte. The source byte is the immediate value in the operand, the destination byte can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SBC (rr8),#32 HEX F3 28 20 Binary 1111 0011 0010 1000 0010 0000 If the carry flag is set, working register pair 8 contains 4028 (decimal) and memory location 4028 contains 74 (decimal), after this instruction memory location 4028 will contain 41. 218/298 1 ST9+ Programming Manual SBCW SBCW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 2E 27 27 27 96 96 A6 A6 SBCW Subtract With Carry (Word) - Register, Register OPC XTN 2 2 2 2 [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address Mode dst src rr rr RR RR rr RR RR rr (r) RR (r) rr RR (r) rr (r) OPERATION: dst dst - src - C The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source and destination word can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SBCW (r8),RR64 HEX 96 40 28 Binary 1001 0110 0100 0000 0010 1000 If the carry flag is set, register pair 64 contains 1102 (decimal), working register 8 contains 200 (decimal) and register pair 200 contains 2550 (decimal), after this instruction register pair 200 will hold 1447. 219/298 1 ST9+ Programming Manual SBCW SBCW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 2E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 2 2 2 2 2 2 2 2 2 2 2 SBCW Subtract With Carry (Word) - Register, Memory [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst - src - C The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src - C rr rr + 2 The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the subtraction has been carried out. OPERATION c: rr rr - 2 dst dst - src - C The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are decremented before the subtraction is carried out. 220/298 1 ST9+ Programming Manual SBCW SBCW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SBCW Subtract With Carry (Word) - Register, Memory Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SBCW RR64,-(rr4) HEX C3 25 40 Binary 1100 0011 0010 0101 0100 0000 If the carry flag is set, working register pair 8 contains 1184 (decimal), register pair 64 contains 5000 (decimal) and memory pair 1182 contains 1100 (decimal), after this instruction register pair 64 will contain 3899 and register pair 4 will contain 1182. 221/298 1 ST9+ Programming Manual SBCW SBCW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 16 18 18 18 18 18 18 18 18 18 20 20 OPC (HEX) 2E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 2 2 2 2 2 2 2 2 2 2 2 SBCW Subtract With Carry (Word) - Memory, Register [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst dst - src - C The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is held in the source register. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src - C rr rr + 2 The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the subtraction has been carried out. OPERATION c: rr rr - 2 dst dst - src - C The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the source register , the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the subtraction is carried out. 222/298 1 ST9+ Programming Manual SBCW SBCW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SBCW Subtract With Carry (Word) - Memory, Register Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SBCW (rr4)+,RR64 HEX D5 24 40 Binary 1101 0101 0010 0100 0100 0000 If the carry flag is set, register pair 64 contains 1250 (decimal), working register pair 4 contains 1064 (decimal) and memory pair 1064 contains 1750, after this instruction has been carried out memory pair 1064 will contain 499 and working register pair 4 will contain 1066. 223/298 1 ST9+ Programming Manual SBCW SBCW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 20 OPC (HEX) 2E SBCW Subtract With Carry (Word) - Memory, Memory OPC XTN - Address Mode dst src (rr) (rr) OPERATION: dst dst - src - C The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SBCW (rr4),(rr6) HEX 2E 57 Binary 0010 1110 0101 0111 If the carry flag is zero, working register pair 6 contains 1002 (decimal), memory pair 1002 contains 2300 (decimal), working register pair 4 contains 1060 (decimal) and memory pair 1060 contains 2700 (decimal), after this instruction memory pair 1060 will contain 400. 224/298 1 ST9+ Programming Manual SBCW SBCW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 18 20 22 22 OPC (HEX) 27 27 BE 06 06 36 SBCW Subtract With Carry (Word) - All, Immediate OPC XTN 2 2 2 21 [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address Mode dst src RR #NN rr #NN (rr) #NN N(rr) NN(rr) NN #NN #NN #NN OPERATION: dst dst - src - C The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SBCW RR64,#4268 HEX 27 41 10 AC Binary 0010 0111 0100 0001 0001 0000 1010 1100 If the carry flag is zero, register pair 64 contains 5000 (decimal), after this instruction has been carried out register pair 64 will contain the decimal value 732. 225/298 1 ST9+ Programming Manual SCF Set Carry Flag SCF INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 4 OPC (HEX) 01 OPC XTN - SCF Address Mode dst src - OPERATION: C1 The carry flag is set to 1. FLAGS: C: Set to one. No other flags affected. EXAMPLE: Instruction SCF HEX 01 Binary 0000 0001 Regardless of its prior condition, after this instruction the carry flag will be set to one. 226/298 1 ST9+ Programming Manual SDM Set Data Memory SDM INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 4 OPC (HEX) FE OPC XTN - SDM Address Mode dst src - OPERATION: Set Data Memory. After executing this instruction, accesses to operands are performed as if these operands were located in data memory. This means that: - wait states defined for data memory are used; - When using extended addressing mechanism through MMU, DPRx registers are used to extend addresses contained in the instruction or registers defined in the instruction. See MMU usage for further details. This instruction sets to one bit 0 of the flag register R231. FLAGS: No flags affected. 227/298 1 ST9+ Programming Manual SLA Shift Left Arithmetic (Byte) SLA dst INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] ] ] [ dst | dst ] [ dst ][ [ XTN |dst,0] [ No. Bytes dst dst,0 ] ] 2 3 3 No. Cycl 4 6 14 OPC (HEX) 42 44 73 OPC XTN 4 SLA Address Mode dst src r R (rr) - OPERATION: dst C dst(7) dst(0) 0 dst(n+1) dst(n) where n=0-6 The content of the destination is shifted one place to the left with the most significant bit shifted into the carry flag and a zero shifted into bit 0. The destination register can be a register or a memory indirectly addressed. FLAGS: C: Z: S: V: D: H: Set if MSB set, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to zero. Set if carry from low-order nibble occurred. EXAMPLE: Instruction SLA r6 HEX 44 66 Binary 0100 0100 0110 0110 If working register 6 contains A4 hex , after this instruction the carry bit will be set and working register 8 will contain 48 hex. NOTE: This instruction is logically and functionally equivalent to the ADD dst, dst operation and is recognized and translated into the corresponding ADD instruction by the ST9 assembler. 228/298 1 ST9+ Programming Manual SLAW Shift Left Arithmetic Word SLAW dst INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] ] ] [ dst | dst ] [ dst,0 ] [ dst,1 ] No. Bytes [ [ dst,0 dst,1 ] ] 2 3 2 No. Cycl 8 8 20 OPC (HEX) 4E 47 4E SLAW OPC XTN - Address Mode dst src rr RR (rr) - OPERATION: dst C dst(15) dst(0) 0 dst(n+1) dst(n) where n=0-14 The content of the destination is shifted one place to the left with the most significant bit shifted into the carry flag and a zero shifted into bit 0. The destination register can be a register or a memory indirectly addressed. FLAGS: C: Z: S: V: D: H: Set if MSB set, otherwise cleared. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined Undefined EXAMPLE: Instruction SLAW RR4 HEX 47 04 04 Binary 0100 0111 0000 0100 0000 0100 If working register pair 4 contains A438 hex , after this instruction the carry bit will be set and working register pair 4 will contain 4870 hex. NOTE: This intruction is logically and functionally equivalent to the ADD dst, dst operation and is recognized and translated into the corresponding ADDW instruction by the ST9 assembler. 229/298 1 ST9+ Programming Manual SPM Set Program Memory SPM INSTRUCTION FORMAT: [ OPC ] No. Bytes 1 No. Cycl 4 OPC (HEX) EE OPC XTN - SPM Address Mode dst src - OPERATION: Set Program Memory. After executing this instruction, accesses to operands are performed as if these operands were located in program memory. This means that: - wait states defined for program memory are used; - When using extended addressing mechanism through MMU, CSR register is used to extend addresses contained in the instruction or registers defined in the instruction. The only exceptions are instructions which use explicitly an operand in the stack (PUSH, PUSHW, POP, POPW, PUSHU, PUSHW, POPU, POPUW, PEA, PEAU, CALL, CALLS, RET, RETS and Interrupts). See MMU usage for further details. This instruction resets to zero bit 0 of the flag register R231. FLAGS: No flags affected. 230/298 1 ST9+ Programming Manual SPP Set Page Pointer SPP src INSTRUCTION FORMAT: [ OPC ][ src ,1,0] No. Bytes 2 No. Cycl 4 OPC (HEX) C7 OPC XTN - SPP Address Mode dst src #N OPERATION: Set to N the Page Pointer Register (R234), where 0 N 63 This instruction selects one of the 64 pages available to be used for the storage of control information relevant to particular peripherals. Each page is composed of 16 registers based on the top group (F) of the register file. After selecting a page any address on the top group (R240-R255) will be referred to the selected page. FLAGS: No flags affected. EXAMPLE: Instruction SPP #5 HEX C7 16 Binary 1100 0111 0001 0110 This instruction will select page 5 of paged registers. Then operations addressing group F of the register file are related to page 5. The page pointer register (R234) contains 0x14. 231/298 1 ST9+ Programming Manual SRA Shift Right Arithmetic Byte SRA dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 4 4 6 6 OPC (HEX) E0 E0 E1 E1 OPC XTN - SRA Address Mode dst src R r (R) (r) - OPERATION: dst(7) dst(7) C dst(0) dst(n) dst(n+1) Where n=0-6 The contents of the destination register are shifted one place to the right with the bit 0 shifted into the carry flag. Bit 7 (the sign bit) is unchanged but its value is also carried into bit position 6. The destination register can be directly or indirectly addressed. FLAGS: C: Z: S: V: D: H: Set if carry from LSB (bit 0 was 1). Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction SRA (r2) HEX E1 D2 Binary 1110 0001 1101 0010 If the carry flag is one, working register 2 contains 137 (decimal) and register 137 contains 11001100, after this instruction register 137 will contain 11100110 and the carry flag will be zero. 232/298 1 ST9+ Programming Manual SRAW Shift Right Arithmetic Word SRAW dst INSTRUCTION FORMAT: [ OPC ] [ dst,0 ] No. Bytes 2 2 No. Cycl 8 8 OPC (HEX) 2F 2F SRAW OPC XTN - Address Mode dst src RR rr - OPERATION: dst(15) dst(15) C dst(0) dst(n) dst(n+1) where n=0-14 The contents of the destination register pair are shifted one place to the right with bit 0 shifted into the carry flag. Bit 15 (the sign bit) is unchanged but its value is also carried into bit position 14. FLAGS: C: Z: S: V: D: H: Set if carry from LSB (bit 0 was 1). Set if the result is zero, otherwise cleared. Set if the result is negative, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction SRAW rr2 HEX 2F D2 Binary 0010 1111 1101 0010 If the carry flag is one, working register pair 2 contains 11001100/11001100B, after this instruction working register pair 2 will contain 11100110/01100110B and the carry flag will be zero. 233/298 1 ST9+ Programming Manual SRP Set Register Pointer SRP src INSTRUCTION FORMAT: [ OPC ] [ src,0,0,0] No. Bytes 2 No. Cycl 4 OPC (HEX) C7 OPC XTN - SRP Address Mode dst src #N OPERATION: Set Register Pointer This instruction selects one pair of the thirty-two groups of 8 registers available in the register file. The pair will always start from the lowest even number equal or lower to the number given in the instruction. When this instruction is followed by a SRP1 instruction, that is when the mode is changed to the twin working register groups, an 8 register group is selected, equivalent to the SRP0 instruction. After having selected the window pair every absolutely addressed register that refers to group D (R208-R223) will be referenced to the working window pair. FLAGS: No flags affected. EXAMPLE: Instruction SRP #3 HEX C7 18 Binary 1100 0111 0001 1000 SRP #3 LD r3, #10 LD R21, #20 The first instruction will select the second pair of register (R16-R31) as working register window. The second instruction therefore will load the value 10 (decimal) in working register 3 which is R19. The register R21 in the third instruction is equivalent to r5. After this instruction register R21 will contain 20 (decimal). 234/298 1 ST9+ Programming Manual SRP0 Set Register Pointer 0 SRP0 src INSTRUCTION FORMAT: [ OPC ] [ src 1,0,0] No. Bytes 2 No. Cycl 4 OPC (HEX) C7 OPC XTN - SRP0 Address Mode dst src #N OPERATION: Set Register Pointer 0 This instruction activates the twin register mode and therefore register pointer 0 will refer to one of the thirty-two available groups in the register file. In particular, after having selected the appropriate window every register between R208 and R215 will be equivalent to working registers r0-r7 and therefore will refer to the window pointed to by RP0. FLAGS: No flags affected. EXAMPLE: Instruction SRP0 #3 HEX C7 1C Binary 1100 0111 0001 1100 SRP0#3 LD r3, #10 LD r5, #20 This instruction will select the window R24-R31. The second instruction will therefore load in the third register of the selected window the immediate data, that is register R27 will contain 10 (decimal). The third instruction will load in the sixth working register, that is R29, the value 20 (decimal). 235/298 1 ST9+ Programming Manual SRP1 Set Register Pointer 1 SRP1 src INSTRUCTION FORMAT: [ OPC ] [ src 1,0,1] No. Bytes 2 No. Cycl 4 OPC (HEX) C7 OPC XTN - SRP1 Address Mode dst src #N OPERATION: Set Register Pointer 1 This instruction activates the twin register mode and therefore register pointer 1 will refer to one of the thirty-two available groups of 8 registers in the register file. In particular after having selected the appropiate window every register between R216 and R223 will be equivalent to working registers r8-r15 and therefore will refer to the window pointed to by RP1. FLAGS: No flags affected. EXAMPLE: Instruction SRP1 #2 HEX C715 Binary 1100 0111 0001 0101 SRP#3 SRP1#2 LD r3, #10 LD r10, #20 The first instruction will select the window pair R16-R31. With the second instruction the mode will be changed to the twin register groups and register RP0 will point to R24-R31 while register RP1 will point to R16-R23. The first load instruction will therefore refer to register pointer zero since the value of the short register is between 0-7 and will place the value 10 (decimal) into R19. The second load refers to register pointer one since the value of the short register is between 8-15 and will place 20 (decimal) into R26. 236/298 1 ST9+ Programming Manual SUB Subtract (byte) Register, Register SUB dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 52 53 54 54 54 E6 E6 E7 OPC XTN 5 5 5 SUB [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address Mode dst src r r r (r) R R r R R r (r) R (r) r R (r) OPERATION: dst dst - src The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source and destination byte can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SUB (r8),R255 HEX E6 FF 58 Binary 1110 0110 1111 1111 0101 1000 If working register 8 contains 28 (decimal), register 28 contains 43 (decimal) and register 255 contains 21 (decimal), after this instruction register 28 will contain 22. 237/298 1 ST9+ Programming Manual SUB Subtract (byte) Register, Memory SUB dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 14 14 14 14 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 5 5 5 5 5 5 5 5 5 5 5 5 SUB [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst - src The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src rr rr + 1 The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are incremented after the SUB has been carried out. OPERATION c: rr rr - 1 dst dst - src The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the destination register. The contents of the source register pair are decremented before the SUB is carried out. 238/298 1 ST9+ Programming Manual SUB Subtract (byte) Register, Memory SUB dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SUB Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SUB r8,(rr4) HEX 72 55 D8 Binary 0111 0010 0101 0101 1101 1000 If working register 8 contains 213 (decimal), working register pair 4 contain 4200 (decimal) and memory location 4200 contains 25 (decimal), after this instruction register 8 will contain 188. 239/298 1 ST9+ Programming Manual SUB Subtract (byte) Memory, Register SUB dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 12 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 5 5 5 5 5 5 5 5 5 5 5 5 SUB [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r Oper a a b b c c a a a a a a OPERATION a: dst dst - src The source byte is subtracted from destination byte and the result is stored in the destination byte. The source byte is held in the source register. The destination byte can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src rr rr + 1 The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the source register, the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the SUB has been carried out. OPERATION c: rr rr - 1 dst dst - src The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the source register , the destination byte is in the memory location addressed by the destination register pair. The contents of the destination register pair are decremented before the SUB is carried out. 240/298 1 ST9+ Programming Manual SUB Subtract (byte) Memory, Register SUB dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SUB Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SUB (rr8),R255 HEX 72 58 FF Binary 0111 0010 0101 1000 1111 1111 If working register pair 8 contains 4028 (decimal) memory location 4028 contains 144 (decimal) and register 255 contains 22 (decimal), after this instruction memory location 4028 will contain 122. 241/298 1 ST9+ Programming Manual SUB Subtract (byte) Memory, Memory SUB dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 14 14 OPC (HEX) 73 73 OPC XTN 5 5 SUB Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION: dst dst - src The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source byte is in the memory location addressed by the source register pair, the destination byte is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SUB (rr4),(rr8) HEX 73 58 D4 Binary 0111 0011 0101 1000 1101 0100 If working register pair 4 contains 2800 (decimal), memory location 2800 contains 46 (decimal), working register pair 8 contains 4200 (deciamal) and memory location 4200 contains 45 (decimal), after this instruction memory location 2800 will contain 1. 242/298 1 ST9+ Programming Manual SUB Subtract (byte) All, Immediate SUB dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 10 16 OPC (HEX) 55 55 F3 2F OPC XTN 5 51 SUB [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: dst dst - src The source byte is subtracted from the destination byte and the result is stored in the destination byte. The source byte is the immediate value in the operand, the destination byte can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, set otherwise indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Always reset to one. Cleared if carry from low-order nibble occurred. EXAMPLE: Instruction SUB (rr8),#32 HEX F3 58 20 Binary 1111 0011 0101 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 74 (decimal), after this instruction memory location 4028 will contain 42. 243/298 1 ST9+ Programming Manual SUBW Subtract (Word) - Register, Register SUBW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 5E 57 57 57 96 96 A6 A6 SUBW OPC XTN 5 5 5 5 [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address dst rr RR rr RR (r) (r) RR rr Mode src rr RR RR rr RR rr (r) (r) OPERATION: dst dst - src The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source and destination words can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SUBW (r8),RR64 HEX 96 40 58 Binary 1001 0110 0100 0000 0101 1000 If register pair 64 contains 1102 (decimal), working register 8 contains 200 (decimal) and register pair 200 contains 2550 (decimal), after this instruction register pair 200 will hold 1448. 244/298 1 ST9+ Programming Manual SUBW Subtract (Word) - Register, Memory SUBW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 5E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 5 5 5 5 5 5 5 5 5 5 5 SUBW [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst - src The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src rr rr + 2 The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the subtraction has been carried out. OPERATION c: rr rr - 2 dst dst - src The contents of the source register pair are decremented before the subtraction is carried out. The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. 245/298 1 ST9+ Programming Manual SUBW Subtract (Word) - Register, Memory SUBW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SUBW Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SUBW RR64,-(rr4) HEX C3 55 40 Binary 1100 0011 0101 0101 0100 0000 If working register pair 8 contains 1184 (decimal), register pair 64 contains 5000 (decimal) and memory location 1182 contains 1100 (decimal), after this instruction register pair 64 will contain 3900 and register pair 4 will contain 1182. 246/298 1 ST9+ Programming Manual SUBW Subtract (Word) - Memory, Register SUBW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 16 18 18 18 18 18 18 18 18 18 20 20 OPC (HEX) 5E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 5 5 5 5 5 5 5 5 5 5 5 SUBW [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst dst - src The source word is subtracted from the destination word and the result is stored in the destination word. The source word is held in the source register. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst - src rr rr + 2 The source word is subtracted from the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the subtraction has been carried out. OPERATION c: rr rr - 2 dst dst - src The contents of the source register pair are decremented before the subtraction is carried out. The source word, along with the carry flag, is subtracted from the destination word and the result is stored in the destination word. The source word is in the source register , the destination word is in the memory location addressed by the destination register pair. 247/298 1 ST9+ Programming Manual SUBW Subtract (Word) - Memory, Register SUBW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: SUBW Cleared if carry from MSB of result, otherwise set indicating a borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SUBW (rr4)+,RR64 HEX D5 54 40 Binary 1101 0101 0101 0100 0100 0000 If register location 64 contains 1250 (decimal), working register pair 4 contains 1064 (decimal) and memory pair 1064 contains 11750, after this instruction has been carried out memory pair 1064 will contain 500 and workig register pair 4 will contain 1066. 248/298 1 ST9+ Programming Manual SUBW Subtract (Word) - Memory, Memory SUBW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 20 OPC (HEX) 5E SUBW OPC XTN - Address Mode dst src (rr) (rr) OPERATION: dst dst - src The source word is subtracted from the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SUBW (rr4),(rr6) HEX 5E 57 Binary 0101 1110 0101 0111 If working register pair 6 contains 1002 (decimal), memory pair 1002 contains 2300 (decimal), working register pair 4 contains 1060 (decimal) and memory pair 1060 contains 2700 (decimal), after this instruction memory pair 1060 will contain 400. 249/298 1 ST9+ Programming Manual SUBW Subtract (Word) - All, Immediate SUBW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 18 20 22 22 OPC (HEX) 57 57 BE 06 06 36 SUBW OPC XTN 5 5 5 51 [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address dst RR rr (rr) N(rr) NN(rr) NN Mode src #NN #NN #NN #NN #NN #NN OPERATION: dst dst - src The source word is subtracted from the destination word and the result is stored in the destination word. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Cleared if carry from MSB of result, otherwise set indicating borrow. Set if the result is zero, otherwise cleared. Set if the result is less than zero, otherwise cleared. Set if arithmetic overflow occurred, cleared otherwise. Undefined. Undefined. EXAMPLE: Instruction SUBW RR64,#4268 HEX 57 41 10 AC Binary 0101 0111 0100 0001 0001 0000 1010 1100 If register pair 64 contains 5000 (decimal), after this instruction has been carried out register pair 64 will contain the decimal value 732. 250/298 1 ST9+ Programming Manual SWAP Swap Nibbles SWAP dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 2 2 2 No. Cycl 8 8 8 8 OPC (HEX) F0 F0 F1 F1 SWAP OPC XTN - Address Mode dst src R r (R) (r) - OPERATION: dst(0-3) - dst(4-7) The upper and lower nibbles of the destination register are swapped. The destination register can be directly or indirectly addressed. FLAGS: C: Z: S: V: D: H: Undefined. Set if the result is zero, otherwise cleared. Set if the result bit 7 is set, otherwise cleared. Undefined. Unaffected. Unaffected. EXAMPLE: Instruction SWAP R32 HEX F0 20 Binary 1111 0000 0010 0000 If register 32 contains 1110 0111B, after this instruction the contents become 01111110B. 251/298 1 ST9+ Programming Manual TCM TCM dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 82 83 84 84 84 E6 E6 E7 OPC XTN 8 8 8 TCM Test complement under mask (byte) Register, Register [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address dst r r R r R (r) (r) R Mode src r (r) R R r R r (r) OPERATION: NOT dst AND src Selected bits in the destination byte are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask). TCM instruction complements the destination byte, which is then ANDed with the source byte. The zero flag can then be checked to determine the result. The destination byte remains unaltered by this instruction. The source byte is held in the source register and the destination byte in the destination register. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCM r8,R64 HEX 84 40 D8 Binary 1000 0100 0100 0000 1101 1000 If working register 8 contains 11001100 and register 64 contains 1000 0100, after this instruction the zero flag will be reset to zero. 252/298 1 ST9+ Programming Manual TCM TCM dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 8 8 8 8 8 8 8 8 8 8 8 8 TCM Test complement under mask (byte) Register, Memory [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: NOT dst AND src Selected bits in the destination byte are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask). TCM instruction complements the destination byte, which is then ANDed with the source byte. The zero flag can then be checked to determine the result. The destination byte remains unaltered by this instruction. The source byte is held in the source memory location and the destination byte in the destination register. The destination register is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: NOT dst AND src rr rr + 1 As operation 'a' (indirect memory addressing only), but the contents of the destination register pair are incremented after the TCM has been carried out. OPERATION c: rr rr - 1 NOT dst AND src As operation 'a' (indirect memory addressing only), but the contents of the destination register pair are decremented before the TCM is carried out. 253/298 1 ST9+ Programming Manual TCM TCM dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. TCM Test complement under mask (byte) Register, Memory EXAMPLE: Instruction TCM r8,4028 HEX C4 88 0F BC Binary 1100 0100 1000 1000 0000 1111 1011 1100 If working register 8 contains 11001100 and memory location 4028 contains 10000101, after this instruction the zero flag will be reset to zero. 254/298 1 ST9+ Programming Manual TCM TCM dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 10 10 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 8 8 8 8 8 8 8 8 8 8 8 8 TCM Test complement under mask (byte) Memory, Register [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r Oper a a b b c c a a a a a a OPERATION a: NOT dst AND src Selected bits in the destination byte are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask). TCM instruction complements the destination byte, which is then ANDed with the source byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is held in the source memory location and the destination byte in the destination register. The source register is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: NOT dst AND src rr rr + 1 As operation 'a' (indirect memory addressing only), but the contents of the source register pair are incremented after the TCM has been carried out. OPERATION c: rr rr - 1 NOT dst AND src As operation 'a' (indirect memory addressing only), but the contents of the source register pair are decremented before the TCM is carried out. 255/298 1 ST9+ Programming Manual TCM TCM dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. TCM Test complement under mask (byte) Memory, Register EXAMPLE: Instruction TCM 4028,r8 HEX C5 88 0F BC Binary 1100 0101 1000 1000 0000 1111 1011 1100 If memory location 4028 contains 11001100 and working register 8 contains 10000101, after this instruction the zero flag will be reset to zero. 256/298 1 ST9+ Programming Manual TCM TCM dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 12 12 OPC (HEX) 73 73 OPC XTN 8 8 TCM Test complement under mask (byte) Memory, Memory Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION: NOT dst AND src Selected bits in the destination byte are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask). TCM instruction complements the destination byte, which is then ANDed with the source byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is in the memory location addressed by the source register pair, the destination byte is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCM (rr4),(rr8) HEX 73 88 D4 Binary 0111 0011 1000 1000 1101 0100 If working register pair 4 contains 2800 (decimal), memory location 2800 contains 11001100, working register pair 8 contain 4200 (decimal) and memory location 4200 contains 11001100, after this instruction the zero flag will be set to one. 257/298 1 ST9+ Programming Manual TCM TCM dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 8 14 OPC (HEX) 85 85 F3 2F OPC XTN 8 81 TCM Test complement under mask (byte) All, Immediate [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: NOT dst AND src Selected bits in the destination byte are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask). TCM instruction complements the destination byte, which is then ANDed with the source byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is the immediate value in the operand, the destination byte can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCM (rr8),#32 HEX F3 88 20 Binary 1111 0011 1000 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 11101100, after this instruction the zero flag will be set to one. 258/298 1 ST9+ Programming Manual TCMW TCMW Test Complement Under Mask (Word) - Register, Register TCMW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 8E 87 87 87 96 96 A6 A6 OPC XTN 8 8 8 8 Address Mode dst src rr rr RR RR rr RR RR rr (r) RR (r) rr RR (r) rr (r) [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] OPERATION: NOT dst AND src Selected bits in the destination word are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bit in the source word (mask). The TCMW instruction complements the destination word, which is then ANDed with source word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source and the destination word can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCMW (r8) RR64 HEX 96 40 88 Binary 1001 0110 0100 0000 1000 1000 If register pair 64 contains 11001100/11001100B, working register 8 contains 200 (decimal) and register pair 200 contains 01001000/01001000B, after this instruction the zero flag will be reset to zero. 259/298 1 ST9+ Programming Manual TCMW TCMW Test Complement Under Mask (Word) - Register, Memory TCMW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 14 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 8E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 8 8 8 8 8 8 8 8 8 8 8 Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] OPERATION a: NOT dst AND src Selected bits in the destination word are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bit in the source word (mask). The TCMW instruction complements the destination word, which is then ANDed with source word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is held in the source memory location and the destination word in the destination register pair. The destination register pair is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: NOT dst AND src rr rr + 2 As operation 'a' (indirect memory addressing only), but the contents of the destination register pair are incremented after the TCMW has been carried out. OPERATION c: rr rr - 2 NOT dst AND src As operation 'a' (indirect memory addressing only), but the contents of the destination register pair are decremented before the TCMW is carried out. 260/298 1 ST9+ Programming Manual TCMW TCMW Test Complement Under Mask (Word) - Register, Memory TCMW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCMW RR64,-(rr4) HEX C3 85 40 Binary 1100 0011 0011 0101 0100 0000 If working register pair 4 contains 1184 (decimal), register pair 64 contains 11001100/ 11001100B and memory location 1182 contains 11001100/11001100B, after this instruction the zero flag will be set and register pair 4 will contain 1182. 261/298 1 ST9+ Programming Manual TCMW TCMW Test Complement Under Mask (Word) - Memory, Register TCMW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 14 14 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 8E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 8 8 8 8 8 8 8 8 8 8 8 Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] OPERATION a: NOT dst AND src Selected bits in the destination word are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bit in the source word (mask). The TCMW instruction complements the destination word, which is then ANDed with the source word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is held in the source register pair and the destination word in the destination memory location. The source register pair is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: NOT dst AND src rr rr + 2 As operation 'a' (indirect memory addressing only), but the contents of the source register pair are incremented after the TCMW has been carried out. OPERATION c: rr rr - 2 NOT dst AND src As operation 'a' (indirect memory addressing only), but the contents of the source register pair are decremented before the TCMW is carried out. 262/298 1 ST9+ Programming Manual TCMW TCMW Test Complement Under Mask (Word) - Memory, Register TCMW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCMW (rr8),RR64 HEX BE 89 40 Binary 1011 1110 1000 1001 0100 0000 If register pair 64 contains 11001100/11001100B, working register pair 8 contains 2000h and memory location 2000 contains 11001100/11001100B, after this instruction the zero flag will be set. 263/298 1 ST9+ Programming Manual TCMW TCMW Test Complement Under Mask (Word) - Memory, Memory TCMW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 16 OPC (HEX) 8E OPC XTN Address Mode dst src (rr) (rr) OPERATION: NOT dst AND src Selected bits in the destination word are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bit in the source word (mask). The TCMW instruction complements the destination word, which is then ANDed with source word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is held in the source memory location and the destination word in the destination register pair. The source word is in the memory location addressed by the contents of the source register pair. the destination word is in the memory location addressed by the contents of the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCMW (rr4),(rr6) HEX 8E 57 Binary 1000 1110 0101 0111 If working register pair 6 contains 1002 (decimal), memory location pair 1002 contains 11001100/11001100B, working register pair 4 contains 1060 (decimal) and memory location 1060 contains 11001100/11001100B, after this instruction the zero flag wil be set. 264/298 1 ST9+ Programming Manual TCMW TCMW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 14 16 18 20 OPC (HEX) 87 87 BE 06 06 36 TCMW Test Complement Under Mask (Word) - All, Immediate OPC XTN 8 8 8 81 [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address Mode dst src RR #NN rr #NN (rr) #NN N(rr) NN(rr) NN #NN #NN #NN OPERATION: NOT dst AND src Selected bits in the destination word are tested for a logical one value. The bits to be tested are selected by setting to one the corresponding bit in the source word (mask). The TCMW instruction complements the destination word, which is then ANDed with source word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is the immediate value held in the operand. The destination word can be in memory or register file. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TCMW RR64, #CCCCh HEX 87 41 CC CC Binary 0011 0111 0100 0001 1100 1100 1100 1100 If register pair 64 contains 01001000/01001000B, after this instruction has been carried out the zero flag will be reset. 265/298 1 ST9+ Programming Manual TM Test under mask (byte) Register, Register TM dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) A2 A3 A4 A4 A4 E6 E6 E7 OPC XTN A A A TM [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address dst r r R r R (r) (r) R Mode src r (r) R R r R r (r) OPERATION: dst AND src Selected bits in the destination byte are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask) which is then ANDed with the destination byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is held in the source register and the destination byte in the destination register. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset Unaffected. Unaffected. EXAMPLE: Instruction TM r8,R64 HEX A4 40 D8 Binary 1010 0100 0100 0000 1101 1000 If working register 8 contains 01001100 and register 64 contains 00110011, after this instruction the zero flag will be set to one. 266/298 1 ST9+ Programming Manual TM Test under mask (byte) Register, Memory TM dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN A A A A A A A A A A A A Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r TM Oper a a b b c c a a a a a a [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] NN(rr) NN(rr) OPERATION a: dst AND src Selected bits in the destination byte are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask) which is then ANDed with the destination byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is held in the source memory location and the destination byte in the destination register. The destination register is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: dst AND src rr rr + 1 As operation 'a' (indirect memory addressing only), but the contents of the destination register pair are incremented after the TM has been carried out. OPERATION c: rr rr - 1 dst AND src As operation 'a' (indirect memory addressing only), but before the TM is carried out the contents of the destination register pair are decremented. 267/298 1 ST9+ Programming Manual TM Test under mask (byte) Register, Memory TM dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset Unaffected. Unaffected. TM EXAMPLE: Instruction TM r8, 0FBCh HEX C4 A8 0F BC Binary 1100 0100 1010 1000 0000 1111 1011 1100 If working register 8 contains 11001100 and memory location 4028 contains 10000101, after this instruction the zero flag will be set. 268/298 1 ST9+ Programming Manual TM Test under mask (byte) Memory, Register TM dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 10 10 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN A A A A A A A A A A A A Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r TM Oper a a b b c c a a a a a a [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofd,1|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] OPERATION a: dst AND src Selected bits in the destination byte are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask) which is then ANDed with the destination byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is held in the source register and the destination byte in the destination memory location. The source register is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: dst AND src rr rr + 1 As operation 'a' (indirect memory addressing only), but the contents of the source register pair are incremented after the TM has been carried out. OPERATION c: rr rr - 1 dst AND src As operation 'a' (indirect memory addressing only), but before the TM is carried out the contents of the source register pair are decremented. 269/298 1 ST9+ Programming Manual TM Test under mask (byte) Memory, Register TM dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset Unaffected. Unaffected. TM EXAMPLE: Instruction TM 0FBCh HEX C5 A8 0F BC Binary 1100 0101 1010 1000 0000 1111 1011 1100 If working register 8 contains 11001100 and memory location 4028 contains 10000101, after this instruction the zero flag will be reset to zero. 270/298 1 ST9+ Programming Manual TM Test under mask (byte) Memory, Memory TM dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 12 12 OPC (HEX) 73 73 OPC XTN A A TM Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION: dst AND src Selected bits in the destination byte are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask) which is then ANDed with the destination byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is in the memory location addressed by the source register pair, the destination byte is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset Unaffected. Unaffected. EXAMPLE: Instruction TM (rr4),(rr8) HEX 73 A8 D4 Binary 0111 0011 1010 1000 1101 0100 If working register pair 4 contains 2800 (decimal), memory location 2800 contains 11001100, working register pair 8 contains 4200 (decimal) and memory location 4200contains 00110011, after this instruction the zero flag will be set to one. 271/298 1 ST9+ Programming Manual TM Test under mask (byte) All, Immediate TM dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 8 14 OPC (HEX) A5 A5 F3 2F OPC XTN A A1 TM [ XTN |dst,0] [ XTN ] [ dst l ] Address Mode dst src R #N r #N (rr) #N NN #N OPERATION: dst AND src Selected bits in the destination byte are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source byte (mask) which is then ANDed with the destination byte. The zero flag can then be checked to determine the results. The destination byte remains unaltered by this instruction. The source byte is the immediate value in the operand, the destination byte can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset Unaffected. Unaffected. EXAMPLE: Instruction TM (rr8),#20h HEX F3 A8 20 Binary 1111 0011 1010 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 11101100, after this instruction the zero flag will be reset to zero. 272/298 1 ST9+ Programming Manual TMW TMW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) AE A7 A7 A7 96 96 A6 A6 OPC XTN A A A A TMW Test Under Mask (Word) - Register, Register [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address Mode dst src rr rr RR RR rr RR RR rr (r) RR (r) rr RR (r) rr (r) OPERATION: dst AND src Selected bits in the destination word are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source word (mask) which is then ANDed with the destination word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source and the destination word can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TMW (r8),RR64 HEX 96 40 A8 Binary 1001 0110 0100 0000 1010 1000 If register pair 64 contains 11001100/11001100B, working register 8 contains 200 (decimal) and register pair 200 contains 00110011/00110011B, after this instruction the zero flag will be reset to zero. 273/298 1 ST9+ Programming Manual TMW TMW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 14 14 14 14 14 14 14 14 14 16 16 OPC (HEX) AE 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN A A A A A A A A A A A TMW Test Under Mask (Word) - Register, Memory [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst AND src Selected bits in the destination word are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source word (mask) which is then ANDed with the destination word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is held in the source memory location and the destination word in the destination register pair. The destination register pair is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: dst AND src rr rr + 2 As operation 'a' (indirect memory addressing only), but the contents of the destination register pair are incremented after the TMW has been carried out. OPERATION c: rr rr - 2 dst AND src As operation 'a' (indirect memory addressing only), but the contents of the destination register pair are decremented before the TMW is carried out. 274/298 1 ST9+ Programming Manual TMW TMW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. TMW Test Under Mask (Word) - Register, Memory EXAMPLE: Instruction TMW RR64,-(rr4) HEX C3 A5 40 Binary 1100 0011 1010 0101 0100 0000 If working register pair 4 contains 1184 (decimal), register pair 64 contains 11001100/ 11001100B and memory location 1182 contains 11001100/11001100B, after this instruction the zero flag will be set and register pair 4 will contain 1182. 275/298 1 ST9+ Programming Manual TMW TMW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 14 14 14 14 14 14 14 14 14 16 16 16 OPC (HEX) AE BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN A A A A A A A A A A A TMW Test Under Mask (Word) - Memory, Register [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst AND src Selected bits in the destination word are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source word (mask) which is then ANDed with the destination word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is held in the source register pair and the destination word in the destination memory location. The source register pair is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: dst AND src rr rr + 2 As operation 'a' (indirect memory addressing only), but the contents of the source register pair are incremented after the TMW has been carried out. OPERATION c: rr rr - 2 dst AND src As operation 'a' (indirect memory addressing only), but the contents of the source register pair are decremented before the TMW is carried out. 276/298 1 ST9+ Programming Manual TMW TMW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. TMW Test Under Mask (Word) - Memory, Register EXAMPLE: Instruction TMW (rr8),RR64 HEX BE A9 40 Binary 1011 1110 1010 1001 0100 0000 If register pair 64 contains 11001100/11001100B, working register pair 8 contains 2000 (decimal) and memory location 2000 contains 11001100/11001100B, after this instruction the zero flag will be set. 277/298 1 ST9+ Programming Manual TMW TMW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 16 OPC (HEX) AE OPC XTN - TMW Test Under Mask (Word) - Memory, Memory Address Mode dst src (rr) (rr) OPERATION: dst AND src Selected bits in the destination word are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source word (mask) which is then ANDed with the destination word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is held in the source memory location and the destination word in the destination register pair. The source word is in the memory location addressed by the contents of the source register pair. the destination word is in the memory location addressed by the contents of the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TMW (rr4),(rr6) HEX AE 57 Binary 1010 1110 0101 0111 If working register pair 6 contains 1002 (decimal), memory location pair 1002 contains 11001100/11001100B, working register pair 4 contains 1060 (decimal) and memory location 1060 contains 11001100/11001100B, after this instruction the zero flag wil be set. 278/298 1 ST9+ Programming Manual TMW TMW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 14 16 18 20 OPC (HEX) A7 A7 BE 06 06 36 OPC XTN A A A A1 TMW Test Under Mask (Word) - All, Immediate [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address Mode dst src RR #NN rr #NN (rr) #NN N(rr) NN(rr) NN #NN #NN #NN OPERATION: dst AND src Selected bits in the destination word are tested for a logical zero value. The bits to be tested are selected by setting to one the corresponding bits in the source word (mask) which is then ANDed with the destination word. The zero flag can then be checked to determine the result. The destination word remains unaltered by this instruction. The source word is the immediate value held in the operand. the destination word can be in memory or register file. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction TMW RR64,#CCCCh HEX A7 41 CC CC Binary 0011 0111 0100 0001 1100 1100 1100 1100 If register pair 64 contains 01001000/01001000B, after this instruction has been carried out the zero flag will be reset. 279/298 1 ST9+ Programming Manual UNLINK Unlink code UNLINK dst INSTRUCTION FORMAT: [ OPC ] [ dst ] No. Bytes 2 No. Cycl 10/6 OPC (HEX) 75 UNLINK OPC XTN - Address Mode dst src rr OPERATION: Stack in memory(10 cycles) SSP = RR RR = (SSP) SSP = SSP + 2 Stack in the register file (6 cycles) SSP(low) = RR(low) RR(low) = SSP SSP(low) = SSP(low) + 1 SSP(high) = undefined In C functions, the compiler needs to push variables in the user/system stacks and to keep the return address location of the function inside the stack. Therefore, a frame pointer is used, and 2 pieces of code named prologue and epilogue need to be added at the beginning and at the end of the function. The "Unlink" instruction is used to get the shortest size in the epilogue of a C function. FLAGS: EXAMPLES: No flags affected. UNLINK RR4 Stack in memory (16 cycles) Stack in the register file (12 cycles) RR4(high) RR4(low) SSP RR4(low) SSP After the instruction, RR4 register will have the value taken in the stack as indicated in the above scheme. 280/298 ST9+ Programming Manual UNLINKU Unlink code UNLINKU INSTRUCTION FORMAT: [ OPC ] No. Bytes 3 No. Cycl 10/6 UNLINKU OPC (HEX) 87 OPC XTN - Address Mode dst src RR #N OPERATION: Stack in memory(10 cycles) USP = RR RR = (USP) SP = USP + 2 Stack in the register file (6 cycles) USP(low) = RR(low) RR(low) = USP USP(low) = USP(low) + 1 USP(high) = undefined In C functions, the compiler needs to push variables in the user/system stacks and to keep the return address location of the function inside the stack. Therefore, a frame pointer is used, and 2 pieces of code named prologue and epilogue need to be added at the beginning and at the end of the function. The "Unlinku" instruction is used to get the shortest size in the epilogue of a C function. FLAGS: EXAMPLES: No flags affected. UNLINKU RR4 Stack in memory (16 cycles) Stack in the register file (12 cycles) RR4(high) RR4(low) USP RR4(low) USP After the instruction, RR4 register will have the value taken in the stack as indicated in the above scheme. 281/298 ST9+ Programming Manual WFI Wait For Interrupt WFI INSTRUCTION FORMAT: [ OPC ] [ XTN ] No. Bytes 2 No. Cycl 4 + ... OPC (HEX) EF OPC XTN 01 WFI Address Mode dst src - OPERATION : FLAGS: This instruction suspends program operation until an interrupt is acknowledged, although DMA requests are still serviced. No flags affected. EXAMPLE: Instruction WFI HEX EF 01 Binary 1110 1111 0000 0001 The program is suspended until an interrupt occurs. 282/298 ST9+ Programming Manual XCH Exchange Registers XCH dst,src INSTRUCTION FORMAT: [ OPC ] [ src ] [ dst ] No. Bytes 3 3 3 3 No. Cycl 6 6 6 6 OPC (HEX) 16 16 16 16 OPC XTN - XCH Address Mode dst src R R R r r R r r OPERATION: dst src The contents of the destination register are loaded into the source register and the contents of the source register loaded into the destination register. FLAGS: No flags affected. EXAMPLE: Instruction XCH r2,r4 HEX 16 D4 D2 Binary 0001 0110 1101 0100 1101 0010 If working register 2 contains 26 (decimal) and working register 4 contains 100 (decimal), after this instruction register 2 will contain 100 and register 4 will contain 26. 283/298 ST9+ Programming Manual XOR Exclusive OR (byte) Register, Register XOR dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [ dst | src ] [ src ] [ dst ] No. Bytes 2 2 3 3 3 3 3 3 No. Cycl 4 6 6 6 6 6 6 6 OPC (HEX) 62 63 64 64 64 E6 E6 E7 OPC XTN 6 6 6 XOR [ [ OPC OPC ] ] [ src ] [ XTN | dst ] [ dst ] [ XTN | src ] Address dst r r R r R (r) (r) R Mode src r (r) R R r R r (r) OPERATION: dst dst XOR src The contents of the source are XORed with the destination byte and the results stored in the destination byte. The contents of the source are not affected. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction XOR r8,R64 HEX 64 40 D8 Binary 0110 0100 0100 0000 1101 1000 If working register 8 contains 11001100 and register 64 contains 10000101, after this instruction working register 8 will contain 01001001. 284/298 ST9+ Programming Manual XOR Exclusive OR (byte) Register, Memory XOR dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,1] [ dst ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 8 8 12 12 12 12 12 12 12 10 14 14 OPC (HEX) 72 72 B4 B4 C2 C2 60 7F 7F C4 7F 7F OPC XTN 6 6 6 6 6 6 6 6 6 6 6 6 XOR [ [ [ [ [ [ [ OPC OPC dst OPC src l OPC ofs l ] [ofs,1|src,0] [ XTN | dst ] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN | dst ] [ XTN |src,0] [ dst ] [ [ src h ofs h ] ] Addr Mode dst src R (rr) r (rr) R (rr)+ r (rr)+ R -(rr) r -(rr) r rr(rrx) R N(rr) r N(rr) r NN R r NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst XOR src The source byte is XORed with the destination byte and the result stored in the destination byte. The destination register is addressed directly, the memory location is addressed either directly, indirectly or by indexing. OPERATION b: dst dst XOR src rr rr + 1 The contents of the memory location addressed by the source register pair are XORed with the contents of the directly addressed destination register the result stored in the destination byte. The contents of the source register pair are incremented after the XOR has been carried out. OPERATION c: rr rr - 1 dst dst XOR src The contents of the source register pair are decremented and then the contents of the memory location addressed by the source register pair are XORed with the contents of the directly addressed destination register. The result is stored in the destination byte. 285/298 ST9+ Programming Manual XOR Exclusive OR (byte) Register, Memory XOR dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. XOR EXAMPLE: Instruction XOR r8,(rr4) HEX 72 65 D8 Binary 0111 0010 0110 0101 1101 1000 If working register 8 contains 11001100, working register pair 4 contains 4200 (decimal) and memory location 4200 contains 10000101, after this instruction register 8 will contain 01001001. 286/298 ST9+ Programming Manual XOR Exclusive OR (byte) Memory, Register XOR dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |dst,0] [ src ] No. Bytes 3 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 12 16 16 OPC (HEX) 72 72 B4 B4 C2 C2 60 26 26 C5 26 26 OPC XTN 6 6 6 6 6 6 6 6 6 6 6 6 XOR [ [ [ [ [ [ [ OPC OPC src OPC dst l OPC ofd l ] [ofs,d|dst,1] [ XTN | src ] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN | src ] [ XTN |dst,0] [ src ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) R (rr) r (rr)+ R (rr)+ r -(rr) R -(rr) r rr(rrx) r N(rr) R N(rr) r NN r NN(rr) NN(rr) R r Oper a a b b c c a a a a a a OPERATION a: dst dst XOR src The source byte is XORed with the destination byte and the result stored in the destination byte. The source registers are addressed directly, the memory location are addressed either directly, indirectly or by indexing. OPERATION b: dst dst XOR src rr rr + 1 The contents of the memory location addressed by the destination register pair (destination byte) are XORed with the contents of the directly addressed source register the result stored in the destination byte. The contents of the destination register pair are incremented after the XOR has been carried out. OPERATION c: rr rr - 1 dst dst XOR src The contents of the destination register pair are decremented and then the contents of the memory location addressed by the destination register pair (destination byte) are XORed with the contents of the directly addressed source register. The result is stored in the destination byte. 287/298 ST9+ Programming Manual XOR Exclusive OR (byte) Memory, Register XOR dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. XOR EXAMPLE: Instruction XOR 4028,r8 HEX C5 18 0F BC Binary 1100 0101 0001 1000 0000 1111 1011 1100 If memory location 4028 contains 11001100 and working register 8 contains 10000101, after this instruction memory location 4028 will contain 01001001. 288/298 ST9+ Programming Manual XOR Exclusive OR (byte) Memory, Memory XOR dst,src INSTRUCTION FORMAT: [ OPC ] [ XTN |src,0] [ dst,0 ] No. Bytes 3 3 No. Cycl 14 14 OPC (HEX) 73 73 OPC XTN 6 6 XOR Address Mode dst src (RR) (rr) (rr)* (rr) OPERATION : dst dst XOR src The contents of the memory addressed by the source register pair are XORed with the content of the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction XOR (rr4),(rr8) HEX 73 68 D4 Binary 0111 0011 0110 1000 1101 0100 If working register pair 4 contains 2800 (decimal), memory location 2800 contains 11001100, working register pair 8 contains 4200 (decimal) and memory location 4200 contains 1100011, after this instruction memory location 2800 will contain 00001111. 289/298 ST9+ Programming Manual XOR Exclusive OR (byte) All, Immediate XOR dst,src INSTRUCTION FORMAT: [ [ [ [ OPC OPC OPC dst h ] ] ] ] [ dst ] [ [ [ src src src ] ] ] No. Bytes 3 3 3 5 No. Cycl 6 6 10 16 OPC (HEX) 65 65 F3 2F OPC XTN 6 61 XOR [ XTN |dst,0] [ XTN ] [ dst l ] Address dst R r (rr) NN Mode src #N #N #N #N OPERATION: dst dst XOR src The value #N is XORed with the content of the destination register or memory location (destination byte) and stored in the destination byte. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 7 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction XOR (rr8),#32 HEX F3 68 20 Binary 1111 0011 0110 1000 0010 0000 If working register pair 8 contains 4028 (decimal) and memory location 4028 contains 11001100, after this instruction memory location 4028 will contain 11101100. 290/298 ST9+ Programming Manual XORW XORW dst,src INSTRUCTION FORMAT: [ [ OPC OPC ] ] [dst,0|src,0] [ src,0 ] No. Bytes [ dst,0 ] 2 3 3 3 3 3 3 3 No. Cycl 8 8 8 8 10 10 10 10 OPC (HEX) 6E 67 67 67 96 96 A6 A6 XORW Exclusive OR (Word) - Register, Register OPC XTN 6 6 6 6 [ [ OPC OPC ] ] [ src,0 ] [ XTN | dst ] [ dst,0 ] [ XTN | src ] Address Mode dst src rr rr RR RR rr RR RR rr (r) RR (r) rr RR (r) rr (r) OPERATION: dst dst XOR src The source word is XORed with the destination word and the result is stored in the destination word. The source and destination word can be addressed either directly or indirectly. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction XORW (r8),RR64 HEX 96 40 68 Binary 1001 0110 0100 0000 0110 1000 If register pair 64 contains 11001100/11001100B, working register 8 contains 200 (decimal) and register pair 200 contains 10101010/10101010B, after this instruction register pair 200 will hold 01100110/01100110B. 291/298 ST9+ Programming Manual XORW XORW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,0|src,1] ] [ XTN |src,0] [ ] [ XTN |src,1] [ No. Bytes dst,0 dst,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 12 12 14 14 14 14 14 14 14 14 16 16 OPC (HEX) 6E 7E D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 6 6 6 6 6 6 6 6 6 6 6 XORW Exclusive OR (Word) - Register, Memory [ [ [ [ [ [ [ OPC OPC dst,0 OPC src l OPC ofs l ] [ofs,0|src,0] [ XTN |dst,0] ] [ XTN |src,1] [ ofs ] ] ] ] ] ] [ XTN |dst,0] [ XTN |src,0] [ dst,0 ] [ [ src h ofs h ] ] Addr Mode dst src rr (rr) RR (rr) RR (rr)+ rr (rr)+ RR -(rr) rr -(rr) rr rr(rrx) RR N(rr) rr N(rr) rr NN RR rr NN(rr) NN(rr) Oper a a b b c c a a a a a a OPERATION a: dst dst XOR src The source word is XORed with the destination word and the result is stored in the destination word. The destination word is held in the destination register. The source word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst XOR src rr rr + 2 The source word is XORed with the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. The contents of the source register pair are incremented after the XOR has been carried out. OPERATION c: rr rr - 2 dst dst XOR src The contents of the source register pair are decremented before the XOR is carried out. The source word is XORed with the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the destination register. 292/298 ST9+ Programming Manual XORW XORW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. XORW Exclusive OR (Word) - Register, Memory EXAMPLE: Instruction XORW RR64,-(rr4) HEX C3 65 40 Binary 1100 0011 0110 0101 0100 0000 If working register pair 4 contains 1184 (decimal), register pair 64 contains 10101010/ 10101010B and memory location 1182 contains 11001100/11001100B, after this instruction register pair 64 will contain 01100110/01100110B and register pair 4 will contain 1182. 293/298 ST9+ Programming Manual XORW XORW dst,src INSTRUCTION FORMAT: [ [ [ OPC OPC OPC ] [dst,1|src,0] ] [ XTN |dst,1] [ ] [ XTN |dst,0] [ No. Bytes src,0 src,0 ] ] 2 3 3 3 3 3 3 4 4 4 5 5 No. Cycl 16 18 18 18 18 18 18 18 18 18 20 20 OPC (HEX) 6E BE D5 D5 C3 C3 60 86 86 E2 86 86 OPC XTN 6 6 6 6 6 6 6 6 6 6 6 XORW Exclusive OR (Word) - Memory, Register [ [ [ [ [ [ [ OPC OPC src,1 OPC dst l OPC ofd l ] [ofd,0|dst,1] [ XTN |src,0] ] [ XTN |dst,1] [ ofd ] ] ] ] ] ] [ XTN |src,1] [ XTN |dst,0] [ src,1 ] [ [ dst h ofd h ] ] Addr Mode dst src (rr) rr (rr) RR (rr)+ RR (rr)+ rr -(rr) RR -(rr) rr rr(rrx) rr N(rr) RR N(rr) rr NN rr NN(rr) NN(rr) RR rr Oper a a b b c c a a a a a a OPERATION a: dst dst XOR src The source word is XORed with the destination word and the result is stored in the destination word. The source word is held in the source register. The destination word can be addressed directly, indirectly or by indexing. OPERATION b: dst dst XOR src rr rr + 2 The source word is XORed with the destination word and the result is stored in the destination word. The source word is in the source register, the destination word is in the memory location addressed by the destination register pair. The contents of the destination register pair are incremented after the XOR has been carried out. OPERATION c: rr rr - 2 dst dst XOR src The contents of the destination register pair are decremented before the XOR is carried out. The source word is XORed with the destination word and the result is stored in the destination word. The source word is in the source register , the destination word is in the memory location addressed by the destination register pair. 294/298 ST9+ Programming Manual XORW XORW dst,src (Cont'd) FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. XORW Exclusive OR (Word) - Memory, Register EXAMPLE: Instruction XORW (rr4)+,RR64 HEX D5 64 40 Binary 1101 0101 0110 0100 0100 0000 If register pair 64 contains 11001100/11001100B, working register pair 4 contains 1064 (decimal) and memory location 1064 contains 10101010/10101010B, after this instruction is carried out memory location 1064 will contain 01100110/01100110B and working register pair 4 will contain 1066. 295/298 ST9+ Programming Manual XORW XORW dst,src INSTRUCTION FORMAT: [ OPC ] [dst,1|src,1] No. Bytes 2 No. Cycl 20 OPC (HEX) 6E XORW Exclusive OR (Word) - Memory, Memory OPC XTN - Address Mode dst src (rr) (rr) OPERATION: dst dst XOR src The source word is XORed with the destination word and the result is stored in the destination word. The source word is in the memory location addressed by the source register pair, the destination word is in the memory location addressed by the destination register pair. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction XORW (rr4),(rr6) HEX 6E 57 Binary 0110 1110 0101 0111 If working register pair 6 contains 1002 (decimal), memory location 1002 contains 11001100/11001100B, working register pair 4 contains 1060 (decimal) and memory location 1060 contains 10101010/10101010B, after this instruction memory location 1060 will contains 01100110/01100110B. 296/298 ST9+ Programming Manual XORW XORW dst,src INSTRUCTION FORMAT: [ [ [ [ [ [ [ [ [ [ OPC src l OPC src l OPC src h OPC ofd l OPC src l ] ] ] ] ] ] ] ] ] ] [ dst,1 ] [ [ [ [ [ [ [ src h src h ofd ofd src src dst h l h l ] ] ] ] ] ] ] No. Bytes 4 4 4 5 6 6 No. Cycl 10 10 18 20 22 22 OPC (HEX) 67 67 BE 06 06 36 XORW Exclusive OR (Word) - All, Immediate OPC XTN 6 6 6 61 [ XTN |dst,0] [ XTN |dst,1] [ src l ] [ XTN |dst,0] [ src h ] [ XTN ] [ dst h ] Address dst RR rr (rr) N(rr) NN(rr) NN Mode src #NN #NN #NN #NN #NN #NN OPERATION: dst dst XOR src The source word is XORed with the destination word and the result is stored in the destination word. The source word is the immediate value in the operand, the destination word can be in memory or in the register file. FLAGS: C: Z: S: V: D: H: Unaffected. Set if the result is zero, otherwise cleared. Set if result bit 15 is set, otherwise cleared. Always reset to zero. Unaffected. Unaffected. EXAMPLE: Instruction XORW RR64,#52428 HEX 67 41 CC CC Binary 0110 0111 0100 0001 1100 1100 1100 1100 If register pair 64 contains 10101010/10101010B, after this instruction has benn carried out register pair 64 will contains 01100110/01100110B. 297/298 ST9+ Programming Manual Notes: Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of SGS-THOMSON Microelectronics. (c)1997 SGS-THOMSON Microelectronics - All rights reserved. Purchase of I2C Components by SGS-THOMSON Microelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. SGS-THOMSON Microelectronics Group of Companies Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. 298/298 |
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