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| HB56D473EJ Series 4,194,304-word x 72-bit High Density Dynamic RAM Module ADE-203-725A (Z) Rev. 1.0 Feb. 27, 1997 Description The HB56D473EJ belongs to 8 Byte DIMM (Dual In-line Memory Module) family, and has been developed as an optimized main memory solution for 4 and 8 Byte processor applications. The HB56D473EJ is a 4M x 72 dynamic RAM module, mounted 16 pieces of 16-Mbit DRAM (HM5117400) sealed in SOJ package and 8 pieces of 4-Mbit DRAM (HM514100) sealed in SOJ package, 1 pieces of 16bit BiCMOS line driver (74ABT16244) sealed in TSSOP package and 1 pieces of 20-bit BiCMOS line driver (74ABT16827) sealed in TSSOP package. An outline of the HB56D473EJ is 168-pin socket type package (dual lead out). Therefore, the HB56D473EJ makes high density mounting possible without surface mount technology. The HB56D473EJ provides common data inputs and outputs. Decoupling capacitors are mounted on the module board. Features * 168-pin socket type package (Dual lead out) Outline: 133.35 mm (Length) x 25.40 mm (Height) x 9.00 mm (Thickness) Lead pitch: 1.27 mm * Single 5 V (5%) supply * High speed Access time: tRAC = 60/70 ns (max) tCAC = 20/25 ns (max) * Low power dissipation Active mode: 12.5/11.3 W (max) Standby mode (TTL): 588 mW (max) (CMOS): 462 mW (max) * Buffered input except RAS and DQ * 4 byte interleave enabled, dual address input (A0/B0) * JEDEC standard outline buffered 8-byte DIMM * Fast page mode capability * 2,048 refresh cycles: 32 ms HB56D473EJ Series * 2 variations of refresh RAS-only refresh CAS-before-RAS refresh * TTL compatible Ordering Information Type No. HB56D473EJ-6 HB56D473EJ-7 Access time 60 ns 70 ns Package 168-pin dual lead out socket type Contact pad Gold Pin Arrangement Front side Back side 1 pin 10 pin 11 pin 85 pin 94 pin 95 pin 40 pin 41 pin 124 pin 125 pin 84 pin 168 pin 2 HB56D473EJ Series Pin Arrangement Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin name VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 DQ17 VSS NC NC VCC WE0 CE0 CE2 RE0 OE0 VSS A0 A2 Pin No. 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 Pin name VSS OE2 RE2 CE4 CE6 WE2 VCC NC NC DQ18 DQ19 VSS DQ20 DQ21 DQ22 DQ23 VCC DQ24 NC NC NC NC DQ25 DQ26 DQ27 VSS DQ28 DQ29 DQ30 DQ31 VCC DQ32 DQ33 DQ34 Pin No. 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 Pin name VSS DQ36 DQ37 DQ38 DQ39 VCC DQ40 DQ41 DQ42 DQ43 DQ44 VSS DQ45 DQ46 DQ47 DQ48 DQ49 VCC DQ50 DQ51 DQ52 DQ53 VSS NC NC VCC NC CE1 CE3 NC NC VSS A1 A3 Pin No. 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 Pin name VSS NC NC CE5 CE7 PDE VCC NC NC DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 NC NC NC NC DQ61 DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 3 HB56D473EJ Series Pin No. 35 36 37 38 39 40 41 42 Pin name A4 A6 A8 A10 NC VCC NC NC Pin No. 77 78 79 80 81 82 83 84 Pin name DQ35 VSS PD1 PD3 PD5 PD7 ID0 (NC) VCC Pin No. 119 120 121 122 123 124 125 126 Pin name A5 A7 A9 NC NC VCC NC B0 Pin No. 161 162 163 164 165 166 167 168 Pin name DQ71 VSS PD2 PD4 PD6 PD8 ID1 (VSS) VCC Pin Description Pin name A0 to A10, B0 Function Address input Row address Column address : A0 to A10, B0 : A0 to A10, B0 Refresh address (D0 to D15) : A0 to10, B0 Refresh address (M0 to M7) : A0 to A9, B0 DQ0 to DQ71 RE0, RE2 CE0 to CE7 WE0, WE2 OE0, OE2 VCC VSS PD1 to PD8 ID0, ID1 PDE NC Data-in/data-out Row address strobe (RAS) Column address strobe (CAS) Read/Write enable Output enable Power supply Ground Presence detect ID bit Presence detect enable No connection 4 HB56D473EJ Series Presence Detect Pin Assignment PDE = Low Pin name PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Note: Pin No. 79 163 80 164 81 165 82 166 1: High level (driver output) 0: Low level (driver output) 60 ns 1 1 0 1 0 1 1 1 70 ns 1 1 0 1 0 0 1 1 PDE = High All High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z 5 HB56D473EJ Series Block Diagram RE0 OE0 WE0 CE0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D0 OE RE2 OE2 WE2 CE4 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D8 OE RAS WE D1 OE RAS WE D9 OE DQ8 CE1 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 RAS WE M0 DQ44 CE5 RAS WE M4 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D2 OE DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D10 OE RAS WE D3 OE RAS WE D11 OE DQ17 CE2 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 RAS WE M1 DQ53 CE6 RAS WE M5 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D4 OE DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D12 OE RAS WE D5 OE RAS WE D13 OE DQ26 CE3 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 RAS WE M2 DQ62 CE7 RAS WE M6 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D6 OE DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 I/O CAS I/O I/O I/O I/O CAS I/O I/O I/O CAS Din/Dout RAS WE D14 OE RAS WE D7 OE RAS WE D15 OE DQ35 RAS WE M3 DQ71 RAS WE M7 PD1 to PD8 A0 B0 A1 to A10 VCC VSS 0.22 F D0 to D7, M0 to M3 D8 to D15, M4 to M7 D0 to D15, M0 to M7 D0 to D15, M0 to M7, 74ABT16244, 74ABT16827 26 pcs D0 to D15, M0 to M7, 74ABT16244, 74ABT16827 VCC VCC VSS VCC VSS VCC VSS VCC VSS VCC PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 Note : D0 to D15 : HM5117400 M0 to M7 : HM514100 : 74ABT16244, 74ABT16827 6 HB56D473EJ Series Absolute Maximum Ratings Parameter Voltage on any pin relative to V SS Supply voltage relative to VSS Short circuit output current Power dissipation Operating temperature Storage temperature Symbol VT VCC Iout Pt Topr Tstg Value -0.5 to +7.0 -0.5 to +7.0 50 25 0 to +70 -55 to +125 Unit V V mA W C C Recommended DC Operating Conditions (Ta = 0 to 70C) Parameter Supply voltage Symbol VSS VCC Input high voltage Input low voltage Note: 1. All voltage referred to VSS . VIH VIL Min 0 4.75 2.4 -0.5 Typ 0 5.0 -- -- Max 0 5.25 5.5 0.8 Unit V V V V 1 1 1 Note 7 HB56D473EJ Series DC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V) 60 ns Parameter Operating current Standby current Symbol Min I CC1 I CC2 -- -- 70 ns Max Min 2384 -- 112 -- Max Unit Test conditions 2144 mA 112 mA t RC = min TTL interface RAS, CAS = VIH Dout = High-Z CMOS interface RAS, CAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH, CAS = VIL Dout = enable t RC = min t PC = min 0 V Vin 5.5 V 0 V Vout 5.5 V Dout = disable High Iout = -5 mA Low Iout = 4.2 mA 1, 3 2 1 Notes 1, 2 -- 88 -- 88 mA RAS-only refresh current Standby current CAS-before-RAS refresh current Fast page mode current Input leakage current Output leakage current Output high voltage Output low voltage I CC3 I CC5 I CC6 I CC7 I LI I LO VOH VOL -- -- -- -- -10 -10 2.4 0 2384 -- 184 -- 2144 mA 184 mA 2384 -- 2224 -- 10 10 VCC 0.4 -10 -10 2.4 0 2144 mA 1984 mA 10 10 VCC 0.4 A A V V Notes: 1. I CC depends on output load condition when the device is selected, ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Address can be changed once or less while CAS = VIH. Capacitance (Ta = 25C, VCC = 5 V 5%) Parameter Input capacitance (Address) Input capacitance (CAS, WE, OE) Input capacitance (RAS) Symbol CI1 CI2 CI3 Typ -- -- -- -- Max 20 20 99 20 Unit pF pF pF pF Notes 1 1 1 1, 2 I/O capacitance (DQ0 to DQ7, DQ9 to DQ16, CI/O1 DQ18 to DQ25, DQ27 to DQ34, DQ36 to DQ43, DQ45 to DQ52, DQ54 to DQ61, DQ63 to DQ70) I/O capacitance (DQ8, DQ17, DQ26, DQ35, DQ44, DQ53, DQ62, DQ71) CI/O2 -- 25 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. CAS = VIH to disable Dout. 8 HB56D473EJ Series AC Characteristics (Ta = 0 to 70C, VCC = 5 V 5%, VSS = 0 V)*1, *2 Test Conditions * * * * Input rise and fall times: 5 ns Input timing reference levels: 0.8 V, 2.4 V Output timing reference levels: 0.4 V, 2.4 V Output load: 2 TTL gate + C L (100 pF) (Including scope and jig) Read, Write and Refresh Cycles (Common parameters) 60 ns Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Refresh period (2,048 cycles) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT t REF Min 110 40 10 60 15 5 10 0 15 20 15 20 60 15 20 0 0 3 -- Max -- -- -- 70 ns Min 130 50 10 Max -- -- -- Unit ns ns ns Notes 10000 70 10000 20 -- -- -- -- 40 25 -- -- -- -- -- -- 50 32 5 10 0 15 20 15 25 70 15 25 0 0 3 -- 10000 ns 10000 ns -- -- -- -- 45 30 -- -- -- -- -- -- 50 32 ns ns ns ns ns ns ns ns ns ns ns ns ns ms 5, 18 6, 18 6 7 3 4 9 HB56D473EJ Series Read Cycle 60 ns Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD Min -- -- -- -- 0 0 5 35 30 2 3 3 -- -- 20 Max 60 20 35 20 -- -- -- -- -- -- -- -- 20 20 -- 70 ns Min -- -- -- -- 0 0 5 40 35 2 3 3 -- -- 25 Max 70 25 40 25 -- -- -- -- -- -- -- -- 25 25 -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 18 13 13, 18 5 12 12 Notes 8, 9 9, 10, 17 9, 11, 17 9, 18 Write Cycle 60 ns Parameter Write command setup time Write command hold time Write command pulse width Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t DS t DH Min 0 15 10 0 20 Max -- -- -- -- -- 70 ns Min 0 15 10 0 20 Max -- -- -- -- -- Unit ns ns ns ns ns 15 15 Notes 14 10 HB56D473EJ Series Refresh Cycle 60 ns Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t WRP t WRH t RPC Min 15 10 5 10 10 Max -- -- -- -- -- 70 ns Min 15 10 5 10 10 Max -- -- -- -- -- Unit ns ns ns ns ns Notes Fast Page Mode Cycle 60 ns Parameter Fast page mode cycle time Fast page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Symbol t PC t RASP t CPA t CPRH Min 40 -- -- 40 Max -- 70 ns Min 45 Max -- Unit ns 16 9, 17 Notes 100000 -- 40 -- -- 45 100000 ns 45 -- ns ns 11 HB56D473EJ Series Notes: 1. AC measurements assume t T = 5 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh cycle or CAS-before-RAS refresh). If the internal refresh counter is used, a minimum of eight CAS-before-RAS refresh cycles are required. 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that tRCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 2TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max) and tOEZ (max) is define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS is not restrictive operating parameters. It is included in the data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle. 15. These parameters are referred to CAS leading edge in early write cycle. 16. t RASP defines RAS pulse width in fast page mode cycles. 17. Access time is determined by the longest among tAA, t CAC or tCPA. 18. Parity bit of this item must not use (DQ8, DQ17, DQ26, DQ35, DQ44, DQ53, DQ62, DQ71). 19. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied VIH or VIL. 12 HB56D473EJ Series Timing Waveforms*19 Read Cycle t RC t RAS t RP RAS t CSH t RCD tT t RSH t CAS t CRP CAS t RAD t ASR t ASC t RAL t CAL t CAH t RAH Address Row Column t RRH t RCS t RCH WE t DZC t CDD Din High-Z t DZO t OEA t OED OE t OEZ t CAC t AA t RAC t CLZ Dout t OFF t OH Dout t OHO 13 HB56D473EJ Series Early Write Cycle t RC t RAS t RP RAS t CSH t RCD tT CAS t RSH t CAS t CRP t ASR t RAH t ASC t CAH Address Row Column t WP t WCS t WCH WE t DS t DH Din Din Dout High-Z* * t WCS t WCS (min) 14 HB56D473EJ Series RAS-Only Refresh Cycle t RC t RAS t RP RAS tT t CRP CAS t RPC t CRP t ASR t RAH Address Row t OFF Dout High-Z 15 HB56D473EJ Series CAS-Before-RAS Refresh Cycle t RC t RP t RAS t RP t RAS t RC t RP RAS tT t RPC t CP t CSR t CHR t RPC t CP t CRP t CSR t CHR CAS t WRP t WRH t WRP t WRH WE Address t OFF High-Z Dout 16 HB56D473EJ Series Fast Page Mode Read Cycle t RASP t CPRH t RP RAS tT t CSH t RCD CAS t RAL t RAD t ASR t RAH Address Row t CAL t ASC t CAH Column 1 t CAL t ASC t CAH Column 2 t CAL t ASC t CAH Column N t CAS t CP t PC t CAS t CP t RSH t CAS t CRP t RCS t RCS WE t DZC t CDD Din t DZO High-Z t OED t DZC t CDD High-Z t DZO t OED t RCH t RCH t RCS t RRH t RCH t DZC t CDD High-Z t DZO t OED , OE t RAC t AA t OH t CPA t AA t OH t CPA t AA t OH t OEA t OHO t OEA t OHO t OFF t OEZ t OHO t OEA t CAC t CLZ t OFF t CAC t OEZ t CLZ t CAC t CLZ t OFF t OEZ Dout Dout 1 Dout 2 Dout N 17 HB56D473EJ Series Fast Page Mode Eary Write Cycle t RASP t RP RAS tT t CSH t RCD t CAS CAS t PC t CP t CAS t CP t RSH t CAS t CRP t ASR t RAH t ASC t CAH t ASC t CAH t ASC t CAH Address Row Column 1 t WP t WCS t WCH Column 2 t WP t WCS t WCH Column N t WP t WCS t WCH WE t DS t DH t DS t DH t DS t DH Din Din 1 Din 2 Din N Dout High-Z* * t WCS t WCS (min) 18 HB56D473EJ Series Physical Outline Unit: mm/inch Front side 133.35 5.250 3.00 0.118 127.35 5.014 9.00 max 0.354 max ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Front) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 1 84 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, C B 36.83 1.450 54.61 2.150 A 11.43 0.450 ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , ,, , 3.00 0.118 8.89 0.350 1.27 0.10 0.050 0.004 Back side 2 - 3.00 2 - 0.118 ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Component area ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (Back) ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, 168 85 4.00 0.157 17.78 0.700 Detail A Detail B 1.27 0.050 1.00 0.039 Detail C 3.175 0.125 6.35 0.250 2.00 0.10 0.079 0.004 2.54 min 0.100 min 0.25 max 0.010 max 1.00 0.05 0.039 0.002 3.125 0.125 0.123 0.005 3.125 0.125 0.123 0.005 6.35 0.250 3.175 0.125 2.00 0.10 0.079 0.004 25.40 1.000 4.00 min 0.157 min 19 HB56D473EJ Series When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Hitachi, Ltd. Semiconductor & IC Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109 For further information write to: Hitachi America, Ltd. Semiconductor & IC Div. 2000 Sierra Point Parkway Brisbane, CA. 94005-1835 USA Tel: 415-589-8300 Fax: 415-583-4207 Hitachi Europe GmbH Electronic Components Group Continental Europe Dornacher Strae 3 D-85622 Feldkirchen Munchen Tel: 089-9 91 80-0 Fax: 089-9 29 30 00 Hitachi Europe Ltd. Electronic Components Div. Northern Europe Headquarters Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA United Kingdom Tel: 0628-585000 Fax: 0628-778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 0104 Tel: 535-2100 Fax: 535-1533 Hitachi Asia (Hong Kong) Ltd. Unit 706, North Tower, World Finance Centre, Harbour City, Canton Road Tsim Sha Tsui, Kowloon Hong Kong Tel: 27359218 Fax: 27306071 20 HB56D473EJ Series Revision Record Rev. Date 1.0 Feb. 27, 1997 Contents of Modification Initial issue Drawn by Approved by 21 |
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