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5812-F 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
5812-F
The UCN5812AF/EPF combine a 20-bit CMOS shift register, data latches, and control circuitry with high-voltage bipolar source drivers and active DMOS pull-downs for reduced supply current requirements. Although designed primarily for vacuum-fluorescent displays, the high-voltage, high-current outputs also allow them to be used in other peripheral power driver applications. They are improved versions of the original UCN5812A/EP.
Data Sheet 26182.26A
BiMOS II 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5812EPF
SERIAL DATA OUT LOGIC SUPPLY LOAD SUPPLY OUT20 SERIAL DATA IN 27 OUT19 OUT 1 26
V DD 28
4
3
2
VBB
1
OUT18
5 6
REGISTER REGISTER LATCHES LATCHES
25 24 23 22 21 20 19
CLK ST
OUT 2
7 8 9 10 OUT12 11
OUT 8
The CMOS shift register and latches allow direct interfacing with microprocessor-based systems. Data input rates are typically over 5 MHz with a 5 V logic supply, and over 7.5 MHz at 12 V. Especially useful for inter-digit blanking, the BLANKING input disables the output source drives and turns on the DMOS sink drivers. Use with TTL may require the use of appropriate pull-up resistors to ensure an input logic high. A CMOS serial data output enables cascade connections in applications requiring additional drive lines. Similar devices are available as the UCN5810AF/LWF (10 bits), UCN5811A (12 bits), and UCN5818AF/EPF (32 bits). The output source drivers are high-voltage PNP-NPN Darlingtons with a minimum breakdown of 60 V and are capable of sourcing up to 40 mA. The DMOS active pull-downs are capable of sinking up to 15 mA. The UCN5812AF is supplied in a 28-pin dual in-line plastic package with 0.600" (15.24 mm) row spacing. For surface-mounting, the UCN5812EPF is furnished in 28-lead plastic chip carrier (quad pack) with 0.050"(1.22 mm) centers. Copper lead-frames, reduced supply current requirements and lower output saturation voltages, allow continuous operation, with all outputs sourcing 25 mA, of the UCN5812AF over the operating temperature range, and the UCN5812EPF up to +75C. All devices are also available for operation between -40C and +85C. To order, change the prefix from `UCN' to `UCQ'.
12
14
17 OUT 10
13
15
OUT11
16
BLANKING
GROUND
STROBE
CLOCK
OUT9
18
Dwg. PP-059-1
ABSOLUTE MAXIMUM RATINGS
at TA = 25C
Logic Supply Voltage, VDD ..................... 15 V Driver Supply Voltage, V BB .................... 60 V Continuous Output Current Range, IOUT ................................. -40 to +15 mA Input Voltage Range, VIN ........................ -0.3 V to VDD + 0.3 V Package Power Dissipation, PD (UCN5812AF) ........................... 3.12 W* (UCN5812EPF) ........................1.92 W Operating Temperature Range, TA .................................. -20C to +85C Storage Temperature Range, TS ................................ -55C to +150C
* Derate at rate of 25 mW/C above TA = +25C Derate at rate of 15 mW/C above TA = +25C Caution: Allegro CMOS devices have input static protection but are susceptible to damage when exposed to extremely high static electrical charges. Note that the UCN5812AF (dual in-line package) and UCN5812EPF (PLCC package) are electrically identical and share a common pin number assignment.
FEATURES
s s s s s High-Speed Source Drivers s Active DMOS Pull-Downs 60 V Source Outputs s Reduced Supply Current To 3.3 MHz Data Input Rate Requirements Low Output-Saturation Voltages s Improved Replacement Low-Power CMOS Logic and Latches for TL5812 UCN5812AF .
Always order by complete part number, e.g.,
5812-F 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5812AF FUNCTIONAL BLOCK DIAGRAM
LOAD SUPPLY SERIAL DATA OUT OUT 20 OUT 19 OUT 18 OUT 17 OUT 16 OUT 15 OUT 14 OUT 13 OUT 12 OUT 11 BLANKING GROUND 1 2 3 4 5 6 VBB VDD 28 27 26 25 24 23 LOGIC SUPPLY SERIAL DATA IN OUT 1 OUT 2 OUT 3 OUT 4 OUT 5 OUT 6 OUT 7 OUT 8 OUT 9 OUT 10 STROBE CLOCK
GROUND OUT 1 OUT 2 OUT 3 OUT N
Dwg. FP-013-1
CLOCK SERIAL DATA IN STROBE
V DD
LOGIC SUPPLY SERIAL DATA OUT
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
BLANKING MOS BIPOLAR LOAD SUPPLY
REGISTER
REGISTER
LATCHES
LATCHES
7 8 9 10 11 12 13 14 BLNK
22 21 20 19 18 17 ST CLK 28 16 27 15
VBB
Dwg. PP-029-7
TYPICAL INPUT CIRCUIT
VDD
TYPICAL OUTPUT DRIVER
V BB
IN
OUT N
Dwg. EP-010-5
Dwg. No. A-14,219
115 Northeast Cutoff, Box 15036 W Worcester, Massachusetts 01615-0036 (508) 853-5000 Copyright (c) 1988, 1996, Allegro MicroSystems, Inc.
5812-F 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
ELECTRICAL CHARACTERISTICS at TA = +25C, VBB = 60 V (unless otherwise noted).
Characteristic Output Leakage Current Output Voltage Symbol ICEX VOUT(1) VOUT(0) Output Pull-Down Current IOUT(0) Test Conditions VOUT = 0 V, TA = +70C IOUT = -25 mA, VBB = 60 V IOUT = 1 mA IOUT = 2 mA VOUT = 5 V to VBB VOUT = 20 V to VBB Input Voltage VIN(1) VIN(0) Input Current IIN(1) IIN(0) Serial Data VOUT(1) VOUT(0) Maximum Clock Frequency Supply Current fclk IDD(1) IDD(0) IBB(1) IBB(0) Blanking to Output Delay tPHL tPLH Output Fall Time Output Rise Time tf tr All Outputs High All Outputs Low Outputs High, No Load Outputs Low CL = 30 pF, 50% to 50% CL = 30 pF, 50% to 50% CL = 30 pF, 90% to 10% CL = 30 pF, 10% to 90% VIN = VDD VIN = 0.8 V IOUT = -200 A IOUT = 200 A Limits @ VDD = 5 V Mln. Typ. Max. -- 58 -- -- 2.0 -- 3.5 -0.3 -- -- 4.5 -- 3.3 -- -- -- -- -- -- -- -- -5.0 58.5 2.0 -- 3.5 -- -- -- 0.05 -0.05 4.7 200 5.0 100 100 1.5 10 2000 1000 1450 650 -15 -- 3.0 -- -- -- 5.3 +0.8 0.5 -0.5 -- 250 -- 300 300 4.0 100 -- -- -- -- Limits @ VDD = 12 V Min. Typ. Max. -- 58 -- -- -- 8.0 10.5 -0.3 -- -- 11.7 -- -- -- -- -- -- -- -- -- -- -5.0 58.5 -- 2.0 -- 13 -- -- 0.1 -0.1 11.8 100 7.5 200 200 1.5 10 1000 850 650 700 -15 -- -- 3.5 -- -- 12.3 +0.8 1.0 -1.0 -- 200 -- 500 500 4.0 100 -- -- -- -- Units A V V V mA mA V V A A V mV MHz A A mA A ns ns ns ns
Negative current is defined as coming out of (sourcing) the specified device pin.
5812-F 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
CLOCK DATA IN C STROBE BLANKING G OUTN
Dwg. No. 12,649A
A
B
D
E
F
Serial Data present at the input is transferred to the shift register on the logic "0" to logic "1" transition of the CLOCK input pulse. On succeeding CLOCK pulses, the registers shift data information towards the SERIAL DATA OUTPUT. The SERIAL DATA must appear at the input prior to the rising edge of the CLOCK input waveform. Information present at any register is transferred to the respective latch when the STROBE is high (serial-to-parallel conversion). The latches will continue to accept new data as long as the STROBE is held high. Applications where the latches are bypassed (STROBE tied high) will require that the BLANKING input be high during serial data entry. When the BLANKING input is high, the output source drivers are disabled (OFF); the DMOS sink drivers are ON, the information stored in the latches is not affected by the BLANKING input. With the BLANKING input low, the outputs are controlled by the state of their respective latches.
TIMING CONDITIONS
(TA = +25C,VDD = 5 V, Logic Levels are VDD and Ground)
A. Minimum Data Active Time Before Clock Pulse (Data Set-Up Time) .......................................................................... 75 ns B. Minimum Data Active Time After Clock Pulse (Data Hold Time) ............................................................................. 75 ns C. Minimum Data Pulse Width ................................................................ 150 ns D. Minimum Clock Pulse Width ............................................................... 150 ns E. Minimum Time Between Clock Activation and Strobe ...................... 300 ns F. Minimum Strobe Pulse Width ............................................................. 100 ns G. Typical Time Between Strobe Activation and Output Transition .......................................................................... 500 ns
TRUTH TABLE
Serial Data Clock Input Input H L X Shift Register Contents I1 H L I2 I3 ... IN-1 IN RN-2 RN-1 RN-2 RN-1 RN-1 RN X X Serial Data Strobe Output Input RN-1 RN-1 RN X PN
X = Irrelevant
Latch Contents I1 I2 I3 ... IN-1 IN Blanking I1
Output Contents I2 I3 ... IN-1 IN
R1 R2 ... R 1 R2 ...
R1 R2 R3 ... X X X ...
L H
R1 R2 R3 ... P1 P2 P3 ... X X X ...
RN-1 RN PN-1 PN X X L H P1 P2 P3 ... L L L ... PN1 PN L L
P1 P2 P3 ...
L = Low Logic Level
PN-1 PN
H = High Logic Level
P = Present State R = Previous State
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5812-F 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5812AF
Dimensions in Inches (controlling dimensions)
28 15 0.015 0.008
0.700
MAX
0.580 0.485
0.600
BSC
1
2 0.070 0.030
3
4 1.565 1.380
14 0.100
BSC
0.005
MIN
0.250
MAX
0.015
MIN
0.200 0.115 0.022 0.014
Dwg. MA-003-28 in
Dimensions in Millimeters (for reference only)
28 15 0.381 0.204
17.78
MAX
14.73 12.32
15.24
BSC
1
2 1.77 0.77
3
4 39.7 35.1
2.54
BSC
14
0.13
MIN
6.35
MAX
0.39
MIN
5.08 2.93 0.558 0.356
Dwg. MA-003-28 mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative. 3. Lead thickness is measured at seating plane or below.
5812-F 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
UCN5812EPF
Dimensions in Inches (controlling dimensions)
18 12
0.013 0.021 0.219 0.191
19
11
0.050
BSC
0.026 0.032 0.456 0.450 0.495 0.485
INDEX AREA
0.219 0.191
25
5
26 0.020
MIN
28
1
4
0.165 0.180
0.456 0.450 0.495 0.485
Dwg. MA-005-28A in
Dimensions in Millimeters (for reference only)
18 12
0.331 0.533 5.56 4.85
19
11
1.27
BSC
0.812 0.661 11.58 11.43 12.57 12.32
INDEX AREA
5.56 4.85
25
5
26 0.51
MIN
28
1
4
4.57 4.20
11.582 11.430 12.57 12.32
Dwg. MA-005-28A mm
NOTES: 1. Exact body and lead configuration at vendor's option within limits shown. 2. Lead spacing tolerance is non-cumulative.
115 Northeast Cutoff, Box 15036 Worcester, Massachusetts 01615-0036 (508) 853-5000
5812-F 20-BIT SERIAL-INPUT, LATCHED SOURCE DRIVERS WITH ACTIVE-DMOS PULL-DOWNS
BiMOS II (Series 5800) & DABiC IV (Series 6800) INTELLIGENT POWER INTERFACE DRIVERS SELECTION GUIDE
Function
8-Bit (saturated drivers) 8-Bit 8-Bit 8-Bit 8-Bit 9-Bit 10-Bit (active pull-downs) 12-Bit (active pull-downs) 20-Bit (active pull-downs) 32-Bit (active pull-downs) 32-Bit 32-Bit (saturated drivers)
Output Ratings *
SERIAL-INPUT LATCHED DRIVERS -120 mA 350 mA 350 mA 350 mA 350 mA 1.6 A -25 mA -25 mA -25 mA -25 mA 100 mA 100 mA 50 V 50 V 80 V 50 V 80 V 50 V 60 V 60 V 60 V 60 V 30 V 40 V
Part Number
5895 5821 5822 5841 5842 5829 5810-F and 6809/10 5811 and 6811 5812-F and 6812 5818-F and 6818 5833 5832
PARALLEL-INPUT LATCHED DRIVERS 4-Bit 8-Bit 8-Bit 350 mA -25 mA 350 mA 50 V 60 V 50 V 5800 5815 5801
SPECIAL-PURPOSE FUNCTIONS Unipolar Stepper Motor Translator/Driver Addressable 28-Line Decoder/Driver
*
1.25 A 450 mA
50 V 30 V
5804 6817
Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits. Negative current is defined as coming out of (sourcing) the output. Complete part number includes additional characters to indicate operating temperature range and package style. Internal transient-suppression diodes included for inductive-load protection.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the design of its products. The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.

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