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(R)
74LVX240
LOW VOLTAGE OCTAL BUS BUFFER (3-STATE INV.) WITH 5V TOLERANT INPUTS
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HIGH SPEED: tPD = 4.7 ns (TYP.) at VCC = 3.3V 5V TOLERANT INPUTS POWER-DOWN PROTECTION ON INPUTS INPUT VOLTAGE LEVEL: VIL = 0.8V, VIH = 2V at VCC = 3V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC LOW NOISE: VOLP = 0.3 V (TYP.) at VCC = 3.3V SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 3.6V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 240 IMPROVED LATCH-UP IMMUNITY
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74LVX240M 74LVX240T It has better speed performance at 3.3V than 5V LSTTL family combined with the true CMOS low power consumption. G output control governs four BUS BUFFERs. This device is designed to be used with 3 state memory address drivers, etc. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The LVX240 is a low voltage CMOS OCTAL BUS BUFFER fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology. It is ideal for low power and low noise 3.3V applications. PIN CONNECTION AND IEC LOGIC SYMBOLS
April 1999
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74LVX240
INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 4,6, 8 9, 7,5, 3 11, 13, 15, 17 18, 16, 14, 12 19 10 20 SYMBOL 1G 1A1 to 1A4 2Y1 to 2Y4 2A1 to 2A4 1Y1 to 1Y4 2G GND VCC NAME AND FUNCT ION Output Enable Input Data Inputs Data Outputs Data Inputs Data Outputs Output Enable Input Ground (0V) Positive Supply Voltage
TRUTH TABLE
INPUT G L L H
X:"H" or "L" Z: High impedance
OUTPUT An L H X Yn H L Z
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC orIGND Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC VCC or Ground Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to 7.0 -0.5 to VCC + 0.5 - 20 20 25 50 -65 to +150 300 Unit V V V mA mA mA mA
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Input Voltage Output Voltage Operating Temperature: Input Rise and Fall Time (VCC = 3V) (note 2) Parameter Supply Voltage (note 1) Valu e 2 to 3.6 0 to 5.5 0 to VCC -40 to +85 0 to 100 Unit V V V
o
C
ns/V
1) Truth Table guaranteed: 1.2V to 3.6V 2) VIN from 0.8V to 2V
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74LVX240
DC SPECIFICATIONS
Symb ol Parameter V CC (V) VIH High Level Input Voltage 2.0 3.0 3.6 VIL Low Level Input Voltage 2.0 3.0 3.6 VOH High Level Output Voltage Low Level Output Voltage Input Leakage Current 3 State Output Leakage Current Quiescent Supply Current 2.0 3.0 3.0 VOL 2.0 3.0 3.0 II IOZ ICC 3.6 3.6 3.6 VI(*) = VIH or VIL VI(*) = VIH or VIL IO=-50 A IO=-50 A IO=-4 mA IO=50 A IO=50 A IO=4 mA 1.9 2.9 2.58 0.0 0.0 0.1 0.1 0.36 0.1 0.25 4 2.0 3.0 Test Co nditions Min. 1.5 2.0 2.4 0.5 0.8 0.8 1.9 2.9 2.48 0.1 0.1 0.44 1 2.5 40 A A A V V T yp. Valu e T A = 25 oC Max. -40 to 85 o C Min. 1.5 2.0 2.4 0.5 0.8 0.8 V V Max. Un it
VI = 5.5Vor GND VI = VIH orVIL VO = VCC orGND VI = VCC orGND
(*) All outputs loaded.
DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 3.3 -0.5 3.3 3.3 CL = 50 pF 0.8 Test Co nditions Min. T yp. 0.3 -0.3 2 V Valu e T A = 25 oC Max. 0.5 -40 to 85 o C Min. Max. Un it
1) Worst case package 2) Max number of outputs defined as (n). Data inputs are driven 0V to 3.3V, (n -1) outputs switching and one output at GND 3) max number of data inputs (n) switching. (n-1) switching 0V to3.3V. Inputs under test switching: 3.3V to threshold (VILD), 0V to threshold (VIHD). f=1MHz
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74LVX240
AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL Propagation Delay Time 2.7 2.7 3.3(*) 3.3(*) 2.7 2.7 3.3 3.3(*) tPLZ tPHZ tOSLH tOSHL Output Disable Time Output to Output Skew Time (note 1, 2) 2.7 3.3(*) 2.7 3.3(*)
(*)
T est Con ditio n CL (p F) 15 50 15 50 15 50 15 50 50 50 50 50 RL = 1 K
Valu e T A = 25 oC -40 to 85 o C Min. T yp. Max. Min. Max. 5.7 10.1 1.0 12.5 8.2 4.3 6.8 7.1 9.6 5.5 8.0 11.6 9.7 13.6 6.2 9.7 13.8 17.3 8.8 12.3 16.0 11.4 1.5 1.5 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 16.0 7.5 11.0 16.5 20.0 10.5 14.0 19.0 13.0 1.5 1.5
Un it
ns
tPZL tPZH
Output Enable Time
RL = 1 K
ns
ns ns
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any twooutputs of the same device switching in the same direction, either HIGH or LOW 2) Parameter guaranteed by design (*) Voltage range is 3.3V 0.3V
CAPACITIVE CHARACTERISTICS
Symb ol Parameter V CC (V) CIN COUT CPD Input Capacitance Output Capacitance Power Dissipation Capacitance (note 1) 3.3 3.3 3.3 fIN = 10 MHz Test Co nditions
o
Valu e T A = 25 C Min. T yp. 4 6 17 Max. 10 -40 to 85 C Min. Max. 10
o
Un it
pF pF pF
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operting current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/n(per circuit)
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74LVX240
TEST CIRCUIT
T EST tPLH , tPHL tPZL , tPLZ tPZH , tPHZ
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RL = R1 = 1K orequivalent RT = ZOUT of pulse generator (typically 50)
SW IT CH Open VCC GND
WAVEFORM 1: PROPAGATION DELAYS (f=1MHz; 50% duty cicle)
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74LVX240
WAVEFORM 2: OUTPUT ENABLE AND DISABLE TIME (f=1MHz; 50% duty cicle)
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74LVX240
SO-20 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012
P013L
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74LVX240
TSSOP20 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 6.4 6.25 4.3 6.5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 6.6 6.5 4.48 0.002 0.335 0.0075 0.0035 0.252 0.246 0.169 0.256 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.260 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
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74LVX240
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A. http://www.st.com .
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