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| (R) STD40NF02L N-CHANNEL 20V - 0.0095 - 40A DPAK LOW GATE CHARGE STripFETTM POWER MOSFET PRELIMINARY DATA TYPE STD40NF02L s s s s s V DSS 20 V RDS(on) < 0.0115 ID 40 A TYPICAL RDS(on) = 0.0095 TYPICAL Qg = 35 nC @ 10V OPTIMAL RDS(on) x Qg TRADE-OFF CONDUCTION LOSSES REDUCED SWITCHING LOSSES REDUCED 3 1 DESCRIPTION This application specific Power Mosfet is the third generation of STMicroelectronics unique "Single Feature SizeTM" strip-based process. The resulting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high efficiency are of paramount importance. APPLICATIONS SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS DPAK TO-252 (Suffix "T4") ADD SUFFIX "T4" FOR ORDERING IN TAPE & REEL INTERNAL SCHEMATIC DIAGRAM s ABSOLUTE MAXIMUM RATINGS Symbol V DS V DGR V GS I D (*) I D (*) IDM (**) P tot Tstg Tj Parameter Drain-source Voltage (V GS = 0) Drain- gate Voltage (R GS = 20 k) Gate-source Voltage Drain Current (continuous) at T c = 25 C Drain Current (continuous) at T c = 100 o C Drain Current (pulsed) Total Dissipation at T c = 25 C Derating Factor Storage Temperature Max. Operating Junction Temperature o o Value 20 20 20 20 20 80 55 0.37 -65 to 175 175 Unit V V V A A A W W/ o C o o C C (*) Current Limited By The Package (**) Pulse width limited by safe operating area September 2000 1/6 STD40NF02L THERMAL DATA R thj-case R thj-amb Tl Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 2.73 62.5 300 o o C/W C/W o C ELECTRICAL CHARACTERISTICS (Tcase = 25 oC unless otherwise specified) OFF Symbol V (BR)DSS I DSS IGSS Parameter Drain-source Breakdown Voltage Test Conditions I D = 250 A V GS = 0 Min. 20 1 10 100 Typ. Max. Unit V A A nA Zero Gate Voltage V DS = Max Rating Drain Current (V GS = 0) V DS = Max Rating Gate-body Leakage Current (V DS = 0) V GS = 20 V T c =125 o C ON () Symbol V GS(th) R DS(on) I D(on) Parameter Gate Threshold Voltage V DS = V GS Static Drain-source On Resistance V GS = 10V V GS = 5V Test Conditions I D = 250 A I D = 20 A I D = 20 A 20 Min. 1 Typ. Max. 2.5 0.0095 0.0115 0.015 0.019 Unit V A On State Drain Current V DS > I D(on) x R DS(on)max V GS = 10 V DYNAMIC Symbol g fs () C iss C oss C rss Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Test Conditions V DS > I D(on) x R DS(on)max V DS = 25 V f = 1 MHz I D =20 A V GS = 0 Min. Typ. 40 1500 900 200 Max. Unit S pF pF pF 2/6 STD40NF02L ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol t d(on) tr Qg Q gs Q gd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions V DD = 15 V I D = 20 A R G = 4.7 V GS = 4.5 V (Resistive Load, see fig. 3) V DD = 16 V I D = 20 A V GS = 10 V Min. Typ. 20 170 36 5 10 45 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol t d(of f) tf Parameter Turn-off Delay Time Fall Time Test Conditions V DD = 15 V I D = 20 A R G = 4.7 V GS = 4.5 V (Resistive Load, see fig. 3) Min. Typ. 40 60 Max. Unit ns ns SOURCE DRAIN DIODE Symbol ISD I SDM (*) V SD () t rr Q rr I RRM Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD =20 A V GS = 0 70 105 2.4 I SD = 20 A di/dt = 100 A/s V DD = 15 V T j = 150 o C (see test circuit, fig. 5) Test Conditions Min. Typ. Max. 20 80 1.2 Unit A A V ns C A () Pulsed: Pulse duration = 300 s, duty cycle 1.5 % (*) Pulse width limited by safe operating area 3/6 STD40NF02L Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuits For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 4/6 STD40NF02L TO-252 (DPAK) MECHANICAL DATA mm MIN. A A1 A2 B B2 C C2 D E G H L2 L4 0.6 2.2 0.9 0.03 0.64 5.2 0.45 0.48 6 6.4 4.4 9.35 0.8 1 0.023 TYP. MAX. 2.4 1.1 0.23 0.9 5.4 0.6 0.6 6.2 6.6 4.6 10.1 MIN. 0.086 0.035 0.001 0.025 0.204 0.017 0.019 0.236 0.252 0.173 0.368 0.031 0.039 inch TYP. MAX. 0.094 0.043 0.009 0.035 0.212 0.023 0.023 0.244 0.260 0.181 0.397 DIM. H A C2 C DETAIL "A" A1 L2 D DETAIL "A" B = = 3 B2 = = G E 2 L4 1 = = A2 0068772-B 5/6 STD40NF02L Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2000 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 6/6 |
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