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INTEGRATED CIRCUITS
DATA SHEET
74HC3G06; 74HCT3G06 Inverter with open-drain outputs
Product specification 2003 May 15
Philips Semiconductors
Product specification
Inverter with open-drain outputs
FEATURES * Wide supply voltage range from 2.0 to 6.0 V * Symmetrical output impedance * High noise immunity * Low power dissipation * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. * Balanced propagation delays * Very small 8 pins package. DESCRIPTION
74HC3G06; 74HCT3G06
The 74HC3G06/74HCT3G06 is a high-speed Si-gate CMOS device. Specified in compliance with JEDEC standard no. 7A. The 74HC3G06/74HCT3G06 provides three inverting buffers. The outputs of the 74HC3G06; 74HCT3G06 devices are open drains and can be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH-level.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 6.0 ns. TYPICAL SYMBOL tPZL tPLZ CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. For 74HC3G06 the condition is VI = GND to VCC. For 74HCT3G06 the condition is VI = GND to VCC - 1.5 V. PARAMETER propagation delay nA to nY propagation delay nA to nY input capacitance power dissipation capacitance per buffer notes 1 and 2 CONDITIONS HC3G CL = 50 pF; VCC = 4.5 V CL = 50 pF; VCC = 4.5 V 9 11 1.5 4 HCT3G 9 12 1.5 4 ns ns pF pF UNIT
2003 May 15
2
Philips Semiconductors
Product specification
Inverter with open-drain outputs
FUNCTION TABLE See note 1. INPUT nA L H Note 1. H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74HC3G06DP 74HCT3G06DP PINNING PIN 1 2 3 4 5 6 7 8 1A 3Y 2A GND 2Y 3A 1Y VCC SYMBOL data input data output data input ground (0 V) data output data input data output supply voltage -40 to +125 C -40 to +125 C PINS 8 8 PACKAGE TSSOP8 TSSOP8
74HC3G06; 74HCT3G06
OUTPUT nY Z L
MATERIAL plastic plastic
CODE SOT505-2 SOT505-2
MARKING H06 T06
DESCRIPTION
handbook, halfpage
1
1
7
handbook, halfpage
1A 1 3Y 2
8 VCC 7 1Y 3A 2Y 6
MNB030
06
2A GND 3 4 6 5
3
1
5
1
2
MNB031
Fig.1 Pin configuration.
Fig.2 Logic symbol.
2003 May 15
3
Philips Semiconductors
Product specification
Inverter with open-drain outputs
74HC3G06; 74HCT3G06
handbook, halfpage
1
1A
1Y
7
handbook, halfpage
Y
3
2A
2Y
5 A
6
3A
3Y
2
GND
MNA586
MNB032
Fig.3 IEC logic symbol.
Fig.4 Logic diagram (one driver).
RECOMMENDED OPERATING CONDITIONS 74HC3G06 SYMBOL VCC VI VO Tamb PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times CONDITIONS MIN. 2.0 0 0 see DC and AC -40 characteristics per device VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V - - - TYP. 5.0 - - +25 MAX. 6.0 6.0 VCC +125 MIN. 4.5 0 0 -40 TYP. 5.0 - - +25 MAX. 5.5 5.5 VCC +125 V V V C 74HCT3G06 UNIT
tr, tf
- 6.0 -
1000 500 400
- - -
- 6.0 -
- 500 -
ns ns ns
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK IOK VO IO ICC, IGND Tstg PD Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 110 C the value of PD derates linearly with 8 mW/K. 2003 May 15 4 PARAMETER supply voltage input diode current output diode current output voltage output sink current VCC or GND current storage temperature power dissipation Tamb = -40 to +125 C; note 2 VO < -0.5 V; note 1 active mode; note 1 high-impedance mode; note 1 -0.5 V < VO < 7.0 V; note 1 note 1 CONDITIONS VI < -0.5 V or VI > VCC + 0.5 V; note 1 - - -0.5 -0.5 - - -65 - MIN. -0.5 MAX. +7.0 20 -20 VCC + 0.5 7.0 -25 50 +150 300 V mA mA V V mA mA C mW UNIT
Philips Semiconductors
Product specification
Inverter with open-drain outputs
DC CHARACTERISTICS
74HC3G06; 74HCT3G06
Type 74HC3G06 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C; note 1 VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOL LOW-level output voltage VI = VIH or VIL IO = 20 A IO = 20 A IO = 4.0 mA IO = 20 A IO = 5.2 mA ILI IOZ ICC input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 2.0 4.5 4.5 6.0 6.0 6.0 6.0 6.0 - - - - - - - - 0 0 0.15 0 0.16 - - - - - - - - - - - - - - - - - 0.1 0.1 0.33 0.1 0.33 1.0 5.0 10 - - - 0.5 1.35 1.8 0.1 0.1 0.4 0.1 0.4 1.0 10 20 V V V V V A A A 1.5 3.15 4.2 - - - 1.2 2.4 3.2 0.8 2.1 2.8 - - - 0.5 1.35 1.8 V V V V V V VCC (V) MIN. TYP. MAX. UNIT
Tamb = -40 to +125 C VIH HIGH-level input voltage 2.0 4.5 6.0 VIL LOW-level input voltage 2.0 4.5 6.0 VOL LOW-level output voltage VI = VIH or VIL IO = 20 A IO = 20 A IO = 4.0 mA IO = 20 A IO = 5.2 mA ILI IOZ ICC Note 1. All typical values are measured at Tamb = 25 C. 2003 May 15 5 input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current VI = VCC or GND; IO = 0 2.0 4.5 4.5 6.0 6.0 6.0 6.0 6.0 - - - - - - - - V V V V V A A A 1.5 3.15 4.2 - - - V V V V V V
Philips Semiconductors
Product specification
Inverter with open-drain outputs
74HC3G06; 74HCT3G06
Type 74HCT3G06 At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C; note 1 VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL IO = 20 A IO = 4.0 mA ILI IOZ ICC ICC input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current additional supply current per input VI = VCC or GND; IO = 0 VI = VCC - 2.1 V; IO = 0 4.5 4.5 5.5 5.5 5.5 4.5 to 5.5 - - - - - - 0 0.15 - - - - 0.1 0.33 1.0 5.0 10 375 V V A A A A 4.5 to 5.5 4.5 to 5.5 2.0 - 1.6 1.2 - 0.8 V V VCC (V) MIN. TYP. MAX. UNIT
Tamb = -40 to +125 C VIH VIL VOL HIGH-level input voltage LOW-level input voltage LOW-level output voltage VI = VIH or VIL IO = 20 A IO = 4.0 mA ILI IOZ ICC ICC Note 1. All typical values are measured at Tamb = 25 C. input leakage current VI = VCC or GND 3-state output OFF current VI = VIH or VIL; VO = VCC or GND quiescent supply current additional supply current per input VI = VCC or GND; IO = 0 VI = VCC - 2.1 V; IO = 0 4.5 4.5 5.5 5.5 5.5 4.5 to 5.5 - - - - - - - - - - - - 0.1 0.4 1.0 10 20 410 V V A A A A 4.5 to 5.5 4.5 to 5.5 2.0 - - - - 0.8 V V
2003 May 15
6
Philips Semiconductors
Product specification
Inverter with open-drain outputs
AC CHARACTERISTICS Type 74HC3G06 GND = 0 V; tr = tf 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +85 C; note 1 tPZL propagation delay nA to nY see Figs 5 and 6 2.0 4.5 6.0 tPLZ propagation delay nA to nY see Figs 5 and 6 2.0 4.5 6.0 tTHL output transition time see Figs 5 and 6 2.0 4.5 6.0 Tamb = -40 to +125 C tPZL propagation delay nA to nY see Figs 5 and 6 2.0 4.5 6.0 tPLZ propagation delay nA to nY see Figs 5 and 6 2.0 4.5 6.0 tTHL output transition time see Figs 5 and 6 2.0 4.5 6.0 Note 1. All typical values are measured at Tamb = 25 C.
74HC3G06; 74HCT3G06
MIN. VCC (V) - - - - - - - - - - - - - - - - - -
TYP.
MAX.
UNIT
22 9 8 24 11 10 18 6 5 - - - - - - - - -
95 18 16 95 20 19 95 19 16
ns ns ns ns ns ns ns ns ns
125 25 20 125 27 23 125 25 20
ns ns ns ns ns ns ns ns ns
2003 May 15
7
Philips Semiconductors
Product specification
Inverter with open-drain outputs
Type 74HCT3G06 GND = 0 V; tr = tf 6.0 ns; CL = 50 pF. TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +85 C; note 1 tPZL tPLZ tTHL propagation delay nA to nY see Figs 5 and 6 propagation delay nA to nY see Figs 5 and 6 output transition time see Figs 5 and 6 2.0 2.0 2.0
74HC3G06; 74HCT3G06
MIN. VCC (V) - - - - - -
TYP.
MAX.
UNIT
9 12 6 - - -
24 27 19
ns ns ns
Tamb = -40 to +125 C tPZL tPLZ tTHL Note 1. All typical values are measured at Tamb = 25 C. AC WAVEFORMS propagation delay nA to nY see Figs 5 and 6 propagation delay nA to nY see Figs 5 and 6 output transition time see Figs 5 and 6 2.0 2.0 2.0 29 32 22 ns ns ns
handbook, full pagewidth
VI nA input GND t PLZ VCC nY output VOL Vx t THL VM t PZL VM
MNB033
VX = 0.1 x VCC. For 74HC3G06: VM = 50%; VI = GND to VCC. For 74HCT3G06: VM = 1.3 V; VI = GND to 3.0 V.
Fig.5 The input (nA) to output (nY) propagation delays and transition times.
2003 May 15
8
Philips Semiconductors
Product specification
Inverter with open-drain outputs
74HC3G06; 74HCT3G06
handbook, full pagewidth
S1 VCC PULSE GENERATOR VI D.U.T. RT CL = 50 pF
MNA742
VCC open GND
RL = VO 1 k
TEST tPLH/tPHL tPLZ/tPZL tPHZ/tPZH open VCC GND
S1
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.6 Load circuitry for switching times.
2003 May 15
9
Philips Semiconductors
Product specification
Inverter with open-drain outputs
PACKAGE OUTLINE
74HC3G06; 74HCT3G06
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm
SOT505-2
D
E
A
X
c y HE vMA
Z
8
5
A pin 1 index
A2 A1
(A3)
Lp L
1
e bp
4
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.00 A2 0.95 0.75 A3 0.25 bp 0.38 0.22 c 0.18 0.08 D(1) 3.1 2.9 E(1) 3.1 2.9 e 0.65 HE 4.1 3.9 L 0.5 Lp 0.47 0.33 v 0.2 w 0.13 y 0.1 Z(1) 0.70 0.35 8 0
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT505-2 REFERENCES IEC JEDEC --JEITA EUROPEAN PROJECTION ISSUE DATE 02-01-16
2003 May 15
10
Philips Semiconductors
Product specification
Inverter with open-drain outputs
SOLDERING Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 220 C (SnPb process) or below 245 C (Pb-free process) - for all the BGA packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 235 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems.
74HC3G06; 74HCT3G06
To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2003 May 15
11
Philips Semiconductors
Product specification
Inverter with open-drain outputs
74HC3G06; 74HCT3G06
Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP Notes 1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. not suitable not suitable(3) SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
2003 May 15
12
Philips Semiconductors
Product specification
Inverter with open-drain outputs
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development
74HC3G06; 74HCT3G06
DEFINITION This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2003 May 15
13
Philips Semiconductors
Product specification
Inverter with open-drain outputs
NOTES
74HC3G06; 74HCT3G06
2003 May 15
14
Philips Semiconductors
Product specification
Inverter with open-drain outputs
NOTES
74HC3G06; 74HCT3G06
2003 May 15
15
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
613508/01/pp16
Date of release: 2003
May 15
Document order number:
9397 750 11187

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