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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT366 Hex buffer/line driver; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Hex buffer/line driver; 3-state; inverting FEATURES * Inverting outputs * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT366 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns 74HC/HCT366 The 74HC/HCT366 are hex inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) are controlled by the output enable inputs (OE1, OE2). A HIGH on OEn causes the outputs to assume a high impedance OFF-state. The "366" is identical to the "365" but has inverting outputs. TYPICAL SYMBOL tPHL/ tPLH CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay nA to nY input capacitance power dissipation capacitance per buffer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 10 3.5 30 HCT 11 3.5 30 ns pF pF UNIT December 1990 2 Philips Semiconductors Product specification Hex buffer/line driver; 3-state; inverting PIN DESCRIPTION PIN NO. 1, 15 2, 4, 6, 10, 12, 14 3, 5, 7, 9, 11, 13 8 16 SYMBOL OE1, OE2 1A to 6A 1Y to 6Y GND VCC NAME AND FUNCTION output enable inputs (active LOW) data inputs data outputs ground (0 V) positive supply voltage 74HC/HCT366 Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Hex buffer/line driver; 3-state; inverting FUNCTION TABLE INPUTS OE1 L L X H Notes OE2 L L H X nA L H X X 74HC/HCT366 OUTPUT nY H L Z Z 1. H = HIGH voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Hex buffer/line driver; 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 -40 to +85 max. 125 25 21 190 38 33 190 38 33 75 15 13 -40 to +125 min. max. 150 30 26 225 45 38 225 45 38 90 18 15 ns 74HC/HCT366 TEST CONDITIONS UNIT V WAVEFORMS CC (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 min. typ. max. min. tPHL/ tPLH propagation delay nA to nY 3-state output enable time OEn to nY 3-state output disable time OEn to nY output transition time 33 12 10 44 16 13 55 20 16 14 5 4 100 20 17 150 30 26 150 30 26 60 12 10 tPZH/ tPZL ns Fig.7 tPHZ/ tPLZ ns Fig.7 tTHL/ tTLH ns Fig.6 December 1990 5 Philips Semiconductors Product specification Hex buffer/line driver; 3-state; inverting 74HC/HCT366 DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE1 OE2 nA UNIT LOAD COEFFICIENT 1.00 0.90 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. TEST CONDITIONS UNIT V WAVEFORMS CC (V) ns ns ns ns 4.5 4.5 4.5 4.5 Fig.6 Fig.7 Fig.7 Fig.6 +25 typ. 13 16 20 5 -40 to +85 -40 to +125 max. 36 53 53 18 max. min. max. min. 24 35 35 12 30 44 44 15 tPHL/ tPLH propagation delay nA to nY tPZH/ tPZL 3-state output enable time OEn to nY tPHZ/ tPLZ 3-state output disable time OEn to nY tTHL/ tTLH output transition time December 1990 6 Philips Semiconductors Product specification Hex buffer/line driver; 3-state; inverting AC WAVEFORMS 74HC/HCT366 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the input (nA) to output (nY) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the 3-state enable and disable times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". December 1990 7 |
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