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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT564 Octal D-type flip-flop; positive-edge trigger; 3-state; inverting Product specification File under Integrated Circuits, IC06 December 1990 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger; 3-state; inverting FEATURES * 3-state inverting outputs for bus oriented applications * 8-bit positive-edge triggered register * Common 3-state output enable input * Independent register and 3-state buffer operation * Output capability: bus driver * ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT564 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. 74HC/HCT564 The 74HC/HCT564 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The "564" is functionally identical to the "574" but has inverting outputs. The "564" is functionally identical to the "534", but has a different pinning. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC; for HCT the condition is VI = GND to VCC - 1.5 V ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". PARAMETER propagation delay CP to Qn maximum clock frequency input capacitance power dissipation capacitance per flip-flop notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 15 127 3.5 27 HCT 16 62 3.5 27 ns MHz pF pF UNIT December 1990 2 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger; 3-state; inverting PIN DESCRIPTION PIN NO. 1 2, 3, 4, 5, 6, 7, 8, 9 10 11 19, 18, 17, 16, 15, 14, 13, 12 20 SYMBOL OE D0 to D7 GND CP Q0 to Q7 VCC NAME AND FUNCTION 74HC/HCT564 3-state output enable input (active LOW) data inputs ground (0 V) clock input (LOW-to-HIGH, edge-triggered) 3-state flip-flop outputs positive supply voltage Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol. December 1990 3 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger; 3-state; inverting FUNCTION TABLE OPERATING MODES load and read register load register and disable outputs Notes INPUTS OE L L H H CP Dn l h l h 74HC/HCT564 INTERNAL FLIP-FLOPS L H L H OUTPUTS Q0 to Q7 H L Z Z 1. H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition Z = high impedance OFF-state = LOW-to-HIGH clock transition Fig.4 Functional diagram. Fig.5 Logic diagram. December 1990 4 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger; 3-state; inverting DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER +25 min. tPHL/ tPLH propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time typ. 50 18 14 44 16 13 50 18 14 14 5 4 80 16 14 60 12 10 5 5 5 6.0 30 35 14 5 4 6 2 2 0 0 0 38 115 137 max. 165 33 28 140 28 24 135 27 23 60 12 10 100 20 17 75 15 13 5 5 5 4.8 24 28 -40 to +85 min. max. 205 41 35 175 35 30 170 34 29 75 15 13 120 24 20 90 18 15 5 5 5 4.0 20 24 -40 to +125 min. max. 250 50 43 210 42 36 205 41 35 90 18 15 ns 74HC/HCT564 TEST CONDITIONS UNIT VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPZH/ tPZL ns Fig.8 tPHZ/ tPLZ ns Fig.8 tTHL/ tTLH ns Fig.6 tW clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency ns Fig.6 tsu ns Fig.7 th ns Fig.7 fmax MHz Fig.6 December 1990 5 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger; 3-state; inverting DC CHARACTERISTICS FOR 74HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: bus driver ICC category: MSI Note to HCT types 74HC/HCT564 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT OE D0 to D7 CP UNIT LOAD COEFFICIENT 0.80 0.25 1.00 AC CHARACTERISTICS FOR 74HCT GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER +25 min. tPHL/ tPLH tPZH/ tPZL tPHZ/ tPLZ tTHL/ tTLH tW tsu th fmax propagation delay CP to Qn 3-state output enable time OE to Qn 3-state output disable time OE to Qn output transition time clock pulse width HIGH or LOW set-up time Dn to CP hold time Dn to CP maximum clock pulse frequency 18 12 3 27 typ. 19 19 19 5 8 3 -2 56 max. 35 35 30 12 23 15 3 22 -40 to +85 min. max. 44 44 38 15 27 18 3 18 -40 to +125 min. max. 53 53 45 18 ns ns ns ns ns ns ns MHz 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 Fig.6 Fig.8 Fig.8 Fig.6 Fig.6 Fig.7 Fig.7 Fig.6 UNIT V CC WAVEFORMS (V) TEST CONDITIONS December 1990 6 Philips Semiconductors Product specification Octal D-type flip-flop; positive-edge trigger; 3-state; inverting AC WAVEFORMS 74HC/HCT564 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. The shaded areas indicate when the input is permitted to change for predictable output performance. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock pulse frequency. Fig.7 Waveforms showing the data set-up and hold times for the data input (Dn). PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.8 Waveforms showing the 3-state enable and disable times. December 1990 7 |
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