View 7835_971695.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PSD913F1
Flash In-System Programmable (ISP) Peripherals For 8-bit MCUs
PRELIMINARY DATA
FEATURES SUMMARY s Single Supply Voltage: - 5 V10% for PSD913F1 - 3.3 V10% for PSD913F1-V
s
Figure 1. Packages
Up to 1Mbit of Primary Flash Memory (8 uniform sectors) 256Kbit Secondary EEPROM (4 uniform sectors) Up to 16Kbit SRAM Over 2,000 Gates of PLD: DPLD 27 Reconfigurable I/O ports Enhanced JTAG Serial Port Programmable power management High Endurance: - 100,000 Erase/Write Cycles of Flash Memory - 10,000 Erase/Write Cycles of EEPROM - 1,000 Erase/Write Cycles of PLD
PQFP52 (T)
s
s s s s s s
PLCC52 (K)
January 2002
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
1/3
Programmable Peripheral
Revision A Flash PSD PSD913F1
Preliminary
1.0 Introduction
Flash In-System-Programmable Microcontroller Peripherals
The PSD913F1 family of Programmable Microcontroller (MCU) Peripherals brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD913F1 devices combine many of the peripheral functions found in MCU based applications: * 1 Mbit of Flash memory * A second EEPROM memory * Over 2,000 gates of Flash programmable logic * Up to 16Kbit SRAM * Reconfigurable I/O ports * Programmable power management.
1
PSD913F1
Preliminary The PSD913F1 family offers two methods to program PSD Flash memory while the PSD is soldered to a circuit board.
1.0 Introduction
(Cont.)
t In-System Programming (ISP) JTAG
An IEEE 1149.1 compliant JTAG interface is included on the PSD enabling the entire device (Flash memory, EEPROM, the PLD, and all configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even while completely blank. The innovative JTAG interface to flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as:
* First time programming - How do I get firmware into the flash the very first time?
JTAG is the answer, program the PSD while blank with no MCU involvement.
* Inventory build-up of pre-programmed devices - How do I maintain an accurate
count of pre-programmed flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer, build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to customer. No more labels on chips and no more wasted inventory.
* Expensive sockets - How do I eliminate the need for expensive and unreliable
sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads.
t In-Application Programming (IAP)
Two independent memory arrays (Flash and EEPROM) are included so the MCU can execute code from one memory while erasing and programming the other. Robust product firmware updates in the field are possible over any communication channel (CAN, Ethernet, UART, J1850, etc) using this unique architecture. Designers are relieved of these problems:
* Simultaneous read and write to flash memory - How can the MCU program the
same memory from which it is executing code? It cannot. The PSD allows the MCU to operate the two memories concurrently, reading code from one while erasing and programming the other during IAP.
* Complex memory mapping - I have only a 64K-byte address space to start with.
How can I map these two memories efficiently? A Programmable Decode PLD is the answer. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the 64K-byte address limit.
* Separate program and data space - How can I write to flash or EEPROM memory
while it resides in "program" space during field firmware updates, my MCU won't allow it! The flash PSD provides means to "reclassify" flash or EEPROM memory as "data" space during IAP, then back to "program" space when complete. PSDsoft Express - ST's software development tool - guides you through the design process step-by-step making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft Express will take you through the remainder of the design with point and click entry, covering...PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft - FlashLINK (JTAG) and PSDpro. The PSD913F1 is available in 52-pin PLCC and PQFP packages as well as a 64-pin TQFP package. 2
Preliminary
PSD913F1
2.0 Key Features
t A simple interface to 8-bit microcontrollers that use either multiplexed or
non-multiplexed busses. The bus interface logic uses the control signals generated by the microcontroller automatically when the address is decoded and a read or write is performed. A partial list of the MCU families supported include:
* * * *
Intel 8031, 80196, 80186, 80C251, and 80386EX Motorola 68HC11, 68HC16, 68HC12, and 683XX Philips 8031 and 8051XA Zilog Z80 and Z8
t Internal 1 Mbit Flash memory. This is the main Flash memory. It is divided into eight
equal-sized blocks that can be accessed with user-specified addresses.
t Internal secondary 256 Kbit EEPROM memory. It is divided into four equal-sized blocks
that can be accessed with user-specified addresses. This secondary memory brings the ability to execute code and update the main Flash concurrently.
t 16 Kbit scratchpad SRAM. The SRAM's contents can be protected from a power failure
by connecting an external battery.
t Optional 64 byte One Time Programmable (OTP) memory that can be used for product
configuration and calibration.
t General purpose PLD (GPLD) with 19 outputs. The GPLD may be used to implement
external chip selects or combinatorial logic function.
t Decode PLD (DPLD) that decodes address for selection of internal memory blocks. t 27 individually configurable I/O port pins that can be used for the following functions: * MCU I/Os * PLD I/Os * Latched MCU address output * Special function I/Os. * 16 of the I/O ports may be configured as open-drain outputs. t Standby current as low as 50 A for 5 V devices, 25 A for 3 V devices. t Built-in JTAG compliant serial port allows full-chip In-System Programmability (ISP).
With it, you can program a blank device or reprogram a device in the factory or the field.
t Internal page register that can be used to expand the microcontroller address space by
a factor of 256.
t Internal programmable Power Management Unit (PMU) that supports a low power mode
called Power Down Mode. The PMU can automatically detect a lack of microcontroller activity and put the PSD913F1 into Power Down Mode.
t Erase/Write cycles:
* Flash memory - 100,000 minimum * EEPROM - 10,000 minimum * PLD - 1,000 minimum * Data Retention: 15 year minimum at 90 degrees Celsius (for Main Flash, Boot, PLD
and Configuration bits).
3
4 PSD913F1
ADDRESS/DATA/CONTROL BUS PAGE REGISTER EMBEDDED ALGORITHM 8 SECTORS POWER MANGMT UNIT 1 OR 2 MBIT MAIN FLASH MEMORY SECTOR SELECTS FLASH DECODE PLD (DPLD) 57 SECTOR SELECTS SRAM SELECT 16 KBIT BATTERY BACKUP SRAM
PLD INPUT BUS
Figure 1. PSD913F1 Block Diagram
VSTDBY (PC2)
CNTL0, CNTL1, CNTL2 256 KBIT SECONDARY EEPROM MEMORY (BOOT OR DATA) 4 SECTORS
PROG. MCU BUS INTRF.
PROG. PORT PORT A
PA0 - PA7
AD0 - AD15
CSIOP RUNTIME CONTROL AND I/O REGISTERS
ADIO PORT 57 GPLD OUTPUT FLASH ISP PLD (GPLD)
PROG. PORT PORT B
PB0 - PB7
GPLD OUTPUT
GPLD OUTPUT PROG. PORT I/O PORT PLD INPUT PORT C
PC0 - PC7
GLOBAL CONFIG. & SECURITY
PROG. PORT PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT D
PD0 - PD2
Preliminary
Preliminary
PSD913F1 The PSD913F1 series architecture allows In-System Programming of all Memory, PLD Logic and Device Configuration.The devices eliminate the need for discrete `glue' logic, and allow the development of entire systems using only a few highly integrated devices.
3.0 General Information
4.0 PSD913F1 Family
All PSD913F1 devices provide these base features: 1 Mbit main Flash Memory, JTAG port, GPLD, DPLD, power management, and 27 I/O pins. The PSD913F1 also adds 64 bytes of OTP memory for any use (product serial number, calibration constants, etc.). Once written, the OTP memory can never be altered. The following table summarizes the PSD913F1:
Table 1. PSD913F1 Product Matrix
Part # PSD913F1 Family PSD913F1 PSD913F1V I/O Pins 27 27 No. of GPLD Output 19 19 Serial ISP JTAG/ISC Port Yes Yes Flash Main Memory Kbit (8 Sectors) 1024 1024 Additional Memory for Boot and/or Data (4 Sectors) 256 Kbit EEPROM 256 Kbit EEPROM
Device PSD913F1 PSD913F1V
SRAM Kbit 16 16
Turbo Mode Yes Yes
Supply Voltage 5V 3V
5
PSD913F1
Preliminary PSD913F1 devices contain several major functional blocks. Figure 1 on page 3 shows the architecture of the PSD913F1 device. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable.
5.0 PSD913F1 Architectural Overview
5.1 Memory
The PSD913F1 contains the following memories: * A 1 Mbit Flash * A secondary 256 Kbit EEPROM memory * A 16 Kbit SRAM. Each of the memories is briefly discussed in the following paragraphs. A more detailed discussion can be found in section 9. The 1 Mbit Flash is the main memory of the PSD913F1. It is divided into eight equally-sized sectors that are individually selectable. The 256 Kbit EEPROM or Flash is divided into four equally-sized sectors. Each sector is individually selectable. The 16 Kbit SRAM is intended for use as a scratchpad memory or as an extension to the microcontroller SRAM. If an external battery is connected to the PSD913F1's Vstby pin, data will be retained in the event of a power failure. Each block of memory can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time.
5.2 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to 256 times.The paged address can be used as part of the address space to access external memory and peripherals or internal memory and I/O. The Page Register can also be used to change the address mapping of blocks of Flash memory into different memory spaces for in-circuit reprogramming.
5.3 PLDs
The device contains two combinatorial PLD blocks, each optimized for a different function, as shown in Table 2. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The Decode PLD (DPLD) is used to decode addresses and generate chip selects for the PSD913F1 internal memory and registers. The general purpose PLD (GPLD) can implement user-defined external chip selects and logic functions. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of Product Terms. The PLDs consume minimal power by using Zero-Power design techniques. The speed and power consumption of the PLD is controlled by the Turbo Bit (ZPSD only) in the PMMR0 register and other bits in the PMMR2 registers. These registers are set by the microcontroller at runtime. There is a slight penalty to PLD propagation time when invoking the ZPSD features.
Table 2. PLD I/O Table Name
Decode PLD General Purpose PLD
Abbreviation
DPLD GPLD
Inputs
57 57
Outputs
15 19
Product Terms
39 114
6
Preliminary
PSD913F1
PSD913F1 Architectural Overview
(cont.)
5.4 I/O Ports
The PSD913F1 has 27 I/O pins divided among four ports (Port A, B, C, and D). Each I/O pin can be individually configured for different functions. Ports A, B, C and D can be configured as standard MCU I/O ports, PLD I/O, or latched address outputs for microcontrollers using multiplexed address/data busses. The JTAG pins can be enabled on Port C for In-System Programming (ISP). Port A can also be configured as a data port for a non-multiplexed bus.
5.5 Microcontroller Bus Interface
The PSD913F1 easily interfaces with most 8-bit microcontrollers that have either multiplexed or non-multiplexed address/data busses. The device is configured to respond to the microcontroller's control signals, which are also used as inputs to the PLDs. Section 9.3.5 contains microcontroller interface examples.
5.6 JTAG Port
In-System Programming can be performed through the JTAG pins on Port C. This serial interface allows complete programming of the entire PSD913F1 device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) are enabled on Port C when selected or when a device is blank. Table 3 indicates the JTAG signals pin assignments.
Table 3. JTAG Signals on Port C Port C Pins
PC0 PC1 PC3 PC4 PC5 PC6
JTAG Signal
TMS TCK TSTAT TERR TDI TDO
7
PSD913F1
Preliminary
PSD913F1 Architectural Overview
(cont.)
5.7 In-System Programming
Using the JTAG signals on Port C, the entire PSD913F1 device can be programmed or erased without the use of the microcontroller. The main Flash memory can also be programmed in-system by the microcontroller executing the programming algorithms out of the EEPROM or SRAM. The EEPROM can be programmed the same way by executing out of the main Flash memory. The PLD logic or other PSD913F1 configuration can be programmed through the JTAG port or a device programmer. Table 4 indicates which programming methods can program different functional blocks of the PSD913F1.
Table 4. Methods of Programming Different Functional Blocks of the PSD913F1 Functional Block
Main Flash memory EEPROM memory PLD Array (DPLD and GPLD) PSD Configuration Optional OTP Row
JTAG Programming
Yes Yes Yes Yes No
Device Programmer
Yes Yes Yes Yes Yes
In-System Parallel Programming
Yes Yes No No Yes
5.8 Power Management Unit
The Power Management Unit (PMU) in the PSD913F1 gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power Down unit (APD) that will turn off device functions due to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce power consumption. The PSD913F1 also has some bits that are configured at run-time by the MCU to reduce power consumption of the GPLD. The turbo bit in the PMMR0 register can be turned off and the GPLD will latch its outputs and go to sleep until the next transition on its inputs. Additionally, bits in the PMMR2 register can be set by the MCU to block signals from entering the GPLD to reduce power consumption. See section 9.5.
8
Preliminary
PSD913F1 The PSD913F1 is supported by PSDsoft a Windows-based (95, 98, NT) software development tool. A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Definition Language (HDL) equations (unless desired) to define PSD pin functions and memory map information. The general design flow is shown in Figure 2 below. PSDsoft is available from our web site (www.psdst.com) or other distribution channels. PSDsoft directly supports two low cost device programmers from ST, PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local rep/distributor, or directly from our web site using a credit card. The PSD913F1 is also supported by third party device programmers, see web site for current list.
6.0 Development System
Figure 2. PSDsoft Development Tool
Choose MCU and PSD
Automatically configures MCU bus interface and other PSD attributes.
Define PSD Pin and Node Functions
Point and click definition of PSD pin functions, internal nodes, and MCU system memory map.
C Code Generation
Generate C Code specific to PSD functions.
Merge MCU Firmware with PSD Configuration
A composite object file is created containing MCU firmware and PSD configuration.
MCU Firmware Hex or S-Record Format
User's choice of Microcontroller Compiler/Linker
*.OBJ File
ST PSD Programmer
PSDPro or FlashLINK (JTAG)
*.OBJ file available for 3rd party programmers. (conventional or JTAG-ISC)
9
PSD913F1
Preliminary The following table describes the pin names and pin functions of the PSD913F1. Pins that have multiple names and/or functions are defined using PSDsoft.
7.0 Table 5. PSD913F1 Pin Descriptions
Pin Name
ADIO0-7
Pin* Type (PLCC)
30-37 I/O
Description
This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD[0:7] to this port. 2. If your MCU does not have a multiplexed address/data bus, or you are using an 80C251 in page mode, connect A[0:7] to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect A[8:15] to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A[8:15] to this port. 3. If you are using an 80C251 in page mode, connect AD[8:15] to this port. 4. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the read signal is active and one of the PSD functional blocks was selected. The addresses on this port are passed to the PLDs. The following control signals can be connected to this port, based on your MCU: 1. WR -- active-low write input. 2. R_W -- active-high read/active low write input. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. The following control signals can be connected to this port, based on your MCU: 1. RD -- active-low read input. 2. E -- E clock input. 3. DS -- active-low data strobe input. 4. PSEN -- connect PSEN to this port when it is being used as an active-low read signal. For example, when the 80C251 outputs more than 16 address bits, PSEN is actually the read signal. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations.
ADIO8-15
39-46
I/O
CNTL0
47
I
CNTL1
50
I
10
Preliminary
PSD913F1
Table 5. PSD913F1 Pin Descriptions
(cont.)
Pin Name Pin* Type (PLCC)
CNTL2 49 I
Description
This pin can be used to input the PSEN (Program Select Enable) signal from any MCU that uses this signal for code exclusively. If your MCU does not output a Program Select Enable signal, this port can be used as a generic input. This port is connected to the PLDs. Active low reset input. Resets I/O Ports and some of the configuration registers. Must be active at power up. These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. General purpose PLD outputs. 3. Inputs to the PLDs. 4. Latched address outputs (see Table 6). 5. Address inputs. For example, PA0-3 could be used for A[0:3] when using an 80C51XA in burst mode. 6. As the data bus inputs D[0:7] for non-multiplexed address/data bus MCUs. 7. D0/A16-D3/A19 in M37702M2 mode. Note: PA0-3 can only output CMOS signals with an option for high slew rate. However, PA4-7 can be configured as CMOS or Open Drain Outputs. These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. General purpose PLD outputs. 3. Inputs to the PLDs. 4. Latched address outputs (see Table 6). Note: PB0-3 can only output CMOS signals with an option for high slew rate. However, PB4-7 can be configured as CMOS or Open Drain Outputs. PC0 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. TMS Input for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output. PC1 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. TCK Input for the JTAG Interface. This pin can be configured as a CMOS or Open Drain output.
Reset PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7
48 29 28 27 25 24 23 22 21
I I/O
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
7 6 5 4 3 2 52 51
I/O
PC0
20
I/O
PC1
19
I/O
11
PSD913F1
Preliminary
Table 5. PSD913F1 Pin Descriptions
(cont.)
Pin Name Pin* Type (PLCC)
PC2 18 I/O
Description
PC2 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. Vstby -- SRAM standby voltage input for SRAM battery backup. This pin can be configured as a CMOS or Open Drain output. PC3 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. TSTAT output for the JTAG interface. 4. Rdy/Bsy output for in-system parallel programming. This pin can be configured as a CMOS or Open Drain output. PC4 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. TERR output for the JTAG interface. 4. Vbaton -- battery backup indicator output. Goes high when power is being drawn from an external battery. This pin can be configured as a CMOS or Open Drain output. PC5 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. TDI input for the JTAG interface. This pin can be configured as a CMOS or Open Drain output. PC6 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. TDO output for the JTAG interface. This pin can be configured as a CMOS or Open Drain output.
PC3
17
I/O
PC4
14
I/O
PC5
13
I/O
PC6
12
I/O
12
Preliminary
PSD913F1
Table 5. PSD913F1 Pin Descriptions
(cont.)
Pin Name
PC7
Pin* Type (PLCC)
11 I/O
Description
PC7 pin of Port C. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. DBE -- active-low Data Byte Enable input from 68HC912 type MCUs. This pin can be configured as a CMOS or Open Drain output. PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input latches address output from the MCU. 2. MCU I/O -- write or read from a standard output or input port. 3. Input to the PLDs. 4. General purpose PLD output. PD1 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. General purpose PLD output. 4. CLKIN -- clock input to the automatic power-down unit's power-down counter, and the PLD AND array. PD2 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O -- write to or read from a standard output or input port. 2. Input to the PLDs. 3. General purpose PLD output. 4. CSI -- chip select input. When low, the MCU can access the PSD memory and I/O. When high, the PSD memory blocks are disabled to conserve power. Power pins Ground pins
PD0
10
I/O
PD1
9
I/O
PD2
8
I/O
VCC GND
15, 38 1,16,26
**The pin numbers in this table are for the PLCC package only. See the package information section for pin
numbers on other package types.
Table 6. I/O Port Latched Address Output Assignments* Microcontroller
8051XA (8-bit) 80C251 (page mode) All other 8-bit multiplexed 8-bit non-multiplexed bus
Port A Port A (3:0) Port A (7:4)
N/A N/A Address [3:0] N/A Address [7:4] N/A Address [7:4] N/A
Port B Port B (3:0) Port B (7:4)
Address [11:8] N/A Address [11:8] Address [15:12] Address [3:0] Address [3:0] Address [7:4] Address [7:4]
N/A = Not Applicable **Refer to the I/O Port Section on how to enable the Latched Address Output function.
13
PSD913F1
Preliminary Table 7 shows the offset addresses to the PSD913F1 registers relative to the CSIOP base address. The CSIOP space is the 256 bytes of address that is allocated by the user to the internal PSD913F1 registers. Table 7 provides brief descriptions of the registers in CSIOP space. For a more detailed description, refer to section 9.
8.0 PSD913F1 Register Description and Address Offset
Table 7. Register Address Offset Register Name Port A Port B Port C Port D Other*
Data In Control Data Out 00 02 04 01 03 05 12 13 10 11
Description
Reads Port pin as input, MCU I/O input mode Selects mode between MCU I/O or Address Out Stores data for output to Port pins, MCU I/O output mode Configures Port pin as input or output Configures Port pins as either CMOS or Open Drain on some pins, while selecting high slew rate on other pins.
Direction
06
07
14
15
Drive Select
08
09
16
17
Flash Protection PSD/EE Protection PMMR0 PMMR2 Page VM
C0 C2
Read only - Flash Sector Protection Read only - PSD Security and EEPROM Sector Protection Power Management Register 0 Power Management Register 2 Page Register Places PSD memory areas in Program and/or Data space on an individual basis.
B0 B4 E0 E2
*Other registers that are not part of the I/O ports.
14
Preliminary
PSD913F1 As shown in Figure 1, the PSD913F1 consists of six major types of functional blocks:
9.0 The PSD913F1 Functional Blocks
t t t t t t
Memory Blocks PLD Blocks Bus Interface I/O Ports Power Management Unit JTAG Interface
The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable.
9.1 Memory Blocks
The PSD913F1 has the following memory blocks: * The main Flash memory * Secondary EEPROM memory * SRAM. The memory select signals for these blocks originate from the Decode PLD (DPLD) and are user-defined in PSDsoft. Table 8 summarizes the PSD913F1 memory blocks.
Table 8. Memory Blocks Device
PSD913F1
Main Flash
128KB
EEPROM
32KB
SRAM
2KB
9.1.1 Main Flash and Secondary EEPROM The 1 Mbit main Flash memory block is divided evenly into eight 16 Kbyte sectors. The EEPROM memory is divided into four sectors of eight Kbytes each. Each sector of either memory can be separately protected from program and erase operations. Flash memory may be erased on a sector-by-sector basis and programmed byte-by-byte. Flash sector erasure may be suspended while data is read from other sectors of memory and then resumed after reading. EEPROM may be programmed byte-by-byte or sector-by-sector, and erasing is automatic and transparent. The integrity of the data can be secured with the help of Software Data Protection (SDP). Any write operation to the EEPROM is inhibited during the first five milliseconds following power-up. During a program or erase of Flash, or during a write of the EEPROM, the status can be output on the Rdy/Bsy pin of Port C3. This pin is set up using PSDsoft.
15
PSD913F1
Preliminary 9.1.1.1 Memory Block Selects The decode PLD in the PSD913F1 generates the chip selects for all the internal memory blocks (refer to the PLD section). Each of the eight Flash memory sectors have a Flash Select signal (FS0-FS7) which can contain up to three product terms. Each of the four EEPROM memory sectors have a Select signal (EES0-3 or CSBOOT0-3) which can contain up to three product terms. Having three product terms for each sector select signal allows a given sector to be mapped in different areas of system memory. When using a microcontroller with separate Program and Data space, these flexible select signals allow dynamic re-mapping of sectors from one space to the other when used with the VM registers (See Section 9.1.3.1). 9.1.1.2 The Ready/Busy Pin (PC3) Pin PC3 can be used to output the Ready/Busy status of the PSD913F1. The output on the pin will be a `0' (Busy) when Flash or EEPROM memory blocks are being written to, or when the Flash memory block is being erased. The output will be a `1' (Ready) when no write or erase operation is in progress. 9.1.1.3 Memory Operation The main Flash and EEPROM memory are addressed through the microcontroller interface on the PSD913F1 device. The microcontroller can access these memories in one of two ways:
The PSD913F1 Functional Blocks
(cont.)
t The microcontroller can execute a typical bus write or read operation just as it would
if accessing a RAM or ROM device using standard bus cycles.
t The microcontroller can execute a specific instruction that consists of several write
and read operations. This involves writing specific data patterns to special addresses within the Flash or EEPROM to invoke an embedded algorithm. These instructions are summarized in Table 9. Typically, Flash memory can be read by the microcontroller using read operations, just as it would read a ROM device. However, Flash memory can only be erased and programmed with specific instructions. For example, the microcontroller cannot write a single byte directly to Flash memory as one would write a byte to RAM. To program a byte into Flash memory, the microcontroller must execute a program instruction sequence, then test the status of the programming event. This status test is achieved by a read operation or polling the Rdy/Busy pin (PC3). The Flash memory can also be read by using special instructions to retrieve particular Flash device information (sector protect status and ID). The EEPROM is a bit different. Data can be written to EEPROM memory using write operations, like writing to a RAM device, but the status of each write event must be checked by the microcontroller. A write event can be one to 64 contiguous bytes. The status test is very similar to that used for Flash memory (read operation or Rdy/Busy). Optionally, the EEPROM memory may be put into a Software Data Protect (SDP) mode where it requires instructions, rather than operations, to alter its contents. SDP mode makes writing to EEPROM much like writing to Flash memory.
16
Preliminary
PSD913F1 9.1.1.3.1 Instructions An instruction is defined as a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard write operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out value. Some instructions are structured to include read operations after the initial write operations. The sequencing of any instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory will reset the device logic into a read array mode (Flash memory reads like a ROM device). An invalid combination or time-out while addressing the EEPROM block will cause the offending byte to be interpreted as a single operation. The PSD913F1 supports these instructions (see Table 9): Flash memory: t Erase memory by chip or sector t Suspend or resume sector erase t Program a byte t Reset to read array mode t Read Flash Identifier value t Read sector protection status EEPROM: t Write data to OTP Row t Read data from OTP Row t Power down memory t Enable Software Data Protect (SDP) t Disable SDP t Return from read OTP Row read mode or power down mode. These instructions are detailed in Table 9. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by a command byte or confirmation byte. The coded cycles consist of writing the data AAh to address X555h during the first cycle and data 55h to address XAAAh during the second cycle. Address lines A15-A12 are don't cares during the instruction write cycles. However, the appropriate sector select signal (FSi or EESi) must be selected.
The PSD913F1 Functional Blocks
(cont.)
17
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Table 9. Instructions
EEPROM Sector Select (EESi) Flash Sector Select (FSi)
(Note 2)
Instruction
Read Flash Identifier (Note 3, 5) Read OTP Row (Note 4) Read Sector Protection Status (Notes 3, 5) Program a Flash Byte (Note 5) Erase one Flash Sector (Note 5) Erase the whole Flash (Note 5) Suspend Sector Erase (Note 5) Resume Sector Erase (Note 5) EEPROM Power Down (Note 4) SDP Enable/ EEPROM Write (Note 4) SDP Disable (Note 4) Write in OTP Row (Notes 4, 6) Return (from OTP Read or EEPROM Power-Down) (Note 4) Reset (Notes 3, 5) Reset (short instruction) (Note 5)
Cycle 1 Cycle 2 Cycle 3
AAh 55h 90h @X555h @XAAAh @X555h
Cycle 4
Read identifier with (A6,A1,A0 at 0,0,1) Read byte 1 Read identifier with (A6,A1,A0 at 0,1,0) Data @ address AAh @X555h
Cycle5
Cycle 6
Cycle 7
0
1
1
0
AAh 55h 90h @X555h @XAAAh @X555h
Read byte 2
Read byte N
0
1
AAh 55h 90h @X555h @XAAAh @X555h
0
1
AAh 55h A0h @X555h @XAAAh @X555h AAh 55h 80h @X555h @XAAAh @X555h
0
1
55h @XAAAh
30h @ Sector address 10h @X555h
30h @ Sector address(1)
0
1
AAh 55h 80h @X555h @XAAAh @X555h B0h @ any address 30h @ any address AAh 55h 30h @X555h @XAAAh @X555h AAh 55h A0h @X555h @XAAAh @X555h AAh 55h 80h @X555h @XAAAh @X555h AAh 55h B0h @X555h @XAAAh @X555h F0h @ any address AAh 55h @X555h @XAAAh F0h @ any address F0h @ any address
AAh @X555h
55h @XAAAh
0
1
0
1
1 1
0 0
Write byte 1 AAh @X555h Write byte 1
Write byte 2 55h @XAAAh Write byte 2 20h @X555h
Write byte N
1 1
0 0
Write byte N
1
0
0
1
0
1
NOTES: 1. Additional sectors to be erased must be entered within 80 s. A Sector Address is any address within the Sector. 2. Flash and EEPROM Sector Selects are active high. Addresses A15-A12 are don't cares in Instruction Bus Cycles. 3. The Reset instruction is required to return to the normal read array mode if DQ5 goes high or after reading the Flash Identifier or Protection status. 4. The MCU cannot invoke these instructions while executing code from EEPROM. The MCU must be operating from some other memory when these instructions are performed. 5. The MCU cannot invoke these instructions while executing code from the same Flash memory for which the instruction is intended. The MCU must operate from some other memory when these instructions are executed. 6. Writing to OTP Row is allowed only when SDP mode is disabled.
18
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.1.1.4 Power Down Instruction and Power Up Condition
9.1.1.4.1 EEPROM Power Down Instruction The EEPROM can enter power down mode with the help of the EEPROM power down instruction (see Table 9). Once the EEPROM power down instruction is decoded, the EEPROM memory cannot be accessed unless a Return instruction (also in Table 9) is decoded. Alternately, this power down mode will automatically occur when the APD circuit is triggered (see section 9.5.1). Therefore, this instruction is not required if the APD circuit is used. 9.1.1.4.2 Power-Up Condition The PSD913F1 Flash memory is reset upon power-up to the read array mode. Any write operation to the EEPROM is inhibited during the first 5 msec following power-up. The FSi and EESi select signals, along with the write strobe signal, must be in the false state during power-up for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. Any write cycle initiation is locked when VCC is below VLKO.
9.1.1.5 Read
Under typical conditions, the microcontroller may read the Flash or EEPROM memory using read operations just as it would a ROM or RAM device. Alternately, the microcontoller may use read operations to obtain status information about a program or erase operation in progress. Lastly, the microcontroller may use instructions to read special data from these memories. The following sections describe these read functions. 9.1.1.5.1 Read the Contents of Memory Main Flash is placed in the read array mode after power-up, chip reset, or a Reset Flash instruction (see Table 9). The microcontroller can read the memory contents of main Flash or EEPROM by using read operations any time the read operation is not part of an instruction sequence. 9.1.1.5.2 Read the Main Flash Memory Identifier The main Flash memory identifier is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 9). During the read operation, address bits A6, A1, and A0 must be 0,0,1, respectively, and the appropriate sector select signal (FSi) must be active. The Flash ID is E3h for the PSD913F1. The MCU can read the ID only when it is executing from the EEPROM. 9.1.1.5.3 Read the Main Flash Memory Sector Protection Status The main Flash memory sector protection status is read with an instruction composed of 4 operations: 3 specific write operations and a read operation (see Table 9). During the read operation, address bits A6, A1, and A0 must be 0,1,0, respectively, while the chip select FSi designates the Flash sector whose protection has to be verified. The read operation will produce 01h if the Flash sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (main Flash or EEPROM) can be read by the microcontroller accessing the Flash Protection and PSD/EE Protection registers in PSD I/O space. See section 9.1.1.9.1 for register definitions.
19
PSD913F1
Preliminary 9.1.1.5.4 Read the OTP Row There are 64 bytes of One-Time-Programmable (OTP) memory that reside in EEPROM. These 64 bytes are in addition to the 32 Kbytes of EEPROM memory. A read of the OTP row is done with an instruction composed of at least 4 operations: 3 specific write operations and one to 64 read operations (see Table 9). During the read operation(s), address bit A6 must be zero, while address bits A5-A0 define the OTP Row byte to be read while any EEPROM sector select signal (EESi) is active. After reading the last byte, an EEPROM Return instruction must be executed (see Table 9). 9.1.1.5.5 Read the Erase/Program Status Bits The PSD913F1 provides several status bits to be used by the microcontroller to confirm the completion of an erase or programming instruction of Flash memory. Bits are also available to show the status of writes to EEPROM. These status bits minimize the time that the microcontroller spends performing these tasks and are defined in Table 10. The status bits can be read as many times as needed.
The PSD913F1 Functional Blocks
(cont.)
Table 10. Status Bit
FSi/ CSBOOTi
Flash VIH VIL
EESi
VIL VIH
DQ7
DQ6
DQ5
DQ4
X
DQ3
Erase Timeout X
DQ2
X
DQ1
X
DQ0
X
Data Toggle Error Polling Flag Flag Data Toggle Polling Flag
EEPROM
X
X
X
X
X
NOTES: 1. X = Not guaranteed value, can be read either 1 or 0. 2. DQ7-DQ0 represent the Data Bus bits, D7-D0. 3. FSi and EESi are active high.
For Flash memory, the microcontroller can perform a read operation to obtain these status bits while an erase or program instruction is being executed by the embedded algorithm. See section 9.1.1.7 for details. For EEPROM not in SDP mode, the microcontroller can perform a read operation to obtain these status bits just after a data write operation. The microcontroller may write one to 64 bytes before reading the status bits. See section 9.1.1.6 for details. For EEPROM in SDP mode, the microcontroller will perform a read operation to obtain these status bits while an SDP write instruction is being executed by the embedded algorithm. See section 9.1.1.1.3 for details.
20
Preliminary
PSD913F1 9.1.1.5.6 Data Polling Flag DQ7 When Erasing or Programming the Flash memory (or when Writing into the EEPROM memory), bit DQ7 outputs the complement of the bit being entered for Programming/Writing on DQ7. Once the Program instruction or the Write operation is completed, the true logic value is read on DQ7 (in a Read operation). Flash memory specific features:
The PSD913F1 Functional Blocks
(cont.)
t Data Polling is effective after the fourth Write pulse (for programming) or after the t t t
sixth Write pulse (for Erase). It must be performed at the address being programmed or at an address within the Flash sector being erased. During an Erase instruction, DQ7 outputs a `0'. After completion of the instruction, DQ7 will output the last bit programmed (it is a `1' after erasing). If the byte to be programmed is in a protected Flash sector, the instruction is ignored. If all the Flash sectors to be erased are protected, DQ7 will be set to `0' for about 100 s, and then return to the previous addressed byte. No erasure will be performed.
9.1.1.5.7 Toggle Flag DQ6 The PSD913F1 offers another way for determining when the EEPROM write or the Flash memory Program instruction is completed. During the internal Write operation and when either the FSi or EESi is true, the DQ6 will toggle from `0' to `1' and `1' to `0' on subsequent attempts to read any byte of the memory. When the internal cycle is complete, the toggling will stop and the data read on the Data Bus D0-7 is the addressed memory byte. The device is now accessible for a new Read or Write operation. The operation is finished when two successive reads yield the same output data. Flash memory specific features:
t The Toggle bit is effective after the fourth Write pulse (for programming) or after the t t
sixth Write pulse (for Erase). If the byte to be programmed belongs to a protected Flash sector, the instruction is ignored. If all the Flash sectors selected for erasure are protected, DQ6 will toggle to `0' for about 100 s and then return to the previous addressed byte.
9.1.1.5.8 Error Flag DQ5 During a correct Program or Erase, the Error bit will set to `0'. This bit is set to `1' when there is a failure during Flash byte programming, Sector erase, or Bulk Erase. In the case of Flash programming, the Error Bit indicates the attempt to program a Flash bit(s) from the programmed state (0) to the erased state (1), which is not a valid operation. The Error bit may also indicate a timeout condition while attempting to program a byte. In case of an error in Flash sector erase or byte program, the Flash sector in which the error occurred or to which the programmed byte belongs must no longer be used. Other Flash sectors may still be used. The Error bit resets after the Reset instruction. 9.1.1.5.9 Erase Time-out Flag DQ3 (Flash Memory only) The Erase Timer bit reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase timer bit is set to `0' after a Sector Erase instruction for a time period of 100 s + 20% unless an additional Sector Erase instruction is decoded. After this time period or when the additional Sector Erase instruction is decoded, DQ3 is set to `1'.
21
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
9.1.1.6 Writing to the EEPROM
Data may be written a byte at a time to the EEPROM using simple write operations, much like writing to an SRAM. Unlike SRAM though, the completion of each byte write must be checked before the next byte is written. To speed up this process, the PSD913F1 offers a Page write feature to allow writing of several bytes before checking status. To prevent inadvertent writes to EEPROM, the PSD913F1 offers a Software Data Protect (SDP) mode. Once enabled, SDP forces the MCU to "unlock" the EEPROM before altering its contents, much like Flash memory programming. 9.1.1.6.1 Write a Byte to EEPROM A write operation is initiated when an EEPROM select signal (EESi) is true and the write strobe signal (wr) into the PSD913F1 is true. If the PSD913F1 detects no additional writes within 120 sec, an internal storage operation is initiated. Internal storage to EEPROM memory technology typically takes a few milliseconds to complete. The status of the write operation is obtained by the MCU reading the Data Polling or Toggle bits (as detailed in section 9.1.1.5), or the Ready/Busy output pin (section 9.1.1.2). Keep in mind that the MCU does not need to erase a location in EEPROM before writing it. Erasure is performed automatically as an internal process. 9.1.1.6.2 Write a Page to EEPROM Writing data to EEPROM using page mode is more efficient than writing one byte at a time. The PSD913F1 EEPROM has a 64 byte volatile buffer that the MCU may fill before an internal EEPROM storage operation is initiated. Page mode timing approaches a 64:1 advantage over the time it takes to write individual bytes. To invoke page mode, the MCU must write to EEPROM locations within a single page, with no more than 120 sec between individual byte writes. A single page means that address lines A14 to A6 must remain constant. The MCU may write to the 64 locations on a page in any order, which is determined by address lines A5 to A0. As soon as 120 sec have expired after the last page write, the internal EEPROM storage process begins and the MCU checks programming status. Status is checked the same way it is for byte writes, described above. Note: be aware that if the upper address bits (A14 to A6) change during page write operations, loss of data may occur. Ensure that all bytes for a given page have been successfully stored in the EEPROM before proceeding to the next page. Correct management of MCU interrupts during EEPROM page write operations is essential. 9.1.1.6.3 EEPROM Software Data Protect (SDP) The SDP feature is useful for protecting the contents of EEPROM from inadvertent write cycles that may occur during uncontrolled MCU bus conditions. These may happen if the application software gets lost or when VCC is not within normal operating range. Instructions from the MCU are used to enable and disable SDP mode (see Table 9). Once enabled, the MCU must write an instruction sequence to EEPROM before writing data (much like writing to Flash memory). SDP mode can be used for both byte and page writes to EEPROM. The device will remain in SDP mode until the MCU issues a valid SDP disable instruction. PSD913F1 devices are shipped with SDP mode disabled. However, within PSDsoft, SDP mode may be enabled as part of programming the device with a device programmer (PSDpro).
22
Preliminary
PSD913F1 9.1.1.6.3 EEPROM Software Data Protect (SDP) (cont.) To enable SDP mode at run time, the MCU must write three specific data bytes at three specific memory locations, as shown in Figure 3. Any further writes to EEPROM when SDP is set will require this same sequence, followed by the byte(s) to write. The first SDP enable sequence can be followed directly by the byte(s) to be written. To disable SDP mode, the MCU must write specific bytes to six specific locations, as shown in Figure 4. The MCU must not be executing code from EEPROM when these instructions are invoked. The MCU must be operating from some other memory when enabling or disabling SDP mode. The state of SDP mode is not changed by power on/off sequences (nonvolatile). When either the SDP enable or SDP disable instructions are issued from the MCU, the MCU must use the Toggle bit (status bit DQ6) or the Ready/Busy output pin to check programming status. The Ready/Busy output is driven low from the first write of AAh @ 555h until the completion of the internal storage sequence. Data Polling (status bit DQ7) is not supported when issuing the SDP enable or SDP disable commands. Note: Using the SDP sequence (enabling, disabling, or writing data) is initiated when specific bytes are written to addresses on specific "pages" of EEPROM memory, with no more than 120 sec between writes. The addresses 555h and AAAh are located on different pages of EEPROM. This is how the PSD913F1 distinguishes these instruction sequences from ordinary writes to EEPROM, which are expected to be within a single EEPROM page.
The PSD913F1 Functional Blocks
(cont.)
Figure 3. EEPROM SDP Enable Flowcharts
SDP Set WRITE AAh to Address 555h
SDP not Set
WRITE AAh to Address 555h
Page Write Instruction
WRITE 55h to Address AAAh Page Write Instruction WRITE A0h to Address 555h
WRITE 55h to Address AAAh
WRITE A0h to Address 555h WRITE is enabled
SDP is set
WRITE Data to be Written in any Address
SDP ENABLE ALGORITHM Write in Memory
Write Data + SDP Set after tWC (Write Cycle Time)
23
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Figure 4. Software Data Protection Disable Flow Chart
WRITE AAh to Address 555h
WRITE 55h to Address AAAh
WRITE 80h to Address 555h Page Write Instruction WRITE AAh to Address 555h
WRITE 55h to Address AAAh
WRITE 20h to Address 555h
Unprotected State after tWC (Write Cycle time)
9.1.1.6.4 Write OTP Row Writing to the OTP row (64 bytes) can only be done once per byte, and is enabled by an instruction. This instruction is composed of three specific Write operations of data bytes at three specific memory locations followed by the data to be stored in the OTP row (refer to Table 9). During the write operations, address bit A6 must be zero, while address bits A5-A0 define the OTP Row byte to be written while any EEPROM Sector Select signal (EESi) is active. Writing the OTP Row is allowed only when SDP mode is not enabled.
9.1.1.7 Programming Flash Memory
Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector, but not byte-by-byte. A byte of Flash memory erases to all logic ones (FF hex), and its bits are programmed to logic zeros. Although erasing Flash memory occurs on a sector basis, programming Flash memory occurs on a byte basis. The PSD913F1 main Flash and optional boot Flash require the MCU to send an instruction to program a byte or perform an erase function (see Table 9). This differs from EEPROM, which can be programmed with simple MCU bus write operations (unless EEPROM SDP mode is enabled). Once the MCU issues a Flash memory program or erase instruction, it must check for the status of completion. The embedded algorithms that are invoked inside the PSD913F1 support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or the Ready/Busy output pin.
24
Preliminary
PSD913F1 9.1.1.7.1 Data Polling Polling on DQ7 is a method of checking whether a Program or Erase instruction is in progress or has completed. Figure 5 shows the Data Polling algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD913F1 begins. The MCU then reads the location of the byte to be programmed in Flash to check status. Data bit DQ7 of this location becomes the compliment of data bit 7of the original data byte to be programmed. The MCU continues to poll this location, comparing DQ7 and monitoring the Error bit on DQ5. When the DQ7 matches data bit 7 of the original data, and the Error bit at DQ5 remains `0', then the embedded algorithm is complete. If the Error bit at DQ5 is `1', the MCU should test DQ7 again since DQ7 may have changed simultaneously with DQ5 (see Figure 5). The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte or if the MCU attempted to program a `1' to a bit that was not erased (not erased is logic `0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to Flash with the byte that was intended to be written. When using the Data Polling method after an erase instruction, Figure 5 still applies. However, DQ7 will be `0' until the erase operation is complete. A `1' on DQ5 will indicate a timeout failure of the erase operation, a `0' indicates no error. The MCU can read any location within the sector being erased to get DQ7 and DQ5. PSDsoft will generate ANSI C code functions which implement these Data Polling algorithms.
The PSD913F1 Functional Blocks
(cont.)
Figure 5. Data Polling Flow Chart
START
READ DQ5 & DQ7 at VALID ADDRESS
DQ7 = DATA7 NO NO
YES
DQ5 =1 YES READ DQ7
DQ7 = DATA NO FAIL
YES
PASS
25
PSD913F1
Preliminary 9.1.1.7.2 Data Toggle Checking the Data Toggle bit on DQ6 is a method of determining whether a Program or Erase instruction is in progress or has completed. Figure 6 shows the Data Toggle algorithm. When the MCU issues a programming instruction, the embedded algorithm within the PSD913F1 begins. The MCU then reads the location of the byte to be programmed in Flash to check status. Data bit DQ6 of this location will toggle each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking DQ6 and monitoring the Error bit on DQ5. When DQ6 stops toggling (two consecutive reads yield the same value), and the Error bit on DQ5 remains `0', then the embedded algorithm is complete. If the Error bit on DQ5 is `1', the MCU should test DQ6 again, since DQ6 may have changed simultaneously with DQ5 (see Figure 6). The Error bit at DQ5 will be set if either an internal timeout occurred while the embedded algorithm attempted to program the byte, or if the MCU attempted to program a `1' to a bit that was not erased (not erased is logic `0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed to compare the byte that was written to Flash with the byte that was intended to be written. When using the Data Toggle method after an erase instructin, Figure 6 still applies. DQ6 will toggle until the erase operation is complete. A `1' on DQ5 will indicate a timeout failure of the erase operation, a `0' indicates no error. The MCU can read any location within the sector being erased to get DQ6 and DQ5. PSDsoft will generate ANSI C code functions which implement these Data Toggling algorithms.
The PSD913F1 Functional Blocks
(cont.)
Figure 6. Data Toggle Flow Chart
START
READ DQ5 & DQ6
DQ6 = TOGGLE
NO
YES NO DQ5 =1 YES READ DQ6
DQ6 = TOGGLE YES FAIL
NO
PASS
26
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.1.1.8 Erasing Flash Memory
9.1.1.8.1. Flash Bulk Erase Instruction The Flash Bulk Erase instruction uses six write operations followed by a Read operation of the status register, as described in Table 9. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the Read Flash memory status. During a Bulk Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.7. The Error bit (DQ5) returns a `1' if there has been an Erase Failure (maximum number of erase cycles have been executed). It is not necessary to program the array with 00h because the PSD913F1 will automatically do this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory will not accept any instructions. 9.1.1.8.2 Flash Sector Erase Instruction The Sector Erase instruction uses six write operations, as described in Table 9. Additional Flash Sector Erase confirm commands and Flash sector addresses can be written subsequently to erase other Flash sectors in parallel, without further coded cycles, if the additional instruction is transmitted in a shorter time than the timeout period of about 100 s. The input of a new Sector Erase instruction will restart the time-out period. The status of the internal timer can be monitored through the level of DQ3 (Erase time-out bit). If DQ3 is `0', the Sector Erase instruction has been received and the timeout is counting. If DQ3 is `1', the timeout has expired and the PSD913F1 is busy erasing the Flash sector(s). Before and during Erase timeout, any instruction other than Erase suspend and Erase Resume will abort the instruction and reset the device to Read Array mode. It is not necessary to program the Flash sector with 00h as the PSD913F1 will do this automatically before erasing (byte=FFh). During a Sector Erase, the memory status may be checked by reading status bits DQ5, DQ6, and DQ7, as detailed in section 9.1.1.7. During execution of the erase instruction, the Flash block logic accepts only Reset and Erase Suspend instructions. Erasure of one Flash sector may be suspended, in order to read data from another Flash sector, and then resumed. 9.1.1.8.3 Flash Erase Suspend Instruction When a Flash Sector Erase operation is in progress, the Erase Suspend instruction will suspend the operation by writing 0B0h to any address when an appropriate Chip Select (FSi) is true. (See Table 9). This allows reading of data from another Flash sector after the Erase operation has been suspended. Erase suspend is accepted only during the Flash Sector Erase instruction execution and defaults to read array mode. An Erase Suspend instruction executed during an Erase timeout will, in addition to suspending the erase, terminate the time out. The Toggle Bit DQ6 stops toggling when the PSD913F1 internal logic is suspended. The toggle Bit status must be monitored at an address within the Flash sector being erased. The Toggle Bit will stop toggling between 0.1 s and 15 s after the Erase Suspend instruction has been executed. The PSD913F1 will then automatically be set to Read Flash Block Memory Array mode. If an Erase Suspend instruction was executed, the following rules apply: * Attempting to read from a Flash sector that was being erased will output invalid data. * Reading from a Flash sector that was not being erased is valid. * The Flash memory cannot be programmed, and will only respond to Erase Resume and Reset instructions (read is an operation and is OK). * If a Reset instruction is received, data in the Flash sector that was being erased will be invalid. 27
PSD913F1
Preliminary 9.1.1.8.4 Flash Erase Resume Instruction If an Erase Suspend instruction was previously executed, the erase operation may be resumed by this instruction. The Erase Resume instruction consists of writing 030h to any address while an appropriate Chip Select (FSi) is true. (See Table 9.)
The PSD913F1 Functional Blocks
(cont.)
9.1.1.9 Flash and EEPROM Memory Specific Features
9.1.1.9.1 Flash and EEPROM Sector Protect Each Flash and EEPROM sector can be separately protected against Program and Erase functions. Sector Protection provides additional data security because it disables all program or erase operations. This mode can be activated through the JTAG Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft Configuration program. This will automatically protect selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash and EEPROM sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The microcontroller can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash or EEPROM sector will be ignored by the device. The Verify operation will result in a read of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash protection and PSD/EE protection registers (CSIOP). See Table 11.
Table 11. Sector Protection/Security Bit Definition
Flash Protection Register Bit 7
Sec7_Prot
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Sec6_Prot Sec5_Prot Sec4_Prot
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit Definitions: Sec_Prot Sec_Prot Bit 7
Security_ Bit
1 = Flash is write protected. 0 = Flash is not write protected. Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PSD/EE Protection Register
*
*
*
Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
*:
Not used.
Bit Definitions: Sec_Prot Sec_Prot Security_Bit
1 = EEPROM Boot Sector is write protected. 0 = EEPROM Boot Sector is not write protected. 0 = Security Bit in device has not been set. 1 = Security Bit in device has been set.
9.1.1.9.2 Reset Instruction The Reset instruction resets the internal memory logic state machine in a few milliseconds. Reset is an instruction of either one write operation or three write operations (refer to Table 9).
28
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.1.2 SRAM
The SRAM is a 16 Kbit (2K x 8) memory. The SRAM is enabled when RS0-- the SRAM chip select output from the DPLD-- is high. RS0 can contain up to two product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Vstby pin (PC2). If you have an external battery connected to the PSD913F1, the contents of the SRAM will be retained in the event of a power loss. The contents of the SRAM will be retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the battery voltage, an internal power switchover to the battery occurs. Pin PC4 can be configured as an output that indicates when power is being drawn from the external battery. This Vbaton signal will be high with the supply voltage falls below the battery voltage and the battery on PC2 is supplying power to the internal SRAM. The chip select signal (RS0) for the SRAM, Vstby, and Vbaton are all configured using PSDsoft.
9.1.3 Memory Select Signals
The main Flash (FSi), EEPROM (EESi), and SRAM (RS0) memory select signals are all outputs of the DPLD. They are setup by entering equations for them in PSDsoft. The following rules apply to the equations for the internal chip select signals: 1. Flash memory and EEPROM memory sector select signals must not be larger than the physical sector size. 2. Any main Flash memory sector must not be mapped in the same memory space as another Flash sector. 3. An EEPROM memory sector must not be mapped in the same memory space as another EEPROM sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. An EEPROM memory sector may overlap a main Flash memory sector. In case of overlap, priority will be given to the EEPROM. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority will be given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, EES0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 will always access the SRAM. Any address in the range of EES0 greater than 87FFh (and less than 9FFFh) will automatically address EEPROM memory segment 0. Any address greater than 9FFFh will access the Flash memory segment 0. You can see that half of the Flash memory segment 0 and one-fourth of EEPROM segment 0 can not be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 7 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level one has the highest priority and level 3 has the lowest.
29
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Figure 7. Priority Level of Memory and I/O Components
Highest Priority
Level 1 SRAM, I /O
Level 2 EEPROM Memory Level 3 Flash Memory Lowest Priority
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces The 8031 and compatible family of microcontrollers, which includes the 80C51, 80C151, 80C251, 80C51XA, and the C500 family, have separate address spaces for code memory (selected using PSEN) and data memory (selected using RD). Any of the memories within the PSD913F1 can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the PSD's CSIOP space. The VM register is set using PSDsoft to have an initial value. It can subsequently be changed by the microcontroller so that memory mapping can be changed on-the-fly. For example, I may wish to have SRAM and Flash in Data Space at boot, and EEPROM in Program Space at boot, and later swap EEPROM and Flash. This is easily done with the VM register by using PSDsoft to configure it for boot up and having the microcontroller change it when desired. Table 12 describes the VM Register.
Table 12. VM Register Bit 7* Bit 6* Bit 5* * * *
Bit 4 Bit 3 FL_Data EE_Data
0 = RD can't access Flash 1 = RD access Flash 0 = RD can't access EEPROM 1 = RD access EEPROM
Bit 2 FL_Code
0 = PSEN can't access Flash
Bit 1 Bit 0 EE_Code SRAM_Code
0 = PSEN can't access EEPROM 0 = PSEN can't access SRAM 1 = PSEN access SRAM
*
*
*
1 = PSEN 1 = PSEN access access Flash EEPROM
NOTE: Bits 5-7 are not used, should set to "0".
30
Preliminary
PSD913F1 9.1.3.2 Configuration Modes for MCUs with Separate Program and Data Spaces 9.1.3.2.1 Separate Space Modes Code memory space is separated from data memory space. For example, the PSEN signal is used to access the program code from the Flash Memory, while the RD signal is used to access data from the EEPROM, SRAM and I/O Ports. This configuration requires the VM register to be set to 0Ch. 9.1.3.2.2 . Combined Space Modes The program and data memory spaces are combined into one space that allows the main Flash Memory, EEPROM, and SRAM to be accessed by either PSEN or RD. For example, to configure the main Flash memory in combined space mode, bits 2 and 4 of the VM register are set to "1". 9.1.3.3 80C31 Memory Map Example See Application Notes for examples.
The PSD913F1 Functional Blocks
(cont.)
Figure 8. 8031 Memory Modes - Separate Space Mode
DPLD
RS0 EES0-3 FS0-7
FLASH
EEPROM
SRAM
CS OE
CS OE
CS OE
PSEN RD
Figure 9. 80C31 Memory Mode - Combined Space Mode
DPLD
RS0 EES0-3 FS0-7
FLASH
EEPROM
SRAM
RD
CS OE
CS OE
CS OE
VM REG BIT 3
VM REG BIT 4
PSEN
VM REG BIT 1
VM REG BIT 2
RD
VM REG BIT 0
31
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a factor of up to 256. The contents of the register can also be read by the microcontroller. The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD and can be included in the Flash Memory, EEPROM, and SRAM chip select equations. If memory paging is not needed, or if not all 8 page register bits are needed for memory paging, then these bits may be used in the PLD for general logic. See Application Note. Figure 10 shows the Page Register. The eight flip flops in the register are connected to the internal data bus D0-D7. The microcontroller can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h.
Figure 10. Page Register
RESET
D0 D1 D0 - D7 D2 D3 D4 D5 D6 R/W D7
Q0 Q1 Q2 Q3 Q4 Q5
PGR0 PGR1 PGR2 PGR3 PGR4 PGR5 PGR6 DPLD AND GPLD
INTERNAL SELECTS AND LOGIC
Q6 PGR7 Q7
PAGE REGISTER
FLASH PLD
32
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD913F1. After specifying the chip selects or logic equations for the PLDs in PSDsoft, the logic is programmed into the device and available upon power-up. The PSD913F1 contains two PLDs: the Decode PLD (DPLD), and the General Purpose PLD (GPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in sections 9.2.1 and 9.2.2. Figure 11 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O port selects. The GPLD can be used to generate external chip selects, control signals or logic functions. The GPLD has 19 outputs that are connected to Ports A, B and D. The AND array is used to form product terms. These product terms are specified using PSsoft. An Input Bus consisting of 57 signals is connected to the PLDs. The signals are shown in Table 13. The complement of the 57 signals are also available as input to the AND array.
Table 13. DPLD and GPLD Inputs Input Source
MCU Address Bus MCU Control Signals Reset Power Down Port A Input Port B Input Port C Input Port D Inputs Page Register Flash Programming Status Bit
NOTE: The address inputs are A[19:4] in 80C51XA mode.
Input Name
A[15:0]* CNTL[2:0] RST PDN PA[7-0] PB[7-0] PC[7-0] PD[2:0] PGR(7:0) Rdy/Bsy
Number of Signals
16 3 1 1 8 8 8 3 8 1
The Turbo Bit
The PLDs in the PSD913F1 can minimize power consumption by switching off when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turbo-off mode increases propagation delays while reducing power consumption. Refer to the Power Management Unit section on how to set the Turbo Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations.
33
PSD913F1
Preliminary
Figure 11. PLD Block Diagrams
8 DATA BUS
PAGE REGISTER
DECODE PLD
57
8 4 1 1
FLASH MEMORY SELECTS EEPROM SELECTS SRAM SELECT CSIOP SELECT
PLD INPUT BUS
GENERAL PURPOSE PLD GPLD
57 PLD OUT 8
PORT A
PLD OUT 8
PORT B
PLD OUT 3
PORT D
PORT C PLD INPUT PORT A PLD INPUT PORT B PLD INPUT PORT D PLD INPUT 8
PORT C
8 8 3
Figure 12. DPLD Logic Array
3 3 3 3 3 3 (INPUTS) I /O PORTS (PORT A,B,C) PGR0 - PGR7 A[15:0] * PD[2:0] (ALE,CLKIN,CSI) PDN (APD OUTPUT) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) RESET RD_BSY (24) 3 (8) 3 (16) 3 (3) 3 (1) 3 (3) (1) 2 (1) CSIOP RS0 SRAM SELECT I/O DECODER SELECT FS7 8 FLASH MEMORY SECTOR SELECTS 3 EES 0 EES 1 EES 2 EES 3
4 EEPROM SECTOR SELECTS
FS0
*NOTE: The address inputs are A[19:4] in 80C51XA mode. 34
Preliminary
PSD913F1 Each of the two PLDs has unique characteristics suited for its applications They are described in the following sections. 9.2.1 Decode PLD (DPLD) The DPLD, shown in Figure 12, is used for decoding the address for internal PSD components. The DPLD can generate the following chip selects:
The PSD913F1 Functional Blocks
(cont.)
* * * *
8 sector selects for the main Flash memory (three product terms each) 4 sector selects for the Secondary Flash memory (three product terms each) 1 internal SRAM select (two product terms) 1 internal CSIOP select (select PSD registers, one product term)
Inputs to the DPLD chip selects may include address inputs, Page Register inputs and other user defined external inputs from Ports A, B, C or D. 9.2.2 General Purpose PLD (GPLD) The General Purpose PLD implements user defined system combinatorial logic function or chip selects for external devices. Figure 13 shows how the GPLD is connected to the I/O Ports. The GPLD has 19 outputs and each are routed to a port pin. The port pin can also be configured as input tot eh GPLD. When it is not used as GPLD output or input, the pin can be configured to perform other I/O functions. The GPLD outputs are identical except in the number of available product terms for logic implementation. Select the pin that can best meet the product term requirement of your logic function or chip selects. The outputs can be configured as active high or low outputs. Table 14 shows the number of product terms that are assigned to the PLD outputs on the I/O Ports. When PSD913F1 is connected to a MCU with non-multiplexed bus, Port A will be configured as the Data Port and the GPLD outputs will not be available.
Table 14. GPLD Output Product Term GPLD Output on Port Pin
Port A, pins PA0-3 Port A, pins PA4-7 Port B, pins PB0-3 Port B, pins PB4-7 Port D, pins PD0-2
Number of Product Terms
3 9 4 7 1
35
36 PSD913F1
I/O PORT REPRESENTS A SINGLE PIN FROM EACH I /O PORT PLD OUTPUT
GENERAL PURPOSE PLD (GPLD)
AND ARRAY
PORT A
PRODUCT TERMS *
*Pin PA0-3 has 3 PT
POLARITY SELECT OTHER I/O FUNCTIONS
MUX
Pin PA4-7 has 9 PT
PLD INPUT
AND ARRAY
PLD OUTPUT
PRODUCT TERMS *
Figure 13. The General Purpose PLD and I/O Port
PORT B
*Pin PB0-3 has 4 PT
POLARITY SELECT
MUX
PLD INPUT BUS OTHER I/O FUNCTIONS PLD INPUT PLD OUTPUT POLARITY SELECT OTHER I/O FUNCTIONS PLD INPUT
Pin PB4-7 has 7 PT
AND ARRAY
PRODUCT TERM *
PORT D
*Pin PD0-2 has 1 PT
MUX
Preliminary
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.3 Microcontroller Bus Interface
The "no-glue logic" PSD913F1 Microcontroller Bus Interface can be directly connected to most popular microcontrollers and their control signals. Key 8-bit microcontrollers with their bus types and control signals are shown in Table 15. The interface type is specified using the PSDsoft.
Table 15. Microcontrollers and their Control Signals
MCU 8031/8051 80C51XA 80C251 80C251 80198 68HC11 68HC05C0 68HC912 Z80 Z8 68330 M37702M2 Data Bus Width 8 8 8 8 8 8 8 8 8 8 8 8 CNTL0 WR WR WR WR WR R/W WR R/W WR R/W R/W R/W CNTL1 RD RD PSEN RD RD E RD E RD DS DS E CNTL2 PSEN PSEN PC7 PD0** ALE ALE ALE ALE ALE AS AS AS ADIO0 A0 A4 A0 A0 A0 A0 A0 A0 A0 A0 A0 A0 PA3-PA0 PA7-PA4
*
PSEN
* * * * * * * *
* * * * * * *
DBE
*
A3-A0
* * * * * *
D3-D0
* * * * * * * *
D7-D4
* * * *
*
AS AS ALE
* *
D3-D0
* *
D7-D4
**Unused CNTL2 pin can be configured as PLD input. Other unused pins (PC7, PD0, PA3-0) can be **configured for other I/O functions. **ALE/AS input is optional for microcontrollers with a non-multiplexed bus 9.3.1. PSD913F1 Interface to a Multiplexed 8-Bit Bus Figure 14 shows an example of a system using a microcontroller with an 8-bit multiplexed bus and a PSD913F1. The ADIO port on the PSD913F1 is connected directly to the microcontroller address/data bus. ALE latches the address lines internally. Latched addresses can be brought out to Port A or B. The PSD913F1 drives the ADIO data bus only when one of its internal resources is accessed and the RD input is active. Should the system address bus exceed sixteen bits, Ports A, B, C, or D may be used as additional address inputs. 9.3.2. PSD913F1 Interface to a Non-Multiplexed 8-Bit Bus Figure 15 shows an example of a system using a microcontroller with an 8-bit non-multiplexed bus and a PSD913F1. The address bus is connected to the ADIO Port, and the data bus is connected to Port A. Port A is in tri-state mode when the PSD913F1 is not accessed by the microcontroller. Should the system address bus exceed sixteen bits, Ports B, C, or D may be used for additional address inputs.
37
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Figure 14. An Example of a Typical 8-Bit Multiplexed Bus Interface
PSD913F1
MICROCONTROLLER
AD [ 7:0] ADIO PORT PORT A A [ 7: 0] (OPTIONAL)
A[ 15:8]
PORT B WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST ALE ALE (PD0) PORT D RESET
A [ 15: 8] (OPTIONAL)
PORT C
Figure 15. An Example of a Typical 8-Bit Non-Multiplexed Bus Interface
PSD913F1
D [ 7:0]
MICROCONTROLLER
A [ 15:0]
ADIO PORT
PORT A
D [ 7:0]
PORT B WR RD BHE WR (CNTRL0) RD (CNTRL1) BHE (CNTRL2) RST
A[ 23:16] (OPTIONAL)
PORT C
ALE
ALE (PD0) PORT D
RESET
38
Preliminary
PSD913F1 9.3.3 Microcontroller Interface Examples Figures 16 through 20 show examples of the basic connections between the PSD913F1 and some popular microcontrollers. The PSD913F1 Control input pins are labeled as to the microcontroller function for which they are configured. The MCU interface is specified using the PSDsoft. 9.3.3.1 80C31 Figure 16 shows the interface to the 80C31, which has an 8-bit multiplexed address/data bus. The lower address byte is multiplexed with the data bus. The microcontroller control signals PSEN, RD, and WR may be used for accessing the internal memory components and I/O Ports. The ALE input (pin PD0) latches the address. 9.3.3.2 80C251 The Intel 80C251 microcontroller features a user-configurable bus interface with four possible bus configurations, as shown in Table 16. Configuration 1 is 80C31 compatible, and the bus interface to the PSD913F1 is identical to that shown in Figure 16. Configurations 2 and 3 have the same bus connection as shown in Figure 17. There is only one read input (PSEN) connected to the Cntl1 pin on the PSD913F1. The A16 connection to the PA0 pin allows for a larger address input to the PSD913F1. Configuration 4 is shown in Figure 18. The RD signal is connected to Cntl1 and the PSEN signal is connected to the CNTL2. The 80C251 has two major operating modes: Page Mode and Non-Page Mode. In Non-Page Mode, the data is multiplexed with the lower address byte, and ALE is active in every bus cycle. In Page Mode, data D[7:0] is multiplexed with address A[15:8]. In a bus cycle where there is a Page hit, the ALE signal is not active and only addresses A[7:0] are changing. The PSD913F1 supports both modes. In Page Mode, the PSD bus timing is identical to Non-Page Mode except the address hold time and setup time with respect to ALE is not required. The PSD access time is measured from address A[7:0] valid to data in valid.
The PSD913F1 Functional Blocks
(cont.)
39
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Table 16. 80C251 Configurations Configuration 80C251 Read/Write Pins
WR RD PSEN WR PSEN only WR PSEN only WR RD PSEN
Connecting to PSD913F1 Pins
CNTL0 CNTL1 CNTL2 CNTL0 CNTL1 CNTL0 CNTL1 CNTL0 CNTL1 CNTL2
Page Mode
1
Non-Page Mode, 80C31 compatible A[7:0] multiplex with D[7:0} Non-Page Mode A[7:0] multiplex with D[7:0} Page Mode A[15:8] multiplex with D[7:0} Page Mode A[15:8] multiplex with D[7:0}
2 3 4
9.3.3.3 80C51XA The Philips 80C51XA microcontroller family supports an 8- or 16-bit multiplexed bus that can have burst cycles. Address bits A[3:0] are not multiplexed, while A[19:4] are multiplexed with data bits D[15:0] in 16-bit mode. In 8-bit mode, A[11:4] are multiplexed with data bits D[7:0]. The 80C51XA can be configured to operate in eight-bit data mode. (shown in Figure 19). The 80C51XA improves bus throughput and performance by executing Burst cycles for code fetches. In Burst Mode, address A19-4 are latched internally by the PSD913F1, while the 80C51XA changes the A3-0 lines to fetch up to 16 bytes of code. The PSD access time is then measured from address A3-A0 valid to data in valid. The PSD bus timing requirement in Burst Mode is identical to the normal bus cycle, except the address setup and hold time with respect to ALE does not apply. 9.3.3.4 68HC11 Figure 20 shows an interface to a 68HC11 where the PSD913F1 is configured in 8-bit multiplexed mode with E and R/W settings. The DPLD can generate the READ and WR signals for external devices.
40
Preliminary
PSD913F1
Figure 16. Interfacing the PSD913F1 with an 80C31
AD [ 7:0] AD[ 7:0 ]
80C31
31 19 18 9 12 13 14 15 1 2 3 4 5 6 7 8 EA/VP X1 X2 RESET INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 16 29 30 11 10 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 RD WR PSEN ALE AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 31 32 33 34 35 36 37
PSD913F1
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21
RESET
39 40 41 42 43 44 45 46
ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11
47 50 49 10 9 8 48
CNTL0 (WR) CNTL1(RD) CNTL2 (PSEN) PD0-ALE PD1 PD2 RESET
RESET RESET
Figure 17. Interfacing the PSD913F1 to the 80C251, with One Read Input
80C251SB
2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17
PSD913F1
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A0 A1 A2 A3 A4 A5 A6 A7 30 31 32 33 34 35 36 37
A17
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RST EA
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
29 A16 28 27 25 24 23 22 21
*
A17
*
AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
39 40 41 42 43 44 45 46 47 50 49
ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL0 ( WR) CNTL1( RD) CNTL 2(PSEN) PD0- ALE PD1 PD2 RESET
7 6 5 4 3 2 52 51
RESET
10
ALE PSEN WR RD/A16
33 32 18 19
ALE RD WR A16
35
10 9 8
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
20 19 18 17 14 13 12 11
RESET
RESET
48
**Connection is optional. **Non-page mode: AD[7:0] - ADIO[7:0].
41
PSD913F1
Preliminary
Figure 18. Interfacing the PSD913F1 to the 80C251, with Read and PSEN Inputs
80C251SB
2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17
PSD913F1
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4 A5 A6 A7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A0 A1 A2 A3 A4 A5 A6 A7 30 31 32 33 34 35 36 37
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 X1 X2 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RST EA
ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7
PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7
29 28 27 25 24 23 22 21
AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15
39 40 41 42 43 44 45 46 47 50 49
ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL0 ( WR) CNTL1( RD) CNTL 2(PSEN) PD0- ALE PD1 PD2 RESET
7 6 5 4 3 2 52 51
RESET
10
ALE PSEN WR RD/A16
33 32 18 19
ALE RD WR PSEN
35
10 9 8
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
20 19 18 17 14 13 12 11
RESET
RESET
48
Figure 19. Interfacing the PSD913F1 to the 80C51XA, 8-Bit Data Bus
80C51XA
21 20 XTAL1 XTAL2 A0/WRH A1 A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 2 3 4 5 43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 A0 A1 A2 A3 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12 A13 A14 A15 A16 A17 A18 A19 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 30 31 32 33 34 35 36 37
PSD913F1
ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 A0 A1 A2 A3
11 13 6 7
RXD0 TXD0 RXD1 TXD1
9 8 16
T2EX T2 T0
RESET
10 14 15
RST INT0 INT1
A12 A13 A14 A15 A16 A17 A18 A19
39 ADIO8 40 ADIO9 41 ADIO10 42 ADIO11 43 AD1012 44 AD1013 45 ADIO14 46 ADIO15
47 50 35 17 32 19 18 33 PSEN RD WR ALE 49 10 8 9 48
CNTL0 (WR) CNTL1(RD) CNTL 2 (PSEN) PD0-ALE PD1 PD2 RESET
EA/WAIT BUSW
PSEN RD WRL ALE
PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
20 19 18 17 14 13 12 11
RESET
42
Preliminary
PSD913F1
Figure 20. Interfacing the PSD913F1 with a 68HC11
AD[7:0] AD[7:0]
PSD913F1 68HC11
8 7 RESET 17 19 18 2 34 33 32 XT EX RESET IRQ XIRQ MODB PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 31 30 29 28 27 42 41 40 39 38 37 36 35 9 10 11 12 13 14 15 16 20 21 22 23 24 25 3 5 4 6 E AS R/W AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15 30 31 32 33 34 35 36 37 39 40 41 42 43 44 45 46 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 MODA E AS R/W
PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7
43 44 45 46 47 48 49 50 52 51
PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VRH VRL
47 50 49 10 9 8 48
CNTL0 (R _W) CNTL1(E) CNTL 2 PD0 - AS PD1 PD2 RESET
RESET
43
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
9.4 I/O Ports
There are four programmable I/O ports: Ports A, B, C, and D. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the microcontroller writing to on-chip registers in the CSIOP address space. The topics discussed in this section are: * General Port Architecture * Port Operating Modes * Port Configuration Registers * Port Data Registers * Individual Port Functionality. 9.4.1 General Port Architecture The general architecture of the I/O Port is shown in Figure 21. Individual Port architectures are shown in Figures 22 through 24. In general, once the purpose for a port pin has been defined, that pin will no longer be available for other purposes. Exceptions will be noted. As shown in Figure 21, the ports contain an output multiplexer whose selects are driven by the configuration bits in the Control Registers (Ports A and B only) and PSDsoft. Inputs to the multiplexer include the following:
t Output data from the Data Out Register t Latched address outputs t General Purpose PLD (GPLD) outputs (external chip selects)
The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The PDB is connected to the Internal Data Bus for feedback and can be read by the microcontroller. The Data Out, Direction and Control Registers, and port pin input are all connected to the PDB. The contents of these registers can be altered by the microcontroller. The PDB feedback path allows the microcontroller to check the contents of the registers.
44
Preliminary
(cont.)
The PSD913F1 Functional Blocks
Figure 21. General I/O Port Architecture
DATA OUT REG. D WR ADDRESS ALE GPLD OUTPUT D G Q Q
DATA OUT
ADDRESS OUTPUT MUX
PORT PIN
INTERNAL DATA BUS
READ MUX P D B DATA IN OUTPUT SELECT
CONTROL REG. D WR DIR REG. D WR Q PLD-INPUT Q
PSD913F1
45
PSD913F1
Preliminary 9.4.2 Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined in PSDsoft, some by the microcontroller writing to the Control Registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the microcontroller can be done so dynamically at run-time. The PLD I/O, Data Port, and Address Input, are the only modes that must be defined before programming the device. All other modes can be changed by the microcontroller at run-time. Table 17 summarizes which modes are available on each port. Table 20 shows how and where the different modes are configured. Each of the port operating modes are described in the following subsections.
The PSD913F1 Functional Blocks
(cont.)
Table 17. Port Operating Modes Port Mode
MCU I/O PLD Outputs PLD Inputs Address Out Address In Data Port JTAG ISP
Port A
Yes Yes Yes Yes (A7 - 0) Yes Yes (D7 - 0) No
Port B
Yes Yes Yes Yes (A7 - 0) or A15 - 8) Yes No No
Port C
Yes No Yes No Yes No Yes
Port D
Yes Yes Yes No Yes No No
46
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
Table 18. Port Operating Mode Settings
Defined In PSDsoft
Declare pins only Logic or chip select equations Selected for MCU with non-mux bus Declare pins only Declare pins only Declare pins only
Mode
MCU I/O PLD I/O Data Port (Port A) Address Out (Port A,B) Address In (Port A,B,C,D) JTAG ISP *NA = Not Applicable
Control Register Setting at Run-Time
0 NA NA 1 NA NA
Direction Register Setting at Run-Time
1 = output, 0 = input,
NA 1 NA NA
9.4.2.1 MCU I/O Mode In the MCU I/O Mode, the microcontroller uses the PSD913F1 ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD913F1 are mapped into the microcontroller address space. The addresses of the ports are listed in Table 7. A port pin can be put into MCU I/O mode by writing a `0' to the corresponding bit in the Control Register. The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register. See the subsection on the Direction Register in the "Port Registers" section. When the pin is configured as an output, the content of the Data Out Register drives the pin. When configured as an input, the microcontroller can read the port input through the Data In buffer. Ports C and D do not have Control Registers, and are in MCU I/O mode by default. They can be used for PLD I/O if they are specified in PSDsoft. 9.4.2.2 PLD I/O Mode The PLD I/O Mode uses a port as an input to the PLDs, and/or as an output from the GPLD. The corresponding bit in the Direction Register must not be set to `1' if the pin is defined as a PLD input pin in PSDsoft. The PLD I/O Mode is specified in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft.
47
PSD913F1
Preliminary 9.4.2.3 Address Out Mode For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a `1' for pins to use Address Out Mode. This must be done by the MCU at run-time. See Table 19 for the address output pin assignments on Ports A and B for various MCUs. For non-multiplexed 8 bit bus mode, address lines A[7:0] are available to Port B in Address Out Mode. Note: Do not drive address lines with Address Out Mode to an external memory device if it is intended for the MCU to boot from the external device. The MCU must first boot from PSD memory so the Direction and Control register bits can be set.
The PSD913F1 Functional Blocks
(cont.)
Table 19. I/O Port Latched Address Output Assignments Microcontroller
8051XA (8-Bit) 80C251 (Page Mode) All Other 8-Bit Multiplexed
Port A (3:0)
N/A* N/A Address (3:0)
Port A (7:4)
Address (7:4) N/A Address (7:4) N/A
Port B (3:0)
Address (11:8) Address (11:8) Address (3:0) Address [3:0]
Port B (7:4)
N/A Address (15:12) Address (7:4) Address [7:4]
8-Bit N/A Non-Multiplexed Bus
N/A = Not Applicable.
9.4.2.4 Address In Mode For microcontrollers that have more than 16 address lines, the higher addresses can be connected to Port A, B, C, and D. The address input can be latched by the address strobe (ALE/AS). Any input that is included in the DPLD equations for the Main Flash, Secondary Flash, or SRAM is considered to be an address input. 9.4.2.5 Data Port Mode Port A can be used as a data bus port for a microcontroller with a non-multiplexed address/data bus. The Data Port is connected to the data bus of the microcontroller. The general I/O functions are disabled in Port A if the port is configured as a Data Port. 9.4.2.6 JTAG ISP Port C is JTAG compliant, and can be used for In-System Programming (ISP). For more information on the JTAG Port, refer to section 9.6.
48
Preliminary
PSD913F1 9.4.3 Port Configuration Registers (PCRs) Each port has a set of PCRs used for configuration. The contents of the registers can be accessed by the microcontroller through normal read/write bus cycles at the addresses given in Table 7. The addresses in Table 7 are the offsets in hex from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, Bit 0 in a register refers to Bit 0 of its port. The three PCRs, shown in Table 20, are used for setting the port configurations. The default power-up state for each register in Table 20 is 00h.
The PSD913F1 Functional Blocks
(cont.)
Table 20. Port Configuration Registers Register Name
Control Direction Drive Select* *NOTE:
Port
A,B A,B,C,D A,B,C,D
MCU Access
Write/Read Write/Read Write/Read
See Table 27 for Drive Register bit definition.
9.4.3.1 Control Register Any bit set to `0' in the Control Register sets the corresponding Port pin to MCU I/O Mode, and a `1' sets it to Address Out Mode. The default mode is MCU I/O. Only Ports A and B have an associated Control Register. 9.4.3.2 Direction Register The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to `1' in the Direction Register will cause the corresponding pin to be an output, and any bit set to `0' will cause it to be an input. The default mode for all port pins is input. Figures 22 and 23 show the Port Architecture diagrams for Ports A, B and C, respectively. The direction of data flow for Ports A, B, and C are controlled by the direction register. An example of a configuration for a port with the three least significant bits set to output and the remainder set to input is shown in Table 22. Since Port D only contains three pins, the Direction Register for Port D has only the three least significant bits active.
Table 21. Port Pin Direction Control Direction Register Bit Port Pin Mode
0 1 Input Output
Table 22. Port Direction Assignment Example
Bit 7 0 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 1 Bit 1 1 Bit 0 1
49
PSD913F1
Preliminary 9.4.3.3 Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS for some port pins, and controls the slew rate for the other port pins. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a `1'. The default pin drive is CMOS. Aside: the slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise. A pin operates in a high slew rate when the corresponding bit in the Drive Register is set to `1'. The default rate is slow slew. Table 23 shows the Drive Register for Ports A, B, C, and D. It summarizes which pins can be configured as Open Drain outputs and which pins the slew rate can be set for.
The PSD913F1 Functional Blocks
(cont.)
Table 23. Drive Register Pin Assignment
Drive Register Port A Port B Port C Port D Bit 7 Open Drain Open Drain Open Drain NA Bit 6 Open Drain Open Drain Open Drain NA Bit 5 Open Drain Open Drain Open Drain NA Bit 4 Open Drain Open Drain Open Drain NA Bit 3 Slew Rate Slew Rate Open Drain NA Bit 2 Slew Rate Slew Rate Open Drain Slew Rate Bit 1 Slew Rate Slew Rate Open Drain Slew Rate Bit 0 Slew Rate Slew Rate Open Drain Slew Rate
NOTE: NA = Not Applicable.
50
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.4.4 Port Data Registers
The Port Data Registers, shown in Table 24, are used by the microcontroller to write data to or read data from the ports. Table 24 shows the register name, the ports having each register type, and microcontroller access for each register type. The registers are described below. 9.4.4.1 Data In Port pins are connected directly to the Data In buffer. In MCU I/O input mode, the pin input is read through the Data In buffer. 9.4.4.2 Data Out Register Stores output data written by the MCU in the MCU I/O output mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to "1". The contents of the register can also be read back by the microcontroller.
Table 24. Port Data Registers Register Name
Data In Data Out
Port
A,B,C,D A,B,C,D Write/Read
MCU Access
Read - input on pin
9.4.5 Ports A and B - Functionality and Structure
Ports A and B have similar functionality and structure, as shown in Figure 22. The two ports can be configured to perform one or more of the following functions:
t t t t t t
MCU I/O Mode GPLD Output - Combinatorial PLD outputs can be connected to Port A or Port B. PLD Input - Input to the PLDs. Latched Address output - Provide latched address output per Table 19. Address In - Additional high address inputs, may be latched by ALE. Open Drain/Slew Rate - pins PA[3:0] and PB[3:0] can be configured to fast slew rate, pins PA[7:4] and PB[7:4] can be configured to Open Drain Mode.
t Data Port - Port A only, connect to non-multiplexed 8-bit data bus.
51
(cont.)
The PSD913F1 Functional Blocks
INTERNAL DATA BUS
52
DATA OUT REG. D WR ADDRESS ALE D G Q ADDRESS A[ 7:0] OR A[15:8] Q DATA OUT OUTPUT MUX GPLD OUTPUT READ MUX P D B CONTROL REG. D WR DIR REG. D WR PLD INPUT Q Q DATA IN OUTPUT SELECT
PSD913F1
Figure 22. Ports A and B Structure
Preliminary
PORT A OR B PIN
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.4.6 Port C - Functionality and Structure
Port C can be configured to perform one or more of the following functions (see Figure 23):
t t t t
MCU I/O Mode PLD Input - Input to the PLDs. Address In - Additional high address inputs using the Input MicroCells. In-System Programming - JTAG port can be enabled for programming/erase of the PSD913F1 device. (See Section 9.6 for more information on JTAG programming.) Pins that are configured as JTAG pins in PSDsoft will not be available for other I/O functions.
t Open Drain - Port C pins can be configured in Open Drain Mode t Battery Backup features - PC2 can be configured as a Battery Input (Vstby) pin.
PC4 can be configured as a Battery On Indicator output pin, indicating when Vcc is less than Vbat. Port C does not support Address Out mode, and therefore no Control Register is required. Pin PC7 may be configured as the DBE input in certain microcontroller interfaces.
9.4.7 Port D - Functionality and Structure
Port D has three I/O pins. See Figure 24. This port does not support Address Out mode, and therefore no Control Register is required. Port D can be configured to perform one or more of the following functions:
t t t t
MCU I/O Mode GPLD Output - Combinatorial PLD output (external chip selects) PLD Input - direct input to PLDs Slew rate - pins can be set up for fast slew rate
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
t PD0 - ALE, as address strobe input t PD1 - CLKIN, as clock input to the PLD and APD counter t PD2 - CSI, as active low chip select input. A high input will disable the
Flash/SRAM and CSIOP.
53
(cont.)
The PSD913F1 Functional Blocks
INTERNAL DATA BUS
54
DATA OUT REG. D WR PORT C PIN OUTPUT MUX Q DATA OUT SPECIAL FUNCTION* READ MUX P D B DATA IN OUTPUT SELECT DIR REG. D WR PLD- INPUT Q SPECIAL FUNCTION*
PSD913F1
Figure 23. Port C Structure
CONFIGURATION BIT
Preliminary
*JTAG ISP or battery back-up.
Preliminary
(cont.)
The PSD913F1 Functional Blocks
Figure 24. Port D Structure
DATA OUT REG. DATA OUT D WR PORT D PIN OUTPUT MUX GPLD OUTPUT READ MUX Q
INTERNAL DATA BUS
P D B DATA IN
OUTPUT SELECT
DIR REG. D WR Q PLD-INPUT
PSD913F1
55
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
9.5 Power Management
The PSD913F1 offers configurable power saving options. These options may be used individually or in combinations, as follows:
t All memory types in a PSD (Flash, EEPROM, and SRAM) are built with Zero-Power
technology. In addition to using special silicon design methodology, Zero-Power technology puts the memories into standby mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up", changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory standby mode when no inputs are changing--it happens automatically. The PLD sections can also achieve standby mode when its inputs are not changing, see PMMR registers below.
t Like the Zero-Power feature, the Automatic Power Down (APD) logic allows the PSD to
reduce to standby current automatically. The APD will block MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD913F1 devices. The APD unit is described in more detail in section 9.5.1. Built in logic will monitor the address strobe of the MCU for activity. If there is no activity for a certain time period (MCU is asleep), the APD logic initiates Power Down Mode (if enabled). Once in Power Down Mode, all address/data signals are blocked from reaching PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in standby mode even if the address/data lines are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of standby mode, but not the memories.
t The PSD Chip Select Input (CSI) on all families can be used to disable the internal
memories, placing them in standby mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD logic, especially if your MCU has a chip select output. There is a slight penalty in memory access time when the CSI signal makes its initial transition from deselected to selected.
t The PMMR registers can be written by the MCU at run-time to manage power.
PSD913F1 supports "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figures 28 and 28a). Significant power savings can be achieved by blocking signals that are not used in PLD logic equations. The PSD913F1 has a Turbo Bit in the PMMR0 register. This bit can be set to disable the Turbo Mode feature (default is Turbo Mode on). While Turbo Mode is disabled, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo Mode is enabled. When the Turbo Mode is enabled, there is a significant DC current component and the AC component is higher. 9.5.1 Automatic Power Down (APD) Unit and Power Down Mode The APD Unit, shown in Figure 25, puts the PSD into Power Down Mode by monitoring the activity of the address strobe (ALE/AS). If the APD unit is enabled, as soon as activity on the address strobe stops, a four bit counter starts counting. If the address strobe remains inactive for fifteen clock periods of the CLKIN signal, the Power Down (PDN) signal becomes active, and the PSD will enter into Power Down Mode, discussed next.
56
Preliminary
PSD913F1 9.5.1 Automatic Power Down (APD) Unit and Power Down Mode (cont.) Power Down Mode By default, if you enable the PSD APD unit, Power Down Mode is automatically enabled. The device will enter Power Down Mode if the address strobe (ALE/AS) remains inactive for fifteen CLKIN (pin PD1) clock periods. The following should be kept in mind when the PSD is in Power Down Mode:
The PSD913F1 Functional Blocks
(cont.)
* If the address strobe starts pulsing again, the PSD will return to normal operation. * *
The PSD will also return to normal operation if either the CSI input returns low or the Reset input returns high. The MCU address/data bus is blocked from all memories and PLDs. Various signals can be blocked (prior to Power Down Mode) from entering the PLDs by setting the appropriate bits in the PMMR registers. The blocked signals include MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from the PLDs will not block CLKIN from the APD unit. All PSD memories enter Standby Mode and are drawing standby current. However, the PLDs and I/O ports do not go into Standby Mode because you don't want to have to wait for the logic and I/O to "wake-up" before their outputs can change. See table 29 for Power Down Mode effects on PSD ports. Typical standby current is 50 A for 5 V devices, and 25 A for 3 V devices. These standby current values assume that there are no transitions on any PLD input.
*
*
Table 25. Power Down Mode's Effect on Ports Port Function
MCU I/O PLD Out Address Out Data Port Peripheral I/O
Pin Level
No Change No Change Undefined Three-State Three-State
Table 26. PSD913F1 Timing and Standby Current During Power Down Mode
PLD Propagation Delay
Normal tpd (Note 1)
Mode
Power Down
Memory Access Time
No Access
Access Recovery Time to Normal Access
tLVDV
5V VCC, Typical Standby Current
50 A (Note 2)
NOTES: 1. Power Down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo Bit. 2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is off.
HC11 (or compatible) Users Note The HC11 turns off its E clock when it sleeps. Therefore, if you are using an HC11 (or compatible) in your design, and you wish to use the Power Down, you must not connect the E clock to the CLKIN input (PD1). You should instead connect an independent clock signal to the CLKIN input. The clock frequency must be less than 15 times the frequency of AS. The reason for this is that if the frequency is greater than 15 times the frequency of AS, the PSD913F1 will keep going into Power Down Mode.
57
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Figure 25. APD Logic Block
APD EN PMMR0 BIT 1=1 TRANSITION DETECTION ALE CLR PD EEPROM SELECT FLASH SELECT EDGE DETECT PD PLD SRAM SELECT POWER DOWN (PDN) SELECT DISABLE BUS INTERFACE
RESET CSI CLKIN
APD COUNTER
DISABLE FLASH/EEPROM/SRAM
Figure 26. Enable Power Down Flow Chart
RESET
Enable APD Set PMMR0 Bit 1 = 1
OPTIONAL
Disable desired inputs to PLD by setting PMMR0 bits 4 and PMMR2 bits 2 through 6.
No
ALE/AS idle for 15 CLKIN clocks? Yes PSD in Power Down Mode
58
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
Table 27. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0 Bit 7 Bit 6 Bit 5 Bit 4 PLD Array clk 1 = off Bit 3 PLD Turbo 1 = off Bit 2 Bit 1 APD Enable 1 = on Bit 0
*
*
*
*
*
***Bits 0, 2, 6, and 7 are not used, and should be set to 0, bit 5 should be set to 1. ***The PMMR0, and PMMR2 register bits are cleared to zero following power up. ***Subsequent reset pulses will not clear the registers. Bit 1 0 1 Bit 3 0 1 Bit 4 0 Automatic Power Down (APD) is disabled. Automatic Power Down (APD) is enabled. PLD Turbo is on. PLD Turbo is off, saving power. CLKIN input to the PLD AND array is connected. Every CLKIN change will power up the PLD when Turbo bit is off. 1 = CLKIN input to PLD AND array is disconnected, saving power. = = = = =
PMMR2 Bit 7 Bit 6 PLD array DBE 1 = off *Unused bits should be set to 0. Bit 2 0 = Cntl0 input to the PLD AND array is connected. 1 = Cntl0 input to PLD AND array is disconnected, saving power. Bit 3 0 = Cntl1 input to the PLD AND array is connected. 1 = Cntl1 input to PLD AND array is disconnected, saving power. Bit 4 0 = Cntl2 input to the PLD AND array is connected. 1 = Cntl2 input to PLD AND array is disconnected, saving power. Bit 5 0 = ALE input to the PLD AND array is connected. 1 = ALE input to PLD AND array is disconnected, saving power. Bit 6 0 = DBE input to the PLD AND array is connected. 1 = DBE input to PLD AND array is disconnected, saving power. Bit 5 PLD array ALE 1 = off Bit 4 PLD array CNTL2 1 = off Bit 3 PLD array CNTL1 1 = off Bit 2 PLD array CNTL0 1 = off Bit 1 Bit 0
*
*
*
59
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Table 28. APD Counter Operation APD Enable Bit
0 1 1 1
ALE PD Polarity
X X 1 0
ALE Level
X Pulsing 1 0
APD Counter
Not Counting Not Counting Counting (Generates PDN after 15 Clocks) Counting (Generates PDN after 15 Clocks)
9.5.2 Other Power Saving Options
The PSD913F1 offers other reduced power saving options that are independent of the Power Down Mode. Except for the SRAM Standby and CSI input features, they are enabled by setting bits in the PMMR0 and PMMR2 registers. 9.5.2.1 Zero Power PLD The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in the PMMR0. By setting the bit to "1", the Turbo mode is disabled and the PLDs consume Zero Power current when the inputs are not switching for an extended time of 70 ns. The propagation delay time will be increased by 10 ns after the Turbo bit is set to "1" (turned off) when the inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is set to a "0" (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD's D.C. power, AC power, and propagation delay. Note: Blocking MCU control signals with PMMR2 bits can further reduce PLD AC power consumption. 9.5.2.2 SRAM Standby Mode (Battery Backup) The PSD913F1 supports a battery backup operation that retains the contents of the SRAM in the event of a power loss. The SRAM has a Vstby pin (PC2) that can be connected to an external battery. When VCC becomes lower than Vstby then the PSD will automatically connect to Vstby as a power source to the SRAM. The SRAM Standby Current (Istby) is typically 0.5 A. The SRAM data retention voltage is 2 V minimum. The battery-on indicator (Vbaton) can be routed to PC4. This signal indicates when the VCC has dropped below the Vstby voltage. 9.5.2.3 The CSI Input Pin PD2 of Port D can be configured in PSDsoft as the CSI input. When low, the signal selects and enables the internal Flash, EEPROM, SRAM, and I/O for read or write operations involving the PSD913F1. A high on the CSI pin will disable the Flash memory, EEPROM, and SRAM, and reduce the PSD power consumption. However, the PLD and I/O pins remain operational when CSI is high. Note: there may be a timing penalty when using the CSI pin depending on the speed grade of the PSD that you are using. See the timing parameter t SLQV in the AC/DC specs. 9.5.2.4 Input Clock The PSD913F1 provides the option to turn off the CLKIN input to the PLD AND array to save AC power consumption. During Power Down Mode, or, if the CLKIN input is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. The CLKIN will be disconnected from the PLD AND array by setting bits 4 to a "1" in PMMR0. 9.5.2.5 Input Control Signals The PSD913F1 provides the option to turn off the input control signals (CNTL0-2, ALE, and DBE) to the PLD to save AC power consumption. These control signals are inputs to the PLD AND array. During Power Down Mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They will be disconnected from the PLD AND array by setting bits 2, 3, 4, 5, and 6 to a "1" in the PMMR2.
60
Preliminary
PSD913F1
The PSD913F1 Functional Blocks
(cont.)
9.5.3 Reset and Power On Requirement
Power On Reset Upon power up the PSD913F1 requires a reset pulse of tNLNH-PO (minimum 1ms) after VCC is steady. During this time period the device loads internal configurations, clears some of the registers and sets the Flash or EEPROM into operating mode. After the rising edge of reset, the PSD913F1 remains in the reset state for an additional tOPR (minimum 120 ns) nanoseconds before the first memory access is allowed. The PSD913F1 Flash or EEPROM memory is reset to the read array mode upon power up. The FSi and EESi select signals along with the write strobe signal must be in the false state during power-up reset for maximum security of the data contents and to remove the possibility of a byte being written on the first edge of a write strobe signal. The PSD automatically prevents write strobes from reaching the EEPROM memory array for about 5 ms (tEEHWL). Any Flash memory write cycle initiation is prevented automatically when VCC is below VLKO. Warm Reset Once the device is up and running, the device can be reset with a much shorter pulse of tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational after warm reset. Figure 27 shows the timing of the power on and warm reset.
Figure 27. Power On and Warm Reset Timing
OPERATING LEVEL t NLNH - PO VCC t NLNH
RESET t OPR POWER ON RESET WARM RESET t OPR
I/O Pin, Register and PLD Status at Reset Table 29 shows the I/O pin, register and PLD status during power on reset, warm reset and power down mode. PLD outputs are always valid during warm reset, and they are valid in power on reset once the internal PSD configuration bits are loaded. This loading of PSD is completed typically long before the VCC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by the PSDsoft equations.
61
PSD913F1
Preliminary
The PSD913F1 Functional Blocks
(cont.)
Table 29. Status During Power On Reset, Warm Reset and Power Down Mode Port Configuration
MCU I/O PLD Output
Power On Reset
Input Mode Valid after internal PSD configuration bits are loaded Tri-stated Tri-stated
Warm Reset
Input Mode Valid
Power Down Mode
Unchanged Depend on inputs to PLD (address are blocked in PD mode) Not defined Tri-stated
Address Out Data Port
Tri-stated Tri-stated
Register
PMMR0, 2 VM Register*
Power On Reset
Cleared to "0" Initialized based on the selection in PSDsoft Configuration Menu. Cleared to "0"
Warm Reset
Unchanged
Power Down Mode
Unchanged
Initialized based on Unchanged the selection in PSDsoft Configuration Menu. Cleared to "0" Unchanged
All other registers
*SR_cod bit in the VM Register are always cleared to zero on power on or warm reset. **
9.6 Programming In-Circuit using the JTAG Interface
The JTAG interface on the PSD913F1 can be enabled on Port C (see Table 30). All memory (Flash and Secondary Flash Block), PLD logic, and PSD configuration bits may be programmed through the JTAG interface. A blank part can be mounted on a printed circuit board and programmed using JTAG. The standard JTAG signals (IEEE 1149.1) are TMS, TCK, TDI, and TDO. Two additional signals, TSTAT and TERR, are optional JTAG extensions used to speed up program and erase operations. By default, on a blank PSD (as shipped from factory or after erasure), four pins on Port C are enabled for the basic JTAG signals TMS, TCK, TDI, and TDO. See Application Note 54 for more details on JTAG In-System-Programming.
Table 30. JTAG Port Signals Port C Pin
PC0 PC1 PC3 PC4 PC5 PC6
JTAG Signals
TMS TCK TSTAT TERR TDI TDO
Description
Mode Select Clock Status Error Flag Serial Data In Serial Data Out
62
Preliminary
PSD913F1 9.6.1 Standard JTAG Signals The JTAG configuration bit (non-volatile) inside the PSD can be set by the user in the PSDsoft. Once this bit is set and programmed in the PSD, the JTAG pins are dedicated to JTAG at all times and is in compliance with IEEE 1149.1. After power up the standard JTAG signals (TDI, TDO TCK and TMS) are inputs, waiting for a serial command from an external JTAG controller device (such as FlashLink or Automated Test Equipment). When the enabling command is received from the external JTAG controller, TDO becomes an output and the JTAG channel is fully functional inside the PSD. The same command that enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT and TERR. The PSD913F1 supports JTAG In-System-Configuration (ISC) commands, but not Boundary Scan. ST's PSDsoft software tool and FlashLink JTAG programming cable implement these JTAG-ISC commands. 9.6.2 JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed programming and erase functions by indicating status on PSD pins instead of having to scan the status out serially using the standard JTAG channel. See Application Note 54. TERR will indicate if an error has occurred when erasing a sector or programming a byte in Flash memory. This signal will go low (active) when an error condition occurs, and stay low until a special JTAG command is executed or a chip reset pulse is received after an "ISC-DISABLE" command. TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will be high when the PSD913F1 device is in read array mode (Flash memory and Boot Block contents can be read). TSTAT will be low when Flash memory programming or erase cycles are in progress, and also when data is being written to the Secondary Flash Block. TSTAT and TERR can be configured as open-drain type signals with a JTAG command. 9.6.3 Security and Flash Memories Protection When the security bit is set, the device cannot be read on a device programmer or through the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed. All other program/erase/verify commands are blocked. Full chip erase returns the part to a non-secured blank state. The Security Bit can be set in PSDsoft. All Flash Memory and EEPROM sectors can individually be sector protected against erasures. The sector protect bits can be set in PSDsoft.
The PSD913F1 Functional Blocks
(cont.)
63
PSD913F1
Preliminary
Absolute Maximum Ratings
Symbol
TSTG
Parameter
Storage Temperature Operating Temperature Voltage on any Pin
Condition
PLDCC Commercial Industrial With Respect to GND With Respect to GND With Respect to GND
Min
- 65 0 - 40 - 0.6 - 0.6 - 0.6
Max
+ 125 + 70 + 85 +7 + 14 +7
Unit
C C C V V V V
VPP VCC
Device Programmer Supply Voltage Supply Voltage ESD Protection
>2000
NOTE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not recommended. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability.
Operating Range
Range
Commercial Industrial Commercial Industrial
Temperature
0 C to +70C -40 C to +85C 0 C to +70C -40 C to +85C
VCC Tolerance
+ 5 V 10% + 5 V 10% 3 V to 3.6 V 3 V to 3.6 V
Recommended Operating Conditions
Symbol
VCC VCC
Parameter
Supply Voltage Supply Voltage
Condition
All Speeds V-Versions All Speeds
Min
4.5 3.0
Typ
5
Max
5.5 3.6
Unit
V V
64
Preliminary
PSD913F1 The following tables describe the AD/DC parameters of the PSD913F1 family:
AC/DC Parameters
t DC Electrical Specification t AC Timing Specification
* PLD Timing *
- Combinatorial Timing Microcontroller Timing - Read Timing - Write Timing - Power Down and Reset Timing
Following are issues concerning the parameters presented:
t In the DC specification the supply current is given for different modes of operation.
Before calculating the total power consumption, determine the percentage of time that the PSD913F1 is in each mode. Also, the supply power is considerably different if the Turbo bit is "OFF".
t The AC power component gives the PLD, Flash memory, EEPROM, and SRAM
mA/MHz specification. Figure 28 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used.
t In the PLD timing parameters, add the required delay when Turbo bit is "OFF". Figure 28. PLD ICC /FrequencyConsumption (VCC = 5 V 10%)
110 100 90 80 ICC - (mA) 70 60 50 40 30 20 10 0 0 5 10 15 20 25 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
TU O RB OF F
TU R B O O FF
N OO URB T (25% )
VCC = 5V
00 N (1 %)
B TUR
OO
PT 100% PT 25%
65
PSD913F1
Preliminary
AC/DC Parameters
(cont.)
Figure 28a. PLD ICC /Frequency Consumption (PSD913F1V Versions, VCC = 3 V)
60 VCC = 3V 50 ICC - (mA) 40
TU
ON ( RBO
100%
)
30
FF
TU
RB
20 10 0 0
O TURB
O
O
ON (2
5%)
TU
RB
5
O
O
FF
PT 100% PT 25%
10
15
20
25
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
Example of PSD913F1 Typical Power Calculation at VCC = 5.0 V Conditions
Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = = = = = = = = = = 8 MHz 4 MHz 80% 15% 5% (no additional power above base) 10% 90% 45 PT 45/153 = 29.4% ON
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x 2 mA/MHz x Freq PLD + #PT x 400 A/PT = 50 A x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz +2 mA/MHz x 8 MHz + 45 x 0.4 mA/PT) = 45 A + 0.1 x (8 + 0.9 + 16 + 18 mA) = 45 A + 0.1 x 42.9 = 45 A + 4.29 mA = 4.34 mA This is the operating power with no Flash writes or erases. Calculation is based on IOUT = 0 mA. 66
Preliminary
PSD913F1
AC/DC Parameters
(cont.)
Example of Typical Power Calculation at VCC = 5.0 V in Turbo Off Mode Conditions
Highest Composite PLD input frequency (Freq PLD) = MCU ALE frequency (Freq ALE) % Flash Access % SRAM access % I/O access Operational Modes % Normal % Power Down Mode Number of product terms used (from fitter report) % of total product terms Turbo Mode = = = = = = = = = 8 MHz 4 MHz 80% 15% 5% (no additional power above base) 10% 90% 45 PT 45/153 = 29.4% Off
Calculation (typical numbers used)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 2.5 mA/MHz x Freq ALE + %SRAM x 1.5 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 A x 0.90 + 0.1 x (0.8 x 2.5 mA/MHz x 4 MHz + 0.15 x 1.5 mA/MHz x 4 MHz + 24 mA) = 45 A + 0.1 x (8 + 0.9 + 24) = 45 A + 0.1 x 32.9 = 45 A + 3.29 mA = 3.34 mA This is the operating power with no Flash writes or erases. Calculation is based on IOUT = 0 mA.
67
PSD913F1
Preliminary (5 V 10% Versions)
PSD913F1 DC Characteristics
Symbol
VCC VIH VIL VIH1 VIL1 VHYS VLKO VOL
Parameter
Supply Voltage High Level Input Voltage Low Level Input Voltage Reset High Level Input Voltage Reset Low Level Input Voltage Reset Pin Hysteresis VCC Min for Flash Erase and Program Output Low Voltage
Conditions
All Speeds 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V (Note 1) (Note 1)
Min
4.5 2 -.5 .8 VCC -.5 0.3 2.5
Typ
5
Max
5.5 VCC +.5 0.8 VCC +.5 .2 VCC -.1 4.2
Unit
V V V V V V V V V V V V
IOL = 20 A, VCC = 4.5 V IOL = 8 mA, VCC = 4.5 V
0.01 0.25 4.4 2.4 VSBY - 0.8 2.0 4.49 3.9
0.1 0.45
VOH VOH1 VSBY ISBY IIDLE VDF ISB ILI ILO
Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Standby Voltage SRAM Standby Current (VSTBY Pin) Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current for Power Down Mode Input Leakage Current Output Leakage Current
IOH = -20 A, VCC = 4.5 V IOH = -2 mA, VCC = 4.5 V IOH1 = 1 A VCC = 0 V VCC > VSBY Only on VSTBY CSI > VCC -0.3 V (Notes 2 and 3) VSS < VIN < VCC 0.45 < VIN < VCC ZPLD_TURBO = OFF, f = 0 MHz (Note 5)
VCC 0.5 1 0.1
V A A V
-0.1 2 50 -1 -10 .1 5 0 400
200 1 10
A A A mA
ZPLD Only ICC (DC) (Note 5) Operating Supply Current Flash or EEPROM SRAM ZPLD AC Adder ICC (AC) (Note 5) FLASH or EEPROM AC Adder SRAM AC Adder
NOTE: 1. 2. 3. 4. 5.
ZPLD_TURBO = ON, f = 0 MHz During Flash or EEPROM, Write/Erase Only Read Only, f = 0 MHz f = 0 MHz Fig.28 (Note 4)
700
A/PT
15 0 0
30 0 0
mA mA mA
2.5 1.5
3.5 3.0
mA/MHz mA/MHz
Reset input has hysteresis. VIL1 is valid at or below .2VCC -.1. VIH1 is valid at or above .8VCC. CSI deselected or internal Power Down mode is active. PLD is in non-turbo mode and none of the inputs are switching Refer to Figure 32 for PLD current calculation. I OUT = 0 mA
68
Preliminary
PSD913F1
Microcontroller Interface - AC/DC Parameters
(5V 10% Versions)
AC Symbols for PLD Timing. Example:
A C D E L N P Q R S T W B - - - - - - - - - - - - - t AVLX - Time from Address Valid to ALE Invalid.
Signal Letters
Address Input CEout Output Input Data E Input ALE Input Reset Input or Output Port Signal Output Output Data WR, UDS, LDS, DS, IORD, PSEN Inputs Chip Select Input R/W Input Internal PDN Signal Vstby Output
Signal Behavior
t L H V X Z PW - - - - - - - Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width
69
PSD913F1
Preliminary
Microcontroller Interface - PSD913F1 AC/DC Parameters
(5V 10% Versions)
Read Timing (5 V 10% Versions)
-90
Symbol
t LVLX t AVLX t LXAX t AVQV t SLQV t RLQV t RHQX t RLRH t RHQZ t EHEL t THEH t ELTL t AVPV
NOTES: 1. 2. 3. 4. 5. 6.
-12
Min
22 8 9 90 120 135 35 42 0 35 25 29 36 13 0 25 28 38 18 0 0 38
-15
Min
28 10 11 150 150 40 45
Parameter
ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Data Valid CS Valid to Data Valid RD to Data Valid 8-Bit Bus RD or PSEN to Data Valid 8-Bit Bus, 8031, 80251 RD Data Hold Time RD Pulse Width RD to Data High-Z E Pulse Width R/W Setup Time to Enable R/W Hold Time After Enable Address Input Valid to Address Output Delay
Conditions
(Note 3) (Note 3) (Notes 3 and 6) (Note 5) (Note 2) (Note 1) (Note 1) (Note 1)
Min
20 6 8
Max
Max
Max
Turbo Off
Unit
ns ns ns
Add 10
ns ns ns ns ns ns
100 32 38 0 32 32 10 0 (Note 4)
33
ns ns ns ns
30
ns
RD timing has the same timing as DS, LDS, UDS, and PSEN signals. RD and PSEN have the same timing. Any input used to select an internal PSD913F1 function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. RD timing has the same timing as DS, LDS, and UDS signals. In Turbo Off mode, add 10ns to t AVQV.
70
Preliminary
PSD913F1
Microcontroller Interface - PSD913F1 AC/DC Parameters
(5V 10% Versions)
Write Timing (5 V 10% Versions)
-90
Symbol
t LVLX t AVLX t LXAX t AVWL t SLWL t DVWH t WHDX t WLWH
-12
Min
22 8 9 25 30 40 5 40 9 0 30 25 35 28
-15
Min
28 10 11 30 35 45 5 45 10 0 38 30 ns ns ns ns ns ns ns ns ns ns ns
Parameter
ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Leading Edge of WR CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width
Conditions
(Note 1) (Note 1) (Notes 1 and 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Notes 3 and 4) (Note 3) (Note 2)
Min
20 6 8 20 25 35 5 35 8 0
Max
Max
Max
Unit
t WHAX1 Trailing Edge of WR to Address Invalid t WHAX2 t WHPV t AVPV
NOTES: 1. 2. 3. 4.
Trailing Edge of WR to DPLD Address Input Invalid Trailing Edge of WR to Port Output Valid Using I/O Port Data Register Address Input Valid to Address Output Delay
Any input used to select an internal PSD913F1 function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Combinatorial Timing (5 V 10%)
-90 -12 -15 TURBO OFF Slew
(Note 1)
Symbol
t PD t ARD
Parameter
PLD Input Pin/Feedback to PLD Combinatorial Output PLD Array Delay
Conditions
Min
Max
25 16
Min
Max
30 18
Min
Max
32 22
Unit
ns ns
Add 10 Sub 2
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
71
PSD913F1
Preliminary
Microcontroller Interface - PSD913F1 AC/DC Parameters
(5V 10% Versions)
Power Down Timing (5 V 10%)
-90
Symbol
t LVDV
-12
Max
90
-15
Min Max
150
Parameter
ALE Access Time from Power Down Maximum Delay from APD Enable to Internal PDN Valid Signal
Conditions
Min
Min
Max
120
Unit
ns
t CLWH
Using CLKIN Input
15 * t CLCL (Note 1)
s
NOTE: 1. t CLCL is the CLKIN clock period.
Vstbyon Timing (5 V 10%)
Symbol
t BVBH t BXBL
Parameter
Vstby Detection to Vstbyon Output High Vstby Off Detection to Vstbyon Output Low
Conditions
Min
Typ
20 20
Max
Unit
s s
Reset Timing (5 V 10%)
Symbol
t NLNH t OPR t NLNH-PO
Parameter
Warm RESET Active Low Time (Note 1) RESET High to Operational Device Power On Reset Active Low Time (Note 2)
Conditions
Min
150
Typ
Max
Unit
ns
120 1
ns ms
NOTE: 1. RESET will not reset Flash or EEPROM programming/erase cycles. 2. tNLNH-PO is 10 ms for devices manufactured before rev. A.
72
Preliminary
PSD913F1
Microcontroller Interface - PSD913F1 AC/DC Parameters
(5V 10% Versions)
Flash Program, Write and Erase Times (5 V 10%)
Symbol Parameter
Flash Bulk Erase (Preprogrammed) (Note 1) Flash Bulk Erase (Not Preprogrammed) t WHQV3 t WHQV2 t WHQV1 t WHWLO t Q7VQV Sector Erase (Preprogrammed) Sector Erase (Not Preprogrammed) Byte Program Program/Erase Cycles (Per Sector) Sector Erase Time-Out DQ7 Valid to Output (DQ7-0) Valid (Data Polling) (Note 2) 100,000 100 30
Min
Typ
3 5 1 2.2 14
Max
30 30 1200
Unit
sec sec sec sec s cycles s ns
NOTES: 1. Programmed to all zeros before erase. 2. The Polling Status DQ7 is valid t Q7VQV ns, before the data byte DQ0-7 is valid for reading.
EEPROM Write Times (5 V 10%)
Symbol
t EEHWL t BLC t WCB t WCP
Parameter
Write Protect After Power Up EEPROM Byte Load Cycle Timing (Note 1) EEPROM Byte Write Cycle Time EEPROM Page Write Cycle Time (Note 2) Program/Erase Cycles (Per Sector)
Min
Typ
5
Max
Unit
msec
0.2 4 6 10,000
120 10 30
sec msec msec cycles
NOTES: 1. If the maximum time has elapsed between successive writes to an EEPROM page, the transfer of this data to EEPROM cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type. 2. These specifications are for writing a page to EEPROM cells.
ISC Timing (5 V 10%)
-90
Symbol
t ISCCF t ISCCH t ISCCL t ISCCF-P t ISCCH-P t ISCCL-P t ISCPSU t ISCPH t ISCPCO t ISCPZV t ISCPVZ
-12
Min
29 29 2 2 240 240 10 5 23 23 23 24 24 24
-15
Min
31 31 2 240 240 10 5 25 25 25
Parameter
TCK Clock Frequency (except for PLD) TCK Clock High Time TCK Clock Low Time TCK Clock Frequency (for PLD only) TCK Clock High Time (for PLD only) TCK Clock Low Time (for PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance
Conditions Min Max
(Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2) 18 26 26 240 240 8 5
Max
16
Max
14
Unit
MHz ns ns MHz ns ns ns ns ns ns ns
NOTES: 1. For "non-PLD" programming, erase or in ISC by-pass mode. 2. For program or erase PLD only.
73
PSD913F1
Preliminary (3.0 V to 3.6 V Versions)
PSD913F1V DC Characteristics
Symbol
VCC VIH VIL VIH1 VIL1 VHYS VLKO VOL
Parameter
Supply Voltage High Level Input Voltage Low Level Input Voltage Reset High Level Input Voltage Reset Low Level Input Voltage Reset Pin Hysteresis VCC Min for Flash Erase and Program Output Low Voltage All Speeds
Conditions
3.0 V < VCC < 3.6 V 3.0 V < VCC < 3.6 V (Note 1) (Note 1)
Min
3.0 .7 VCC -.5 .8 VCC -.5 0.3 1.5
Typ
Max
3.6 VCC +.5 0.8 VCC +.5 .2 VCC -.1 2.2
Unit
V V V V V V V V V V V V
IOL = 20 A, VCC = 3.0 V IOL = 4 mA, VCC = 3.0 V
0.01 0.15 2.9 2.7 VSBY - 0.8 2.0 2.99 2.8
0.1 0.45
VOH VOH1 VSBY ISBY IIDLE VDF ISB ILI ILO
Output High Voltage Except VSTBY On Output High Voltage VSTBY On SRAM Standby Voltage SRAM Standby Current Idle Current (VSTBY Pin) SRAM Data Retention Voltage Standby Supply Current for Power Down Mode Input Leakage Current Output Leakage Current
IOH = -20 A, VCC = 3.0 V IOH = -1 mA, VCC = 3.0 V IOH1 = 1 A VCC = 0 V VCC > VSBY Only on VSTBY CSI >VCC -0.3 V (Note 2) VSS < VIN < VCC 0.45 < VIN > VCC ZPLD_TURBO = OFF, f = 0 MHz (Note 3)
VCC 0.5 1 0.1
V A A V
-0.1 2 25 -1 -10 .1 5 0 200 10 0 0
100 1 10
A A A mA
ZPLD Only ICC (DC) (Note 3) Operating Supply Current FLASH or EEPROM
ZPLD_TURBO = ON, f = 0 MHz During FLASH or EEPROM Write/Erase Only Read Only, f = 0 MHz
400 25 0 0
A/PT mA mA mA Figure 28a
SRAM ZPLD AC Adder ICC (AC) (Note 3) FLASH or EEPROM AC Adder SRAM AC Adder
f = 0 MHz
1.5 0.8
2.0 1.5
mA/MHz mA/MHz
NOTES: 1. Reset input has hysteresis. VIL1 is valid at or below .2VCC -.1. VIH1 is valid at or above .8VCC. 2. CSI deselected or internal PD is active. 3. I OUT = 0 mA
74
Preliminary
PSD913F1
Microcontroller Interface - PSD913F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
AC Symbols for PLD Timing. Example:
A C D E L N P Q R S T W B - - - - - - - - - - - - - t AVLX - Time from Address Valid to ALE Invalid.
Signal Letters
Address Input CEout Output Input Data E Input ALE Input Reset Input or Output Port Signal Output Output Data WR, UDS, LDS, DS, IORD, PSEN Inputs Chip Select Input R/W Input Internal PDN Signal Vstby Output
Signal Behavior
t L H V X Z PW - - - - - - - Time Logic Level Low or ALE Logic Level High Valid No Longer a Valid Logic Level Float Pulse Width
75
PSD913F1
Preliminary
Microcontroller Interface - PSD913F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Read Timing (3.0 V to 3.6 V Versions)
-15
Symbol
t LVLX t AVLX t LXAX t AVQV t SLQV t RLQV t RHQX t RLRH t RHQZ t EHEL t THEH t ELTL t AVPV
NOTES: 1. 2. 3. 4. 5. 6.
-20
Min
30 12 14
Parameter
ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Data Valid (Notes 3 and 6) CS Valid to Data Valid RD to Data Valid 8-Bit Bus RD or PSEN to Data Valid 8-Bit Bus, 8031, 80251 RD Data Hold Time RD Pulse Width (also DS, LDS, UDS) RD or PSEN Pulse Width (8031, 80251) RD to Data High-Z E Pulse Width R/W Setup Time to Enable R/W Hold Time After Enable Address Input Valid to Address Output Delay
Conditions
(Note 3) (Note 3)
Min
26 10 12
Max
Max
Turbo Off
Unit
ns ns ns
150 150 (Note 5) (Note 2) (Note 1) 0 40 55 (Note 1) 45 18 0 (Note 4) 35 40 52 20 0 35 50 0 45 60
200 200 40 55
Add 20
ns ns ns ns ns ns ns
45
ns ns ns ns
40
ns
RD timing has the same timing as DS, LDS, UDS, and PSEN signals. RD and PSEN have the same timing for 8031. Any input used to select an internal PSD913F1 function. In multiplexed mode latched address generated from ADIO delay to address output on any Port. RD timing has the same timing as DS, LDS, and UDS signals. In Turbo Off mode, add 20ns to t AVQV.
76
Preliminary
PSD913F1
Microcontroller Interface - PSD913F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Write, Erase and Program Timing (3.0 V to 3.6 V Versions)
-15
Symbol
t LVLX t AVLX t LXAX t AVWL t SLWL t DVWH t WHDX t WLWH t WHAX1 t WHAX2 t WHPV t WLMV t DVMV t AVPV
NOTES: 1. 2. 3. 4. 5. 6.
-20
Min
30 12 14 25 25 50 10 53 17 0 45 90 90 48 50 100 100 55 ns ns ns ns ns ns ns ns ns ns ns ns ns
Parameter
ALE or AS Pulse Width Address Setup Time Address Hold Time Address Valid to Leading Edge of WR CS Valid to Leading Edge of WR WR Data Setup Time WR Data Hold Time WR Pulse Width Trailing Edge of WR to Address Invalid Trailing Edge of WR to DPLD Address Input Invalid Trailing Edge of WR to Port Output Valid Using I/O Port Data Register WR Valid to Port Output Valid Using MicroCell Register Preset/Clear Data Valid to Port Output Valid Using MicroCell Register Preset/Clear Address Input Valid to Address Output Delay
Conditions
(Note 1) (Note 1) (Notes 1 and 3) (Note 3) (Note 3) (Note 3) (Note 3) (Note 3) (Notes 3 and 6) (Note 3) (Notes 3 and 4) (Notes 3 and 5) (Note 2)
Min
26 10 12 20 20 45 8 48 12 0
Max
Max
Unit
Any input used to select an internal PSD913F1 function. In multiplexed mode, latched addresses generated from ADIO delay to address output on any Port. WR timing has the same timing as E, LDS, UDS, WRL, and WRH signals. Assuming data is stable before active write signal. Assuming write is active before data becomes valid. Address Hold Time for DPLD inputs that are used to generate chip selects for internal PSD memory.
PLD Combinatorial Timing (3.0 V to 3.6 V Versions)
-15 -20 TURBO OFF Slew
(Note 1)
Symbol
t PD t ARD
Parameter
PLD Input Pin/Feedback to PLD Combinatorial Output PLD Array Delay
Conditions
Min
Max
48 29
Min
Max
55 33
Unit
ns ns
Add 20 Sub 6
NOTE: 1. Fast Slew Rate output available on PA[3:0], PB[3:0], and PD[2:0].
77
PSD913F1
Preliminary
Microcontroller Interface - PSD913F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Power Down Timing (3.0 V to 3.6 V Versions)
-15
Symbol
t LVDV t CLWH
-20
Min Max
200
Parameter
ALE Access Time from Power Down Maximum Delay from APD Enable to Internal PDN Valid Signal
Conditions
Min
Max
150
Unit
ns s
Using CLKIN Input
15 * t CLCL (Note 1)
NOTE: 1. tCLCL is the CLKIN clock period.
Vstbyon Timing (3.0 V to 3.6 V Versions)
Symbol
t BVBH t BXBL
Parameter
Vstby Detection to Vstbyon Output High Vstby Off Detection to Vstbyon Output Low
Conditions
Min
Typ
2.0 2.0
Max
Unit
s s
Reset Timing (3.0 V to 3.6 V Versions)
Symbol
t NLNH t OPR t NLNH-PO
Parameter
Warm RESET Active Low Time (Note 1) RESET High to Operational Device Power On Reset Active Low Time (Note 2)
Conditions
Min
300
Typ
Max
Unit
ns
300 1
ns ms
NOTE: 1. RESET will not reset Flash or EEPROM programming/erase cycles. 2. tNLNH-PO is 10 ms for devices manufactured before the rev. A.
78
Preliminary
PSD913F1
Microcontroller Interface - PSD913F1V AC/DC Parameters
(3.0 V to 3.6 V Versions)
Flash Program, Write and Erase Times (3.0 V to 3.6 V Versions)
Symbol Parameter
Flash Bulk Erase (Preprogrammed) (Note 1) Flash Bulk Erase (Not Preprogrammed) t WHQV3 t WHQV2 t WHQV1 t WHWLO t Q7VQV Sector Erase (Preprogrammed) Sector Erase (Not Preprogrammed) Byte Program Program/Erase Cycles (Per Sector) Sector Erase Time-Out DQ7 Valid to Output (DQ7-0) Valid (Data Polling) (Note 2) 100,000 100 30
Min
Typ
3 5 1 2.2 14
Max
30 30 1200
Unit
sec sec sec sec s cycles s ns
NOTES: 1. Programmed to all zeros before erase. 2. The Polling Status DQ7 is valid t Q7VQV ns before the data byte DQ0-7 is valid for reading.
EEPROM Write Times (3.0 V to 3.6 V Versions)
Symbol
t EEHWL t BLC t WCB t WCP
Parameter
Write Protect After Power Up EEPROM Byte Load Cycle Timing (Note 1) EEPROM Byte Write Cycle Time EEPROM Page Write Cycle Time (Note 2) Program/Erase Cycles (Per Sector)
Min
Typ
5
Max
Unit
msec
0.2 4 6 10,000
120 10 30
sec msec msec cycles
NOTES: 1. If the maximum time has elapsed between successive writes to an EEPROM page, the transfer of this data to EEPROM cells will begin. Also, bytes cannot be written (loaded) to a page any faster than the indicated minimum type. 2. These specifications are for writing a page to EEPROM cells.
ISC Timing (3.0 V to 3.6 V Versions)
-15
Symbol
t ISCCF t ISCCH t ISCCL t ISCCF-P t ISCCH-P t ISCCL-P t ISCPSU t ISCPH t ISCPCO t ISCPZV t ISCPVZ
-20
Min Max
9 51 51 2 2 240 240 15 10 36 36 36 40 40 40
Parameter
TCK Clock Frequency (except for PLD) TCK Clock High Time TCK Clock Low Time TCK Clock Frequency (for PLD only) TCK Clock High Time (for PLD only) TCK Clock Low Time (for PLD only) ISC Port Set Up Time ISC Port Hold Up Time ISC Port Clock to Output ISC Port High-Impedance to Valid Output ISC Port Valid Output to High-Impedance
Conditions
(Note 1) (Note 1) (Note 1) (Note 2) (Note 2) (Note 2)
Min
Max
10
Unit
MHz ns ns MHz ns ns ns ns ns ns ns
45 45 240 240 13 10
NOTES: 1. For "non-PLD" programming, erase or in ISC by-pass mode. 2. For program or erase PLD only.
79
PSD913F1
Preliminary
Figure 29. Read Timing
tAVLX ALE/AS tLVLX A/D MULTIPLEXED BUS ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS
tLXAX*
ADDRESS VALID tAVQV ADDRESS VALID
DATA VALID
DATA VALID tSLQV
CSI tRLQV tRLRH RD (PSEN, DS) tRHQZ tRHQX
tEHEL E tTHEH tELTL
R/W
tAVPV ADDRESS OUT
*tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
80
Preliminary
PSD913F1
Figure 30. Write Timing
tAVLX ALE/AS
t LXAX
t LVLX A/D MULTIPLEXED BUS ADDRESS VALID tAVWL ADDRESS NON-MULTIPLEXED BUS DATA NON-MULTIPLEXED BUS tSLWL CSI tDVWH WR (DS) t WLWH t WHDX t WHAX ADDRESS VALID DATA VALID DATA VALID
t EHEL E t THEH R/ W t WLMV tAVPV ADDRESS OUT t WHPV STANDARD MCU I/O OUT t ELTL
81
PSD913F1
Preliminary
Figure 31. Combinatorial Timing - PLD
CPLD INPUT t PD CPLD OUTPUT
Figure 32. ISC Timing
t ISCCH
TCK
t ISCCL t ISCPSU t ISCPH
TDI/TMS
t ISCPZV t ISCPCO
ISC OUTPUTS/TDO
t ISCPVZ
ISC OUTPUTS/TDO
82
Preliminary
PSD913F1
Figure 33. Reset Timing
OPERATING LEVEL t NLNH-PO VCC t NLNH
RESET t OPR POWER ON RESET WARM RESET t OPR
Figure 34. Key to Switching Waveforms
WAVEFORMS
INPUTS
OUTPUTS
STEADY INPUT
STEADY OUTPUT
MAY CHANGE FROM HI TO LO MAY CHANGE FROM LO TO HI
WILL BE CHANGING FROM HI TO LO WILL BE CHANGING LO TO HI
DON'T CARE
CHANGING, STATE UNKNOWN
OUTPUTS ONLY
CENTER LINE IS TRI-STATE
83
PSD913F1
Preliminary
Pin Capacitance
TA = 25 C, f = 1 MHz
Symbol
CIN COUT CVPP
Parameter 1
Capacitance (for input pins only) Capacitance (for input/output pins) Capacitance (for CNTL2/VPP)
Conditions Typical 2 Max Unit
VIN = 0 V VOUT = 0 V VPP = 0 V 4 8 18 6 12 25 pF pF pF
NOTES: 1. These parameters are only sampled and are not 100% tested. 2. Typical values are for TA = 25C and nominal supply voltages.
Figure 35. AC Testing Input/Output Waveform
3.0V TEST POINT 0V 1.5V
Figure 36. AC Testing Load Circuit
DEVICE UNDER TEST
2.01 V
195
CL = 30 pF (INCLUDING SCOPE AND JIG CAPACITANCE)
Programming
Upon delivery from ST, the PSD913F1 device has all bits in the PLDs and memories in the "1" or high state. The configuration bits are in the "0" or low state. The code, configuration, and PLDs logic are loaded through the procedure of programming. Information for programming the device is available directly from ST. Please contact your local sales representative. (See the last page.)
84
Preliminary
PSD913F1
PSD913F1 Pin Assignments
52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J) Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Pin Assignments
GND PB5 PB4 PB3 PB2 PB1 PB0 PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 (VSTBY) PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND
Pin No.
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Pin Assignments
PA2 PA1 PA0 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 VCC AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1 PB7 PB6
85
PSD913F1
Preliminary
PSD913F1 Pin Assignments
52-Pin Plastic Quad Flatpack (PQFP) (Package Type M) Pin No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Pin Assignments
PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0 PA7 PA6 PA5 PA4 PA3 GND PA2 PA1 PA0 AD0 AD1 AD2 AD3
Pin No.
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
Pin Assignments
AD4 AD5 AD6 AD7 VCC AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 CNTL0 RESET CNTL2 CNTL1 PB7 PB6 GND PB5 PB4 PB3 PB2 PB1 PB0
86
Preliminary
PSD913F1
PSD913F1 Package Information
Figure 37. Drawing J7 - 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J)
CNTL2 RESET CNTL1 CNTL0 46 45 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 32 33 GND 1
PB0
PB1
PB2
PB3
PB4
PB5
PB6
7 PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 (VSTBY) PC1 PC0 8 9 10 11 12 13 14 15 16 17 18 19 20
6
5
4
3
2
52 51 50 49 48 47 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 VCC AD7 AD6 AD5 AD4
PB7
AD1
CNTL0
AD2
GND
Figure 38. Drawing M3 - 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
PB1 PB4 PB5 RESET CNTL1 GND PB0 PB2 PB3 PB6 PB7 CNTL2
52 51 50 49 48 47 46 45 44 43 42 41 40
PD2 PD1 PD0 PC7 PC6 PC5 PC4 VCC GND PC3 PC2 PC1 PC0
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
AD0
AD3
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
39 38 37 36 35 34 33 32 31 30 29 28 27
AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 VCC AD7 AD6 AD5 AD4
AD1
PA7
AD0
GND
AD2
AD3
PA2
PA5
PA4
PA3
PA6
PA1
PA0
87
PSD913F1
Preliminary
Figure 37A. Drawing J7 - 52-Pin Plastic Leaded Chip Carrier (PLDCC) (Package Type J)
D D1
3 2 1 52 51
E1
E .025 .045 R
View A
B1 A2
C
B D3 D2 A1 A E3 E2
e1
View A
Family: Plastic Leaded Chip Carrier
Millimeters Symbol
A A1 A2 B B1 C D D1 D2 D3 E E1 E2 E3 e1 N
020197R1
Inches Notes Min
0.165 0.100 0.144 0.013 0.026 0.0097 0.785 0.750 0.690 Reference 0.600 0.785 0.750 0.690 Reference Reference 0.600 0.050 52 0.795 0.754 0.730 Reference Reference
Min
4.19 2.54 3.66 0.33 0.66 0.246 19.94 19.05 17.53 15.24 19.94 19.05 17.53 15.24 1.27 52
Max
4.57 2.79 3.86 0.53 0.81 0.261 20.19 19.15 18.54 20.19 19.15 18.54
Max
0.180 0.110 0.152 0.021 0.032 0.0103 0.795 0.754 0.730
Notes
Reference
88
Preliminary
PSD913F1
Figure 38A. Drawing M3 - 52-Pin Plastic Quad Flatpack (PQFP) (Package Type M)
D D1 D3
52
1 2 3
Index Mark E3 E1 E
Standoff: 0.05 mm Min. A2 A C
L B e1 Lead Coplanarity: 0.1mm Max.
Family: Plastic Quad Flatpack (PQFP)
Millimeters Symbol
A A2 B C D D1 D3 E E1 E3 e1 L N 0.73 52 12.95 9.90 7.80 0.65 1.03 12.95 9.90 7.80 13.45 10.10 Reference Reference 0.029 52
060198R0
Inches Notes Min
0 - 0.077 Reference 0.009 0.510 0.390 Reference 0.510 0.390 0.307 0.026 0.041 0.307 0.530 0.398 Reference Reference
Min
0 - 1.95 0.22
Max
7 2.35 2.10 0.38 0.23 13.45 10.10
Max
7 0.093 0.083 0.015 0.009 0.530 0.398
Notes
Reference
89
Selector Guide
90
PSD913F1
Selector Guide - PSD813F1 and PSD913F1 Family
Part #
PSD @ 5V PSD @ 3V
MCU
PLDs/Decoders
I/O
Memory
Other
Data Path PLD Inputs Interface Input MicroCells Output MicroCells
Ports Flash Program Store JTAG OTP EPROM Boot Parallel ISP EEPROM/EEPROM Boot ISP Flash 2nd Flash Boot ISP CPLD PLD Outputs SRAM Periph. Mode (w/BB) Page Security Reg. PMU APD
PSD813F1 PSD913F1
PSD813F1V PSD913F1V
8 8
PLUS1 PLUS1
73 24 16 57 0 0
19 19
8-Bit 27 8-Bit 27
1024Kb 1024Kb
256Kb 256Kb
16Kb 16Kb
X X
X X
X X
X X
X X
XX XX
X X
Legend:
ZPSD ZPSDV STD STD-M PLUS w/BB APD = = = = = = = Zero Power version available at 4.5 V to 5.5 V VCC (Example: ZPSD311-15J). Zero Power version available at 2.7 V to 5.5 V VCC (Example: ZPSD311V-25J). 2.7 V to 3.6 V VCC on PSD8XXF family. Standard MCU interfaces supported (Multiplexed and Non-Multiplexed). Standard MCU interfaces supported (Multiplexed only). New Intel 80C251 and Philips 80C51XA supported plus all standard MCUs. Battery backed-up SRAM. Automatic Power Down.
Preliminary
Preliminary
PSD913F1
Part Number Construction
PSD 413A2 V
-A -20 J
I Temperature (Blank = Commercial, I = Industrial, M = Military) Package Type Speed (-70 = 70ns, -90 = 90ns, -15 = 150ns -20 = 200ns, -25 = 250ns) Revision (Blank = No Revision) Supply Voltage (Blank = 5V, V = 3 Volt) Base Part Number - see Selector Guide PSD (ST Programmable System Device) Fam.
Ordering Information
Part Number
PSD913F1-90J PSD913F1-90JI PSD913F1-90M PSD913F1-90MI PSD913F1-12JI PSD913F1-12MI PSD913F1V-15J PSD913F1V-15M PSD913F1V-20JI PSD913F1V-20MI
Speed (ns)
90 90 90 90 120 120 150 150 200 200
Package Type
52 Pin PLDCC 52 Pin PLDCC 52 Pin PQFP 52 Pin PQFP 52 Pin PLDCC 52 Pin PQFP 52 Pin PLDCC 52 Pin PQFP 52 Pin PLDCC 52 Pin PQFP
Operating Temperature Range
Comm'l Industrial Comm'l Industrial Industrial Industrial Comm'l Comm'l Industrial Industrial
91
PSD913F1-A
REVISION HISTORY Table 1. Document Revision History
Date Aug-2000 04-Jan-2002 Rev. 1.0 1.1 Description of Revision Document written in the WSI format Front page, and back two pages, in ST format, added to the PDF file References to Waferscale, WSI, EasyFLASH and PSDsoft 2000 updated to ST, ST, Flash+PSD and PSDsoft Express
2/3
PSD913F1-A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com
3/3

▲Up To Search▲

Price & Availability of 7835

	To Download 7835 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .