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| PRELIMINARY RoboClockII CY7B994V CY7B993V High-Speed Multi-Phase PLL Clock Buffer Features * 12/100-MHz (CY7B993V), or 24/185-MHz (CY7B994V) output operation * Matched pair outputs skew <200 ps * Zero input-to-output delay * 18 LVTTL 50% duty-cycle outputs capable of driving 50 terminated lines * Commercial Temp. Range with 16 outputs at 185 MHz * Industrial Temp. Range with 6 outputs at 185 MHz * 3.3V LVTTL/LV Differential (LVPECL), Fault Tolerant and Hot Insertable reference inputs * Phase adjustments in 625/1300 ps steps up to 10.4 ns * Multiply/Divide ratios of (1-6, 8, 10, 12):(1-6, 8, 10, 12) * Operation up to 12x input frequency (input as low as 1 MHz (CY7B993V) or 2 MHz (CY7B994V)) * Individual Output Bank disable for aggressive power management and EMI reduction * Fault tolerant and Hot Insertable Reference inputs * Output high-impedance option for testing purposes * Fully integrated PLL with Lock Indicator * Low Cycle-to-Cycle Jitter (<100 ps peak-peak) * Single 3.3V 10% supply * 100-Pin TQFP package Functional Description The CY7B993V and CY7B994V High-Speed Multi-Phase PLL Clock buffers offer user-selectable control over system clock functions. This multiple-output clock driver provides the system integrator with functions necessary to optimize the timing of high-performance computer and communication systems. Eighteen configurable outputs can each drive terminated transmission lines with impedances as low as 50 while delivering minimal and specified output skews at LVTTL levels. The outputs are arranged in five banks. Banks 1 to 4 of four outputs allow a divide function of 1 to 12, while simultaneously allowing phase adjustments in 625 ps-1300 ps increments up to 10.4 ns. One of the output banks also includes independent clock invert function. The feedback bank consists of two outputs, which allows divide-by functionality from 1 to 12 and limited phase adjustments. Any one of these eighteen outputs can be connected to the feedback input as well as driving other inputs. Selectable reference input is a fault tolerance feature which allows smooth change over to secondary clock source, when the primary clock source is not in operation. The reference inputs and feedback inputs are configurable to accommodate both LVTTL or Differential (LVPECL) inputs. The completely integrated PLL reduces jitter and simplifies board layout Functional Block Diagram FBKA+ FBKA- FBKB+ FBKB- FBSEL REFA+ REFA- REFB+ REFB- REFSEL FBF0 FBDS0 FBDS1 FBDIS 4F0 4F1 4DS0 4DS1 DIS4 3F0 3F1 3DS0 3DS1 DIS3 INV3 2F0 2F1 2DS0 2DS1 DIS2 1F0 1F1 1DS0 1DS1 DIS1 LOCK Phase Freq. Detector Filter VCO Control Logic Divide and Phase Generator FS OUTPUT_MODE Divide and Phase Select Matrix Divide and Phase Select Matrix 3 3 Feedback Bank 3 3 3 QFA0 QFA1 Bank 4 3 3 3 3 4QA0 4QA1 4QB0 4QB1 3QA0 3QA1 3QB0 3QB1 2QA0 2QA1 2QB0 2QB1 1QA0 1QA1 1QB0 1QB1 Bank 3 3 3 3 3 3 3 3 3 3 Divide and Phase Select Matrix Bank 2 Divide and Phase Select Matrix Bank 1 3 3 3 3 Divide and Phase Select Matrix Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 October 21, 1999 PRELIMINARY Pin Configuration RoboClockII CY7B993V CY7B994V FBDS1 FBDS0 FBKB+ FBKA+ FBSEL FBKB- FBKA- 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND 3F1 4F1 3F0 4F0 4DS1 3DS1 GND 4QB1 VCCN 4QB0 GND GND 4QA1 VCCN 4QA0 GND 2DS1 1DS1 VCCQ 4DS0 3DS0 2DS0 1DS0 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 75 74 73 72 71 70 69 68 67 66 65 VCCQ REFA+ REFA - REFSEL REFB- REFB+ 2F0 FS GND 2QA0 VCCN 2QA1 GND GND 2QB0 VCCN 2QB1 GND FBF0 1F0 GND VCCQ FBDIS DIS4 DIS3 CY7B993/4V VCCQ 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND VCCN VCCN VCCN LOCK 1QB1 1QB0 1QA1 1QA0 QFA0 QFA1 GND GND GND GND GND GND GND GND VCCN 3QB0 3QB1 GND INV3 OUTPUT_MODE VCCQ VCCQ VCCQ VCCN 2 VCCQ GND GND GND GND GND 3QA0 3QA1 GND 2F1 1F1 DIS1 DIS2 PRELIMINARY Pin Definitions[1] Name FBSEL FBKA+, FBKA- FBKB+, FBKB- I/O Input Input Type LVTTL LVTTL/ LVDIFF Description RoboClockII CY7B993V CY7B994V Feedback Input Select: When LOW, FBKA inputs are selected. When HIGH, the FBKB inputs are selected. This input has an internal pull-down. Feedback Inputs: One pair of inputs selected by the FBSEL is used to feedback the clock output xQn to the phase detector. The PLL will operate such that the rising edges of the reference and feedback signals are aligned in both phase and frequency. These inputs can operate as differential PECL or single-ended TTL inputs. When operating as a singleended LVTTL input, the complementary input must be left open. Reference Inputs: These inputs can operate as differential PECL or single-ended TTL reference inputs to the PLL. When operating as a single-ended LVTTL input, the complementary input must be left open. Reference Select Input: The REFSEL input controls how the reference input is configured. When LOW, it will use the REFA pair as the reference input. When HIGH, it will use the REFB pair as the reference input. This input has an internal pull-down. Frequency Select: This input must be set according to the nominal frequency (fNOM). See Table 1. Feedback Output Phase Function Select: This input determines the phase function of the Feedback Bank's QFA[0:1] outputs. See Table 3. Feedback Divider Function Select: These inputs determine the function of the QFA0 and QFA1 outputs. See Table 4. Feedback Disable: This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1] is disabled to the "HOLD-OFF" or "HI-Z" state; the disable state is determined by OUTPUT_MODE. When LOW, the QFA[0:1] is enabled. See Table 5. This input has an internal pull-down. Output Phase Function Select: Each pair controls the phase function of the respective bank of outputs. See Table 3. Output Divider Function Select: Each pair controls the divider function of the respective bank of outputs. See Table 4. Output Disable: Each input controls the state of the respective output bank. When HIGH, the output bank is disabled to the "HOLD-OFF" or "HI-Z" state; the disable state is determined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled. See Table 5. These inputs each has an internal pull-down. Invert Mode: This input only affects Bank 3. When this input is LOW, each matched output pair will become complementary (3QA0+, 3QA1-, 3QB0+, 3QB1-). When this input is HIGH, all four outputs in the same bank will be inverted. When this input is MID all four outputs will be non-inverting. PLL Lock Indicator: When HIGH, this output indicates the internal PLL is locked to the reference signal. When LOW, the PLL is attempting to acquire lock. Output Mode: This pin determines the clock outputs' disable state. When this input is HIGH, the clock outputs will disable to high impedance (HI-Z). When this input is LOW, the clock outputs will disable to "HOLD-OFF" mode. When in MID, the device will enter factory test mode. Clock Feedback Output: This pair of clock outputs is intended to be connected to the FB input. These outputs have numerous divide options and three choices of phase adjustments. The function is determined by the setting of the FBDS[0:1] pins and FBF0. Clock Output: These outputs provide numerous divide and phase select functions determined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs. Output Buffer Power: Power supply for each output pair. Internal Power: Power supply for the internal circuitry. Device Ground. REFA+, REFA- REFB+, REFB- REFSEL Input LVTTL/ LVDIFF LVTTL Input FS FBF0 FBDS[0:1] FBDIS Input Input Input Input 3-level Input 3-level Input 3-level Input LVTTL [1:4]F[0:1] [1:4]DS[0:1] DIS[1:4] Input Input Input 3-level Input 3-level Input LVTTL INV3 Input 3-level Input LOCK Output LVTTL 3-Level Input OUTPUT_MODE Input QFA[0:1] Output LVTTL [1:4]Q[A:B][0:1] VCCN VCCQ GND Output LVTTL PWR PWR PWR Note: 1. For all three-state inputs, HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 3 PRELIMINARY Block Diagram Description Phase Frequency Detector and Filter These two blocks accept signals from the REF inputs (REFA+, REFA-, REFB+ or REFB-) and the FB inputs (FBKA+, FBKA-, FBKB+ or FBKB-). Correction information is then generated to control the frequency of the Voltage Controlled Oscillator (VCO). These two blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal. The RoboClockII has a flexible REF and FB input scheme. These inputs allow the use of either differential LVPECL or single ended LVTTL inputs. To configure as single-ended LVTTL inputs, the complementary pin must be left open (internally pulled to 1.5V), then the other input pin can be used as a LVTTL input. The REF inputs are also tolerant to hot insertion. The REF inputs can be changed dynamically. When changing from one reference input to the other reference input of the same frequency, the PLL is optimized to ensure that the clock outputs period will not be less than the calculated system budget (tMIN = tREF (nominal reference clock period) - tCCJ (cycleto-cycle jitter) - tPDEV (max. period deviation)) while re-acquiring lock. VCO, Control Logic, Divider, and Phase Generator The VCO accepts analog control inputs from the PLL filter block. The FS control pin setting determines the nominal operational frequency range of the divide by one output (fNOM) of the device. fNOM is directly related to the VCO frequency. There are two versions of the RoboClock II, a low-speed version device (CY7B993V) which fNOM ranges from 12 MHz to 100 MHz, and a high-speed version device (CY7B994V) which ranges from 24 MHz to 200 MHz. The FS setting for each device is shown in Table 1. The fNOM frequency is seen on "divide-by-one" outputs. For the CY7B994V, the upper fNOM range extends from 96 MHz to 200 MHz, but the maximum output frequency is limited to185 MHz. Table 1. Frequency Range Select CY7B993V fNOM (MHz) FS [2] RoboClockII CY7B993V CY7B994V nominal output frequency. The equation to be used to determine the tU value is as follows: tU = 1/(fNOM*N) N is a multiplication factor which is determined by the FS setting. fNOM is nominal frequency of the device. N is defined in Table 2. Table 2. N Factor Determination CY7B993V FS LOW MID HIGH N 64 32 16 fNOM (MHz) at which tU =1.0 ns 15.625 31.25 62.5 N 32 16 8 CY7B994V fNOM (MHz) at which tU =1.0 ns 31.25 62.5 125 Divide and Phase Select Matrix The Divide and Phase Select Matrix is comprised of five independent banks: four banks of clock outputs and one bank for feedback. Each clock output bank has two pairs of low-skew, high fan out output buffers ([1:4]Q[A:B][0:1]), two phase function select inputs ([1:4]F[0:1]), two divider function selects ([1:4]DS[0:1]) and one output disable (DIS[1:4]). The feedback bank has one pair of low-skew, high-fanout output buffers (QFA[0:1]). One of these outputs may connect to the selected feedback input (FBKA[0:1]). This feedback bank also has one phase function select input (FBF0), two divider function selects FSDS[0:1], and one output disable (FBDIS). The phase capabilities that are chosen by the phase function select pins are shown in Table 3. The divide capabilities for each bank are shown in Table 4. Table 3. Output Skew Select Function Function Selects [1:4]F0 and FBF0 Output Skew Function Feedback Bank [1:4]F1 Bank1 Bank2 Bank3 Bank4 CY7B994V fNOM (MHz) Min. 24 48 96 Max. 52 100 200[3] LOW LOW LOW MID MID MID HIGH HIGH HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH -4tU -3tU -2tU -1tU 0tU +1tU +2tU +3tU +4tU -4tU -3tu -2tU -1tU 0tU +1tU +2tU +3tU +4tU -8tU -7tU -6tU BK1[4] 0tU BK2 [4] -8tU -7tU -6tU BK1[4] 0tU BK2 [4] -4tU NA NA NA 0tu NA NA NA +4tU Min. 12 24 48 Max. 26 52 100 LOW MID HIGH +6tU +7tU +8tU +6tU +7tU +8tU Time Unit Definition Selectable skew is in discrete increments of time unit (tU). The value of a tU is determined by the FS setting and the maximum Notes: 2. The level to be set on FS is determined by the "nominal" operating frequency (fNOM) of the VCO and Phase Generator. f NOM always appears on an output when the output is operating in the undivided mode. The REF and FB are at fNOM when the output connected to FB is undivided. 3. The maximum output frequency is 185 MHz. 4. BK1, BK2 denotes following the skew setting of bank1 and bank2 respectively. 4 PRELIMINARY Table 4. Output Divider Function Function Selects [1:4]DS1 and FBDS1 [1:4]DS0 and FBDS0 Bank 1 RoboClockII CY7B993V CY7B994V Output Divider Function Bank 2 Bank 3 Bank 4 Feedback Bank LOW LOW LOW MID MID MID HIGH HIGH HIGH LOW MID HIGH LOW MID HIGH LOW MID HIGH /1 /2 /3 /4 /5 /6 /8 /10 /12 /1 /2 /3 /4 /5 /6 /8 /10 /12 /1 /2 /3 /4 /5 /6 /8 /10 /12 /1 /2 /3 /4 /5 /6 /8 /10 /12 /1 /2 /3 /4 /5 /6 /8 /10 /12 Figure 1 illustrates the timing relationship of programmable skew outputs. All times are measured with respect to REF with the output used for feedback programmed with 0tU skew. The PLL naturally aligns the rising edge of the FB input and REF input. If the output used for feedback is programmed to another skew position, then the whole tU matrix will shift with respect to REF. For example, if the output used for feedback is programmed to shift -8tU, then the whole matrix is shifted forward in time by 8tU. Thus an output programmed with 8tU of skew will effectively be skewed 16tU with respect to REF. U U U U U U U U U U U U U U t - 6t t - 5t t - 4t t - 3t t - 2t t - 8t t - 7t t - 1t U t +7t FBInput REFInput 1F[1:0] 2F[1:0] (N/A) (N/A) (N/A) LL LM LH ML MM MH HL HM HH (N/A) (N/A) (N/A) 3F[1:0] 4F[1:0] LL LM LH (N/A) (N/A) (N/A) (N/A) MM (N/A) (N/A) (N/A) (N/A) HL HM HH - 8t U - 7t U - 6t U - 4t U - 3t U -2tU -1tU 0t U +1t U +2t U +3t U +4t U +6t U +7t U +8t U Figure 1. Typical Outputs with FB Connected to a Zero-Skew Output[5] Note: 5. FB connected to an output selected for "zero" skew (i.e. FBF0=MID or XF[1:0]=MID). 5 t +8t t +1t t +2t t +3t t +4t t +5t t +6t 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 t 0 U PRELIMINARY Output Disable Description The feedback Divide and Phase Select Matrix Bank has two outputs, and each of the four Divide and Phase Select Matrix Banks have four outputs. The outputs of each bank can be independently put into a HOLD-OFF or high-impedance state. The combination of the OUTPUT_MODE and DIS[1:4]/FBDIS inputs determines the clock outputs' state for each bank. When the DIS[1:4]/FBDIS is LOW, the outputs of the corresponding bank will be enabled. When the DIS[1:4]/FBDIS is HIGH, the outputs for that bank will be disabled to a high-impedance (HI-Z) or HOLD-OFF state depending on the OUTPUT_MODE input. Table 5 defines the disabled output functions. The HOLD-OFF state is intended to be a power saving feature. An output bank is disabled to the HOLD-OFF state in a maximum of six output clock cycles from the time when the disable input (DIS[1:4]/FBDIS) is HIGH. When disabled to the HOLDOFF state, non-inverting outputs are driven to a logic LOW state on its falling edge. Inverting outputs are driven to a logic HIGH state on its rising edge. This ensures the output clocks are stopped without glitch. When a bank of output is disabled to HI-Z state, the respective bank of outputs will go HI-Z immediately. Table 5. DIS[1:4]/FBDIS Pin Functionality OUTPUT_MODE HIGH/LOW HIGH LOW MID INV3 Pin Function Bank3 has signal invert capability. The four outputs of Bank3 will act as two pairs of complementary outputs when the INV3 pin is driven LOW. In complementary output mode, 3QA0 and 3QB0 are non-inverting; 3QA1and 3QB1 are inverting outputs. All four outputs will be inverted when the INV3 pin is driven HIGH. When the INV3 pin is left in MID, the outputs will not invert. Inversion of the outputs are independent of the skew and divide functions. Therefore, clock outputs of Bank3 can be inverted, divided, and skewed at the same time. Lock Detect Output Description The LOCK detect output indicates the lock condition of the integrated PLL. Lock detection is accomplished by comparing the phase difference between the reference and feedback inputs. Phase error is declared when the phase difference between the two inputs is greater than the specified device propagation delay limit (tPDFSL, M, H). When in the locked state, after four or more consecutive feedback clock cycles with phase-errors, the LOCK output will be forced LOW to indicate out-of-lock state. When in the out-of-lock state, 32 consecutive phase-errorless feedback clock cycles are required to allow the LOCK output to indicate lock condition (LOCK = HIGH). If the feedback clock is removed after LOCK has gone HIGH, a "watchdog" circuit is implemented indicate out-of-lock condition after time-out by deasserting LOCK LOW. This time out period is base upon a divided down reference clock. DIS[1:4]/FBDIS LOW HIGH HIGH X Output Mode ENABLED HI-Z HOLD-OFF FACTORY TEST Factory Test Mode Description RoboClockII CY7B993V CY7B994V The device will enter factory test mode when the OUTPUT_MODE is driven to MID. In factory test mode, the device will operate with its internal PLL disconnected; input level supplied to the reference input will be used in place of the PLL output. All functions of the device are still operational in factory test mode except the internal PLL. The OUTPUT_MODE input is designed to be a static input. Dynamically toggling this input from LOW to HIGH may temporarily cause the device to go into factory test mode (when passing through the MID state). Factory Test Reset When in factory test mode (OUTPUT_MODE=MID), the device can be reset to a deterministic state by driving the DIS4 input HIGH. When the DIS4 input is driven HIGH in factory test mode, all clock outputs will go to HI-Z; after the selected reference clock pin has 5 positive transitions, all the internal finite state machines (FSM) will be set to a deterministic state. The deterministic state of the state machines will depend on the configurations of the divide selects, skew selects, and frequency select input. All clock outputs will stay in high-impedance mode and all FSMs will stay in the deterministic state until DIS4 is deasserted. When DIS4 is deasserted (with OUTPUT_MODE still at MID), the device will re-enter factory test mode. Safe Operating Zone The following figure illustrates the operating condition at which the device does not exceed its allowable maximum junction temperature of 150C. Figure 2 shows the maximum number of outputs that can operate at 185 MHz (with 25-pF load and no air flow) at various ambient temperature. At the limit line, all other outputs are configured to divide-by-two (i.e. operating at 92.5 MHz) or lower frequencies. The device will operate below maximum allowable junction temperature of 150C when its configuration (with the specified constraints) falls within the shaded region (safe operating zone). Figure 2 shows that at 85C, the maximum number of outputs that can operate at 185 MHz is 6; and at 70C, the maximum number of outputs that can operate at 185 MHz is 16 (with 25-pF load and 0 m/s air flow). Typical Safe Operating Zone (25-pF Load, 0-m /s air flow ) 100 Ambient Temperature (C) 95 90 85 80 75 70 65 60 55 50 2 4 6 8 10 12 14 16 18 Safe Operating Zone Num ber of Outputs at 185 MHz Figure 2. Typical Safe Operating Zone 6 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature .....................................-40C to +125C Ambient Temperature with Power Applied ..-40C to +125C Supply Voltage to Ground Potential..................-0.5V to +4.6V DC Input Voltage ..........................................-0.3V to VCC+0.5V Output Current into Outputs (LOW) ..........................TBD mA RoboClockII CY7B993V CY7B994V Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ............................................................ TBD Operating Range Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V 10% 3.3V 10% Electrical Characteristics Over the Operating Range Parameter VOH VOL IOZ VIH Description LVTTL HIGH Voltage QFA[0:1], [1:4]Q[A:B][0:1] LOCK LOCK High Impedance State Leakage Current LVTTL Input HIGH FBK[A:B], REF[A:B] REFSEL, FBSEL, FBDIS, DIS[1:4] VIL LVTTL Input LOW FBK[A:B], REF[A:B] REFSEL, FBSEL, FBDIS, DIS[1:4] II IlH LVTTL VIN >VCC LVTTL Input HIGH Current LVTTL Input LOW Current FBK[A:B], REF[A:B] FBK[A:B], REF[A:B] REFSEL, FBSEL, FBDIS, DIS[1:4] FBK[A:B], REF[A:B] REFSEL, FBSEL, FBDIS, DIS[1:4] Min. < VCC < Max. Min. < VCC < Max. Min. < VCC < Max. VIN = V CC VIN = V CC / 2 VIN = GND -50 -200 400 1.0 GND 0.8 VCC VCC VCC-0.4 VCC VCC = GND, VIN = 3.63V VCC = Max., VIN = VCC VIN = VCC VCC = Max., VIN = GND TBD -500 TBD TBD Min. < VCC < Max. Min. < VCC < Max. Test Conditions VCC = Min., IOH = -30 mA IOH = -2 mA, VCC = Min. VCC = Min., IOL= 30 mA IOL= 2 mA, VCC = Min. TBD 2.0 2.0 -0.3 -0.3 Min. 2.4 2.4 0.5 0.5 TBD VCC+0.3 VCC+0.3 0.8 0.8 100 500 TBD Max. Units V V V V A V V V V A A A A A LVTTL Compatible Output Pins (QFA[0:1], [1:4]Q[A:B][0:1], LOCK) LVTTL LOW Voltage QFA[0:1], [1:4]Q[A:B][0:1] LVTTL Compatible Input Pins (FBKA, FBKB, REFA, REFB, FBSEL, REFSEL, FBDIS, DIS[1:4]) IlL 3-Level Input Pins (FBF0, FBDS[0:1], [1:4]F[0:1], [1:4]DS[0:1], FS, OUTPUT_MODE(TEST)) VIHH VIMM VILL IIHH IIMM IILL VDIFF VIHHP VILLP VCOM Three Level Input HIGH[6] Three Level Input MID[6] Three Level Input LOW [6] 0.87*VCC 0.47*VCC 0.53*VCC 0.13*VCC 200 50 V V V A A A mV V V V Three Level Input HIGH Current Three Level Input MID Current Three Level Input LOW Current Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW Voltage Common Mode Range (crossing voltage) LVDIFF Input Pins (FBK[A:B], REF[A:B]) Note: 6. These inputs are normally wired to VCC, GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold the unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all data sheet limits are achieved. 7 PRELIMINARY Electrical Characteristics Over the Operating Range (continued) Parameter ICCI ICCN Description Internal Operating Current CY7B993V CY7B994V VCC = Max., CLOAD = 25 pF, RLOAD = 50 at VCC/2, fMAX Test Conditions VCC = Max., fMAX[8] Min. RoboClockII CY7B993V CY7B994V Max. TBD TBD TBD TBD Units mA mA mA mA Operating Current Output Current CY7B993V Dissipation / Bank[7] CY7B994V Capacitance Parameter CIN Description Input Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Min. TBD Max. TBD Units pF Notes: 7. This is dependent upon frequency and number of outputs of a bank being loaded. The value indicates maximum ICCN at maximum frequency and maximum load of 25 pF terminated to 50 at VCC/2. For any other frequencies and load conditions the following equation can be used to calculate the maximum output current: TBD. 8. ICCI measurement is performed with Bank1 and FB Bank configured to run at maximum frequency (fNOM = 100 MHz for CY7B993V, fNOM = 185 MHz for CY7B994V), and all other clock output banks to run at half the maximum frequency. FS and OUTPUT_MODE is asserted to HIGH state, FBDS[0:1], 1DS[0:1] are asserted to LOW state, all other three-level inputs are left open. 8 PRELIMINARY Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13] RoboClockII CY7B993V CY7B994V CY7B993/4V-5 CY7B993/4V-7 Parameter fout tSKEWPR tSKEWBNK tSKEW0 tSKEW1 tSKEW2 Clock Output Frequency Matched-Pair Skew [14, 15] Intrabank Skew [14, 15] Description CY7B993V CY7B994V Min. Max. 100 185 200 300 600 700 900 Min. Max. 100 185 200 400 800 900 1200 Unit MHz MHz ps ps ps ps ps Output-Output Skew (same frequency and phase, rise to rise, fall to fall)[14, 15] Output-Output Skew (same frequency and phase, other banks at different frequency, rise to rise, fall to fall)[14, 15] Output-Output Skew (invert to nominal of different banks, compared banks at same frequency, rising edge to falling edge aligned, other banks at same frequency)[14, 15] Output-Output Skew (invert to nominal of different banks, compared banks at same frequency, rising edge to falling edge aligned, other banks at different frequency)[14, 15] Output-Output Skew (divideX to divideY, or inverted to divideX, rising edge to falling edge aligned, other banks at different frequency)[14,15] Output-Output Skew (divideX to divideY, or inverted to divideX, rise to rise, fall to fall, other banks at different frequency)[14, 15] Output-Output Skew (rise to fall, complementary outputs of the same bank)[14, 15] Complementary Outputs Skew (crossing to crossing, complementary outputs of the same bank)[14, 15, 16] Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 1, 2, 3) Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 4, 5, 6) Cycle-to-Cycle Jitter (divide by 1 output frequency, FB = divide by 8, 10, 12) Propagation Delay, REF to FB Rise, FS = LOW Propagation Delay, REF to FB Rise, FS = MID Propagation Delay, REF to FB Rise, FS = HIGH Propagation Delay difference between two devices with same configuration (same VCC and temperature)[17, 18] Propagation Delay difference between two devices with same configuration (full VCC range difference and small temperature difference)[17, 18] Propagation Delay difference between two devices with different configuration (same V CC and moderate temperature difference)[17, 18] Propagation Delay difference between two devices with same configuration (full VCC range difference and wide temperature difference)[17, 18] -500 -500 -500 tSKEW3 900 1200 ps tSKEW4 tSKEW5 tSKEW6 tSKEWCPR tCCJ1-3 tCCJ4-6 tCCJ8-12 tPDFSL tPDFSM tPDFSH tPDDELTA1 tPDDELTA2 1000 900 900 TBD 100 200 400 500 500 500 200 400 -700 -700 -700 1300 1100 1100 TBD 100 200 400 700 700 700 300 500 ps ps ps ps ps PeakPeak ps PeakPeak ps PeakPeak ps ps ps ps ps tPDDELTA3 tPDDELTA4 600 1000 700 1100 ps ps Notes: 9. This is for non-three level inputs. 10. Assumes 25 pF Max. Load Capacitance. 11. Both outputs of pair must be terminated, even if only one is being used. 12. Each package must be properly decoupled. 13. AC parameters are measured at 1.5V, unless otherwise indicated. 14. Test Load CL= 25 pF, terminated to VCC/2 with 50. 15. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same phase delay has been selected when all outputs are loaded with 25 pF and properly terminated. 16. Complementary output skews are measured at complementary signals pairs intersections. 17. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 18. Full VCC difference = ((VCC1-VCC2)/(VCC1+VCC2))*0.5 < 5%. Small temperature difference = Tambient1-Tambient2<10C. Moderate temperature difference = Tambient1 - Tambient2<20C. Full temperature difference = Tambient1 - Tambient2<40C. 9 PRELIMINARY Switching Characteristics Over the Operating Range[9, 10, 11, 12, 13](continued) RoboClockII CY7B993V CY7B994V CY7B993/4V-5 CY7B993/4V-7 Parameter tREFrf tREFpwh tREFpwl tr/tf tLOCK tRELOCK1 tRELOCK2 tODCV tPWH tPWL tPDEV tOHZ tOLZ tOZH tOZL Description REF input Rise/Fall Time [19, 20] REF input (Pulse Width HIGH) REF input (Pulse Width LOW) Output Rise/Fall Time[20] PLL Lock TIme From Power-Up PLL Re-Lock Time (from same frequency, different phase) With Stable Power Supply PLL Re-Lock Time (from different frequency, different phase) With Stable Power Supply[26] Output duty cycle deviation from 50%[13] Output HIGH time deviation from 50% [21] [19] [19] Min. 2.0 2.0 0.15 Max. 1.0 Min. 2.0 2.0 Max. 1.0 Unit ns ns ns 1.2 10 TBD TBD 0.15 1.2 10 TBD TBD ns ms s s ns ns ns UI ns ns ns ns -1.0 1.0 1.5 2.0 -1.0 1.0 1.5 2.0 TBD Output LOW time deviation from 50%[21] Period deviation when changing from reference to reference [25] TBD 1.0 1.0 0.5 [22] DIS[1:4]/FBDIS HIGH to output high-impedance from HIGH[14, 22] DIS[1:4]/FBDIS HIGH to output high-impedance from LOW[14, 22] DIS[1:4]/FBDIS LOW to output HIGH from output is highimpedance[23] DIS[1:4]/FBDIS LOW to output LOW from high-impedance[23] 10 10 14 [24] 1.0 1.0 0.5 [22] 10 10 14 [24] 0.5[22] 14[24] 0.5[22] 14[24] AC Test Loads and Waveform[27] 3.3V R1 For LOCK output only R1 = 910 R2 = 910 CL < 30 pF For all other outputs R1 = 100 R2 = 100 CL < 25 pF OUTPUT CL R2 (Includes fixture and probe capacitance) (a) LVTTL AC Test Load 3.0V 2.0V GND < 1 ns 0.8V 2.0V 0.8V < 1 ns (b) TTL Input Test Waveform Notes: 19. Tested initially and after any design or process changes that may affect these parameters. 20. Rise and fall times are measured between 2.0V and 0.8V. 21. tPWH is measured at 2.0V. tPWL is measured at 0.8V. 22. Measured at 0.5V deviation from starting voltage. 23. For t OZL and tOZH minimum, CL = 0pF, RL = 1k (to VCC for t OZL, to GND for t OZH). For t OZL and tOZH maximum, CL= 25pF and RL = 100 (to VCC for t OZL, to GND for tOZH). 24. tOZL maximum is measured at 0.5V. tOZH maximum is measured at 2.4V. 25. UI = Unit Interval. Examples: 1 UI is a full period. 0.1UI is 10% of period. 26. fNOM must be within the frequency range defined by the same FS state. 27. These figures are for illustrations only. The actual ATE loads may vary. 10 PRELIMINARY AC Timing Diagrams[13] tREFpwl tREFpwh REF t SKEWPR tPDFSL,M,H t PWH 2.0V FB 0.8V tCCJ1-3,4-6,8-12 Q [1:4]QA[0:1] tSKEWBNK [1:4]QB[0:1] REF TO DEVICE 1 and 2 t SKEWBNK t PWL QFA1 or [1:4]Q[A:B]1 t SKEWPR QFA0 or [1:4]Q[A:B]0 RoboClockII CY7B993V CY7B994V tPDFSL,M,H DIVIDED BY X FB DEVICE1 tSKEW4 tPDELTA1,2,3,4 FB DEVICE2 tPDELTA1,2,3,4 INVERTED OR DIVIDED BY Y tODCV tODCV Q tSKEW0,1 Other Q t SKEW0,1 DIVIDED BY X tSKEW4 INVERTED OR DIVIDED BY Y DIVIDED BY X Q tSKEW2,3,6 INVERTED Q tSKEW2,3,6 INVERTED OR DIVIDED BY Y tSKEW5 tSKEWCPR COMPLEMENTARY A DIVIDED BY X crossing tSKEW5 crossing COMPLEMENTARY B INVERTED OR DIVIDED BY Y 11 PRELIMINARY Ordering Information Propagation Delay (ps) 500 500 500 500 700 700 Max. Speed (MHz) 100 100 185 185 100 185 Ordering Code CY7B993V-5AC CY7B993V-5AI CY7B994V-5AC CY7B994V-5AI CY7B993V-7AC CY7B994V-7AC Package Name A100 A100 A100 A100 A100 A100 Package Type RoboClockII CY7B994V CY7B993V Operating Range 100-Lead Thin Quad Flat Pack Commercial 100-Lead Thin Quad Flat Pack Industrial 100-Lead Thin Quad Flat Pack Commercial 100-Lead Thin Quad Flat Pack Industrial 100-Lead Thin Quad Flat Pack Commercial 100-Lead Thin Quad Flat Pack Commercial Document #: 38-00747-C Package Diagram 100-Pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048-B (c) Cypress Semiconductor Corporation, 1999. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. |
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