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(R)
VND830ASP
DOUBLE CHANNEL HIGH SIDE SOLID STATE RELAY
TYPE VND830ASP
(*) Per channel
RDS(on) 60 m (*)
IOUT 6 A (*)
VCC 36 V (*)
10
DC SHORT CIRCUIT CURRENT: 6A s CMOS COMPATIBLE INPUTS s PROPORTIONAL LOAD CURRENT SENSE s UNDERVOLTAGE AND OVERVOLTAGE SHUT-DOWN s OVERVOLTAGE CLAMP s THERMAL SHUT-DOWN s CURRENT LIMITATION s VERY LOW STAND-BY POWER DISSIPATION
s
1
PowerSO-10TM ORDER CODES
PACKAGE TUBE T&R
PowerSO-10TM VND830ASP VND830ASP13TR side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device has two channels in high side configuration; each channel has an analog sense output on which the sensing current is proportional (according to a known ratio) to the corresponding load current. Built-in thermal shut-down and outputs current limitation protect the chip from over temperature and short circuit. Device turns off in case of ground pin disconnection.
PROTECTION AGAINST: LOSS OF GROUND AND LOSS OF VCC s REVERSE BATTERY PROTECTION (**)
s
DESCRIPTION The VND830ASP is a monolithic device made using STMicroelectronics VIPower M0-3 technology. It is intended for driving any kind of load with one BLOCK DIAGRAM
VCC
OVERVOLTAGE VCC CLAMP UNDERVOLTAGE PwCLAMP 1
DRIVER 1
INPUT 1 LOGIC INPUT 2 GND
DRIVER 2
ILIM1 Vdslim1 IOUT1 K
Ot1
OUTPUT 1
CURRENT SENSE 1 OUTPUT 2
Ot2
PwCLAMP 2
Ot1
ILIM2 Vdslim2 IOUT2
OVERTEMP. 1 OVERTEMP. 2
Ot2
K
CURRENT SENSE 2
(**) See application schematic at page 8
July 2003
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VND830ASP
ABSOLUTE MAXIMUM RATING
Symbol VCC -VCC -IGND IOUT IR IIN VCSENSE Parameter DC Supply Voltage Reverse Supply Voltage DC Reverse Ground Pin Current Output Current Reverse Output Current Input Current Current Sense Maximum Voltage Electrostatic Discharge (Human Body Model: R=1.5; C=100pF) - INPUT VESD - CURRENT SENSE - OUTPUT - VCC Maximum Switching Energy (L=1.8mH; RL=0; Vbat=13.5V; Tjstart=150C; IL=9A) Power Dissipation at TC=25C Junction Operating Temperature Case Operating Temperature Storage Temperature 4000 2000 5000 5000 100 74 Internally Limited - 40 to 150 - 55 to 150 V V V V mJ W C C C Value 41 - 0.3 - 200 Internally Limited -6 +/- 10 -3 +15 Unit V V mA A A mA V V
EMAX Ptot Tj Tc Tstg
CONNECTION DIAGRAM (TOP VIEW)
GROUND INPUT2 INPUT1 C.SENSE1 C.SENSE2
6 7 8 9 10 11 VCC
5 4 3 2 1
OUTPUT 2 OUTPUT 2 N.C. OUTPUT 1 OUTPUT 1
CURRENT AND VOLTAGE CONVENTIONS
IS VCC IIN1 INPUT1 VIN1 IOUT1 OUTPUT1 ISENSE1 IOUT2 INPUT2 OUTPUT2 VSENSE1 VOUT1 VCC
CURRENT SENSE 1 IIN2 VIN2
VOUT2 ISENSE2 VSENSE2
CURRENT SENSE 2 GROUND IGND
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VND830ASP
THERMAL DATA
Symbol Rthj-case Rthj-amb Parameter Thermal Resistance Junction-case Thermal Resistance Junction-ambient Value 1.2 51.2 (*) Unit C/W C/W
(*) When mounted on a standard single-sided FR-4 board with 0.5cm2 of Cu (at least 35m thick). Horizontal mounting and no artificial air flow
ELECTRICAL CHARACTERISTICS (8VSymbol VCC VUSD VOV RON Vclamp Parameter Operating Supply Voltage Undervoltage Shut-down Overvoltage Shut-down On State Resistance Clamp voltage Test Conditions Min 5.5 3 36 Typ 13 4 Max 36 5.5 60 41 48 12 12 120 55 40 25 7 50 0 5 3 Unit V V V m m V A A mA A A A A
IOUT =2A; Tj=25C IOUT =2A; Tj=150C ICC=20 mA (see note 1) Off State; VCC=13V; VIN=VOUT=0V Off State; VCC=13V; VIN=VOUT=0V; Tj =25C On State; VIN=5V; VCC=13V; IOUT=0A; RSENSE=3.9K VIN=VOUT=0V; VCC=36V; Tj=125C VIN=0V; VOUT=3.5V VIN=VOUT=0V; VCC=13V; Tj =125C VIN=VOUT=0V; VCC=13V; Tj =25C
IS
Supply Current
IL(off1) IL(off2) IL(off3) IL(off4)
Off State Output Current Off State Output Current Off State Output Current Off State Output Current
0 -75
SWITCHING (VCC =13V)
Symbol td(on) td(off) Parameter Turn-on Delay Time Turn-off Delay Time Test Conditions RL=6.5 from VIN rising edge to VOUT=1.3V RL=6.5 from VIN falling edge to VOUT=11.7V RL=6.5 from VOUT=1.3V to VOUT=10.4V Min Typ 30 30 See relative diagram See relative diagram Max Unit s s V/s
dVOUT/dt(on) Turn-on Voltage Slope
dVOUT/dt(off) Turn-off Voltage Slope
RL=6.5 from VOUT=11.7V to VOUT=1.3V
V/s
LOGIC INPUT (Channels 1,2)
Symbol VIL IIL VIH IIH VI(hyst) VICL Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage Test Conditions VIN=1.25V VIN=3.25V IIN=1mA IIN=-1mA 0.5 6 6.8 -0.7 Min 1 3.25 10 8 Typ Max 1.25 Unit V A V A V V V
Note 1: Vclamp and VOV are correlated. Typical difference is 5V.
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1
VND830ASP
ELECTRICAL CHARACTERISTICS (continued) PROTECTIONS
Symbol Ilim TTSD TR THYST Vdemag VON Parameter Current limitation Vcc=13V Test Conditions Min 6 Typ 9 Max 15 15 150 135 7 175 200 Unit A A C C C V mV
5.5V15
VCC-41 VCC-48 VCC-55 50
CURRENT SENSE (9VVCC16V) (See figure 1)
Symbol K0 K1 dK1/K1 K2 dK2/K2 K3 dK3/K3 Parameter IOUT/ISENSE IOUT/ISENSE Current Sense Ratio Drift Test Conditions IOUT1 or IOUT2=0.05A; VSENSE=0.5V; other channels open; Tj= -40C...150C IOUT1 or IOUT2=0.25A; VSENSE=0.5V; other channels open; Tj= -40C...150C IOUT1 or IOUT2=0.25A; VSENSE=0.5V; other channels open; Tj= -40C...150C IOUT1 or IOUT2=1.6A; VSENSE=4V; other channels open; Tj=-40C Tj=25C...150C Current Sense Ratio Drift IOUT1 or IOUT2=1.6A; VSENSE=4V; other channels open; Tj=-40C...150C IOUT1 or IOUT2=2.5A; VSENSE=4V; other channels open; Tj=-40C Tj=25C...150C Current Sense Ratio Drift IOUT1 or IOUT2=2.5A; VSENSE=4V; other channels open; Tj=-40C...150C VIN=0V; IOUT=0A; VSENSE=0V; Tj=-40C...150C VIN=5V; IOUT=0A; VSENSE=0V; Tj=-40C...150C VCC=5.5V; IOUT1,2=1.3A; RSENSE=10k VCC>8V, IOUT1,2=2.5A; RSENSE=10k VCC=13V; RSENSE=3.9k Min 600 1000 -10 1280 1300 -6 1280 1340 -6 0 0 2 4 5.5 400 500 1500 1500 1500 1500 Typ 1300 1400 Max 2000 1900 +10 1800 1780 +6 1680 1600 +6 5 10 % A A V V V s % % Unit
IOUT/ISENSE
IOUT/ISENSE
ISENSE
Analog Sense Leakage Current Max Analog Sense Output Voltage Sense Voltage in Overtemperature conditions
VSENSE VSENSEH
Analog Sense Output VCC=13V; Tj>TTSD; All Channels Open RVSENSEH Impedance in Overtemperature Condition Current sense delay to 90% ISENSE (see note 2) tDSENSE response
Note 2: current sense signal delay after positive input slope. Note: Sense pin doesn't have to be left floating.
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VND830ASP
TRUTH TABLE (per channel)
CONDITIONS Normal operation Overtemperature Undervoltage Overvoltage INPUT L H L H L H L H L H H L H L OUTPUT L H L L L L L L L L L H H L SENSE 0 Nominal 0 VSENSEH 0 0 0 0 0 (TjTTSD) VSENSEH 0 < Nominal 0
Short circuit to GND
Short circuit to VCC Negative output voltage clamp
ELECTRICAL TRANSIENT REQUIREMENTS
ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 ISO T/R 7637/1 Test Pulse 1 2 3a 3b 4 5 CLASS C E I -25 V +25 V -25 V +25 V -4 V +26.5 V II -50 V +50 V -50 V +50 V -5 V +46.5 V TEST LEVELS III -75 V +75 V -100 V +75 V -6 V +66.5 V TEST LEVELS RESULTS II III C C C C C C C C C C E E IV -100 V +100 V -150 V +100 V -7 V +86.5 V Delays and Impedance 2 ms 10 0.2 ms 10 0.1 s 50 0.1 s 50 100 ms, 0.01 400 ms, 2
I C C C C C C
IV C C C C C E
CONTENTS All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device is not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device.
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VND830ASP
Figure 1: IOUT/ISENSE versus IOUT
Iout/Isense
2250
2000
1750
m ax Tj= -40C m ax Tj=25...150C
1500
typical value m in Tj=25...150C m in Tj= -40C
1250
1000
750
500 0 0.5 1 1.5 2 2.5 3
Iout (A)
Figure 2: Switching Characteristics (Resistive load RL=6.5)
VOUT
80% dVOUT /dt(on) tr ISENSE 90% 10%
90% dVOUT /dt(off) tf t
INPUT
tDSENSE
t td(off)
td(on)
t
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VND830ASP
Figure 3: Waveforms
NORMAL OPERATION INPUTn LOAD CURRENTn SENSEn UNDERVOLTAGE VCC INPUTn LOAD CURRENTn SENSEn OVERVOLTAGE
VOV VUSD VUSDhyst
VCC INPUTn LOAD CURRENTn SENSEn
VCC < VOV
VCC > VOV
SHORT TO GROUND INPUTn LOAD CURRENTn LOAD VOLTAGEn SENSEn
SHORT TO VCC INPUTn LOAD VOLTAGEn LOAD CURRENTn SENSEn
OVERTEMPERATURE Tj INPUTn LOAD CURRENTn SENSEn
ISENSE= VSENSEH RSENSE TTSD TR
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VND830ASP
APPLICATION SCHEMATIC
+5V
Rprot INPUT1
VCC
Dld
C
Rprot Rprot
CURRENT SENSE1 INPUT2
OUTPUT1
Rprot
CURRENT SENSE2 GND OUTPUT2
RSENSE1
RSENSE2
VGND
RGND
DGND
GND PROTECTION REVERSE BATTERY
NETWORK
AGAINST
Solution 1: Resistor in the ground line (RGND only). This can be used with any type of load. The following is an indication on how to dimension the RGND resistor. 1) RGND 600mV / IS(on)max. 2) RGND (-VCC) / (-IGND) where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device's datasheet. Power Dissipation in RGND (when VCC<0: during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSD. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that if the microprocessor ground is not common with the device ground then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND.
If the calculated power dissipation leads to a large resistor or several devices have to share the same resistor then the ST suggests to utilize Solution 2 (see below). Solution 2: A diode (DGND) in the ground line. A resistor (RGND=1k) should be inserted in parallel to DGND if the device will be driving an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input thresholds and the status output values if the microprocessor ground is not common with the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network.
LOAD DUMP PROTECTION
Dld is necessary (Voltage Transient Suppressor) if the load dump peak voltage exceeds VCC max DC rating. The same applies if the device will be subject to transients on the VCC line that are greater than the ones shown in the ISO T/R 7637/1 table.
C I/Os PROTECTION:
If a ground protection network is used and negative transient are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot ) in line to prevent the C I/Os pins to latch-up. The value of these resistors is a compromise between the leakage current of C and the current required by the
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VND830ASP
HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os. -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Calculation example: For VCCpeak= - 100V and Ilatchup 20mA; VOHC 4.5V 5k Rprot 65k. Recommended Rprot value is 10k.
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VND830ASP
Off State Output Current
IL(off1) (uA)
8 7 6 5 4 3 2 1 0 -50 -25 0 25 50 75 100 125 150 175
High Level Input Current
Iih (uA)
5 4.5
Off state Vcc=13V Vin=Vout=0V
Vin=3.25V
4 3.5 3 2.5 2 1.5 1 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Clamp Voltage
Vicl (V)
8 7.8
Input High Level
Vih (V)
3.6 3.4
Iin=1mA
7.6 7.4 7.2 7 6.8 6.6
Vcc=13V
3.2 3 2.8 2.6 2.4
6.4 6.2 6 -50 -25 0 25 50 75 100 125 150 175
2.2 2 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Input Low Level
Vil (V)
2.6 2.4
Input Hysteresis Voltage
Vhyst (V)
1.5 1.4
Vcc=13V
2.2
Vcc=13V
1.3 1.2
2 1.8 1.6 1.4
1.1 1 0.9 0.8 0.7
1.2 1 -50 -25 0 25 50 75 100 125 150 175
0.6 0.5 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
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VND830ASP
Overvoltage Shutdown
Vov (V)
50 47.5 45 42.5 40 37.5 35 32.5 30 -50 -25 0 25 50 75 100 125 150 175
ILIM Vs Tcase
Ilim (A)
20 17.5
Vcc=13V
15 12.5 10 7.5 5 2.5 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
Turn-on Voltage Slope
dVout/dt(on) (V/ms)
600 550 500 450 400 350 300
Turn-off Voltage Slope
dVout/dt(off) (V/ms)
500 450
Vcc=13V Rl=6.5Ohm
400 350 300 250 200 150 100
Vcc=13V Rl=6.5Ohm
250 200 -50 -25 0 25 50 75 100 125 150 175
50 0 -50 -25 0 25 50 75 100 125 150 175
Tc (C)
Tc (C)
On State Resistance Vs Tcase
Ron (mOhm)
100 90 80 70 60 50 40 30
On State Resistance Vs VCC
Ron (mOhm)
100 90
Tc=150C
Iout=5A Vcc=8V & 36V
80
Iout=5A
70 60 50
Tc=25C
40
20 10 0 -50 -25 0 25 50 75 100 125 150 175 30 20 5 10 15 20 25 30 35 40
Tc= -40C
Tc (C)
Vcc (V)
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VND830ASP
Maximum turn off current versus load inductance
ILMAX (A) 100
10
A B C
1 0.1 1 L(mH)
A = Single Pulse at TJstart=150C B= Repetitive pulse at TJstart=100C C= Repetitive Pulse at TJstart=125C Conditions: VCC=13.5V Values are generated with RL=0 In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves B and C. VIN, IL Demagnetization Demagnetization Demagnetization
10
100
t
12/17
VND830ASP
PowerSO-10TM THERMAL DATA
PowerSO-10TM PC Board
Layout condition of Rth and Zth measurements (PCB FR4 area= 58mm x 58mm, PCB thickness=2mm, Cu thickness=35m, Copper areas: from minimum pad lay-out to 8cm2).
Rthj-amb Vs PCB copper area in open box free air condition
55 50 45 40 35 30 25 20 0 5
RTHjamb
10
PCB Cu heatsink area (cm )
2
15
20
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VND830ASP
PowerSO-10 Thermal Impedance Junction Ambient Single Pulse
100
Footprint 4 cm2 8 cm2 16 cm2
10 ZTH (C/W) 1 0.1 0.0001
0.001
0.01
0.1
1
10
100
1000
Time (s)
Thermal fitting model of a double channel HSD in PowerSO-10
Pulse calculation formula
Z TH = R TH + Z THtp ( 1 - )
where
= tp T
2 0.12 0.5 0.7 0.8 13 37 0.0006 0.0012 0.013 0.3 0.75 3 4 8 16
Thermal Parameter
Tj_1
Pd1 C1 C2 C1 C2 C3 C4 C5 C6
R1
R2
R3
R4
R5
R6
Tj_2
R1 Pd2
R2
T_amb
Area/island (cm2) R1 (C/W) R2 (C/W) R3( C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C)
25
20
15
4
6
9
14/17
VND830ASP
PowerSO-10TM MECHANICAL DATA
DIM. A A (*) A1 B B (*) C C (*) D D1 E E2 E2 (*) E4 E4 (*) e F F (*) H H (*) h L L (*) (*)
(*) Muar only POA P013P
mm. MIN. 3.35 3.4 0.00 0.40 0.37 0.35 0.23 9.40 7.40 9.30 7.20 7.30 5.90 5.90 1.27 1.25 1.20 13.80 13.85 0.50 1.20 0.80 0 2 1.80 1.10 8 8 0.047 0.031 0 2 1.35 1.40 14.40 14.35 0.049 0.047 0.543 0.545 TYP MAX. 3.65 3.6 0.10 0.60 0.53 0.55 0.32 9.60 7.60 9.50 7.60 7.50 6.10 6.30 MIN. 0.132 0.134 0.000 0.016 0.014 0.013 0.009 0.370 0.291 0.366 0.283 0.287 0.232 0.232
inch TYP. MAX. 0.144 0.142 0.004 0.024 0.021 0.022 0.0126 0.378 0.300 0.374 300 0.295 0.240 0.248 0.050 0.053 0.055 0.567 0.565 0.002 0.070 0.043 8 8
B
0.10 A B
10
H
E
E2
E4
1
SEATING PLANE e
0.25
B
DETAIL "A"
A
C D = D1 = = = SEATING PLANE
h
A F A1
A1
L DETAIL "A"
P095A
15/17
VND830ASP
PowerSO-10TM SUGGESTED PAD LAYOUT
14.6 - 14.9
B
TUBE SHIPMENT (no suffix)
CASABLANCA MUAR
C
10.8- 11 6.30
A A
C
0.67 - 0.73 1 2 3 4 5 10 9 8 7 6 1.27 0.54 - 0.6
B
9.5
All dimensions are in mm. Base Q.ty Bulk Q.ty Tube length ( 0.5) Casablanca Muar 50 50 1000 1000 532 532 A B C ( 0.1) 0.8 0.8
10.4 16.4 4.9 17.2
TAPE AND REEL SHIPMENT (suffix "13TR")
REEL DIMENSIONS
Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 600 600 330 1.5 13 20.2 24.4 60 30.4
All dimensions are in mm.
TAPE DIMENSIONS
According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing W P0 ( 0.1) P D ( 0.1/-0) D1 (min) F ( 0.05) K (max) P1 ( 0.1) 24 4 24 1.5 1.5 11.5 6.5 2
End
All dimensions are in mm.
Start Top cover tape 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min No components Components No components
16/17
1
VND830ASP
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in ITALY- All Rights Reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
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