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 (R)
SMP100MC-xxx
TELECOM EQUIPMENT PROTECTION: TRISILTM
PRELIMINARY DATASHEET
FEATURES
s s s s s s s
Bidirectional crowbar protection Voltage range from 65V to 270V Low VBO / VR ratio Micro capacitance from 20 to 30pF typ @ 50V Low leakage current : IR = 2 A max Holding current: IH = 150 mA min Repetitive peak pulse current : IPP = 100 A (10/1000s) SMB (JEDEC DO-214AA)
MAIN APPLICATIONS Any sensitive equipment requiring protection against lightning strikes and power crossing: Analog and digital line cards (ADSL, VDSL, T1/ E1, ISDN...) Terminals (phone, fax, modem...) and central office equipment
s s
SCHEMATIC DIAGRAM DESCRIPTION The SMP100MC-xxx series is a micro capacitance transient surge arrestor designed for the protection of high debit rate communication equipment. Its micro capacitance avoids any distortion of the signal and is compatible with digital line cards (ADSL, VDSL, T1/E1, ISDN...).
BENEFITS Trisils are not subject to ageing and provide a fail safe mode in short circuit for a better protection. They are used to help equipment to meet main standards such as UL1950, IEC950 / CSA C22.2 and UL1459. They have UL94 V0 approved resin. SMB package is JEDEC registered (DO-214AA). Trisils are UL497B approved (file: E136224) and comply with the following standards GR-1089 Core, ITU-T-K20/K21, VDE0433, VDE0878, IEC61000-4-5 and FCC part 68.
August 2003 - Ed: 1A
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SMP100MC-xxx
IN COMPLIANCES WITH THE FOLLOWING STANDARDS STANDARD GR-1089 Core First level GR-1089 Core Second level GR-1089 Core Intra-building ITU-T-K20/K21 ITU-T-K20 (IEC61000-4-2) VDE0433 VDE0878 IEC61000-4-5 FCC Part 68, lightning surge type A FCC Part 68, lightning surge type B Peak Surge Voltage (V) 2500 1000 5000 1500 6000 1500 8000 15000 4000 2000 4000 2000 4000 4000 1500 800 1000 Required Minimum serial Voltage Current peak current resistor to meet Waveform waveform (A) standard ( ) 2/10 s 10/1000 s 2/10 s 2/10 s 10/700 s 1/60 ns 10/700 s 1.2/50 s 10/700 s 1.2/50 s 10/160 s 10/560 s 9/720 s 500 100 500 100 150 37.5 2/10 s 10/1000 s 2/10 s 2/10 s 5/310 s 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ESD contact discharge ESD air discharge 100 50 100 50 100 100 200 100 25 5/310 s 1/20 s 5/310 s 8/20 s 10/160 s 10/560 s 5/320 s
THERMAL RESISTANCES Symbol Rth(j-a) Rth(j-l) Junction to leads Parameter Junction to ambient with recommended footprint Value 100 20 Unit C/W C/W
ELECTRICAL CHARACTERISTICS (Tamb = 25C) Symbol VRM IRM VR IR VBR VBO IH IBO IPP C Parameter Stand-off voltage Leakage current at VRM Continuous reverse voltage Leakage current at VR Breakdown voltage Breakover voltage Holding current Breakover current Peak pulse current Capacitance
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SMP100MC-xxx
ABSOLUTE RATINGS (Tamb = 25C) Symbol Ipp Parameter Repetitive peak pulse current: 10/1000 s 8/20 s 10/560 s 5/310 s 10/160 s 1/20 s 2/10 s IFS ITSM Fail-safe mode : maximum current (note 1) Non repetitive surge peak on-state current (Sinusoidal) 8/20 s t = 20ms t = 16.6ms t = 0.2s t = 2s t = 16.6ms t = 20ms 100 400 150 150 200 400 500 5 TBD 50 TBD TBD TBD 260 - 55 to + 150 150 A Value Unit
kA A
It TL Tstg Tj
It value for fusing Maximum lead temperature for soldering during 10s Storage temperature range Maximum junction temperature
As C C C
Note 1: in fail safe mode, the device acts as a short circuit.
Repetitive peak pulse current tr: rise time (s) tp: pulse duration time (s) ex: Pulse waveform 10/1000s tr = 10s tp = 1000s ELECTRICAL PARAMETERS (Tamb = 25C) Type IRM @ VRM max. A SMP100MC-65* SMP100MC-90* SMP100MC-120* SMP100MC-140* SMP100MC-160* SMP100MC-200* SMP100MC-230* SMP100MC-270
Note 1: Note 2: Note 3:
% IPP
100 50 0 tr tp
t
I R @ VR max. Note 1 A V 65 90 120 50 140 160 200 230 270
Dynamic VBO max. Note 2 V 85 115 155 180 205 255 295 345
Static VBO @ IBO max. max Note 3 V 80 115 150 175 200 250 285 335 800 mA
IH min. Note 4 mA 150 150 150 150 150 150 150 150
C typ. Note 5 pF 30 30 25 20 20 20 20 20
C typ. Note 6 pF 60 55 50 40 40 40 40 40
V 55 81 108 120 144 170 200 230
2
IR measured at VR guarantee VBR min VR See functional test circuit 1 See test circuit 2
Note 4: Note 5: Note 6:
See funtional holding current test circuit 3 VR = 50V bias, VRMS=1V, F=1MHz VR = 2V bias, VRMS=1V, F=1MHz
* in development
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SMP100MC-xxx
Fig. 1: On-state voltage versus on-state current (typical values)
IT(A) 50
Tj=25C
Fig. 2: Relative variation of holding current versus junction temperature .
IH[Tj] / IH[Tj=25C] 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0
10
VT(V) 1 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
Tj(C) -25 0 25 50 75 100 125
Fig. 3: Relative variation of breakover voltage versus junction temperature.
VBO[Tj] / VBO[Tj=25C] 1.08 1.06 1.04 1.02 1.00 0.98 Tj(C) 0.96 -25 0 25 50 75 100 125
Fig. 4: Relative variation of leakage current versus junction temperature (typical values).
IRM[Tj] / IRM[Tj=25C] 2000 1000
VRM > 50V
100
10 Tj(C) 1 25 50 75 100
VRM < 50V
125
Fig. 5: Variation of thermal impedance junction to ambient versus pulse duration (Printed circuit board FR4, SCu=35m, recommended pad layout).
Zth(j-a)(CW) 100
Fig. 6: Relative variation of junction capacitance versus reverse voltage applied (typical values).
C [VR] / C [VR=2V] 1.4 1.2 1.0
Tj=25C F=1MHz VRMS=1V
10
0.8 0.6 0.4
tp(s)
0.2
1E+1 1E+2 5E+2
1 1E-3
VR(V) 1 2 5 10 20 50 100 300
1E-2
1E-1
1E+0
0.0
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SMP100MC-xxx
TEST CIRCUIT 1 FOR DYNAMIC IBO AND VBO PARAMETERS
100 V / s, di/dt < 10 A / s, Ipp = 100 A
2
45 66 470
83 0.36 nF
46 H
U
10 F
KeyTek 'System 2' generator with PN246I module
1 kV / s, di/dt < 10 A / s, Ipp = 10 A
26 H
250 12
47
46 H
U
60 F
KeyTek 'System 2' generator with PN246I module
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SMP100MC-xxx
TEST CIRCUIT 2 FOR IBO and VBO parameters :
K
ton = 20ms
R1 = 140 R2 = 240
220V 50Hz Vout
DUT
VBO measurement
1/4 IBO measurement
TEST PROCEDURE : Pulse test duration (tp = 20ms): - For Bidirectional devices = Switch K is closed - For Unidirectional devices = Switch K is open. VOUT Selection - Device with VBO < 200 Volt - VOUT = 250 VRMS, R1 = 140 . - Device with VBO 200 Volt - VOUT = 480 VRMS, R2 = 240 .
TEST CIRCUIT 3 FOR IH PARAMETER
R
Surge generator
VBAT = - 48 V
D.U.T
This is a GO-NO GO test which allows to confirm the holding current (IH) level in a functional test circuit. TEST PROCEDURE : - Adjust the current level at the IH value by short circuiting the D.U.T. - Fire the D.U.T. with a surge current : Ipp = 10A, 10/1000 s. - The D.U.T. will come back to the off-state within 50 ms max.
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SMP100MC-xxx
PACKAGE MECHANICAL DATA SMB (Plastic)
E1
DIMENSIONS REF.
D
Millimeters Min. Max. 2.45 0.20 2.20 0.41 5.60 4.60 3.95 1.60 1.90 0.05 1.95 0.15 5.10 4.05 3.30 0.75
Inches Min. 0.075 0.002 0.077 0.006 0.201 0.159 0.130 0.030 Max. 0.096 0.008 0.087 0.016 0.220 0.181 0.156 0.063
A1 A2 b
E
c
A1
E E1 D
b
C L
A2
L
FOOT PRINT in millimeters (inches)
2.3 (0.09)
1.52 (0.059)
2.75 (0.108)
1.52 (0.059)
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SMP100MC-xxx
ORDER CODE
SMP
100
MC
-
xxx
Micro Capacitance Trisil Surface Mount Voltage IPP = 100 A
Ordering type SMP100MC-65 SMP100MC-90 SMP100MC-120 SMP100MC-140 SMP100MC-160 SMP100MC-200 SMP100MC-230 SMP100MC-270
Marking ML06 ML09 ML12 ML14 ML16 ML20 ML23 ML27
Package
Weight
Base qty
Delivery mode
SMB
0.11g
2500
Tape & Reel
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - Printed in Italy - All rights reserved. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 8/8


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