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Multimedia ICs
Synchronization signal processor for high definition displays
BA7078S
The BA7078S is a synchronization signal processing LSI chip designed for multiscan high-definition displays. It generates a synchronization signal and clamp pulse for three types of input signals: separate synchronization, composite synchronization, and synchronization on video.
*Applications CRT displays *Features on a single 5V power supply, with low 1) Operates
power consumption. 2) Synchronization signal existence and polarity detection output. 3) Adjustable clamp pulse width, allowing for the selection of front or back editing. 4) Vertical synchronization separation is based on horizontal frequency tracking, for separation starting at 1H. 5) Minimal attached components.
*Absolute maximum ratings (Ta = 25C)
Parameter Power supply voltage Power dissipation Operating temperature Storage temperature Symbol VCC Pd Topr Limits 7.0 600 - 25 ~ + 75 - 55 ~ + 125 Unit V mW C C
Tstg
Reduced by 6mW for each increase in Ta of 1C over 25C.
*Recommended operating conditions (Ta = 25C)
Parameter Power supply voltage Symbol VCC Min. 4.5 Typ. 5.0 Max. 5.5 Unit V
1
Multimedia ICs
BA7078S
*Block diagram
HSCTL 1 18 POLH
C / HSYNC IN
2
H SYNC Det.
17
EXIH
VIDEO IN
3
SYNC Sepa.
16
POLV
VSEPA
4 V SYNC Sepa.
Hor. SYNC Control
15
EXIV
VSYNC IN
5
14
Vcc
CVPOL
6 V SYNC Det.
13
HDRV
CVEXI
7
12
CLAMP
CPSEL
8
Clamp Pulse Gen.
11
VDRV
GND
9
10
CPWID
2
Multimedia ICs
BA7078S
*Pin descriptions
Pin No. Pin name Function Used to select whether to output the VDRV section of the HDRV output signal. High: VDRV section of HDRV is output Low: VDRV section of HDRV is not output Inputs either the composite synchronization signal or the horizontal synchronization signal. Input is clamped, and is initiated by capacitor coupling. Inputs the SYNC ON VIDEO signal (green). Input is sink chip clamped. Input is initiated by capacitor coupling. 1 HSCTL HDRV output
2
CHSYNC IN
Composite sync / H SYNC input
3
VIDEO IN
SYNC ON VIDEO input
4
VSEPA
f-V conversion
Converts the horizontal synchronization signal frequency into a voltage. The voltage generated is proportional to the frequency of the horizontal synchronization signal. Attach a 0.56F capacitor between the ground pins. Inputs the vertical synchronization signal. Integrates the vertical synchronization signal polarity detection circuit. Attach a 1.5F capacitor between this pin and the ground. Integrates the vertical synchronization signal existence detection circuit. Attach a 1F capacitor between this pin and the ground. Used to set the clamp pulse generation position to either the front or back edge of HSYNC High: The front edge is the generation position Open: Composite / H SYNC IN: The front edge is the generation position VIDEO IN: The back edge is the generation position Low: The back edge is the generation position -- Sets the clamp pulse width according to the attached time constant. Attach a resistor between this pin and Vcc, and a capacitor between this pin and GND. When R = 3.9k and C = 100pF, pulse width is approximately 400 ns. Set the resistor to register an abnormality at 1k. Outputs the vertical synchronization signal. The output signal has positive polarity. Outputs the clamp pulse generated from the vertical synchronization signal. The output signal has a positive polarity. Outputs the clamp pulse generated from the horizontal synchronization signal. The output signal has positive polarity. --
5
VSYNC IN
V SYNC input
6
CVPOL
Vertical polarity integration
7
CVEXI
Vertical existence integration
8
CPSEL
Setting the clamp position
9
GND
Ground
10
CPWID
Setting the clamp pulse width
11
VDRV
VDRV output
12
CLAMP
Clamp output
13 14
HDRV VCC
HDRVoutput Power supply
3
Multimedia ICs
Pin No. 15 Pin name EXIV Vertical existence output Function Indicates whether the vertical synchronization signal exists. For the output logic, refer to the separate table. Indicates the polarity of the vertical synchronization signal. For the output logic, refer to the separate table. Indicates whether the horizontal synchronization signal exists. For the output logic, refer to the separate table. Indicates the polarity of the horizontal synchronization signal. For the output logic, refer to the separate table.
BA7078S
16
POLV
Vertical polarity output
17
EXIH
Horizontal existence output
18
POLH
Horizontal polarity output
*Input / output circuits
HSCTL VSEPA VCC CHSYNC IN VCC 670 60k 51k 1pin 1k 4pin 200 2pin VCC
30k
10A
VSYNC IN VCC
VIDEO IN VCC 2k
CVPOL VCC
200 10k 5pin 3pin
200
6pin
200
50k
4
Multimedia ICs
CVEXI VCC CPWID VCC CPSEL
BA7078S
VCC 50k
7pin
10pin
8pin
1k
50k
VDRV VCC
GND
CLAMP VCC
9pin 12pin 11pin
HDRV
POLV
VCC VCC
VCC
VCC 10k 14pin
13pin
16pin
5
Multimedia ICs
EXIH VCC 10k EXIV VCC 10k POLH
BA7078S
VCC 10k
17pin
15pin
18pin
*Electrical characteristics (unless otherwise noted, VCC = 5V, Ta = 25C)
Parameter Power supply voltage Quiescent current VDRV output voltage (high) VDRV output voltage (low) VDRV output current (low) VDRV rising delay time HDRV output voltage (high) HDRV output voltage (low) HDRV output current (low) HDRV rising delay time (1) HDRV rising delay time (2) CLAMP output voltage (high) CLAMP output voltage (low) CLAMP output current (low) CLAMP rising delay time (1) CLAMP rising delay time (2) Synchronization detection output voltage (high) Synchronization detection output voltage (low) Synchronization detection output current (low) Synchronization detection output impedance Minimum synchronization separation level HSCTL high level threshold voltage HSCTL low level threshold voltage CPSEL high level threshold voltage CPSEL low level threshold voltage Symbol VCC ICC V VDH V VDL I VDL t rdVD V HDH V HDL I HDL trdHD1 trdHD2 V CPH V CPL I CPL trdCP1 trdCP2 V DH V DL I DL Z oD V SMin. V tHSH V tHSL V tCPH V tCPL Min. 4.5 21 4.5 -- 8 -- 4.5 -- 8 -- -- 4.5 -- 8 -- -- 4.5 -- 3 7 -- 2.5 -- 3.8 -- Typ. 5.0 30 5.0 0.2 -- 280 5.0 0.2 -- 65 95 5.0 0.2 -- 75 95 5.0 0.2 -- 10 -- -- -- -- -- Max. 5.5 39 -- 0.5 -- 450 -- 0.5 -- 115 145 -- 0.5 -- 125 145 -- 0.5 -- 13 0.2 -- 1.5 -- 1.2 Unit V mA V V mA ns V V mA ns ns V V mA ns ns V V mA k VP-P V V V V front edge back edge CHSYNC IN VIDEO IN VSYNC IN Conditions
6
Multimedia ICs
BA7078S
*Measurement circuit
1
V1
HSCTL
POLH
18
1
SW18 2 3 4
V
3mA
V
A
Oscilloscope
SW2 1 4.7F 2 4.7F 75 V2 3
2
CHSYNC IN
EXIH
17
1
SW17 2 3 4
V
3mA
V
A
Oscilloscope
SW3 1 1F 2 1F 75 3 V3
3
VIDEO IN
POLV
16
1
SW16 2 3 4
V
3mA
V
A
Oscilloscope
4
0.56F
VSEPA
EXIV
15
1
SW15 2 3 4
V
3mA
V
Vcc 5V
A
Oscilloscope
SW5 1 2 3 V5
5
VSYNC IN
VCC
14
A
0.01F
47F
75
6
1.5F
CVPOL
HDRV
13
1
SW13 2 3
V
8mA
V
Oscilloscope
7
1F
CVEXI
CLAMP
12
1
SW12 2 3
V
8mA
V
Oscilloscope
8
V8
CPSEL
VDRV
11
1
SW11 2 3
V
8mA
V
Oscilloscope
9
GND
CPWID
10
VCC 3.9k
100pF
Fig. 1
7
Multimedia ICs
BA7078S
*Conditions for measurement of electrical characteristics
Parameter Quiescent current VDRV output voltage (high) VDRV output voltage (low) VDRV output current (low) VDRV rising delay time HDRV output voltage (high) HDRV output voltage (low) HDRV output current (low) HDRV rising delay time (1) HDRV rising delay time (2) CLAMP output voltage (high) CLAMP output voltage (low) CLAMP output current (low) CLAMP rising delay time (1) CLAMP rising delay time (2) POLH output voltage (high) POLH output voltage (low) POLH output current (low) POLH output impedance EXIH output voltage (high) EXIH output voltage (low) EXIH output current (low) EXIH output impedance POLV output voltage (high) POLV output voltage (low) POLV output current (low) POLV output impedance EXIV output voltage (high) EXIV output voltage (low) EXIV output current (low) EXIV output impedance Minimum synchronization separation level HSCTL high level threshold voltage HSCTL low level threshold voltage CPSEL high level threshold voltage CPSEL low level threshold voltage Switch condition 2 1 1 1 1 1 3 3 3 2 1 2 2 3 2 1 2 2 3 3 2 1 3 3 1 1 1 1 1 1 1 1 1 2 2 1 2 3 1 1 1 1 1 1 1 1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 2 1 5 1 3 3 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 2 1 3 3 1 2 2 1 1 11 1 1 1 2 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 12 1 1 1 1 1 1 1 1 1 1 3 3 2 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 13 1 1 1 1 1 1 1 2 3 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 3 3 3 3 15 16 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 17 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 18 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
8
Multimedia ICs
BA7078S
*Application example
HSCTL
1
C1 4.7F
18 H SYNC Det.
POL H
C / H SYNC IN
2
17
EXIST H
VIDEO IN
C2 1F
3
SYNC Sepa.
16
POL V
4
C3 V SYNC IN 0.56F
V SYNC Sepa 5
Hor. SYNC Control
15
EXIST V Vcc 5V
14
0.01F 47F H DRV
6
C4 1.5F
13 V SYNC Det.
7
C5 CP SEL OPEN: AUTO H: Front L : Back 1F
12
CLAMP
8
Clamp Pulse Gen.
11
Vcc
V DRV
9
10
R1
3.9k
C6
100pF
Fig. 2
9
Multimedia ICs
BA7078S
*Attached components
C1: 47F Coupling capacitor for C / H SYNC IN A low capacitance increases the size of the input pin waveform's sag. Coupling capacitor for VIDEO IN A low capacitance increases the size of the input pin waveform's sag. Conversion capacitor for f-V A low capacitance increases the size of the ripple of the f-V conversion voltage. A large capacitance is not a problem, but will delay the reaction speed. Capacitor for POLH (detection of the vertical synchronization signal's polarity) The minimum capacotance is determined as follows: The internal hysteresis comparator does not react when the duty of minimum frequency synchronization (fV = 40Hz, T = 25ms) is 50%. CMin. = 30 T[F] A large capacitance is not a probrem, buit will deray the reaction speed. Capacitor for EXIH (detection of the vertical synchronization signal's existence) The minimum capacitance is determined as follows: The internal hysteresis comparator does not react at the minimum frequency synchronization (fV = 40Hz, T = 25ms) CMin. = 16 T[F] A large capacitance is not a probrem, but will deray the reaction speed. Constant for setting the clamp pulse width A low resistance results in a narrow clamp pulse width. Set no lower than 1k. C2: 1F
C3: 0.56F
C4: 1.5F
C5: 1F
C6: 100pF R1: 3.9k
10
Multimedia ICs
BA7078S
*Electrical characteristic curves
PROPAGATION DELAY OF RISE TIME: trdhd (ms) PROPAGATION DELAY OF RISE TIME: trdcl (ns) 100 90 80 70 60 50 40 30 20 10 0 - 50 Vcc = 5.0V - 25 0 25 50 75 100
Output position: front edge 120 100 80 60 40 20 Vcc = 5.0V 0 - 50 - 25 0 25 50 75 100
PROPAGATION DELAY OF RISE TIME: trdhd (ns)
140
160 140 120 100 80 60 40 20 Vcc = 5.0V 0 - 50 - 25 0 25 50 75 100
TEMPERATURE: Ta (C)
TEMPERATURE: Ta(C)
TEMPERATURE: Ta (C)
Fig. 3 C / HSYNC IN-HDRV Rising delay time vs. temperature
260 240 220 200 180 160 140 120
Fig. 4 C / HSYNC IN-CLAMP Rising delay time vs. temperature
3 2.5 PIN VOLTAGE: VS (V) 2
Fig. 5 VIDEO IN-HDRV Rising delay time vs. temperature
PROPAGATION DELAY OF RISE TIME: trdcl (ns)
Output position back edge 120 100 80 60 40 20 Vcc = 5.0V 0 - 50 - 25 0 25 50 75 100
PROPAGATION DELAY OF RISE TIME: trdvd (ns)
140
1.5 1 0.5
Vcc = 5.0V 100 - 50 - 25 0 25 50 75 100 0 0
Vcc = 5.0V 20 40 60 80 100 120 140 160 180 200 HORIZONTAL FREQUENCY: fH (kHz)
TEMPERATURE: Ta (C)
TEMPERATURE: Ta (C)
Fig. 6 VIDEO IN-CLAMP Rising delay time vs. temperature
Fig. 7 VSYNC IN-HDRV Rising delay time vs. temperature
Fig. 8 VSEPA horizontal frequency vs. pin voltage
*External dimensions (Units: mm)
19.4 0.3 18 10 6.5 0.3 0.51Min. 3.95 0.3 1 9 7.62
3.4 0.2
0.3 0.1
1.778
0.5 0.1
0~15
SDIP18
11

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