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PRELIMINARY TECHNICAL DATA
a
64-Position OTP I2C Compatible Digital Potentiometer
Preliminary Technical Data
FEATURES * Set & Forget One Time Programmable Wiper Set * 64-Position * End-to-End Resistance 5k, 10k, 50k, 100k * Compact SOT23-8 (2.9 x 3mm) Package 2 * I C interface * Full Read/write of wiper register * Extra Package address decode pin A0 * Power ON Reset to Midscale * IDD ~ 0.01 A * Single Supply +2.7V to +5.5V * Low Temperature Coefficient 35ppm/C * Wide Operating Temperature -40C to +125C Applications * Permanent Factory PCB Setting * Resistor Adjustment & Final Set * Replacement of Trimmers(R) in new designs * Pressure, Temperature, Position, Chemical and Optical Sensor Calibration * RF Amplifier biasing * Automotive Electronics Adjustment * Gain Control and Offset Adjustment
AD5171
trimmer). This one time program sets a validation bit, which can be read through the I2C interface. Once this acknowledge bit is set the wiper position can not be changed due to power supply sequencing, temperature, RF fields, ESD exposure, when maintained within its absolute maximum ratings. For applications that require continuous infrequent adjustment of wiper resistance settings, see the AD523x/AD525x families of nonvolatile memory digital potentiometers. Operating from a 2.7 to 5.5 volt power supply consuming less than 1uA allows for usage in portable battery operated applications. FUNCTIONAL DIAGRAM
VDD A I2C INTERFACE W WIPER REGISTER B
SCL SDA A0
GENERAL DESCRIPTION The AD5171 provides a compact 2.9x3mm packaged solution for 64-position OTP adjustment applications. This device performs the same electronic adjustment function as a mechanical trimmer(R) or a variable resistor. Available in four different end-to-end resistance values (5k, 10k, 50k, 100k) these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments. These devices will provide variable resistance under 2-wire I2C compatible program control in servo adjustment factory applications. Once the final value is determined. The user programs a permanent write command freezing the wiper position at the desired setting (analogous to placing epoxy on a mechanical
Notes:
1. The terms digital potentiometers, VR, and RDAC are used interchangeably.
GND
PIN CONFIGURATION
1W 2 VDD 3 GND
A8 B7 A0 6
4 SCL SDA 5
REV PrB, 20 FEB'03 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2003
PRELIMINARY TECHNICAL DATA
64 Position Digital Potentiometer
Parameter
+3V 10%, VA = +VDD, VB = 0V, -40C < TA < +125C unless otherwise noted.)
AD5171
Min
-1 -2 -30 35 50
AD5171 ELECTRICAL CHARACTERISTICS 5K, 10K, 50K, 100K VERSION (VDD = +5V 10%, or
Symbol
R-DNL R-INL RAB RAB/T RW N DNL INL VW/T VWFSE VWZSE VA,B,W CA,B CW IDD_SD ICM VIH VIL VIH VIL IIL CIL VLOGIC VDD RANGE IDD PDISS PSS
Conditions
Typ1
0.25 0.5
Max
+1 +2 30 100
Units
LSB LSB % ppm/C
DC CHARACTERISTICS RHEOSTAT MODE Resistor Differential Nonlinearity2 Resistor Integral Nonlinearity2 Nominal Resistor Tolerance3 Resistance Temperature Coefficient Wiper Resistance RWB, VA = No Connect RWB, VA = No Connect TA = 25C VAB = VDD, Wiper = No Connect VDD = +5V
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs Resolution Differential Nonlinearity4 Integral Nonlinearity4 Voltage Divider Temperature Coefficient Full-Scale Error Zero-Scale Error RESISTOR TERMINALS Voltage Range5 Capacitance6 A, B Capacitance6 W Shutdown Supply Current7 Common-Mode Leakage DIGITAL INPUTS & OUTPUTS Input Logic High Input Logic Low Input Logic High Input Logic Low Input Current Input Capacitance6 POWER SUPPLIES Logic Supply Single-Supply Range Supply Current Power Dissipation8 Power Supply Sensitivity DYNAMIC CHARACTERISTICS6, 9 Bandwidth -3dB Bandwidth -3dB Total Harmonic Distortion VW Settling Time (10K/50K) Resistor Noise Voltage Density BW_10K BW_50K THDW tS eN_WB RAB = 10K, Code = 80H RAB = 50K, Code = 80H VA =1Vrms, VB = 0V, f=1KHz, RAB = 10K VA= 5V, VB=0V, 1 LSB error band RWB = 5K, RS = 0 600 100 0.003 2/9 9 KHz KHz % s nVHz VSS = 0V VIH = +5V or VIL = 0V VIH = +5V or VIL = 0V, VDD = +5V VDD = +5V 10%, Code = Midscale 2.7 -0.3 5 -0.01 0.001 0.2 +0.01 5.5 5.5 V V A mW %/% 2.4 0.8 VDD = +3V VDD = +3V VIN = 0V or +5V 2.1 0.6 1 5 V V V V A pF VSS f = 1 MHz, measured to GND, Code = 80H f = 1 MHz, measured to GND, Code = 80H VDD = 5.5V VA =VB = VDD / 2 45 60 0.01 1 5 VDD V pF pF A nA 8 -1 -2 Code = 80H Code = FFH Code = 00H -1.5 0 1/4 1/2 5 -0.5 +0.5 +1 +2 +0 +1.5 Bits LSB LSB ppm/C LSB LSB
REV PrB, 20 FEB' 03 -2-
PRELIMINARY TECHNICAL DATA
64 Position Digital Potentiometer
Parameter
+3V 10%, VA = +VDD, VB = 0V, -40C < TA < +125C unless otherwise noted.)
AD5171
Min Typ1 Max 400 1.3 0.6 1.3 0.6 0.6 100 300 300 0.6 Units KHz s s s s s s ns ns ns s
AD5171 ELECTRICAL CHARACTERISTICS 5K, 10K, 50K, 100K VERSION (VDD = +5V 10%, or
Symbol Conditions INTERFACE TIMING CHARACTERISTICS applies to all parts(Notes 6,12) SCL Clock Frequency fSCL tBUF Bus free time between STOP & START t1 tHD;STA Hold Time (repeated START) t2 After this period the first clock pulse is generated tLOW Low Period of SCL Clock t3 tHIGH High Period of SCL Clock t4 tSU;STA Setup Time For START Condition t5 tHD;DAT Data Hold Time t6 tSU;DAT Data Setup Time t7 tF Fall Time of both SDA & SCL signals t8 tR Rise Time of both SDA & SCL signals t9 tSU;STO Setup time for STOP Condition t10 NOTES:
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. Typicals represent average readings at +25C and VDD = +5V. Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. VAB = VDD, Wiper (VW) = No connect INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0V. DNL specification limits of 1LSB maximum are Guaranteed Monotonic operating conditions. Resistor terminals A,B,W have no limitations on polarity with respect to each other. Guaranteed by design and not subject to production test. Measured at the A terminal. A terminal is open circuited in shutdown mode. PDISS is calculated from (IDD x VDD). CMOS logic level inputs result in minimum power dissipation All dynamic characteristics use VDD = +5V. See timing diagram for location of measured values. All input control voltages are specified with tR=tF=2ns(10% to 90% of +3V) and timed from a voltage level of 1.5V. Switching characteristics are measured using VLOGIC = +5V. The AD5171 contains xxxx transistors. Die Size: 30.7mil x 76.8 mil, 2358sq. mil. See timing diagram for location of measured values.
50 0.9
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5171 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
REV PrB, 20 FEB' 03 -3-
PRELIMINARY TECHNICAL DATA
64 Position Digital Potentiometer
ABSOLUTE MAXIMUM RATINGS (TA = +25C, unless otherwise noted) VDD to GND ...................................................... -0.3, +7V VA, VB, VW to GND ................................................... VDD IMAX ..................................................................... 20mA2 Digital Inputs & Output Voltage to GND.............. 0V, +7V Operating Temperature Range ..............-40C to +125C Maximum Junction Temperature (TJ MAX)..............+150C Storage Temperature.............................-65C to +150C Lead Temperature (Soldering, 10 sec) ................+300C 3 Thermal Resistance JA, SOT23-8 ................................................ 230C/W
NOTES 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. Maximum terminal current is bounded by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance 3. Package Power Dissipation (TJMAX-TA)/ JA
1
AD5171
ORDERING GUIDE
Model# AD5171BRJ5 AD5171BRJ10 AD5171BRJ50 AD5171BRJ100 R () 5K 10K 50K 100K Package Description SOT23-8 SOT23-8 SOT23-8 SOT23-8 Package Option RJ-8 RJ-8 RJ-8 RJ-8 Brand D12 D13 D14 D15
REV PrB, 20 FEB' 03 -4-
PRELIMINARY TECHNICAL DATA
64 Position Digital Potentiometer
Write Mode:
S 0 1 0 1 1 0 A 0 W A X R S S D X X X X X A D X D X D 5 D 4 D 3
AD5171
D 2 D 1 D 0 A P
Slave Address Byte
Instruction Byte
Data Byte
Read Mode:
S 0 1 0 1 1 0 A 0 R A D X D X D 5 D 4 D 3 D 2 D 1 D 0 A P
Slave Address Byte
Data Byte
S = Start Condition P = Stop Condition A = Acknowledge X = Don't Care W = Write R = Read
RS = Reset wiper to Midscale 20H SD = Shutdown connects wiper to B terminal and open circuits A terminal. It does not change contents of wiper register. D5,D4,D3,D2,D1,D0 = Data Bits
t8
SDA
t1 t8 t9 t6
SCL
t2
P S
t3
t4
t7
S
t5
P
t10
Figure 1. Detail Timing Diagram
1 SCL S DA 0 1
9
1
9
1
9
0
1
1
0
AD0
R/W ACK. BY A D5171
0
RS
SD
X
X
X
X
X
ACK. BY AD5171
X
X
D5
D4
D3
D2
D1
D0
START BY MASTER
FRAME 1 Slave Address Byte
FRAME 2 Instruction B yte
FRAME 3 Data Byte
ACK. BY STOP BY AD5171 MA STER
Figure 2a. Writing to the RDAC Register
1 SCL S DA 0 1 9
1
9
1
9
0
1
1
0
AD0
R/W ACK. BY A D5171
T
X
X
X
X
X
X
X
ACK. BY AD5171
X
X
D5
D4
D3
D2
D1
D0
START BY MASTER
FRAME 1 Slave Address Byte
FRAME 2 Instruction B yte
FRAME 3 Data Byte
ACK. BY STOP BY AD5171 MA STER
Figure 2b. Activating One Time Programming
1 SCL SDA 0 1 9
1
9
0
1
1
0
AD0
R/W ACK. BY AD5171
E1
E0
D5
D4
D3
D2
D1
D0 NO ACK. B Y MASTER S TOP B Y MA STER
START BY MASTE R
FRAME 1 Slave Address Byte
FRAME 2 Data Byte From Selected RDA C Register
Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode
REV PrB, 20 FEB' 03 -5-
PRELIMINARY TECHNICAL DATA
64 Position Digital Potentiometer
TABLE 1: AD5171 PIN Descriptions Pin Name Description
1 2 3 4 5 6 7 8 W VDD GND SCL SDA A0 B A W Terminal Positive Power Supply Ground Serial Clock Input, positive edge triggered Serial Data Input/Output Programmable address bit 0 for multiple package decoding B Terminal A Terminal
1W 2 VDD 3 GND
AD5171
PIN CONFIGURATION
A8 B7 A0 6
4 SCL SDA 5
REV PrB, 20 FEB' 03 -6-
PRELIMINARY TECHNICAL DATA
64 Position Digital Potentiometer
AD5171
REV PrB, 20 FEB' 03 -7-

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