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| (R) ADS 784 2 ADS7842 12-Bit, 4-Channel Parallel Output Sampling ANALOG-TO-DIGITAL CONVERTER FEATURES q SINGLE SUPPLY: 2.7V to 5V q 4-CHANNEL INPUT MULTIPLEXER q UP TO 200kHz SAMPLING RATE q FULL 12-BIT PARALLEL INTERFACE q 1 LSB INL AND DNL q GUARANTEED NO MISSING CODES q 72dB SINAD q LOW POWER: 2mW q 28-LEAD SSOP PACKAGE DESCRIPTION The ADS7842 is a complete, 4-channel, 12-bit analogto-digitial converter (ADC). It contains a 12-bit, capacitor-based, SAR A/D with a sample-and-hold amplifier, interface for microprocessor use and parallel, three-state output drivers. The ADS7842 is specified at a 200kHz sampling rate while dissipating only 2mW of power. The reference voltage can be varied from 100mV to VCC with a corresponding LSB resolution from 24V to 1.22mV. The ADS7842 is guaranteed down to 2.7V operation. Low power, high speed and an on-board multiplexer make the ADS7842 ideal for battery-operated systems such as portable, multi-channel dataloggers and measurement equipment. The ADS7842 is available in a 28-lead SSOP package and is guaranteed over the -40C to +85C temperature range. APPLICATIONS q DATA ACQUISITION q TEST AND MEASUREMENT q INDUSTRIAL PROCESS CONTROL q MEDICAL INSTRUMENTS q LABORATORY EQUIPMENT A0 A1 SAR AIN0 AIN1 AIN2 CDAC AIN3 4-Channel MUX ADS7842 Comparator VREF Output Latches and Three State Drivers Three State Parallel Data Bus CLK BUSY WR CS RD International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 Twx: 910-952-1111 * Internet: http://www.burr-brown.com/ * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (c) 1998 Burr-Brown Corporation PDS-1484A Printed in U.S.A. December, 1998 SPECIFICATIONS: +5V At TA = -40C to +85C, +VCC = +5V, VREF = +5V, f SAMPLE = 200kHz, and fCLK = 16 * fSAMPLE = 3.2MHz, unless otherwise noted. ADS7842E PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span Capacitance Leakage Current SYSTEM PERFORMANCE No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise + Distortion) Spurious Free Dynamic Range Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current VIN VIN VIN VIN = = = = 5Vp-p 5Vp-p 5Vp-p 5Vp-p at at at at 10kHz 10kHz 10kHz 50kHz 0 25 1 12 0.8 0.15 0.1 30 70 2 3 1.0 4 1.0 12 0.5 T T T T 1 1 T T 3 T CONDITIONS MIN TYP MAX 12 VREF T T T MIN ADS7842EB TYP MAX T T UNITS Bits V pF A Bits LSB(1) LSB LSB LSB LSB LSB Vrms dB Clk Cycles Clk Cycles kHz ns ns ps dB dB dB dB V G A A A 12 3 200 500 30 100 -78 71 79 120 -72 70 76 T T T -80 72 81 T T T T -76 68 72 0.1 DCLK Static f SAMPLE = 12.5kHz DCLK Static 5 40 2.5 0.001 CMOS | IIH | +5A | IIL | +5A IOH = -250A IOL = 250A 3.0 -0.3 3.5 Straight Binary 0.2 Specified Performance f SAMPLE = 12.5kHz Power-Down Mode(3), CS = +V CC 4.75 550 300 +VCC 100 3 T T T T T T T T T DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format External Clock POWER SUPPLY REQUIREMENTS +VCC Quiescent Current 5.5 +0.8 0.4 T T T T T T T V V V V MHz V A A A mW C 8 5.25 900 3 4.5 T T T T T T T T T Power Dissipation TEMPERATURE RANGE Specified Performance T Same specifications as ADS7842E. -40 +85 T T NOTE: (1) LSB means Least Significant Bit. With VREF equal to +5.0V, one LSB is 1.22mV. (2) First five harmonics of the test frequency. (3) Power-down mode at end of conversion when WR, CS, and BUSY conditions have all been met. Refer to Table I of this data sheet. The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) ADS7842 2 SPECIFICATION: +2.7V At TA = -40C to +85C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 * fSAMPLE = 2MHz, unless otherwise noted. ADS7842E PARAMETER RESOLUTION ANALOG INPUT Full-Scale Input Span Capacitance Leakage Current SYSTEM PERFORMANCE Resolution No Missing Codes Integral Linearity Error Differential Linearity Error Offset Error Offset Error Match Gain Error Gain Error Match Noise Power Supply Rejection SAMPLING DYNAMICS Conversion Time Acquisition Time Throughput Rate Multiplexer Settling Time Aperture Delay Aperture Jitter DYNAMIC CHARACTERISTICS Total Harmonic Distortion(2) Signal-to-(Noise + Distortion) Spurious Free Dynamic Range Channel-to-Channel Isolation REFERENCE INPUT Range Resistance Input Current VIN VIN VIN VIN = = = = 2.5Vp-p 2.5Vp-p 2.5Vp-p 2.5Vp-p at at at at 10kHz 10kHz 10kHz 50kHz 0 25 1 12 12 0.8 0.15 0.1 30 70 2 5 1.0 4 1.0 12 0.5 T T T T 1 1 T T 3 T CONDITIONS MIN TYP MAX 12 VREF T T T T MIN ADS7842EB TYP MAX T T UNITS Bits V pF A Bits Bits LSB (1) LSB LSB LSB LSB LSB Vrms dB Clk Cycles Clk Cycles kHz ns ns ps dB dB dB dB V G A A A 12 3 125 500 30 100 -77 71 78 100 -70 70 76 T T T -79 72 80 T T T T -74 68 72 0.1 DCLK Static fSAMPLE = 12.5kHz DCLK Static 5 13 2.5 0.001 CMOS | IIH | +5A | IIL | +5A IOH = -250A IOL = 250A +VCC * 0.7 -0.3 +VCC * 0.8 Straight Binary 0.2 Specified Performance fSAMPLE = 12.5kHz Power-Down Mode(3), CS = +V CC 2.7 280 220 +VCC 40 3 T T T T T T T T T DIGITAL INPUT/OUTPUT Logic Family Logic Levels VIH VIL VOH VOL Data Format External Clock POWER SUPPLY REQUIREMENTS +VCC Quiescent Current 5.5 +0.8 0.4 T T T T T T T V V V V MHz V A A A mW C 8 3.6 650 3 1.8 T T T T T T T T T Power Dissipation TEMPERATURE RANGE Specified Performance T Same specifications as ADS7842E. -40 +85 T T NOTE: (1) LSB means Least Significant Bit. With VREF equal to +2.5V, one LSB is 610mV. (2) First five harmonics of the test frequency. (3) Power-down mode at end of conversion when WR, CS, and BUSY conditions have all been met. Refer to Table I of this data sheet. (R) 3 ADS7842 PIN CONFIGURATION Top View SSOP PIN DESCRIPTIONS PIN 1 NAME AIN0 AIN1 AIN2 AIN3 VREF AGND DB11 DB10 DB9 DB8 DB7 DB6 DB5 DGND DB4 DB3 DB2 DB1 DB0 RD CS DESCRIPTION Analog Input Channel 0 Analog Input Channel 1 Analog Input Channel 2 Analog Input Channel 3 Voltage Reference Input. See Specifications Tables for ranges. Analog Ground Data Bit 11 (MSB) Data Bit 10 Data Bit 9 Data Bit 8 Data Bit 7 Data Bit 6 Data Bit 5 Digital Ground Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0 (LSB) Read Input. Active LOW. Reads the data outputs in combination with CS. Chip Select Input. Active LOW. The combination of CS taken LOW and WR taken LOW initiates a new conversion and places the outputs in the tri-state mode. Write Input. Active LOW. Starts a new conversion and selects an analog channel via address inputs A0 and A1, in combination with CS. BUSY goes LOW and stays LOW during a conversion. BUSY rises when a conversion is complete and enables the parallel outputs. External Clock Input. The clock speed determines the conversion rate by the equation fCLK = 16 * fSAMPLE. Address Inputs. Selects one of four analog input channels in combination with CS and WR. The address inputs are latched on the rising edge of either RD or WR. A0 0 0 1 1 27 28 VDIG VANA A1 0 1 0 1 Channel Selected AIN0 AIN1 AIN2 AIN3 AIN0 AIN1 AIN2 AIN3 VREF AGND DB11 DB10 DB9 1 2 3 4 5 6 7 8 8 ADS7842E 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VANA VDIG A1 A0 CLK BUSY WR CS RD DB0 DB1 DB2 DB3 DB4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 DB8 10 DB7 11 DB6 12 DB5 13 DGND 14 ABSOLUTE MAXIMUM RATINGS(1) +VCC to GND ........................................................................ -0.3V to +6V Analog Inputs to GND ............................................ -0.3V to +VCC + 0.3V Digital Inputs to GND ........................................................... -0.3V to +6V Power Dissipation .......................................................................... 250mW Maximum Junction Temperature ................................................... +150C Operating Temperature Range ........................................ -40C to +85C Storage Temperature Range ......................................... -65C to +150C Lead Temperature (soldering, 10s) ............................................... +300C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. 22 WR 23 BUSY 24 25, 26 CLK A0, A1 ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION MINIMUM RELATIVE ACCURACY (LSB) 2 " 1 " SPECIFICATION TEMPERATURE RANGE -40C to +85C " -40C to +85C " Digital Supply Input. Nominally +5V. Analog Supply Input. Nominally +5V. PRODUCT ADS7842E " ADS7842EB " SINAD (dB) 68 " 70 " PACKAGE 28-Lead SSOP " 28-Lead SSOP " PACKAGE DRAWING NUMBER(1) 324 " 324 " ORDERING NUMBER(2) ADS7842E ADS7842E/1K ADS7842EB ADS7842EB/1K TRANSPORT MEDIA Rails Tape and Reel Rails Tape and Reel NOTES: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 1000 pieces of "ADS7842E/1K" will get a single 1000-piece Tape and Reel. For detailed Tape and Reel mechanical information, refer to Appendix B of Burr-Brown IC Data Book. (R) ADS7842 4 TYPICAL PERFORMANCE CURVES: +5V At TA = +25C, +VCC = +5V, VREF = +5V, fSAMPLE = 200kHz, and fCLK = 16 * fSAMPLE = 3.2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,123Hz, -0.2dB) 0 -20 0 -20 FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.3kHz, -0.2dB) Amplitude (dB) Amplitude (dB) -40 -60 -80 -100 -120 0 25 50 Frequency (kHz) 75 100 -40 -60 -80 -100 -120 0 25 50 Frequency (kHz) 75 100 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY 74 SNR 73 SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 85 SFDR 80 SFDR (dB) -85 SNR and SINAD (dB) -80 THD (dB) (R) 72 SINAD 71 70 75 THD -75 70 69 68 1 10 Input Frequency (kHz) 100 -70 65 1 10 Input Frequency (kHz) -65 100 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 12.0 CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 0.6 0.4 Delta from +25C (dB) 0.2 0.0 -0.2 -0.4 fIN = 10kHz, -0.2dB -0.6 Effective Number of Bits 11.8 11.6 11.4 11.2 11.0 1 10 Input Frequency (kHz) 100 -40 -20 0 20 40 60 80 100 Temperature (C) 5 ADS7842 TYPICAL PERFORMANCE CURVES: +2.7V At TA = +25C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 * fSAMPLE = 2MHz, unless otherwise noted. FREQUENCY SPECTRUM (4096 Point FFT; fIN = 10.6kHz, -0.2dB) 0 -20 FREQUENCY SPECTRUM (4096 Point FFT; fIN = 1,129Hz, -0.2dB) 0 -20 Amplitude (dB) Amplitude (dB) 0 15.6 31.3 Frequency (kHz) 46.9 62.5 -40 -60 -80 -100 -120 -40 -60 -80 -100 -120 0 15.6 31.3 Frequency (kHz) 46.9 62.5 SIGNAL-TO-NOISE RATIO AND SIGNAL-TO(NOISE+DISTORTION) vs INPUT FREQUENCY 78 SNR 74 SNR and SINAD (dB) 70 90 85 SPURIOUS FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY -90 -85 SFDR 80 -80 -75 -70 THD 65 60 -65 -60 -55 -50 1 10 Input Frequency (kHz) 100 75 70 SFDR (dB) 66 SINAD 62 58 54 1 10 Input Frequency (kHz) 100 55 50 EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY 12.0 11.5 Effective Number of Bits CHANGE IN SIGNAL-TO-(NOISE+DISTORTION) vs TEMPERATURE 0.4 fIN = 10kHz, -0.2dB 0.2 Delta from +25C (dB) 0.0 -0.2 -0.4 -0.6 -0.8 11.0 10.5 10.0 9.5 9.0 1 10 Input Frequency (kHz) 100 -40 -20 0 20 40 60 80 100 Temperature (C) (R) ADS7842 6 THD (dB) TYPICAL PERFORMANCE CURVES: +2.7V (CONT) At TA = +25C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 * fSAMPLE = 2MHz, unless otherwise noted. SUPPLY CURRENT vs TEMPERATURE 400 350 Supply Current (A) 300 250 200 150 100 -40 -20 0 20 40 60 80 100 Temperature (C) Supply Current (nA) POWER DOWN SUPPLY CURRENT vs TEMPERATURE 140 120 100 80 60 40 20 -40 -20 0 20 40 60 80 100 Temperature (C) INTEGRAL LINEARITY ERROR vs CODE 1.00 0.75 0.50 ILE (LSB) 1.00 0.75 0.50 DIFFERENTIAL LINEARITY ERROR vs CODE 0.25 0.00 -0.25 -0.50 -0.75 -1.00 000H DLE (LSB) 800H Output Code FFFH 0.25 0.00 -0.25 -0.50 -0.75 -1.00 000H 800H Output Code FFFH CHANGE IN GAIN vs TEMPERATURE 0.15 0.10 CHANGE IN OFFSET vs TEMPERATURE 0.6 0.4 Delta from +25C (LSB) Delta from +25C (LSB) 0.05 0.00 -0.05 -0.10 -0.15 -40 -20 0 20 40 60 80 100 Temperature (C) 0.2 0.0 -0.2 -0.4 -0.6 -40 -20 0 20 40 60 80 100 Temperature (C) (R) 7 ADS7842 TYPICAL PERFORMANCE CURVES: +2.7V (CONT) At TA = +25C, +VCC = +2.7V, VREF = +2.5V, fSAMPLE = 125kHz, and fCLK = 16 * fSAMPLE = 2MHz, unless otherwise noted. REFERENCE CURRENT vs SAMPLE RATE 14 12 Reference Current (A) 18 16 REFERENCE CURRENT vs TEMPERATURE 10 8 6 4 2 0 0 25 50 75 100 125 Sample Rate (kHz) Reference Current (A) 14 12 10 8 6 -40 -20 0 20 40 60 80 100 Temperature (C) SUPPLY CURRENT vs +VCC 320 300 Supply Current (A) 1M MAXIMUM SAMPLE RATE vs +VCC Sample Rate (Hz) 280 260 240 220 200 180 2 fSAMPLE = 12.5kHz VREF = +VCC 100k 10k VREF = +VCC 1k 2.5 3 3.5 +VCC (V) 4 4.5 5 2 2.5 3 3.5 +VCC (V) 4 4.5 5 (R) ADS7842 8 THEORY OF OPERATION The ADS7842 is a classic successive approximation register (SAR) analog-to-digital (A/D) converter. The architecture is based on capacitive redistribution which inherently includes a sample/hold function. The converter is fabricated on a 0.6s CMOS process. The basic operation of the ADS7842 is shown in Figure 1. The device requires an external reference and an external clock. It operates from a single supply of 2.7V to 5.25V. The external reference can be any voltage between 100mV and +VCC. The value of the reference voltage directly sets the input range of the converter. The average reference input current depends on the conversion rate of the ADS7842. ANALOG INPUTS The ADS7842 features four, single-ended inuts. The input current into each analog input depends on input voltage and sampling rate. Essentially, the current into the device must charge the internal hold capacitor during the sample period. After this capacitance has fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance to a 12-bit settling level within the same period, which can be as little as 350ns in some operating modes. While the converter is in the hold mode, or after the sampling capacitor has been fully charged, the input impedance of the analog input is greater than 1G. EXTERNAL CLOCK The ADS7842 requires an external clock to run the conversion process. This clock can vary between 200kHz (12.5kHz throughput) and 3.2MHz (200kHz throughput). The duty cycle of the clock is unimportant as long as the minimum HIGH and LOW times are at least 50ns and the clock period is at least 125ns. The minimum clock frequency is set by the leakage on the capacitors internal to the ADS7842. BASIC OPERATION Figure 1 shows the simple circuit required to operate the ADS7842 with Channel 0 selected. A conversion can be initiated by bringing the WR pin (pin 22) LOW for a minimum of 25ns. BUSY (pin 23) will output a LOW during the conversion process and rises only after the conversion is complete. The 12 bits of output data will be valid on pin 713 and 15-19 following the rising edge of BUSY. ADS7842 0V to VREF 1 2 3 4 2.5V + 5 2.2F 6 7 8 9 AIN0 AIN1 AIN2 AIN3 VREF AGND DB11 DB10 DB9 VANA 28 VDIG 27 A1 26 A0 25 CLK 24 BUSY 23 WR 22 CS 21 RD 20 DB0 19 DB1 18 DB2 17 DB3 16 DB4 15 Read Input 3.2MHz Clock BUSY Output Write Input + 0.1F + +5V Analog Supply 10F 10 DB8 11 DB7 12 DB6 13 DB5 14 DGND FIGURE 1. Basic Operation of the ADS7842. (R) 9 ADS7842 STARTING A CONVERSION A conversion is initiated on the rising edge of the WR input, with valid signals on A0, A1, and CS. The ADS7842 will enter the conversion mode on the first rising edge of the external clock following the WR pin going LOW. The ADS7842 will start the conversion on the 1st clock cycle. The MSB will be approximated by the Capacitive Digital-toAnalog Converter (CDAC) on the 1st clock cycle, the 2nd MSB on the 2nd cycle, and so on until the LSB has been decided on the 12th clock cycle. The BUSY output will go LOW 20ns after the falling edge of the WR pin. The BUSY output will return HIGH just after the ADS7842 has finished a conversion and the data will be valid on pins 7 - 19. The rising edge of BUSY can be used to latch the data. It is recommended that the data be read immediately after each conversion. The switching noise of the asynchronous data transfer can cause digital feedthrough degrading the converter's performance. See Figure 2. READING DATA Data from the ADS7842 will appear at pins 7 - 13 and 15 - 19. The MSB will output on pin 7 while the LSB will output on pin 19. The outputs are coded in Straight Binary (with 0V = 000Hand V REF = FFF H, see Table IV). Following a conversion, the BUSY pin will go HIGH. After BUSY goes HIGH, the CS and RD pins may be brought LOW to enable the 12-bit output bus. CS and RD must be held LOW for at least 25ns seconds following BUSY HIGH. Data will be valid 25ns seconds after the falling edge of both CS and RD. The output data will remain valid for 25ns seconds following the rising edge of both CS and RD. See Figure 4 for the read cycle timing diagram. POWER-DOWN MODE The ADS7842 has two different power-down modes: sleep and nap. In the sleep mode, all analog and digital circuitry have been switched off. In the nap mode, the voltage reference remains on while all remaining circuitry is switched off. The simplest way to use the power-down mode is following a conversion. After a conversion has finished and BUSY has returned HIGH, CS and RD must be brought LOW for a minimum of 25ns. When CS and RD are both returned HIGH, the ADS7842 will enter the power-down mode on the rising edge of the RD pin. Depending on the status of the A0 and A1 address pins, the ADS7842 will either enter the nap or sleep mode (refer to Table III and Figure 5 for more details). The typical supply current of the ADS7842 with a 5V supply and a 500kHz sampling rate is 2.6mA. In the nap mode, the typical supply current is 600A. In the sleep mode, the current is reduced to 10A typically. In order to return the ADS7852 to normal operation following either power-down mode, the CS and RD pins must be toggled from HIGH to LOW a second time. On the second rising edge of RD, the ADS7842 will exit the power-down mode and enter the sampling mode. See Figure 6. SYMBOL tCONV tACQ tCKP tCKL t CKH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 DESCRIPTION Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH CS to WR Setup Time Address to CS Hold Time CS LOW CLK to WR Setup Time CS to BUSY LOW CLK to WR LOW CLK to WR HIGH WR to CLK LOW Address Hold Time Address Setup Time BUSY to RD Delay CLK LOW to BUSY HIGH BUS Access BUS Relinquish Address to RD HIGH Address Hold Time RD HIGH to CLK LOW MIN TYP MAX UNITS 3.5 1.5 300 150 150 150 0 25 25 20 5 25 25 5 5 0 10 25 25 2 2 50 s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TABLE I. Timing Specifications (+VCC = +2.7V to 3.6V, TA = -40C to +85C, CLOAD = 50pF). SYMBOL tCONV tACQ tCKP tCKL t CKH t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 DESCRIPTION Conversion Time Acquisition Time Clock Period Clock LOW Clock HIGH CS to WR Setup Time Address to CS Hold Time CS LOW CLK to WR Setup Time CS to BUSY LOW CLK to WR LOW CLK to WR HIGH WR to CLK LOW Address Hold Time Address Setup Time BUSY to RD Delay CLK LOW to BUSY HIGH BUS Access BUS Relinquish Address to RD HIGH Address Hold Time RD HIGH to CLK LOW MIN TYP MAX UNITS 3.5 1.5 300 150 150 150 0 25 25 20 5 25 25 5 5 0 10 25 25 2 2 50 s s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns TABLE II. Timing Specifications (+VCC = +4.75V to +5.25V, TA = -40C to +85C, CLOAD = 50pF). (R) ADS7842 10 CS 0 0 RD WR X X BUSY 1 X A0 1 0 A1 X X COMMENTS Sleep Mode Nap Mode DESCRIPTION Least Significant Bit (LSB) Full Scale Midscale Midscale -1LSB Zero Full Scale ANALOG INPUT 1.2207mV 4.99878V 2.5V 2.49878V 0V DIGITAL OUTPUT STRAIGHT BINARY BINARY CODE 1111 1000 0111 0000 1111 0000 1111 0000 1111 0000 1111 0000 HEX CODE FFF 800 7FF 000 means rising edge triggered. X = Don't care. TABLE III. Truth Table for Sleep and Nap Modes. Table IV. Ideal Input Voltages and Output Codes. CS Latching in Address for Next Channel WR Conversion CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Sample 15 16 BUSY RD A0 A1 FIGURE 2. Normal Operation, 16 Clocks per Conversion. CS t1 WR t6 CLK tCKL t5 BUSY t10 A0, A1 N + 1(1) t9 t4 t8 t7 t3 t2 NOTE: (1) Addresses for next conversion (N + 1) latched in with rising edge of current WR (N). FIGURE 3. Initiating a Conversion. (R) 11 ADS7842 CS t1 RD t3 t2 CLK t12 t11 BUSY n-1 Conversion n t10 A0 t13 DB0-DB11 t14 DATA VALID t9 To prevent PWD A0 must be 0 NOTE: Internal register of current conversion updated 1/2 clock cycle prior to BUSY going HIGH. FIGURE 4. Read Timing Following a Conversion. CS t1 t3 RD t2 CLK t12 BUSY t15 A0 NOTE: Rising edge of RD while A0 = 1 initiates power down immediately. t16 t11 FIGURE 5. Entering Power-Down Using RD and A0. CS t1 t3 RD t17 CLK t2 A0 t15 t16 NOTE: Rising edge of 2nd RD while A0 = 0 places the ADS7842 in sample mode. FIGURE 6. Initiating Wake-Up Using RD and A0. (R) ADS7842 12 |
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