View AT76C713_974965.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Features
* Advanced RISC Architecture, 130 Powerful Instructions, Most Single-Clock Cycle
Execution
* Clock Generator Provides CPU Rates up to 48 MHz * Only One External Clock Crystal of 12 MHz Can Generate All the Required System
Clocks: - Internal Clock for Standard UART Rates - A 48 MHz and 96 MHz Clock for USB Data Recovery - AVR Processor and System Clock Full-speed USB Interface (12 Mbits per Second) 2.0 Compliant JTAG (IEEE std. 1149.1 compliant) Interface - Boundary-Scan Capabilities According to the JTAG Standard - Extensive On-Chip Debug Support Two On-chip 16550 UARTs Supporting Baud Rates up to 921 Kbaud - Both UARTs Incorporate Individual Transmit and Receive FIFOs of 16 Bytes - UART0 Supports Modem Control Signals Programmable SPI Interface On-chip Bootstrap ROM Provides a Variety of Firmware Upgrade Modes - Device Firmware Upgrade Through USB for the Internal Program SRAM (No External Non-volatile SPI Memory Required) - Device Firmware Upgrade Through USB for both the Internal Program SRAM and the External SPI DataFlash(R) or EEPROM - SPI Program Mode from the External DataFlash or EEPROM External Memory Interface Supporting up to 32 Kbytes of External RAM in Address Multiplexed Mode, 2 Banks of 256 Bytes in Non-multiplexed Mode, FIFO, or with an Extra 20 GPIOs DMA Channels Allow Fast Data Transfers between Endpoint Buffers and Internal or External SRAM (DMA Transfer Rate is 12 MHz for All Channels) 8K x 16 bits (up to 11K x 16 Bits), In-System SRAM for Program Code (Program Memory) On-chip 8 Kbytes SRAM for Data and Variables (2, 4, or 6 Kbytes can be Remapped for Program Storage in the Address Area Above the Program Memory Two 8-bit Timer/Counters One 16-bit Timer/Counter Four External Interrupts Through GPIOs Programmable Watchdog Timer Low Voltage Operation: - 1.8V for the Core - 1.8V or 3.3V for the Periphery - 3.3V for the USB 100-pin TQFP Package Applications - Programmable USB-to-Serial Bridge for RS-2332 Devices (Cell Phones, Printers, PDAs, etc.) - IrDA Control over USB - USB Memory Sticks - General High-speed Microcontroller Application
* *
*
* *
High-speed (48 MHz) AVR(R) Microcontroller with USB Interface AT76C713
*
* * * * * * * *
* *
5665B-USB-04/05
ATMEL CONFIDENTIAL
ATMEL CONFIDENTIAL
1. Overview
The AT76C713 is a low-power, high performing USB 2.0 full-speed microcontroller providing advanced features for USB peripherals. It combines a number of functions required in such a device, including the following: The device is based on the AVR-enhanced RISC architecture core, which combines an advanced instruction set with 32 general-purpose working registers. By executing powerful instructions in a single clock cycle, the AT76C713 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize the power consumption versus the processing speed The clock generation circuit requires a clock input of 12 MHz and provides standard clock rates for the USB module and the on-chip UARTs, as well as several AVR CPU rates varying from 16 MHz up to 48 MHz Internal DMA channels allow fast data transfers between the USB buffers and the external or the on-chip memory without processor interruption. USB DMA transfers use devoted data paths with a 12 Mbytes transfer rate An on-chip flexible memory controller allows dynamic memory mapping and provides the required timing for interfacing with slow or fast external memory devices, like SRAM or FIFOs Five multipurpose I/O ports, PORT(A-E), provide the signals for all the serial and parallel interfaces. Programmable strobe signals are provided for external FIFO access. In addition, the AT76C713 supports various power-down modes and offers four external interrupts, a programmable Watchdog Timer, and flexible Timer/Counters with compare modes On power-up, the bootstrap code is executed from the boot ROM. The purpose of the bootstrap code is to load the application code into the program memory. The application code is executed from the on-chip SRAM program memory, contributing to the low-power consumption. Different programming modes are supported, depending on the application (that is, the mode is selected externally by the PMODE0 and PMODE1 pins) In the slave programming mode, an external system (that is, the Host), operating as SPI master, can transfer the program image in a raw format to the program memory of the device. In this case, the AT76C713 operates as an SPI slave and starts running from the internal boot ROM code, which switches to the start of program memory when it detects the end of a valid program transfer from the Host to the AT76C713 In the master programming mode, the AT76C713 reads the whole program image from an external serial EEPROM or DataFlash(R) and switches to the start of the program memory when it completes this reading. Alternatively, the AT76C713 reads only configuration parameters from a small serial non-volatile memory (EEPROM or DataFlash), enables the USB Controller, and executes the USB Device Firmware Upgrade (DFU) code that is stored in the boot ROM The USB Controller consists of a Serial Interface Engine (SIE), a Function Interface Unit (FIU), and a System Interface (SI). The SIE performs bit processing, line coding, packet generation, packet type recognition, serial-parallel data conversion, and packet delineation. The FIU consists of a protocol engine and a USB device with one Control Endpoint (EP0) and four programmable Endpoints with up to 512 bytes maximum total size. All Endpoints support double buffering in order to provide the maximum performance specified for the USB The AT76C713 supports two 16550 UART modules with 16 bytes FIFOs in each direction. The UART0 serial interface provides full modem control functionality with the RTS/CTS, DTR/DSR, RI, and CD signals. These signals are provided by the general-purpose I/O pins of PORTD 2
AT76C713
5665B-USB-04/05
AT76C713
The AT76C713 AVR is supported with a full suite of program and system development tools, including: C compiler, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits
2. AT76C713 Functional Diagram
LFT XIN XOUT Program Memory Controller Boot ROM 8Kx16bits SRAM Clock Generator I/O Mapped modules WD Timer
JTAG TAP OCD
PM0 PM1 nRST SUSP USB_ATTACH nCS[0:1] nFWR nFRD PA[7:0]/AD[7:0] PB0/T0 PB1/T1 PB2/T2 PB3/ICP PB4/nSS PB5/MOSI PB6/MISO PB7/SCK PC[7:0]/A[14:8], ALE/A[7:0] PD0/SIN0 PD1/SOUT0 PD2/ RTS PD3/CTS PD4/DSR PD5/ DTR PD6/CD PD7/RI PE0 /SIN1 PE1/SOUT1 PE2/INT0 PE3/INT1 PE4/INT2 PE5/INT3 PE6/nWR PE7/nRD
TESTEN TEST_CK
FIFOs
Memory Controller DP, DM DMA USB Controller Controller FIFOs Memory Mapped modules SRAM 8Kbytes
UART0 UART1
IrDA 1.0
ATMEL CONFIDENTIAL
5665B-USB-04/05
Boundary Scan Chain (JTAG)
TMS TCK TDI TDO
Timers AVR core Register File SPI Controller
Port Interface
3
ATMEL CONFIDENTIAL
3. Pin Diagram
3.1 100-pin TQFP Package
N/C N/C PVDD TEST_CLK TEST_EN PB0/T0 PB1/T1 PA0 PA1 PA2 CVDD nFRD nFWR nCS0 nCS1 CGND JS_TDO JS_TDI JS_TMS JS_TCK USB_ATTACH PVDD PGND N/C PGND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
N/C N/C PGND nRST CVDD PE7/nRD PE6/nWR PE5/nINT3 PE4/nINT2 PE3/nINT1 PE2/nINT0 PE1/SOUT1 PE0/SIN1 PVDD PMODE0 PMODE1 CGND PGND LFT PAGND XIN XOUT PAVDD N/C PAVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
PVDD N/C PA3 PA4 PA5 PA6 PA7 PVDD_USB DM DP SUSP CGND PGND CVDD PD0/SIN0 PD1/SOUT0 PD2/RTS PD3/CTS PD4/DSR PD5/DTR PD6/CD PD7/RI PVDD_PORTD N/C PGND
4
AT76C713
5665B-USB-04/05
PAGND VEXT POR_VSEL PVDD PC7/ALE PC6/A14 PC5/A13 CGND PC4/A12 PC3/A11 PC2/A10 PC1/A9 PC0/A8 CVDD PB7/SCK PB6/MISO PB5/MOSI PB4/nSS PB3/ICP PB2/T2 PVDD PGND N/C N/C PVDD
AT76C713
4. Pin Summary - Pin Assignment
Table 4-1.
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
Pin Summary - Pin Assignment
Pin Name N/C N/C PGND nRST CVDD PE7/nRD PE6/nWR PE5/nINT3 PE4/nINT2 PE3/nINT1 PE2/nINT0 PE1/SOUT1 PE0/SIN1 PVDD PMODE0 PMODE1 CGND PGND LFT PAGND XIN XOUT PAVDD N/C PAVDD PAGND VEXT POR_VSEL PVDD PC7/ALE PC6/A14 PC5/A13 CGND PC4/A12 Pin # 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Pin Name PC3/A11 PC2/A10 PC1/A9 PC0/A8 CVDD PB7/SCK PB6/MISO PB5/MOSI PB4/nSS PB3/ICP PB2/T2 PVDD PGND N/C N/C PVDD PGND N/C PVDD_PORTD PD7/RI PD6/CD PD5/DTR PD4/DSR PD3/CTS PD2/RTS PD1/SOUT0 PD0/SIN0 CVDD PGND CGND SUSP DP DM PVDD_USB Pin # 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name PA7 PA6 PA5 PA4 PA3 N/C PVDD PGND N/C PGND PVDD USB_ATTACH TCK TMS TDI TDO CGND nCS1 nCS0 nFWR nFRD CVDD PA2 PA1 PA0 PB1/T1 PB0/T0 TEST_EN TEST_CLK PVDD N/C N/C
ATMEL CONFIDENTIAL
5665B-USB-04/05
5
ATMEL CONFIDENTIAL
5. Signal Description
Table 5-1. Signal Description Type: I = Input, O = Output, I/O = Bi-directional, A = Analog Signal
Name JTAG Signals TCK TDI TDO TMS Port Signals Port A is used in configurations with external memory, where it acts as the AD0-7 address and/or data bus. If the alternative function of the port is not used, Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors. Port A output buffers can sink 20 mA and can drive the LED displays directly. Port A pins that are externally pulled low will source current. The Port A pins are inputs when a reset condition becomes active, even if the clock is not running. The high nibble of port B (PB[7-4]) offers the signals for the SPI interface. The low-nibble (PB[3-0]) is used from the three internal timers as trigger and capture inputs. These functions can operate regardless the direction of the PB[3-0] pins. Port B serves also as an 8-bit bi-directional I/O port with internal pull-up resistors, if the alternative functions of the port are not used. The Port B output buffers can sink 20 mA and can drive LED displays directly. As inputs, Port B pins that are externally pulled low will source current. The Port B pins are inputs when a reset condition becomes active, even if the clock is not running. The alternative functions of Port B are explained in more details at the following table and at the proper sections. I I O I JTAG clock input Scan chain bitstream input Scan chain bitstream output JTAG mode select input Type Description
PA[0:7]
B
Alternative Functions of Port B
PB[0:7] B Port PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 Alternate Function T0: Timer/Counter 0 clock input T1: Timer/Counter 1 clock input T2: Timer/Counter 2 clock input ICP1: Input Capture Pin for Timer/Counter1 nSS: SPI slave port select input MOSI: SPI slave port select input MISO: SPI master data in, slave data out SCK: SPI master clock out, slave clock in
PC[0:7]
B
Port C is used in configurations with external memory, where it acts as the address bus bits A8-15 and ALE in a multiplexed address mode and A0-7 in a non-multiplexed mode. If the alternative functions of the port are not used, Port C also serves as an 8-bit bi-directional I/O port with internal pull-up resistors.The Port C output buffers can sink 20 mA and can drive the LED displays directly. Port C pins that are externally pulled low will source current. The Port C pins are inputs when a reset condition becomes active, even if the clock is not running.
6
AT76C713
5665B-USB-04/05
AT76C713
Table 5-1. Signal Description (Continued) Type: I = Input, O = Output, I/O = Bi-directional, A = Analog Signal
Name Type Description Port D offers the data and handshaking signals for UART0 interface, as listed below. When the UART0 is not used, PORT D is also an 8-bit bi-directional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. Port D pins that are externally pulled low will source current. The Port D pins are inputs when a reset condition becomes active, even if the clock is not running.
Alternative Functions of Port D
Port PD0 PD[0:7] B PD1 PD2 PD3 PD4 PD5 PD6 PD7 Alternate Function SIN0, Serial In UART0 (I): This pin provides the serial receive data input to UART0 SOUT0, Serial Out UART0 (O): This pin provides the serial transmit data from the UART0 nRTS, Ready To Send (B): RTS UART0 handshaking signal nCTS, Clear To Send (B): CTS UART0 handshaking signal nDSR, Data Set Ready (B): DSR UART0 handshaking signal nDTR, Data Terminal Ready (B): DTR UART0 handshaking signal nCD, Carrier Detect (B): CD UART0 handshaking signal nRI, Ring Indicator (B): RI UART0 handshaking signal
Port E offers the data signals for the UART1 interface, offers 4 external interrupt lines (edge triggered or level sensitive external interrupt) and the nWR/nRD signals for configurations with external memory. If the alternative functions are not used, PORT E serves as an 8-bit bi-directional I/O port with internal pullup/down resistors. Pins PE2 and PE3 have pull-down resistors while the rest pins have pull-up resistors. The output buffers of Port E pads can sink 20 mA. Port E pins that are externally pulled low (or high for PE2 and PE3 pins) will source current. The Port E pins are inputs when a reset condition becomes active, even if the clock is not running.
Alternative Functions of Port E
Port PE[0:7] B PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 Alternate Function SIN1, Serial In UART1 (I): This pin provides the serial receive data input to UART1. SOUT1, Serial Out UART1 (O): This pin provides the serial transmit data from the UART1 INT0, edge-triggered or level sensitive interrupt with pull-down INT1, edge-triggered or level sensitive interrupt with pull-down INT2, edge-triggered or level sensitive interrupt with pull-up INT3, edge-triggered or level sensitive interrupt with pull-up nWR nRD
ATMEL CONFIDENTIAL
5665B-USB-04/05
7
ATMEL CONFIDENTIAL
Table 5-1. Signal Description (Continued) Type: I = Input, O = Output, I/O = Bi-directional, A = Analog Signal
Name Type Description
USB Serial Interface DP DM USB_ATTACH I/O I/O O USB data I/O (positive differential line). DP and DM form the differential signal pin pair connected to the Host Controller or an upstream Hub. USB data I/O (negative differential line) This output controls the pullup resistor of the DP signal. When low, it enforces the host to re-enumerate the device.
Programming Mode Control Signals PMODE0 PMODE1 Test Signals TEST_EN TEST_CLK POR_VSEL VEXT Other Signals nRST SUSP nCS0 nCS1 nFWR nFRD XIN XOUT LFT Power Supply pins CGND CVDD PGND PVDD PVDD_PortD PVDD_USB PAGND PAVDD Power Power Power Power Power Power Power Power 0 Volts supply to the core 1.8 Volts supply to the core 0 Volts supply to the external section of the I/O circuitry 1.8V or 3.3 Volts supply to the external section of the I/O circuitry 1.8V or 3.3 Volts supply to the external section of the Port D I/O circuitry 3.3 Volts supply for the USB and SUSPEND pins 0 Volts Analog supply to the core, AC and DC sections of the I/O circuitry 1.8 Volts Analog supply to the core, AC and DC sections of the I/O circuitry I O O O O O I O A Reset input. A low on this pin for two clock cycles while the oscillator is running resets the device. Note that there is no internal pull-up resistor on this pin. Indicates if the IC is in power down mode External Memory Chip Select 0 External Memory Chip Select 1 External FIFO Write External FIFO Readl System clock oscillator pad, input to the inverting oscillator amplifier and input to the internal system clock operating circuit. System clock oscillator pad, output from the inverting oscillator amplifier. An external RC filter should be connected to this pin to stabilize the lock-in time of the internal PLL for the master clock input XIN.Main PLL LFT input I I I I General-purpose signal for test. Tied to VSS in normal conditions. Used only for production setting. Tied to VSS in normal conditions. Used in production phase only. Tied to VSS in normal conditions. Used in production phase only. Tied to 1.8V in normal conditions. I PMODE0 and PMODE1 pins are used from the on-chip bootstrap code and define the programming mode. For more details refer to the Program Modes section.
8
AT76C713
5665B-USB-04/05
AT76C713
6. Functional Description
6.1 Bootstrap ROM and Programming Modes
The bootstrap code in the boot ROM of the AT76C713 is always activated on power-up or after a system reset. The functionality of the bootstrap code is configured by pins PMODE0 and PMODE1. In the SPI master programming modes, the AT76C713 is master over the SPI interface and can support an external EEPROM or DataFlash. The SPI slave programming mode is useful in a system where an external host is present and keeps the image code for the AT76C713 in its own memory.
Table 6-1.
PMODE0 0 0 1 1
Programming Modes
PMODE1 0 1 0 1 Programming Mode USB DFU only (SPI disabled) SPI Slave: SPI master host must be present SPI Master: SPI serial EEPROM is assumed SPI Master: SPI DataFlash is assumed
6.1.1
USB DFU-only Mode When both the PMODE0 and PMODE1 pins are tied low, the bootstrap code will not enable the USB controller but not the SPI controller. The system will wait for a USB DFU sequence using the default USB descriptors stored in the boot ROM. Slave Programmming Mode When the PMODE0 pin is tied low and the PMODE1 pin is tied high, the bootstrap ROM configures the SPI as a slave and waits for a specific sequence of data through the SPI. The sequence is as follows 1. The nSS pin is enabled. 2. The Configuration Header (256 bytes) is transmitted. 3. Image of the code to be stored in program memory is transmitted, starting from address 0. (The code size is determined in the Configuration Header.) 4. The nSS pin is disabled and re-enabled. 5. Confirmation byte 1 is transmitted. 6. Confirmation byte 2 is transmitted. 7. The nSS pin is disabled
6.1.2
ATMEL CONFIDENTIAL
5665B-USB-04/05
9
ATMEL CONFIDENTIAL
Figure 6-1. Slave Programming Mode Sequence
Configuration
Data transfer Image Code Data
Confirmation
MISO MOSI nSS
Config. Header
C1 C1
C2 C2
(8-bit Received Data Counter)
During the transmission of the configuration data and code image, the AT76C713 returns an 8bit counter value that counts the received bytes. Thus, the Host can verify if the AT76C713 has received the correct amount of data. During the first confirmation cycle, the SPI master sends $CA to command "Continue Analyzing" or $AB to command "Abort". The SPI slave will return "Data was OK" by sending $D0 or "Error" by sending $EE. During the second confirmation cycle, the SPI master data is ignored and the SPI slave sends the positive acknowledgment $AD "Analyzing Data", or one of the following error messages: $DD "Discarding data", $DE "Discarding due to transmission error", or $EE "Error in confirmation command". Table 6-2. Possible Cases of Programming during the Slave Program Mode
Case Master Cycle 1 Slave Master Cycle 2 Slave Programming $AD OK $DD Fail $DE Fail $EE Fail $D0 xx $D0 xx $EE xx xx xx 1 $CA 2 $AB 3 xx 4 Invalid
If the slave programming sequence fails, then the AT76C713 will enable the USB controller waiting for the DFU sequence, using the default USB descriptors. 6.1.3 Master Programming Modes When the PMODE0 pin is tied high, the bootstrap ROM configures the SPI as a master and is prepared to communicate either with a serial EEPROM if PMODE1 is tied low, or with a DataFlash if PMODE1 is tied high. The AT76C713 supports any Atmel EEPROM of the AT25xxx type (for example, AT25040) and Dataflash of the AT45xxx type. The first 256 bytes that are read by the EEPROM or DataFlash are known as the configuration header, which contains useful information for the rest of the downloading procedure. The bytes fetched from the external serial memory may be an image code or configuration parameters. If the bytes are an image code, after data fetching is complete the program running in the boot ROM resets the AVR program counter and switches to the SRAM program memory by setting the remap bit in the memory access interface.
10
AT76C713
5665B-USB-04/05
AT76C713
If the data fetched from the external serial memory is configuration parameters only, the bootstrap code of the boot ROM will not switch to the program memory at the end of data fetching. Instead, it will enable the USB controller. The USB will enumerate using the descriptors loaded from the SPI memory. Upon enumeration completion, if a DFU application is enabled in the host, then the bootstrap ROM will support program storing in the program memory through the USB. When program storing is complete, the device will switch to the program memory. 6.1.4 Configuration Header The Configuration Header is at least 256 bytes length and consumes the first page of the SPI memory. For systems that use SPI slave programming or SPI EEPROM memory (for example, AT25128A), the Configuration Header length is fixed to 256 bytes. For systems that use SPI DataFlash, the page size is equal to the page size of the used DataFlash. For example, using the AT45DB011B, the page size is 264 bytes and thus, the Configuration Header will consume 264 bytes. The meaning of each byte is described in Table 6-3. Table 6-3.
Byte 0 1 2 3 4 5
Configuration Header
Description $55 $AA Size[7:0] Size[15:8] Control Byte MEMMAP Device descriptor Configuration descriptor
6
CIS[ ] Serial descriptor Product descriptor
The first 2 bytes must be $55 and $AA in order to detect the rest of the information as valid. If those bytes are invalid, then the bootstrap code rejects the operation immediately and starts the USB DFU procedures. Size[15:0] is the length of the image code counted in pages. During the slave programming mode and the SPI EEPROM master programming mode, each page is 256 bytes long. The control bitmap (or control byte) is described in Table 6-4.
Table 6-4.
Control Bitmap
Control Byte
Bit 7 6 5
Field WSOF -- PLCK Wait USB SOF. Reserved to zero (`0').
Description
If set, then don't use the PLL Lock signal (see also the PLCK bit of "Clock Control Register (CLK_CNTR)" on page 51).
ATMEL CONFIDENTIAL
5665B-USB-04/05
11
ATMEL CONFIDENTIAL
Table 6-4. Control Bitmap
Control Byte Bit 4 3 2 1 0 Note: Field REMAP STDBY INTPROT DTCH SUSP Description If set, then remap right after the downloading of the image code is successful. If set, use for sleep state in suspend mode the stand-by mode instead of powerdown mode. Interrupt Protect. Detach Enable: If set, detach before remap. If set the Suspend Circuit is on.
Bits 7, 3, 2, 1 and 0 affect only the bootstrap USB DFU process
MEMMAP byte will be assigned immediately to the MEMMAP register (see MEMMAP description in the "Memory Access Interface" on page 15). This register configures the size of the program memory and data memory. CIS[ ] is a table that carries the USB descriptors. Each descriptor starts right after the end of the previous one. The order is shown in Table 6-3. The remaining bytes from the end of the CIS[ ] table up to the end of the page have no meaning.
Note: If the Remap bit of the control byte is cleared, then the image code will be loaded into the AT76C713 program memory (see Size[15:0]), the system will not remap, and the bootstrap code will enable the USB core and enumerate using the new USB descriptors (CIS[ ]) instead of the default USB descriptors.
6.2
AVR Core
The AT76C713 chip is based on the AVR core architecture. All peripherals, apart from SPI, IrDA, and timers, are memory mapped to the data address space.
6.2.1
Interrupt Handling The interrupt vector table of the AT76C713 is shown in Table 6-5.
Table 6-5.
Vector Number 1 2 3 4 5 6 7 8 9 10 11
Interrupt Vector Table of the AT76C713
Program Address $0000 $0002 $0004 $0006 $0008 $000A $000C $000E $0010 $0012 $0014 Source RESET SUSP_RESM USB INT0 INT1 INT2 INT3 TIMER2_OVF TIMER1_CAPT TIMER1_COMPA TIMER1_COMPB Interrupt Definition H/W Pin and Watchdog Reset USB Suspend and Resume USB H/W & USB DMA Interrupt External Interrupt Request 0 External Interrupt Request 1 External Interrupt Request 2 External Interrupt Request 3 Timer/Counter2 Overflow Timer/Counter1 Capture Event Timer/Counter1 Compare Match A Timer/Counter1 Compare Match B
12
AT76C713
5665B-USB-04/05
AT76C713
Table 6-5.
Vector Number 12 13 14 15 16 Note:
Interrupt Vector Table of the AT76C713
Program Address $0016 $0018 $001A $001C $001E Source TIMER1_OVF TIMER0_OVF SPI_STC UART0_IRQ UART1_IRQ Interrupt Definition Timer/Counter1 Overflow Timer/Counter0 Overflow SPI Serial Transfer Complete UART0 Interrupt Request UART1 Interrupt Request
The program memory word length is 16-bits wide.
6.3
Oscillator and Clock Generator
The AT76C713 clock generation circuit is based on a single clock input from an external 12 MHz crystal connected to the oscillator pad. All internal clocks are generated by multiplying this clock input incorporating an on-chip PLL. The output of the PLL can be configured in 96 MHz (default) or 192 MHz. In order to produce the desired clocks, the clock generator circuit divides the PLL output. Generating and then dividing a high frequency PLL output reduces the impact of jitter imported by the PLL. An elaborate gobbling circuit produces a 14.769 MHz clock from the PLL output, which can support all standard baud rates with an acceptable frequency error. Figure 6-2. AT76C713 Clock Generation Tree
CLK_CNTR.PLCK PLL Lock XTAL 12MHz CLK_CNTR.OSC_NSLP O S C P L L Delay 96or 192M Hz /2 M U X M 96MHz U X /32 /2 CLK_CNTR.NPCIP CLK_CNTR.PIVOC1 CLK_CNTR.MUL16 CLK_CNTR.MUL16 /4 /5 /6 M U X 2/13 3MHz 48MHz 96MHz 14.769MHz
PLL Stable
WDT USB UARTs System (AVR,etc)
CLK_CNTR.MCSP1.0
6.3.1
PLL LFT Pin Figure 6-3 shows the circuit that must be attached to an LFT pin. The circuit consists of R1 = 330 , C1 = 33nF, and C2 = 3.3nF.
ATMEL CONFIDENTIAL
5665B-USB-04/05
13
ATMEL CONFIDENTIAL
Figure 6-3. LFT Pin Circuit
LFT
R1 330 Ohm C2 3.3nF C1 33nF
6.4
Memory Map
Base Address $FF00 $F800 $F300 $F200 $F000 $A000 External Memory (Application Specific) $2000 Internal SRAM Bank 6,7 $1800 Internal SRAM Bank 4,5 $1000 Internal SRAM Bank 2,3 $0800 Internal SRAM Bank 0,1 $0060 $0020 $0000 I/O Registers AVR Core Registers Min. Internal Data Memory Registers Max. Internal Data Memory External Data Memory UART0 USB Module Program Memory Controller Memory Access Interface UART1 Memory Mapped Peripherals Description
14
AT76C713
5665B-USB-04/05
AT76C713
Table 6-6. Memory Map
Address Space $FF00-$FF04 $F800-$F802 $F300-$F30C $F200-$F20C $F000-$F0FD (End of Internal SRAM)-$7FFF $1800-$1FFF $1000-$17FF $0800-$0FFF $0060-$07FF $0020-$005F $0000-$001F Size (Bytes) 5 3 13 13 254 (Application specific) 2048 2048 2048 2048 64 32 Module Program memory controller (PMC) Memory access interface UART1 UART0 USB External SRAM Internal SRAM bank 3 Internal SRAM bank 2 Internal SRAM bank 1 Internal SRAM bank 0 I/O registers AVR registers
6.5
Memory Access Interface
The memory access interface consists of the memory remapping interface and the external memory interface.
6.5.1
Memory Remapping Interface On power-up, the device has 11K words (22K x 8) of program SRAM and 2 Kbytes of Data SRAM. Utilizing the MEMMAP register (allocated in $F800 Data Memory address), it is possible to resize the two memory spaces. The last three 2-Kbyte banks of program memory can be reallocated and used as data memory and vice versa. According to Table 6-7, there are three possible options: 1. To remap the last 2 Kbytes (data banks 6 and 7) 2. To remap the last 4 Kbytes (data banks 4 to 7) 3. To remap the last 6 Kbytes (data banks 2 to 7) Figure 6-4 and Table 6-7 illustrate the remapping.
ATMEL CONFIDENTIAL
5665B-USB-04/05
15
ATMEL CONFIDENTIAL
Figure 6-4. Memory Remapping
Data Memory 8
Program Memory 16 8 8K Program Memory 1 Program SRAM Bank 0,1 (dedicated) 8 Data Memory 6 8 Data Memory 4 8 Data Memory 2
8K Program Memory 0
1K 8 1K Data Memory 0 Data SRAM bank 0,1 (dedicated) 8 1K Data Memory 1 1K Data SRAM bank 2,3 1K 8 Data Memory 2 8 Data Memory 3 1K 1K
8 Data Memory 7 8 Data Memory 5 8 Data Memory 3
1K 1K 1K
Program SRAM Bank 2, 3 (Data SRAM Bank 7, 6) Program SRAM Bank 4, 5 (Data SRAM Bank 5, 4) Program SRAM Bank 6, 7 (Data SRAM Bank 3, 2)
8 1K Data Memory 4 Data SRAM bank 4,5 1K 8 Data Memory 5
8 1K Data Memory 6 Data SRAM bank 6,7 8 1K Data Memory 7
Table 6-7.
Memory Map Allocation Cases
Data Banks Allocated to Data Memory Space 0 2 4 6
MEMMAP Register value 1 3 5 7
Data Address Space $0000-$07FF (2 Kbytes) $0000-$0FFF (4 Kbytes) $0000-$17FF (6 Kbytes) $0000-$1FFF (8 Kbytes)
Program Address Space $8000-$D7FF (22 Kbytes) $8000-$CFFF (20 Kbytes) $8000-$C7FF (18 Kbytes) $8000-$BFFF (16 Kbytes)
16
AT76C713
5665B-USB-04/05
AT76C713
6.5.2 External Memory Interface (EMI) The external memory can have various configurations and can be accessed by either the AVR core or the USB DMA Controller (see also the "USB DMA Controller" on page 19). The PERIPHEN I/O register (EMIEN bit) (see description on page 52) enables and disables the external memory interface. The registers that control the external memory access by the AVR core are located in the I/O space and named EMICRA and EMICRB. The registers that control the external memory access by the USB DMA controller are located in the memory space and named DMA_EMICRA, DMA_EMICRB.
Table 6-8.
Register EMICRA
The EMI Registers
Offset Address $1C ($3C) ($F801) $1D ($3D) ($F802) Function Controls the external memory access by the AVR core Controls the external memory access by the USB DMA controller Controls the external memory access by the AVR core Controls the external memory access by the USB DMA controller
DMA_EMICRA EMICRB DMA_EMICRB
The bit position of the two register pairs, EMICRA with DMA_EMICRA and EMICRB with DMA_EMICRB, are identical. The EMD0/1 bits select the external memory interface mode, according to Table 6-9.
Table 6-9.
EMD1 0 0 1 1
EMDO/1 Bits
EMD0 0 1 0 1 External Memory Interface Mode FIFO Reserved Demultiplexed Multiplexed
There are three control signals related to the control bits: * The read signal (nRD or nFRD) controlled by RW0/1 and RM0/1 bits * The write signal (nWR or nFWR) controlled by WW0/1 and WM0/1 bits * The address latch enable signal (ALE) controlled by AW0/1 and AM0/1 bits The RW0/1, WW0/1, and AW0/1 bits control the wait states inserted in the corresponding (read, write, and ALE) signals. The RM0/1, WM0/1, and AM0/1 bits control the mode (waveform) of the corresponding (read, write, and ALE) signals. Figure 6-5 shows the signal waveform as defined by the corresponding control bits xW0/1 and xM0/1, where `x' can be `R', `W', or `A' (for read, write, or ALE signal).
ATMEL CONFIDENTIAL
5665B-USB-04/05
17
ATMEL CONFIDENTIAL
Figure 6-5. The Signal Waveform of Control Bits xW0/1, xM0/1
Wait Cycles (xW0/1)
00 00 00 00 01 01 01 01 10 10 10 10 11 11 11 11
Mode (xM0/1)
00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 0 1 2 3 4
(RESERVED)
(RESERVED)
CPU Cycles
Table 6-10.
The Functionality of the nCS0 and nCS1 Pins During an External Memory Access Cycle
ramadr[8] x 0 1 x nCS0 1 0 1 1 nCS1 1 1 0 0
External Memory Interface Mode FIFO DeMUX DeMUX MUX Note:
"ramadr[8]" is the address bit 8 of the internal AVR data memory space.
The external memory address bus is equal to the internal AVR data address bus.The nCS0 (or nCS1) and the data bus are valid during the write cycle. During the read cycle, the nCS0 (or nCS1) is valid during the access cycle, while the data bus must be valid during the end of the cycle (rising edge of system clock, which causes the rising edge of nCS pin). Figure 6-6 shows an example of the read and write accesses on a demultiplexed external memory (EMD1/0 = 10). The read cycle is defined with zero wait states (RW1/0 = 00) and waveform mode 01 (RM1/0 = 01). The write cycle is defined with one wait state (WW1/0 = 01) and waveform mode 10 (WM1/0 = 10).
18
AT76C713
5665B-USB-04/05
AT76C713
Figure 6-6. Example of Read and Write Access on a Demultiplexed External Memory
System Clock nCS Address bus Read Access cycle Data bus nRD
nCS Write Access cycle Address bus
Data bus nWR
6.6
USB DMA Controller
The AT76C713 offers a flexible DMA mechanism for fast data transfers between the Endpoint buffers and the memory. Using DMA, the AVR program is not occupied with data transfers and this results in the conservation of processing time. The DMA controller is capable of moving data as fast as 12 Mbytes per second. The USB DMA controller has direct access to either internal or external data memory. When the USB starts a DMA transfer to or from the data memory, then the DMA controller prevents the AVR from accessing the same data memory area (internal or external). During a DMA transfer, the AVR can access any of the general-purpose registers. Once the AVR performs an access to the data memory area where a DMA transfer is occupied, the DMA controller then imposes wait cycles to the AVR until the DMA transfer is complete. Thus, no further improvement is required from the firmware to prevent external or internal memory access during the DMA transfers. To enable a DMA transfer, the following steps should be performed 1. Program the offset address of the FIFO Data register of the associated Endpoint (this is the address of the FDRx register, that is, $F0CE for FDR1) 2. Program the number of the bytes to be moved to/from the FIFO Data register 3. Enable the write or read DMA cycle The AVR must poll the USB in order to detect the DMA completion.
ATMEL CONFIDENTIAL
5665B-USB-04/05
19
ATMEL CONFIDENTIAL
6.7 USB Controller
The USB controller contains its own internal register file, which is memory mapped onto the AVR data bus. The USB block implements the low-level processing functions of the USB protocol stack described in Universal Serial Bus Specification, Version 1.1 and handles the data transfers between the Endpoint (EP) FIFOs and the system memory. The USB controller consists of an SIE, an FIU, and the SI. Figure 6-7. USB Controller
USB Controller
AVR Memory Bus
FIU SI SIE DP DM
FIFOs
The USB controller supports one control Endpoint and seven programmable Endpoints in terms of the type (BULK, INT, or ISO) and the direction (IN, OUT). The FIU includes the Endpoint buffers and the controllers of Endpoints shown in Table 6-11.
Table 6-11.
USB Function Interface Unit Structure
Type Control Any Any Any Number of Bytes 16 128 (2 x 64) 64 0 Buffer Type Single Double Single Single
Endpoint Endpoint 0 Endpoint 1..3 Endpoint 4 Endpoints 5..7
A Pair Endpoint address scheme is also supported. According to this scheme, two Endpoints may have the same address, provided one of the endpoints has been configured as IN and the other as OUT. 6.7.1 USB System Interface (SI) The USB SI is necessary to bridge the AVR data bus with the USB controller because the system clock and the USB controller clock are asynchronous. When the AVR accesses the USB registers, the USB system interface inserts wait cycles to the AVR core in order to synchronize the data memory bus with the USB local bus.
20
AT76C713
5665B-USB-04/05
AT76C713
6.7.2 USB Interrupt Handling All interrupt signals from the USB functions (protocol handler) are consolidated into the USB interrupt line. The interrupt line from the USB protocol handler is then multiplexed with the individual interrupt signals generated internally, and a single interrupt output is provided to the system interrupt controller. All interrupts are masked through the interrupt enable registers that exist in the USB controller. The external resume and received resume interrupts are cleared when the firmware clears the interrupt bit. The suspend interrupt is automatically cleared when activity is detected. All other interrupts are cleared when the processor sets a corresponding bit in an Interrupt Acknowledge register in the USB macro cell. There is only one bit for each interrupt source. Table 6-12 describes each of the interrupt sources of the USB protocol handler (see also the UISR register).
Table 6-12.
USB Interrupt Sources
Description See control transfers at function EP0 for details For an OUT Endpoin,t it indicates that Function Endpoint1 has received a valid OUT packet and that the data is in the FIFO. For an IN Endpoint, it means that the Endpoint has received an IN token, sent out the data stored in the FIFO, and received an ACK from the Host. The FIFO is now ready to be written by new data from the processor See Function EP1 interrupt See Function EP1 interrupt See Function EP1 interrupt See Function EP1 interrupt See Function EP1 interrupt The USB H/W decodes a valid Start of Frame The H/W has received a remote wake-up request The H/W has received resume signaling. The processor's firmware should take the function out of the suspended state The H/W has detected a suspend condition and is preparing to enter the suspend mode. The processor's firmware should place the embedded function in the suspend mode
Interrupt Function EP0 interrupt
Function EP1 interrupt
Function EP2 interrupt Function EP3 interrupt Function EP4 interrupt Function EP5 interrupt Function EP6 interrupt SOF Received EXT RSM RCVD RSM
SUSP
6.7.3
Interrupt Priority The USB macro interrupt priority is defined in Table 6-13. Table 6-13.
Priority Level 2: High level 1: Same level (low level)
USB Macro Interrupt Priority
Interrupt Name SOF Received Function EP0 to EP6
6.7.4
Endpoint Interrupt Endpoint interrupts are triggered by the setting or clearing of one or more bits in the Control and Status registers of an Endpoint. These interrupts are caused by events during packet transac-
ATMEL CONFIDENTIAL
5665B-USB-04/05
21
ATMEL CONFIDENTIAL
tions and are different for Control and non-Control Endpoints. The interrupts are described below with respect to the Control and Status register bit definitions. 6.7.5 Interrupt for Non-control Endpoints * RX OUT Packet set (0 -> 1) * TX Packet Ready clear (1 -> 0) 6.7.6 Interrupt for Control Endpoints * RX OUT Packet set (0 -> 1) * RX SETUP set (0 -> 1) * TX Packet Ready clear (1 -> 0) * TX Complete set (0 -> 1) 6.7.7 USB Function Interface (FIU) The FIU provides the interface between the processor (via the SI) and the SIE. It manages transactions at the packet level with minimal intervention from the processor, handles the Endpoints' FIFOs, monitors the status of the transactions and communicates with the AVR through a set of status and control registers. The FIU is designed to operate in single-packet mode and to manage the USB packet protocol layer. To operate the FIU, the firmware must first enable the Endpoints of the FIU, and then select a direction and ping-pong capability. Once enabled, the Endpoints are in receive mode by default. The FIU notifies the processor when a valid token has been received. The data contained in the data packet will be supplied in the FIFO. The processor transfers the data to and from the Host by interacting with each Endpoint's FIFO and Control and Status registers. For example, when transmitting an IN packet, the FIU assembles the data of the Endpoint's FIFO in a USB packet, transmits the packet, and then signals the processor after the Host receives and acknowledges the packet. The FIU performs automatic data packet retransmission and DATA0/DATA1 PID toggling. For SETUP tokens, the processor must parse the device request and then respond appropriately. After a SETUP token, there may be 0 or more DATA IN or DATA OUT packets for which the processor must either supply or receive the data. 6.7.8 USB Serial Interface Engine (SIE) The SIE performs the following functions: * NRZI data encoding/decoding * Bit stuffing/un-stuffing * CRC generation and checking * ACKs and NACKs * Identifying the type of a token * Address checking * Clock generation (via DPLL) 6.7.9 Control Transfers at Function EP0 Legend: DATA1/DATA0 = Data packet with DATA1 or DATA0 PID
22
AT76C713
5665B-USB-04/05
AT76C713
DATA 1 (0) = Zero length DATA1 packet
Host
USB Macro SETUP Stage
Microcontroller
1. [SYNC]-[SETUP] 2. [SYNC]-[DATA0] 3. Data are put in FIFO 4. If CRC OK, send:[SYNC]-[ACK] 5. if CRC OK, set RX_SETUP bit 6. INTERRUPT 7. Read UISR (bit 0 is set) 8. Read FCSR0 (RX_SETUP bit) 9. Read FBYTE_CNT0 10. Read FIFO 0 11. Parse Data If Control Read Phase: Set Control Direction Clear RX_SETUP bit Fill FIFO with data Set TX_Packet_Ready If Control Write Phase: Clear Control Direction Clear RX_SETUP bit If No data Stage Phase: Clear Control Direction Set Data_End bit Set FORCE_STALL bit If Unsupported Command: Set FORCE_STALL bit 12. SET UIAR (EP0 INTA) Status Stage, No DATA Stage 1. [SYNC]-[IN] 2. Send DATA1(0) 3. If CRC Ok, send [SYNC]-[ACK] 4. Set TX_Complete bit 5. INTERRUPT 6. Read UISR 7. Read CSR
ATMEL CONFIDENTIAL
5665B-USB-04/05
23
ATMEL CONFIDENTIAL
Host USB Macro Microcontroller 8. If SET_ADDRESS Write Device Address to FADDR Set FADD Enable bit of Global State Registe If SET_CONFIGURATION with a 1: Set CONFIG bit of Global State Register 9. Clear Tx_Complete bit 10. Clear Data_End bit 11. Set FORCE_STALL bit 12. SET UIAR (EP0 INTA) DATA Stage, Control READ 1. [SYNC]-[IN] 2. If TX_Packet_Ready = 1 send DATA0 / DATA1 else, send STALL 3. If CRC OK, send [SYNC]-[ACK] 4. Clear TX_Packet_Ready 5. Set TX_Complete bit 6. INTERRUPT 7. Read UISR 8. Read CSR 9. Clear Tx_Complete bit 10. If more data
fill FIFO with data and set TX_Packet_Ready
else if a NULL packet should be sent,
set DATA_END and set TX_Packet_Ready
else if all bytes sent and need to send a NULL packet,
set DATA_END and set SET_FORCE_STALL
11. SET UIAR (EP0 INTA) STATUS/Early STATUS Stage with READ DATA Stage 1. [SYNC]-[OUT]
24
AT76C713
5665B-USB-04/05
AT76C713
Host 2. [SYNC]-[DATA1(0)] 3. If TX_Complete = 0 then send [SYNC]-[ACK] and set RX_OUT else send [SYNC]-[NACK] 4. INTERRUPT 5. Read UISR 6. Read CSR 7. Clear RX-OUT 8. Set Data_end 9. Set Force_Stall Comment: A SETUP token will clear Data_End. Not cleared by firmware in case Host retries 1 through 3 10. DATA Stage, Control WRITE 1. [SYNC]-[OUT] 2. [SYNC][DATA1/DATA0] 3. Data are put in FIFO 4. If CRC ok send [SYNC]- [ACK] 5. if CRC ok, set RX_OUT 6. INTERRUPT 7. Read UISR 8. Read CSR 9. Read FIFO 10. Clear RX_OUT If last packet, Set Data_End Set Force_Stall 11. SET UIAR (EP0 INTA) STATUS Stage with WRITE DATA Stage 1. [SYNC]-[IN] 2. Send DATA1(0) 3. If CRC Ok, send [SYNC]-[ACK] 4. Set TX_Complete bit 5. INTERRUPT 6. Read UISR 11. SET UIAR (EP0 INTA) USB Macro Microcontroller
ATMEL CONFIDENTIAL
5665B-USB-04/05
25
ATMEL CONFIDENTIAL
Host USB Macro Microcontroller 7. Read CSR 8. Clear Tx_Complete bit 9. Clear Data_End bit 10. Set FORCE_STALL bit 11. SET UIAR (EP0 INTA)
6.7.10
Interrupt and Bulk In Transfers The USB hardware automatically starts the Endpoint in the receive mode and NAKs all IN tokens, as long as the CSR[TX Packet Ready] is cleared. The processor checks this bit and if it is 0, it writes the data into the FIFO and then sets CSR[TX Packet Ready]. At the next IN token, the USB hardware sends the packet out and waits for an ACK. Until an ACK is received, the USB hardware will retransmit the packet. After receiving an ACK, the USB hardware clears the CSR[TX Packet Ready], signaling a successful completion to the processor. Bulk IN Transfers
Figure 6-8.
IN Token without Ping-pong
HOST reads USB fifo TX_Complete =0 IN token UC fills USB fifo HOST reads USB fifo TX_pkt_rdy = 0 Tx_pkt_rdy = 1 IN token TX_Complete= 1 ACK
TX_pkt_rdy = 0
TX_Complete= 1 ACK
IN Token with Ping-pong
UC fills data Uc polling Tx_Complete Tx_pkt_rdy = 1 UC fills data Uc polling Tx_Complete Tx_pkt_rdy = 1
HOST reads last data TX_Complete = 0 IN token TX_Complete = 1 ACK
HOST reads last data TX_Complete = 0 IN token TX_Complete =1 ACK
6.7.11
Interrupt and Bulk OUT Transfers The USB hardware automatically starts the Endpoint in receive mode. When an OUT token is received and if the CSR[RX OUT Packet] is cleared, it stores the data in the FIFO. It ACKs the Host if the data received are not corrupted and then interrupts the processor. If the CSR[RX OUT Packet] is set, the USB hardware responds with a NAK to the incoming OUT token. The processor checks the CSR[RX OUT Packet] and if it is 1, it reads the data from the FIFO and clears CSR[RX OUT Packet Ready].
26
AT76C713
5665B-USB-04/05
AT76C713
Figure 6-9. Bulk OUT Transfers
OUT Token without Ping-pong
HOST fills USB fifo UC reads fifo OUT Token OUT token Rx_OUT =1 ACK Rx_OUT = 0 OUT token
Rx_OUT =1
HOST fills USB fifo
UC reads fifo
OUT Token with Ping-pong
UC Reads last data Uc pooling Rx_out Rx_OUT =0 UC Reads last data Uc pooling Rx_out Rx_OUT =0
HOST fills USB fifo ACK OUT token Rx_OUT =1
HOST fills USB fifo ACK OUT token
Rx_OUT =1
6.7.12
Interrupt and Isochronous Transfers Isochronous transfers use the same protocol with bulk transfers except that error correction and data packet retransmission are not supported: * No ACK token * No NAK token * Data PID is always 0
6.7.13
Interrupt and Interrupt IN Transfers Interrupt transfers use the same protocol with bulk IN transfers (Interrupt OUT is not supported in USB Spec 1.0). Suspend Mode A USB device enters the suspend mode only when requested by the USB Host through bus inactivity for at least 3 ms. The USB H/W detects this request, sets the SUSP bit of the Suspend/Resume register (SPRSR), and interrupts the processor if the interrupt is enabled. The processor should shut down any peripheral activity, enter power-down mode, and signal the USB H/W that it can enter the suspend mode by writing 1 to the sleep mode USB_Macro input pin. The firmware must then execute the SLEEP instruction and set the system to a power-down state. The oscillator, PLL, AVR, and all peripherals will stop and the SUSP pin will be set to high.The USB suspend interrupt hits twice; one time in the beginning of the suspend, and one time at the end of the suspend. Resume Mode Resume mode is signaled by a J-to-K state transition at the USB port. The USB H/W enables the oscillator/PLL and sets the RSM bit of the SPRSR, which generates an interrupt. The processor starts executing where it left off and services the interrupt. The firmware clears the RCVD RSM bit.
6.7.14
6.7.15
6.7.16
Remote Wakeup During Remote Wakeup, a resume is signaled by the firmware by setting the RSM bit of the SPRSR register.The firmware must wait for some time (8 ms) before clearing the the RSM bit in order to give time to the Host to detect the resume signal on the bus.
ATMEL CONFIDENTIAL
5665B-USB-04/05
27
ATMEL CONFIDENTIAL
6.8 UART0, UART1
UART0 and UART1 are 16550-compatible UARTs with some additional features. The main features of the UARTs are: * Can run 16550 software * All registers are in 16550-compatible mode after reset * Programmable baud rate generator * Maximum data rate 921.6 Kbaud * Exception handling using either prioritized interrupts or polled modes * Parity, framing, and overrun error detection * Two dedicated controller channels * 16-byte transmit FIFO * 16-byte plus 3 error bits receive FIFO * 5-, 6-, 7-, and 8-bit word length * Bi-directional handshaking modem control signals (available only for UART0) * Line break generation and detection * Multidrop mode: Address detection and generation * Diagnostic loopback mode (with or without an echo) 6.8.1 Baud Rate Generator The input to the baud rate generator is 14.769 MHz, which is derived from the internal clock generator. Receiver The UART detects the start of a received word by sampling the SIN signal until it detects a valid start bit. A low-level (that is, a space) on SIN is interpreted as a valid start bit if it is detected for more than 7 cycles of the sampling clock, which is 16 times the baud rate. Thereore, a space which is longer than 7/16 of the bit period is detected as a valid start bit. A space, which is 7/16 of a bit period or shorter, is ignored and the receiver continues to wait for a valid start bit. When a valid start bit has been detected, the receiver samples the SIN at the theoretical midpoint of each bit. It is assumed that each bit lasts 16 cycles of the sampling clock (1 bit period) so the sampling point is 8 cycles (0.5 bit periods) after the beginning of the bit. The first sampling point is sampled 24 cycles (1.5 bit periods) after the falling edge of the start bit was detected. Each subsequent bit is sampled 16 cycles (1 bit period) after the previous one. 6.8.3 Receive FIFO Operation The 16-byte plus 3 error bits receive data FIFO is enabled by the FCR bit 0. The user can set the receiver trigger level. Time-out The receiver section includes a time-out mechanism in order to trace the time interval between the received words. The RTO register contains the maximum bit periods, for which the UART will wait for the next word to arrive. Whenever the time-out counter expires (reaches $00), then a time-out indication interrupt will be issued.
6.8.2
6.8.4
28
AT76C713
5665B-USB-04/05
AT76C713
The XR1[5] Start Time-out Control bit selects the Start Time-out and RTO load mechanism. If the XR1[5] bit is reset to 0 (16550 compatible mode), then the RTO loads the value 4 times the word length plus 12 on each LCR write operation. After reset, the word length is 5 bits and the RTO is $20. The time-out counter will then start counting down only in FIFO mode (FCR[0] is set) and if the Rx FIFO holds at least 1 word. If XR1[5] is set to 1, then the time-out function is available and in FIFO-disabled mode. The RTO value does not change with the LCR write operations. The time-out counter will start counting down whenever the RTO is not $00. In all cases, the core has immediate access to the contents of the RTO. The time-out counter resets on a RHR read access from core or when a new word is completely received and transferred to the Receive Holding register or when the XR1[4] bit is forced to logic 1. 6.8.5 Receive Break The break condition is detected by the receiver when the SIN line is held in the spacing state (logic 0) for longer than a full word transmission time (that is, the total time of all data, parity, and stop bits). At the moment of the low stop bit detection, the receiver asserts receive break indication (LSR[4]). The end of the receive break is detected by a high level for at least 2/16 of the bit period. 6.8.6 Transmitter The start bit, data bits, parity bit, and stop bits are serially shifted, with the lowest significant bit first, on the falling edge of the UART clock. The LCR controls the number of data bits, the parity bit and the number of stop bits. When a word is written to THR (Transmit Holding register), it is transferred to the Shift register as soon as it is empty. When the transfer occurs, the THR ready (bit-5) in LSR is set until a new word is written to THR. If the Transmit Shift register and THR are both empty, the transmitter empty (bit-6) in LSR is set. 6.8.7 Transmit FIFO Operation When the FCR[0] is set to logic 1 and XR2[7] is reset to 0, then the 16-byte transmit FIFO is enabled. The LCR[5] (and the XR2[5]) THR Empty bit indicates whether the Tx FIFO is empty or full. When XR2[4] is in logic 0 (16550 compatible mode), then the THR Empty bit indicates that Tx FIFO is empty. If XR2[4] is set to logic 1, then THR Empty bit indicates Tx FIFO is not full. If the THR Empty bit is active (high), then a THR Empty interrupt will be issued. The firmware has two choices: 1) Reset XR2[4] bit to logic 0 and enable the THR Empty interrupt. On each THR Empty interrupt, the software will transfer up to 16 words to the THR (no check for FIFO full). 2) Set XR2[4] bit to logic 1 and enable THR Empty Interrupt. On each THR Empty interrupt, the software will know that it is possible to transfer more words to THR (until THR Empty bit is 0). 6.8.8 Time-guard The Time-guard function allows the transmitter to insert an idle state between two words on the SOUT line. The duration of the idle state is programmed in U _TTG (Transmitter Time-guard). When this register is set to 0, no time-guard is generated. 6.8.9 Transmit Break The transmitter can generate a break condition on the SOUT line when the Start Break command is issued by setting LCR[6] to logic 1. During the break condition SOUT line is held to space state (logic 0). The Start Break command will take effect right after the complete transmission of all words in Transmit Shift register and THR (or Tx FIFO, if enabled). No software
ATMEL CONFIDENTIAL
5665B-USB-04/05
29
ATMEL CONFIDENTIAL
synchronization is needed. To remove the break condition on the SOUT line, a Stop Break command should be issued by resetting US_LCR[6] to logic 0. The UART generates minimum break duration of one word length. After the Stop Break commandhas been issued, the SOUT line returns to high level (idle state) for at least 12 bit periods to ensure that the end of break is correctly detected. The transmitter resumes the normal operation. 6.8.10 Interrupt Generation The UART prioritizes interrupts into five levels and records these in the Interrupt Identification register (IIR). The five levels of interrupt conditions in order of priority are: Receiver Line Status, RHR Ready, Time-out, THR Ready, and Modem Status. When the CPU accesses the IIR, the UART freezes the contents of IIR and indicates the highest priority pending an interrupt to the CPU. During this CPU access, the UART records new interrupts, but does not change its current indication until the access is complete. The Interrupt Enable register (IER) controls which interrupt condition will issue an interrupt to the core. Disabling all interrupts, the UART works in polled mode. 6.8.11 Handshaking Signals Both UARTs implement all the modem control handshaking signals, but none of those signals are mapped to any I/O port for UART1. For UART0, the nOUT1 and nOUT2 signals are not mapped to any I/O ports. The only available handshaking signals are the nRTS, nCTS, nDSR, nDTR, nCD, and nRI of UART0. All modem control signals are bi-directional and the firmware has the full control of their status. 6.8.12 Loopback Mode In the diagnostic loopback mode, the UART deactivates the output signals (stack at logic 1) and loops-back their status to the proper input signals. The UART offers the option of not stacking the UART output pins at logic 1 but rather echoing their status at the external UART interface. The loopback mode cannot be asserted if the direction of the modem control signals (MDR) are not in the default state.
6.9
IrDA 1.0 Codec
The IrDA 1.0 codec can be attached on either the UART0 or UART1. The operation of IrDA codec is controlled by the "IrDA Control Register (IRDACR)" on page 53. The IrDA 1.0 codec can effect the UART's SIN and SOUT signals by applying 3/16 or 4/16 modulation of the Return-to-Zero encoding scheme that the UART produces. According to the IrDA standard, for data rates up to and including 1.152 Mbit/s, the RZI modulation scheme is used and a 0 is represented by a light pulse. For rates up to and including 115.2 Kbit/s, the optical pulse duration is nominally 3/16 of a bit duration (or 3/16 of a 115.2 Kbit/s bit duration). For 0.576 Mbit/s and 1.152 Mbit/s, the optical pulse duration is nominally 4/16 of a bit duration.
30
AT76C713
5665B-USB-04/05
AT76C713
Figure 6-10. Pulse Duration
NRZ
1.6 sec
<115.2Kbps
1/4 bit 0.576 and 1.152 Mbps
6.10 Watchdog Timer
The main features of the Watchdog Timer (WDT) are: * 3 MHz clock * 22-bit up-counter * Programmable prescaler * Write access protection on the timer disable The WDT is used to prevent a system lock-up if the software becomes trapped in a deadlock. The WDT is clocked with a 3 MHz clock from the clock generator. In a normal operation, the user resets the WDT at regular intervals, using the WDR instruction. By controlling the WDT prescaler, the Watchdog reset interval can be adjusted (see WDTCR register, WDP2..0 bits). Eight different clock cycle periods can be selected to determine the reset period. If the reset period expires without another Watchdog reset, the system resets and executes from the reset vector. To prevent unintentional disabling of the watchdog, a special turnoff sequence must be followed when the WDT is disabled. Refer to the description of the WDTCR register for details.
6.11
Serial Peripheral Interface (SPI)
The AT76C713 SPI features are: * Full-duplex 3-wire synchronous data transfers * Master or slave operation * LSB first or MSB first data transfer * Four programmable bit rates * End-of-Transmission interrupt request * Write collision flag protection * Wake-up from idle or power-down mode (slave mode only) The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfers between the AT76C713 and peripheral devices (memories, controllers, etc.). The interconnection between master and slave SPI controllers is shown in Figure 6-11. The two shift registers of the master and the slave SPI controllers can be considered as one distributed 16-bit circular shift register. As Figure 6-11 shows, when data is shifted from the master
ATMEL CONFIDENTIAL
5665B-USB-04/05
31
ATMEL CONFIDENTIAL
to the slave, data is also shifted in the opposite direction simultaneously. This means that during one shift cycle the data in the master and the slave are interchanged. Figure 6-11. Interconnection Between Master and Slave SPI Controllers
SPI Master
MOSI MISO MOSI MISO
SPI Slave
8-bit Shift Register
8-bit Shift Register
SPI Clock Generator
SCK nSS
SCK nSS
The PB4(SCK) pin is the clock output in the master mode and the clock input in the slave mode. Writing to the SPI Data register of the SPI master starts the SPI clock generator and the data written shifts out of the Master MOSI pin and into the Slave MOSI pin. After shifting one byte, the SPI clock generator stops setting the End-of-Transmission flag (SPIF). If the SPI interrupt enable bit (SPIE) in the SPCR register is set, an interrupt is issued. The Slave Select input (nSS) is set low to select an individual slave SPI device. The system is single-buffered in both transmit and receive directions. This means that bytes to be transmitted cannot be written to the SPI Data register before the entire shift cycle is completed. When receiving data, we must read the received byte before the next reception is started. Otherwise, the first byte is lost. When the SPI is enabled (PERIPHEN register, SPI bit), the data direction of the MOSI, MISO, SCK, and nSS pins is overridden, according to Table 6-14. Table 6-14.
Pin PB4 PB5 PB6 PB7
Data Direction of SPI pins
SPI Master User defined Output Input Output SPI Slave Input Input Output/Hi-Z Input Description nSS (SPI Slave Select Input) MOSI (SPI Bus Master Output/Slave Input) MISO (SPI Bus Master Input/Slave Output) SCK (SPI Bus Serial Clock)
6.11.1
nSS(PB4) Pin Functionality When the SPI is configured as a master (MSTR in SPCR register), the user can determine the direction of the nSS (PB4) pin. If the nSS is configured as an output, the pin is a general output pin, which does not affect the SPI system. If the nSS is configured as an input, it must be held high to ensure master SPI operation. If the nSS pin is driven low by peripheral circuitry when the SPI is configured as master with the nSS pin defined as an input, then the SPI system interprets this as another master selecting the SPI as a slave and starts to send data to it. To avoid bus contention, the SPI system takes the following actions
32
AT76C713
5665B-USB-04/05
AT76C713
1. The MSTR bit in SPCR is cleared and the SPI system becomes a slave. As a result of the SPI becoming a slave, the MOSI and SCK pins become inputs. 2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled and the I-bit in SREG is set, then the interrupt routine will be executed. Thus, when the interrupt-driven SPI transmittal is used in the master mode and there exists a possibility that the nSS is driven low, the interrupt should always check that the MSTR bit is still set. Once the MSTR bit has been cleared by a slave select, it must be set by the user to reenable the SPI master mode. When the SPI is configured as a slave, the nSS pin is always an input. When nSS is held low, the SPI is activated and MISO becomes an output. All other pins (MOSI and SCK) are inputs. When nSS is driven high, all pins are inputs and the SPI is passive, which means that it will not receive incoming data. Note that the SPI logic will be reset once the nSS pin is brought high. If the nSS pin is brought high during a transmission, the SPI will stop sending and receiving immediately, and both data received and data sent must be considered lost. 6.11.2 SPI Modes The SPI bus protocol includes 4 modes. These modes determine the relationship between the serial clock and the data bits. The SPI mode is fully programmable using the SPI Control register (SPICR). The four modes are determined with the CPOL and CPHA bits, as illustrated in the following four figures.
Note: In all modes, the data pins MOSI and MISO are driven in the opposite SCLK edge. For example, if the data input is latched on the rising edge, then the data output is driven on the falling edge.
Figure 6-12. SPI Mode 0
Mode 0: CPOL= 0,CPHA = 0
nSS SCK MOSI/MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6-13. SPI Mode 1
Mode 1: CPOL= 0,CPHA =1
nSS SCK MOSI/MISO
D7
D6
D5
D4
D3
D2
D1
D0
ATMEL CONFIDENTIAL
5665B-USB-04/05
33
ATMEL CONFIDENTIAL
Figure 6-14. SPI Mode 2
Mode 2: CPOL=1, CPHA= 0
nSS SCK MOSI/MISO
D7
D6
D5
D4
D3
D2
D1
D0
Figure 6-15. SPI Mode 3
Mode 3: CPOL=1, CPHA=1
nSS SCK MOSI/MISO
D7
D6
D5
D4
D3
D2
D1
D0
6.12
JTAG Interface and On-chip Debug System
The main features of the JTAG and On-chip Debug (OCD) System are: * JTAG (IEEE Std. 1149.1 Compliant) interface * Boundary-scan capabilities according to the IEEE Std. 1149.1 (JTAG) * Debugger access to: - All Internal Peripheral Units - Internal and external data RAM - Program memory - Internal register file - Program counter * Extensive on-chip debug support for break conditions, including: - AVR break instruction - Break on change of program memory flow - Single step break - Program memory break points on a single address or address range - Data memory break points on a single address or address range The AVR IEEE Std. 1149.1 compliant JTAG interface can be used for the following: * Testing PCBs by using the JTAG boundary-scan capability * On-chip debugging Detailed descriptions for the boundary-scan chain can be found in the section "IEEE 1149.1 (JTAG) Boundary-scan" of the IEEE 1149.1 Standard. The on-chip debug support contains confidential JTAG instructions and is distributed within Atmel and to selected third party vendors only.
34
AT76C713
5665B-USB-04/05
AT76C713
Figure 6-16 shows a block diagram of the JTAG interface and the on-chip debug system. The TAP controller selects either the JTAG Instruction register or one of several Data registers as the scan chain (Shift register) between the TDI input and TDO output. The Instruction register holds JTAG instructions controlling the behavior of a Data register. The ID register, Bypass register, and the boundary-scan chain are the Data registers used for board-level testing. The internal scan-chain and break point scan chain are used for on-chip debugging purposes only. Figure 6-16. JTAG Interface and On-chip Debug System Block Diagram
TDI TDO TMS TCK
TAP Controller
Instruction Register ID Register BYPASS Register Break Point Scan Chain Address Decoder Program Memory Controller
Internal Scan Chain
PC Instruction AVR CPU
Boundary Scan Chain
M U X
I/O Pins
Break Point Unit Flow Control Unit OCD Status and Control JTAG/AVR core Communication Interface Peripheral Units
6.12.1
Test Access Port (TAP) The JTAG interface is accessed through four pins. In JTAG terminology, these pins constitute the Test Access Port (TAP). These four pins are: * TMS: Test Mode Select - This pin is used for navigating through the TAP-controller state machine * TCK: Test Clock - JTAG operation is synchronous to TCK * TDI: Test Data In - Serial input data to be shifted in to the Instruction register or Data register (scan chains) * TDO: Test Data Out - Serial output data from Instruction register or Data register The IEEE Std. 1149.1 also specifies the optional TAP signal TRST (Test ReSeT) which is not provided. For the on-chip debug system, in addition to the JTAG interface pins, the nRST pin is monitored by the debugger in order to detect external reset sources. The debugger can also pull the nRST pin low (using the AVR_RESET command) in order to reset the entire system.
6.12.2
TAP Controller The TAP controller is a 16-state finite-state machine that controls the operation of the boundaryscan circuitry or the on-chip debug system. The state transitions depicted in Figure 6-17 depend
ATMEL CONFIDENTIAL
5665B-USB-04/05
35
ATMEL CONFIDENTIAL
on the signal present on the TMS (shown adjacent to each state transition) at the time of rising edge at the TCK. The initial state after a Power-on Reset is a Test-Logic-Reset. As a definition in this document, the LSB is shifted in and out first for all Shift registers. Assuming Run-Test/Idle is the present state, a typical scenario for using the JTAG interface is as follows: * In the TMS input, apply the sequence 1, 1, 0, 0 at the rising edges of the TCK to enter the Shift Instruction register (Shift-IR) state. While in this state, shift the four bits of the JTAG instructions into the JTAG Instruction register from the TDI input at the rising edge of TCK. The TMS input must be held low during input of the 3 LSBs in order to remain in the Shift-IR state. The MSB of the instruction is shifted in when this state is left by setting the TMS to high. While the instruction is shifted in from the TDI pin, the captured IR-state 0x01 is shifted out on the TDO pin. The JTAG instruction selects a particular Data register as path between TDI and TDO and controls the circuitry surrounding the selected Data register. * Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. The instruction is latched onto the parallel output from the Shift register path in the Update-IR state. The Exit-IR, Pause-IR, and Exit2-IR states are only used for navigating the state machine. * At the TMS input, apply the sequence 1, 0, 0 at the rising edges of the TCK to enter the Shift Data register (Shift-DR) state. While in this state, upload the selected Data register (selected by the present JTAG instruction in the JTAG Instruction register) from the TDI input at the rising edge of the TCK. In order to remain in the Shift-DR state, the TMS input must be held low during the input of all bits except the MSB. The MSB of the data is shifted in when this state is left by setting the TMS high. While the Data register is shifted in from the TDI pin, the parallel inputs to the Data register captured in the Capture-DR state is shifted out on the TDO pin. * Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state. The Exit-DR, Pause-DR, and Exit2-DR states are only used for navigating the state machine. As shown in the state diagram, the Run-Test/Idle state need not be entered between selecting JTAG instruction and using the Data registers. Some JTAG instructions may select certain functions to be performed in the Run-Test/Idle, making it unsuitable as an idle state.
Note: Independent of the initial state of the TAP controller, the Test-Logic-Reset state can always be entered by holding the TMS high for five TCK clock periods.
36
AT76C713
5665B-USB-04/05
AT76C713
Figure 6-17. JTAG TAP State Diagram
TMS = 1 Test-Logic-Reset TMS =0 TMS = 0 Run-Test/Idle TMS=1 Select-DR-Scan TMS = 0 Capture-DR TMS =1 TMS = 0 Shift-DR TMS =1 Exit1-DR TMS =1 TMS = 0 Pause-DR TMS =1 TMS = 0 TMS = 0 Exit2-DR TMS =1 Update-DR TMS =1 TMS = 0 Exit2-IR TMS =1 Update-IR TMS =1 TMS = 0 TMS = 0 TMS = 0 Pause-IR TMS =1 TMS = 0 TMS = 0 TMS =1 TMS =1 Select-IR-Scan TMS = 0 Capture-IR TMS = 0 Shift-IR TMS =1 Exit1-IR TMS = 0 TMS =1
TMS =1
6.12.3
Using the On-chip Debug System As shown in Figure 6-16 on page 35, the hardware support for the on-chip debugging consists mainly of the following: * A scan chain on the interface between the internal AVR CPU and the internal peripheral units * Break point unit * Communication interface between the CPU and JTAG system All read or modify/write operations needed for implementing the debugger are done by applying AVR instructions via the internal AVR CPU scan chain. The CPU sends the result to an I/O memory mapped location which is part of the communication interface between the CPU and the JTAG system. The break point unit implements a break on the change of program flow, single step break, two program memory break points, and two combined break points. Together, the four break points can be configured as either: * Four single program memory break points * Three single program memory break point plus 1 single data memory break point * Two single program memory break points plus 2 single data memory break points * Two single program memory break points plus1 program memory break point with mask ("range break point") * Two single program memory break points plus 1 data memory break point with mask ("range break point")
ATMEL CONFIDENTIAL
5665B-USB-04/05
37
ATMEL CONFIDENTIAL
However, a debugger may use one or more of these resources for its internal purpose, leaving less flexibility to the end user. 6.12.4 On-chip Debug Specific JTAG Instructions The on-chip debug support contains private JTAG instructions and distributed within Atmel and to selected third party vendors only. Instruction opcodes are listed for reference in the Table 615. Table 6-15. OCD Specific JTAG Instructions
Opcode PRIVATE 0; $8 PRIVATE 1; $9 PRIVATE 2; $A PRIVATE 3; $B Description Private JTAG instruction for accessing On-chip debug system Private JTAG instruction for accessing On-chip debug system Private JTAG instruction for accessing On-chip debug system Private JTAG instruction for accessing On-chip debug system
6.13
IEEE 1149.1 (JTAG) Boundary-scan
Features: * JTAG (IEEE Std. 1149.1 compliant) interface * Boundary-scan capabilities according to the JTAG standard * Full scan of all port functions, as well as analog circuitry having off-chip connections * Supports the optional IDCODE instruction * Additional public AVR_RESET instruction to reset the AVR The boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins. At system level, all ICs having JTAG capabilities are connected serilly by the TDI/TDO signals to form a long Shift register. An external controller sets up the devices to drive values at their output pins and observe the input values received from other devices. The controller compares the received data with the expected result. In this way, the boundary-scan provides a mechanism for testing interconnections and integrity of components on printed circuits boards by using the four TAP signals only. The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRELOAD, and EXTEST, as well as the AVR-specific public JTAG instruction AVR_RESET can be used for testing the printed circuit board. Initial scanning of the Data register path will show the ID code of the device, since IDCODE is the default JTAG instruction. It may be desirable to have the AVR device in reset during test mode. If not reset, inputs to the device may be determined by the scan operations, and the internal software may be in an undetermined state when exiting the test mode. Entering reset, the outputs of any port pin will instantly enter the high impedance state, making the HIGHZ instruction redundant. If needed, the BYPASS instruction can be issued to make the shortest possible scan chain through the device. The device can be set in the reset state either by pulling the external nRST pin low, or issuing the AVR_RESET instruction with appropriate setting of the Reset Data register. The EXTEST instruction is used for sampling external pins and loading output pins with data. The data from the output latch will be driven out on the pins as soon as the EXTEST instruction is loaded into the JTAG IR register. The SAMPLE/PRELOAD instruction should also be used for setting initial values to the scan ring in order to avoid damaging the board when issuing the
38
AT76C713
5665B-USB-04/05
AT76C713
EXTEST instruction for the first time. The SAMPLE/PRELOAD instruction can also be used for taking a snapshot of the external pins during normal operation of the part. When using the JTAG interface for the boundary-scan, using a JTAG TCK clock frequency higher than the internal chip frequency is possible. The chip clock is not required to run. 6.13.1 Data Registers The Data registers relevant to the boundary-scan operations include: * Bypass register * Device Identification register * Reset register * Boundary-scan chain 6.13.1.1 Bypass Register The Bypass register consists of a single Shift register stage. When the Bypass register is selected as a path between the TDI and TDO, the register is reset to 0 when leaving the Capture-DR controller state. The Bypass register can be used to shorten the scan chain on a system when the other devices are to be tested. Device Identification Register
6.13.1.2
Bit 31:28
Field Version
Value $1
Description Version is a 4-bit number identifying the revision of the component The part number is a 16-bit code identifying the component. The unique JTAG Part Number for AT76C713 and AT76C713 is $C712 The Manufacturer ID is an 11-bit code identifying the manufacturer. The JTAG manufacturer ID for ATMEL is $01F
27:12
Part number
$C712
11:1 0
Manufacturer ID 1
$01F $1
6.13.1.3
Reset Register The Reset register is a test Data register used to reset the part. Since the AVR tri-states Port Pins when reset, the Reset register can also replace the function of the not implemented optional JTAG instruction HIGHZ. A high value in the Reset register corresponds to pulling the external Reset low. The part is reset, as long as there is a high value present in the Reset register. The output from this Data register is not latched, so the reset will take place immediately.
6.13.1.4
Boundary-scan Chain Register The boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins. See the "Boundary-scan Chain" on page 41 for a complete description. Boundary-scan Specific JTAG Instructions The Instruction register is 4-bit wide and supports up to 16 instructions. Listed below are the JTAG instructions useful for the boundary-scan operation. Note that the optional HIGHZ instruc-
6.13.2
ATMEL CONFIDENTIAL
5665B-USB-04/05
39
ATMEL CONFIDENTIAL
tion is not implemented, but all outputs with tri-state capability can be set in a high-impedance state by using the AVR_RESET instruction, since the initial state for all port pins is tri-state. As a definition in this data sheet, the LSB is shifted in and out first for all Shift registers. The OPCODE for each instruction is shown behind the instruction name in a hex format. The text describes which Data register is selected as the path between the TDI and TDO for each instruction. 6.13.2.1 EXTEST; $0 EXTEST; $0 is the mandatory JTAG instruction for selecting the boundary-scan chain as the Data register for testing circuitry external to the AVR package. The contents of the latched outputs of the boundary-scan chain are driven out as soon as the JTAG IR-register is loaded with the EXTEST instruction.
The active states are: * Capture-DR: Data on the external pins is sampled into the boundary-scan chain * Shift-DR: The internal scan chain is shifted by the TCK input * Update-DR: Data from the scan chain is applied to output pins 6.13.2.2 IDCODE; $1 IDCODE; $1 is an optional JTAG instruction selecting the 32 bit ID-register as the Data register. The ID-register consists of a version number, a device number, and the manufacturer code chosen by JEDEC. This is the default instruction after power-up. The active states are: * Capture-DR: Data in the IDCODE register is sampled into the boundary-scan chain * Shift-DR: The IDCODE scan chain is shifted by the TCK input. 6.13.2.3 SAMPLE_PRELOAD; $2 SAMPLE_PRELOAD; $2 is a mandatory JTAG instruction for pre-loading the output latches and taking a snap-shot of the input/output pins without affecting the system operation. However, the output latches are not connected to the pins. The boundary-scan chain is selected as Data Register. The active states are: * Capture-DR: Data on the external pins are sampled into the boundary-scan chain. * Shift-DR: The boundary-scan chain is shifted by the TCK input * Update-DR: Data from the boundary-scan chain is applied to the output latches. However, the output latches are not connected to the pins 6.13.2.4 AVR_RESET; $C AVR_RESET; $C is the AVR-specific public JTAG instruction for forcing the AVR device into the reset mode or releasing the JTAG reset source. The TAP controller is not reset by this instruction. The one bit Reset register is selected as the Data register. Note that the reset will be active as long as there is a logic 1 in the reset chain. The output from this chain is not latched. The active states are: * Shift-DR: The Reset register is shifted by the TCK input
40
AT76C713
5665B-USB-04/05
AT76C713
6.13.2.5 BYPASS; $F BYPASS; $F is the mandatory JTAG instruction selecting the Bypass register for Data register. The active states are: * Capture-DR: Loads a logic 0 into the Bypass register * Shift-DR: The Bypass register cell between TDI and TDO is shifted 6.13.3 Boundary-scan Chain The boundary-scan chain consists of two kind of cells. The first one is a standard scan cell with observe and drive capabilities, while the second one is an observe-only cell. AT76C713 Boundary-scan Order Table 6-16 shows the scan order between the TDI and TDO when the boundary-scan chain is selected as the data path. Bit 0 is the LSB; the first bit scanned in, and the first bit is scanned out. The scan order follows the pin-out order. Therefore, the bits of Port A for example are not scanned in order. Figure 6-18 shows an I/O pin with scan logic. Figure 6-18. I/O Pin With Scan Logic
PINxn PORTxn DDRDxn I/O Registers Scan Cel Scan Cell Scan Cell xINn xOUTn
ENB
6.13.3.1
PA D
OExn
Boundary Scan Signals
Note: x=A,B,C,D,E n=0..7
Table 6-16.
Bit Number (LSB) 0 1 2 3 4 5 6 7 8 9 10 11
AT76C713 Boundary-scan Order
Signal Name TEST_EN TEST_CK nRST EOUT7 EIN7 EOE7 EOUT6 EIN6 EOE6 EOUT5 EIN5 EOE5 PE5 PE6 PE7 Description (observe only) (observe only) (observe only)
ATMEL CONFIDENTIAL
5665B-USB-04/05
41
ATMEL CONFIDENTIAL
Table 6-16.
Bit Number 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
AT76C713 Boundary-scan Order (Continued)
Signal Name EOUT4 EIN4 EOE4 EOUT3 EIN3 EOE3 EOUT2 EIN2 EOE2 EOUT1 EIN1 EOE1 EOUT0 EIN0 EOE0 PMODE0 PMODE1 COUT7 CIN7 COE7 COUT6 CIN6 COE6 COUT5 CIN5 COE5 COUT4 CIN4 COE4 COUT3 CIN3 COE3 COUT2 CIN2 COE2 PC2 PC3 PC4 PC5 PC6 PC7 PE0 PE1 PE2 PE3 PE4 Description
42
AT76C713
5665B-USB-04/05
AT76C713
Table 6-16.
Bit Number 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82
AT76C713 Boundary-scan Order (Continued)
Signal Name COUT1 CIN1 COE1 COUT0 CIN0 COE0 BOUT7 BIN7 BOE7 BOUT6 BIN6 BOE6 BOUT5 BIN5 BOE5 BOUT4 BIN4 BOE4 BOUT3 BIN3 BOE3 BOUT2 BIN2 BOE2 DOUT7 DIN7 DOE7 DOUT6 DIN6 DOE6 DOUT5 DIN5 DOE5 DOUT4 DIN4 DOE4 PD4 PD5 PD6 PD7 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
43
ATMEL CONFIDENTIAL
Table 6-16.
Bit Number 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118
AT76C713 Boundary-scan Order (Continued)
Signal Name DOUT3 DIN3 DOE3 DOUT2 DIN2 DOE2 DOUT1 DIN1 DOE1 DOUT0 DIN0 DOE0 SUSPEND AOUT7 AIN7 AOE7 AOUT6 AIN6 AOE6 AOUT5 AIN5 AOE5 AOUT4 AIN4 AOE4 AOUT3 AIN3 AOE3 USB_ATTACH nCS1 nCS0 nFWR nFRD AOUT2 AIN2 AOE2 PA2 PA3 PA4 PA5 PA6 PA7 PD0 PD1 PD2 PD3 Description
44
AT76C713
5665B-USB-04/05
AT76C713
Table 6-16.
Bit Number 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 (MSB) 135
AT76C713 Boundary-scan Order (Continued)
Signal Name AOUT1 AIN1 AOE1 AOUT0 AIN0 AOE0 BOUT1 BIN1 BOE1 BOUT0 BIN0 BOE0 Idle-mode (sleep state) Power-down (sleep state) AVR clock stopped PLL Stable Indication PLL lock signal (observe only) (observe only) (observe only) (observe only) (observe only) PB0 PB1 PA0 PA1 Description
7. I/O Space (Register Description)
The I/O space definition of the AT76C713 is shown in Table 7-1. This space is defined in the area $00 - $3F and can be directly accessed by IN and OUT instructions or by ordinary SRAM accesses in the area $20-$5F. The notation used (with the SRAM address in parentheses), will be followed in the rest of this document.
Table 7-1.
AT76C713 I/O Space
Name SREG SPH SPL IDR TIMSK TIFR EIMSK MCUCR MCUSR TCCR0 Function Status register Stack pointer high Stack pointer low OCD Debug register Timer Interrupt Mask register Timer Interrupt Flag register External Interrupt Mask register MCU General Control register MCU Status register Timer0 Control registerregister
I/O Address (SRAM Address) $3F($5F) $3E($5E) $3D($5D) $3C($5C) $39($59) $38($58) $37($57) $35($55) $34($54) $33($53)
ATMEL CONFIDENTIAL
5665B-USB-04/05
45
ATMEL CONFIDENTIAL
Table 7-1. AT76C713 I/O Space (Continued)
Name TCNT0 PRELD0 TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 PRELD2 IRDACR WDTCR PMOD EMICRB EMICRA PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR CLK_CNTR Function Timer0 (8-bit) Pre-load register 0 Timer1 Control register B Timer1 high byte Timer1 low byte Timer1 Output Compare register A High Byte Timer1 Output Compare register a low byte Timer1 Output Compare register B high byte Timer1 Output Compare register B low byte Timer1 Input Capture register high byte Timer1 Input Capture registerregister low byte Timer2 Control register Timer2 (8-bit) Pre-load register 2 IrDA Control register Watchdog Timer Control register Program Mode (PMODE0, PMODE1 pins value) External Memory Interf. Control registerB External Memory Interf. Control register A Data register, Port A Data Direction register, Port A Input pins, Port A Data register, Port B Data Direction register, Port B Input Pins, Port B Data register, Port C Data Direction register, Port C Input Pins, Port C Data register, Port D Data Direction register, Port D Input Pins, Port D SPI I/O Data register SPI Status register SPI Control register Clock Control register
I/O Address (SRAM Address) $32($52) $31($51) $2E($4E) $2D($4D) $2C($4C) $2B($4B) $2A($4A) $29($49) $28($48) $27($47) $26($46) $25($45) $24($44) $23($43) $22($42) $21($41) $1F($3F) $1D($3D) $1C($3C) $1B($3B) $1A($3A) $19($39) $18($38) $17($37) $16($36) $15($35) $14($34) $13($33) $12($32) $11($31) $10($30) $0F($2F) $0E($2E) $0D($2F) $0C($2C)
46
AT76C713
5665B-USB-04/05
AT76C713
Table 7-1. AT76C713 I/O Space (Continued)
Name PERIPHEN PORTE DDRE PINE Function Peripheral Enable register Data register, Port E Data Direction register, Port E Input pins, Port E I/O Address (SRAM Address) $0B($2B) $0A($2A) $09($29) $08($28)
AVR Status Register (SREG) addr $3F($5F)
Bit Field I:Global interrupt enable T: Bit copy storage H: Half carry flag S: Sign bit V: Two's complement overflow flag N: Negative flag Z: Zero flag C: Carry flag
8 bits
AVR Description When set, the interrupts are enabled. The individual interrupt enable control is performed in the Individual Mask registers. This bit is cleared by H/W after an interrupt has occurred and is set by the RETI instruction to enable subsequent interrupts Bit load (BLD) and bit store (BST) instructions use the T bit as source and destination for the operated bit Indicates a half carry in some arithmetic operations Is an eXclusive OR between the negative flag N and the two's complement overflow flag V Supports two's complement arithmetic When set, this indicates a negative result in arithmetic and logic operations When set, this indicates a 0 result after the different arithmetic and logic operations When set, this indicates a carry in the arithmetic or logic operations
7
R/W
6 5 4
R/W R/W R/W
3
R/W
2 1 0
R/W R/W R/W
Stack Pointer (SP) addr $3E($5E), $3D($5D)
Bit 15:11 10 9 8 SP10 SP9 SP8 Field AVR R/W R/W SPH R/W R/W
11 bits
Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
47
ATMEL CONFIDENTIAL
Bit 7 6 5 4 3 2 1 0 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 Field AVR R/W R/W R/W R/W SPL R/W R/W R/W R/W Description
External Memory Interface Control Register A (EMICRA) addr $1C($3C)
Bit 7 6 5 4 3 2 1 0 Field RW1 RW0 RM1 RM0 WW1 WW0 WM1 WM0 Default 0 0 0 0 0 0 0 0
8 bits
AVR R/W R/W R/W R/W R/W R/W R/W R/W Description These bits control the Wait states inserted in the corresponding (read, write and ALE) signals These bits control the mode (waveform) of the corresponding (read, write and ALE) signals These bits control the Wait states inserted in the corresponding (read, write and ALE) signals These bits control the mode (waveform) of the corresponding (read, write and ALE) signals
External Memory Interface Control Register B (EMICRB) addr $1D ($3D)
Bit 7 6 5 4 Field AW1 AW0 AM1 AM0 Default 0 0 0 0
8 bits
AVR R/W R/W R/W R/W Description These bits control the Wait states inserted in the corresponding (read, write and ALE) signals Thse bits control the mode (waveform) of the corresponding (read, write and ALE) signals
48
AT76C713
5665B-USB-04/05
AT76C713
Bit 3:2 1 Field -- EMD0 Default 0 0 AVR R/W R/W These bits select the external memory interface mode according to the following table EMD1 0 EMD1 0 R/W 0 0 1 1 EMD0 0 1 0 1 External Memory Interface Mode FIFO Reserved Demultiplexed Multiplexed Description
MCU Control Register (MCUCR) The MCU Control register controls the effect of the SLEEP instruction (see AVR instruction set). Note that when the AVR is in sleep mode (stand-by or power-down mode), it will wake up on any enabled interrupt or on any USB activity (if the USB core is activated). Also, on any JTAG activity, if the system is in the power-down mode, it switches into stand-by mode. addr $35 ($55)
Bit 7 6 Field -- SE:Slee p Enable SM:Sle ep Mode select bit -- Default 0 0
8 bits
AVR -- R/W Description Reserved When set, this permits the MCU to enter in the sleep mode when the SLEEP instruction is executed This bit selects between the two available sleep modes When the MCU enters into the sleep state and the SM bit is cleared, then it enters into Idle Mode and only the AVR clock is stopped. Otherwise, if the SM bit is set, then the MCU enters into the power- down mode and the MCU disables the oscillator, stopping all clocks and any activity Reserved
5
0
R/W
4:0
0
--
ATMEL CONFIDENTIAL
5665B-USB-04/05
49
ATMEL CONFIDENTIAL
MCU Status Register (MCUSR) The MCU Status register provides information on which reset source caused an MCU reset. addr $34 ($54)
Bit 7:2 Field -- EXTRF: Externa l Reset Flag PORF: Power on Reset Flag Default --
8 bits
AVR -- Description -- External Reset Flag. This flag indicates that an external reset has occurred
1
R/W See Table 72 R/W
0
This flag indicates that a power-on reset has occurred
Table 7-2.
PORF and EXTRF Values After Reset
PORF 1 Unchanged Unchanged EXTRF Undefined 1 Unchanged
Reset Source Power-on Reset External Reset Watchdog Reset
The user program must clear these bits as early as possible. If these bits are cleared before a reset condition occurs, the source of resource can be found by using the truth table shown in Table 7-3.
Table 7-3.
Reset Source Identification
PORF 0 0 1 EXTRF 0 1 x Reset Source Watchdog Reset External Reset Power on Reset
External Interrupt Mask Register (EIMSK) The External Interrupt Mask register masks the external interrupts. External Interrupts should be acknowledged using general-purpose output pins. addr $37 ($57)
Bit 7 6 5 Field POL3: Polarity of external interrupt 1 POL2: Polarity of external interrupt 1 POL1: Polarity of external interrupt 1
8 bits
Default 0 0 0 AVR R/W R/W R/W Description INT3 is active high when this bit is low INT2 is active high when this bit is low INT1 is active high when this bit is low
50
AT76C713
5665B-USB-04/05
AT76C713
Bit 4 3 2 1 0 Field POL0: Polarity of external interrupt 0 INT3 INT2 INT1 INT0 Default 0 0 0 0 0 AVR R/W R/W R/W R/W R/W Description INT0 is active high when this bit is low If this is set and the I-bit in the Status register is set, the external pin interrupt 3 is enabled If this is set and the I-bit in the Status register is set, the external pin interrupt 2 is enabled If this is set and the I-bit in the Status register is set, the external pin interrupt 1 is enabled If this is set and the I-bit in the Status register is set, the external pin interrupt 0 is enabled
Clock Control Register (CLK_CNTR) The Clock Control register controls the clock generation circuit. For example, the PLL output clock rate can be switched from 96 MHz to 192 MHz by setting the CLK_CNTR register to $4C. addr $0C ($2C)
Bit 7 Field NPICP
8 bits
Default 0 AVR R/W Description Is equal to the reversed PLL ICP bit. Controls the PLL Charge-Pump current If this is set, the PLL Lock signal is used for `PLL Stable' indication. If cleared, the `PLL Stable' indication is equal to the `PLL Enable' signal delayed by a significant factor Select DPLL96 instead of DPLL48 for USB clock recovery If this is set, then do not close the oscillator during the power-down sleep mode PLL IVCO[1]. Selects the PLL frequency range. Normally, this bit must be equal to the MUL16 bit Selects the multiplier of the PLL. When this is set, the external 12 MHz crystal frequency is multiplied by 16 to generate an internal fast clock of 192 MHz. When cleared, the external 12 MHz crystal frequency is multiplied by 8, generating an internal fast clock of 96 MHz AVR core speed select bits. These bits control the AVR clock divisor according to Table 7-4
6 5 4 3
PLCK UDPLL OSC_NSLP PIVCO1
0 0 0 0
R/W R/W R/W R/W
2
MUL16
0
R/W
1 0
MCSP1 MCSP0
0 0
R/W R/W
Table 7-4.
MUL16 0 0 0 0 1
Microcontroller Speed Select Bits
MCSP1 0 0 1 1 0 MCSP0 0 1 0 1 0 48 MHz AVR clock rate 24 MHz 19, 2 MHz 16 MHz Reserved 192 div 4 Notes 96 div 4 96 div 5 96 div 6
ATMEL CONFIDENTIAL
5665B-USB-04/05
51
ATMEL CONFIDENTIAL
Table 7-4.
MUL16 1 1 1
Microcontroller Speed Select Bits
MCSP1 0 1 1 MCSP0 1 0 1 AVR clock rate 38,4 MHz 32 MHz Reserved Notes 192 div 5 192 div 6
Peripheral Enable Control Register (PERIPHEN) The Peripheral Enable Control register enables the peripheral components of the system. It controls the SPI, UARTs, USB, and external memory controllers. addr $0B ($2B)
Bit 7:6 5 4 3 2 1 Field -- SPI: SPI Enable UART1 Enable UART0 Enable UATTACH USB Enable EMIEN: External Memory Interface Enable 0 0 0 0 0 0
8 bits
Default AVR R R/W R/W R/W R/W R/W Description This bit is always read as 0 When set, this bit enables the SPI controller When set, this bit enables the function of UART1 When set, this bit enables the function of UART0 When set, this bit activates (logic 1) the USB_ATTACH pin When set, this bit enables the function of USB (clock enable) When set, this bit enables the external memory interface and the pin functions of Port A and Port C(1) are set to their alternative pin functions. The EMEN bit overrides any bit direction settings in the respective data direction registers
0
0
R/W
Program Mode Register (PMOD) The Program Mode register returns the value of the PMODE0 and PMODE1 input pins. addr $1F ($3F)
Bit 7:2 1 0 Field -- PMODE1 PMODE0 0 N/A N/A
8 bits
Default AVR R R R Description Always read as 0 The value of the PMODE1 input pin The value of the PMODE0 input pin
52
AT76C713
5665B-USB-04/05
AT76C713
I/O Debug Register (IDR) The I/O Debugs register communicates between the on-chip debug system (through JTAG) and the AVR CPU. It provides a communication channel from the running program in the microcontroller to the debugger. The CPU can transfer a byte to the debugger by writing to this location. addr $3C ($5C)
Bit 7 6 5 4 3 2 1 0 LSB Field IDRD:I/O Debug Register Dirty
8 bits
Default 0 0 0 0 0 0 0 0 AVR R/W R/W R/W R/W R/W R/W R/W R/W When the CPU reads the IDR register, the 7 LSB will be from the IDR register, while the MSB is from the IDRD bit. The debugger clears the IDRD bit after it has read the information Description This bit is set to indicate to the debugger that the register has been written
IrDA Control Register (IRDACR) The IrDA Control register controls the IrDA 1.0 codec. The IrDA codec is connected between the UART0 and UART1 SIN and SOUT signals and the corresponding pins. addr $22 ($42)
Bit 7:5 4 Field -- TXPOL: Transmit Polarity RXPOL: Receive Polarity MODE USEL: UART Select IRDAEN 0 0
8 bits
Default AVR R R/W If this bit is set, the SOUT signal is inverted Description
3
0
R/W
If this bit is set, the SIN signal is inverted before entering the IrDA codec When this bit is cleared, it enables the 3/16 return-to-zero encoding scheme. When this bit is set, it enables the 4/16 return-to-zero encoding scheme When this bit is cleared, the codec uses UART0. When this bit is set, the codec uses UART1 When this bit is set, it enables the IrDA codec. When this bit is cleared, the codec is transparent to the UART0/1 SIN/SOUT pins
2
0
R/W
1
0
R/W
0
0
R/W
ATMEL CONFIDENTIAL
5665B-USB-04/05
53
ATMEL CONFIDENTIAL
7.1 Timers/Counters
Timer/Counter Interrupt Mask Register (TIMSK) The Timer/Counter Interrupt Mask register masks the internal timer interrupts. addr $39 ($59)
Bit Field TOIE1: Timer/Counter 1 Overflow Interrupt Enable OCIE1A: Timer/Counter 1 Output Compare A Match Interrupt Enable OCIE1B: Timer/Counter 1 Output Compare B Match Interrupt Enable -- TICIE1: Timer/Counter 1 Input Capture Interrupt Enable TOIE2: Timer/Counter 2 Overflow Interrupt Enable TOIE0: Timer/Counter 0 Overflow Interrupt Enable --
8 bits
Default AVR Description When this bit is set and the I-bit in the Status register is 1, the Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $001C) is executed if an overflow in Timer/Counter1 occurs. The Timer/Counter1 Overflow Flag is set in the Timer/Counter1 Interrupt Flag register (TIFR) When this bit is set and the I-bit in the Status register is 1, the Timer/Counter1 Compare A Match interrupt is enabled. The corresponding interrupt (at vector $0018) is executed if a Compare A match in Timer/Counter1 occurs. The Compare A flag in Timer/Counter 1 is set, in the Timer/Counter Interrupt flag register (TIFR) When this bit is set and the I-bit in the Status register is 1, the Timer/Counter1 Compare B Match interrupt is enabled. The corresponding interrupt (at vector $001A) is executed if a Compare B match in Timer/Counter1 occurs.The Compare B flag in Timer/Counter 1 is set, in the Timer/Counter Interrupt flag register (TIFR)
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R When this bit is set and the I-bit in the Status register is 1, the Input Capture Event interrupt is enabled. The corresponding interrupt (at vector $0016) is executed if a capture event occurs on pin PB3. The Input Capture Flag in Timer/Counter1 is set in the Timer/Counter Interrupt Flag Register (TIFR) When this bit is set and the I-bit in the Status register is 1, the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt (at vector $0020) is executed if an overflow in Timer/Counter2 occurs. The Timer/Counter2 Overflow Flag is set in the Timer/Counter2 Interrupt Flag Register (TIFR) When this bit is set and the I-bit in the Status register is 1, the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $0020) is executed if an overflow in Timer/Counter0 occurs. The Timer/Counter0 Overflow Flag is set in the Timer/Counter0 Interrupt Flag Register (TIFR)
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R
54
AT76C713
5665B-USB-04/05
AT76C713
Timer/Counter Interrupt Flag Register (TIFR) addr $38 ($58)
Bit 7 6 OCFA: Output Compare Flag A OCFB: Output Compare Flag 1B -- ICF1: Input Capture Flag TOV2: Timer/Counter 2 Overflow Flag TOV0: Timer/Counter 1 Overflow Flag. -- Field 0 0
8 bits
Default AVR R/W R/W The OCFA is set when a compare match between Timer/Counter1 and the OCR1A register occurs. This flag is cleared when written with a logic 1 The OCF1B is set when a compare match between Timer/Counter1 and the OCR1B register occurs. This flag is cleared when written with a logic 1 Description
5 4
0 0
R/W R
3
0
R/W
This flag when set indicates an input capture event, where the contents of the Timer/Counter1 are transferred to the ICR1 register. This flag is cleared when written with a logic 1 Timer/Counter2 Overflow Flag. The TOV2 is set when an overflow occurs in Timer/Counter2. This flag is cleared when written with a logic 1 Timer/Counter0 Overflow Flag. The TOV0 is set when an overflow occurs in Timer/Counter0. This flag is cleared when written with a logic 1
2
0
R/W
1
0
R/W
0
0
R
7.2
Timer/Counter 0 and Timer/Counter 2
Timer/Counter 0 Control Register (TCCR0) addr $33 ($53)
Bit 7:3 Field -- 0
8 bits
Default AVR R Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
55
ATMEL CONFIDENTIAL
Bit 2 1 Field CS02 CS01 Default 0 AVR R/W R/W CS02 0 0 0 0 0 CS00 R 1 1 1 CS01 0 0 1 1 0 0 1 CS00 0 1 0 1 0 1 0 Description Stop, Timer/Counter0 is stopped CK CK/8 CK/64 CK/256 CK/1024 External Pin T0 (orT2), Falling Edge External Pin T0 (or T2), Rising Edge Description
1
1
1
The Timer/Counter2 Control Register (TCCR2) addr $25 ($45)
Bit 7:3 2 Field Reserved CS02: Clock Select 0 bit 2 CS01: Clock Select 0 bit 1 0 0
8 bits
Default AVR R R/W Description -- The Clock Select0 bits 2,1, and 0 define the pre-scaling source of Timer0
1
0
R/W
CS02 0 0 0 0
CS01 0 0 1 1 0 0 1 1
CS00 0 1 0 1 0 1 0 1
Description Stop, Timer/Counter0 is stopped CK CK/8 CK/64 CK/256 CK/1024 External Pin T0 (or T2), Falling Edge External Pin T0 (or T2), Rising Edge
0
CS00: Clock Select 0 bit 0
0
R/W
1 1 1 1
56
AT76C713
5665B-USB-04/05
AT76C713
Timer/Counter0 Register (TCNT0) addr $32 ($52)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB 0 0 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W R/W R/W Both Timer/Counter0 and Timer/Counter2 are realized as an up-counter with read and write access. If the TCNT0 (or TCNT2 respectively) is written and a clock source is present, the Timer/Counter0 (or Timer/Counter2) continues counting in the clock cycle following the write operation Description
Timer/Counter2 Register (TCNT2) Both Timer/Counter0 and Timer/Counter2 are realized as an up-counter with read and write access. If the TCNT0 (or TCNT2 respectively) is written and a clock source is present, the Timer/Counter0 (or Timer/Counter2) continues counting in the clock cycle following the write operation. addr $24 ($44)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB 0 0 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W R/W R/W Both Timer/Counter0 and Timer/Counter2 are realized as an up-counter with read and write access. If the TCNT0 (or TCNT2 respectively) is written and a clock source is present, the Timer/Counter0 (or Timer/Counter2) continues counting in the clock cycle following the write operation Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
57
ATMEL CONFIDENTIAL
Pre-load Register 0 (PRELD0) addr $31 ($51)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB 0 0 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W R/W R/W An 8-bit R/W register with a 0 initial value. The contents of this register are loaded to Timer/Counter0 TCNT0 (or Timer/Counter2 TCNT2 respectively) after an overflow Description
Pre-load Register 2 (PRELD2) addr $23 ($43)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB 0 0 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W R/W R/W An 8-bit R/W register with 0 initial value. The contents of this register are loaded to Timer/Counter0 TCNT0 (or Timer/Counter2 TCNT2 respectively) after an overflow Description
58
AT76C713
5665B-USB-04/05
AT76C713
7.3 Timer/Counter 1
Timer/Counter1 Register (TCCR1B) addr $2E ($4E)
Bit Field
8 bits
Default AVR Description When this bit is 0, the input canceler function is disabled. The input capture is triggered at the first rising/falling edge sampled on the Input Capture Pin (ICP), as specified by the ICES1 bit. When this bit is set, four successive samples are measured and all samples must be high/low according to the input capture trigger specification in the ICES1 bit. The actual sampling frequency is the CPU clock frequency When this bit is cleared, the Timer/Counter1 contents are transferred to the Input Capture register (ICR1) on the falling edge of the ICP. When this bit is 1, the contents are transferred on the rising edge
7
ICNC1: Input Capture 1 Noise Canceler (4 CKs
0
R/W
6
ICES1: Input Capture1 Edge Select -- CTCA1: Clear Timer/Counter 1 on Compare A match CS12: Clock Select 1,bit 2 CS11:Clock Select 1, bit 1
0
R/W
5:4
0
R When this bit is 1, the Timer/Counter1 is reset to $0000 after compare A match. If this bit is cleared, the Timer/Counter1 continues counting after a compare A match These bits select prescaling source for the Timer/Counter,1 according to the following table
3
0
R/W
2 1
0 0
R/W R/W
CS02 0 0 0 0 0 CS11:Clock Select 0, bit 0 0 R/W 1 1 1
CS01 0 0 1 1 0 0 1
CS00 0 1 0 1 0 1 0
Description Stop, Timer/Counter0 is stopped CK CK/8 CK/64 CK/256 CK/1024 External Pin T0 (orT2), Falling Edge External Pin T0 (or T2), Rising Edge
1
1
1
ATMEL CONFIDENTIAL
5665B-USB-04/05
59
ATMEL CONFIDENTIAL
Timer/Counter1 (TCNT1H and TCNT1L) The Timer/Counter1 is realized as a 16-bit up counter consisted of two 8-bit registers TCNT1H and TCNT1L. These registers have read and write access with an initial value of $00. If the Timer/Counter1 (TCNT1H and TCNT1L) register is written to and a clock source is selected, the Timer/Counter1 continues counting in the timer clock cycle after it is preset with the written value. To ensure that both the high and low bytes are read and written simultaneously when the CPU accesses these registers, the access is performed using an 8-bit temporary register (TEMP). This temporary register is also used when accessing OCR1A, OCR1B, and ICR1. If the main program and also interrupt routines perform access to registers using TEMP, the interrupts must be disabled during access from the main program. addr $2D ($4D), $2c ($4C)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LSB Field MSB Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AVR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT1 Timer/Counter1 Write: When the CPU writes to the high byte TCNT1H, the written data is placed in the TEMP register. Next, when the CPU writes the low byte TCNT1L, this byte of data is combined with the TEMP register and all 16-bits are written simultaneously to the Timer/Counter1 TCNT1 register. Consequently, the high byte must be accessed first for a full 16-bit write operation. When using the Timer/Counter1 as an 8-bit counter, it is sufficient to write the low byte only TCNT1 Timer/Counter1 Read: When the CPU reads the low byte TCNT1L, the data are placed in the TEMP register. Next, when the CPU reads the high byte TCNT1H, the CPU receives the data in the TEMP register. Consequently, the low byte must be accessed first for a full 16-bit read operation. When using Timer/Counter1 as an 8-bit counter, it is sufficient to read the low byte only
16 bits
Description
60
AT76C713
5665B-USB-04/05
AT76C713
Timer/Counter1 Output Compare Register A (OCR1AH and OCR1AL) Timer/Counter Output Compare register A consists of 16 bits and is made by two 8-bit R/W registers, with the initial value of 0, namely the OCR1AH and OCR1AL. Full 16-bit write and read operations are made according to the way specified for the Timer/Counter1 TCNT1. addr $2B ($4B), $2A ($4A)
Bit 15 14:8 7:1 0 LSB Field MSB Default 0 0 0 0 AVR R/W OCR1AH R/W R/W OCR1AL R/W
16 bits
Description
Timer/Counter1 Output Compare Register B (OCR1BH and OCR1BL) Timer/Counter Output Compare register B consists of 16 bits and is made by two 8-bit R/W registers, with the initial value of 0, namely the OCR1BH and OCR1BL. Full 16-bit write and read operations are made according to the way specified for the Timer/Counter1 TCNT1. addr $29 ($49), $28 ($48)
Bit 15 14:8 7:1 0 LSB Field MSB Default 0 0 0 0 AVR R/W OCR1BH R/W R/W OCR1BL R/W
16 bits
Description
The Timer/Counter1 Input Capture Register (ICR1H and ICR1L) The Timer/Counter Input Compare register consists of 16-bits and is made by two 8-bit read only registers, with initial value of 0, namely the ICR1H and ICR1L. When the rising or falling edge (according to the Input Capture Edge Setting (ICES1) of the signal at the Input Capture Pin (ICP) is detected, the current value of the Timer/Counter1 is transferred to the Input Capture register (ICR1). At the same time, the Input Capture Flag (ICF1) is set to 1. Full 16-bit read operations are made according to the way specified for the Timer/Counter1 TCNT1 above. addr $27 ($47), $26 ($46)
Bit 15 14:8 7:1 0 LSB Field MSB Default 0 0 0 0 AVR R OCR1H R R OCR1L R
16 bits
Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
61
ATMEL CONFIDENTIAL
7.4 Watchdog Timer
Watchdog Timer Control Register (WDTCR) addr $21 ($41)
Bit 7:5 Field -- WDTOE: Watchdog Turn Off Enable 0
8 bits
Default AVR R This bit must be set when the WDE bit is cleared. Otherwise, the Watchdog Timer will not be disabled. Once set, H/W will clear this bit to 0 after four clock cycles When this bit is set, the Watchdog Timer is enabled. When this bit is 0, the Watchdog Timer is disabled. The WDE bit can only be cleared if the WDTOE bit is set. To disable an enabled Watchdog Timer, the following procedure must be followed: In the same operation, write a logical 1 to bits WDTOE and WDE. A logical 1 must be written to the WDE bit even though it is set to 1 before the disable operation starts. Within the next four clock cycles, write a logical 0 to bit WDE. This disables the watchdog. Description
4
0
R/W
3
WDE: Watchdog Enable
0
R/W
2
WDP2: Watchdog Timer Prescaler 2 WDP1:Watc hdog Timer Prescaler 1 WDP0:Watc hdog Timer 0 Prescaler 0
0
R/W
1
R/W
These bits determine the Watchdog Timer prescaling when the Watchdog Timer is enabled, according to Table 7-5
0
R/W
Table 7-5.
WDP2 0 0 0 0 1 1 1 1
Watchdog Timer Prescale Register Select
WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 5.5 ms 11 ms 22 ms 47 ms 87 ms 175 ms 350 ms 700 ms Time-out Period 16K cycles 32K cycles 64K cycles 128K cycles 256K cycles 512K cycles 1024K cycles 2084K cycles
62
AT76C713
5665B-USB-04/05
AT76C713
7.5 SPI Interface
SPI Control Register (SPCR) addr $0D ($2F)
Bit 7 Field SPIE: SPI Interrupt Enable SPE: SPI Enable DORD: Data Order
8 bits
Default 0 AVR R/W Description This bit causes the setting of the SPIF bit in the SPSR register to execute the SPI interrupt provided that the global interrupt is enabled When this bit is set, the SPI is enabled and SS, MOSI, MISO, and SCK are connected to pins PB4, PB5, PB6, and PB7 When this bit is 1, the LSB of the data word is transmitted first. When this bit is cleared, the MSB of the data word is transmitted first This bit selects the master SPI when set and the slave SPI mode when cleared. If the SS is configured as input and driven low while the MSTR is set, the MSTR will be cleared, and the SPIF in the SPSR will become set. The user will then have to set the MSTR to re-enable the SPI master mode When this bit is set, SCK is high when idle. When the CPOL is cleared, the SCK is low when idle When this bit is set, the data is valid in the falling edge of the SCK if the CPOL = 0, or in the rising edge of the SCK when the CPOL = 1. When this bis is cleared, the data is valid in the rising edge of the SCK if the CPOL = 0 and in the falling edge of the SCK if the CPOL = 1 These two bits control the SCK rate of the device configured as a master. SPR1 and SPR0 have no effect during the slave mode. The relationship between the slave and the AVR clock frequency is shown in the following table: SPR1 SPR0 0 1 0 1 SCG Frequency {AVR clock rate} div 4 {AVR clock rate} div 16 {AVR clock rate} div 64 {AVR clock rate} div 128
6
0
R/W
5
0
R/W
4
MSTR: Master/Slave Select
0
R/W
3
CPOL: Clock Polarity
0
R/W
2
CPHA: Clock Phase
0
R/W
1
SPR1: SPI Clock Rate Select 1
0
R/W
0
SPR0: SPI Clock Rate Select 0
0 0 R/W 0 1 1
ATMEL CONFIDENTIAL
5665B-USB-04/05
63
ATMEL CONFIDENTIAL
SPI Status Register (SPSR) addr $0E ($2E)
Bit Field
8 bits
Default AVR Description When a serial transfer is complete, the SPIF bit is set and an interrupt is generated if SPIE in SPCR is set and the global interrupts are enabled. Alternatively, the SPIF bit is cleared by first reading the SPI status register with SPIF set, then accessing the SPI Data register. The WCOL bit is set if the SPI Data register (SPDR) is written during a data transfer. The WCOL and the SPIF bits are cleared by first reading the SPI Status register with the WCOL set, and then by accessing the SPI Data register Always read as 0
7
SPIF: SPI Interrupt Flag
0
R/W
6
WCOL: Write Collision Flag
0
R/W
5:0
--
0
R
SPI Data Register (SPDR0 addr $0F ($2F)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description It is used for data transfer between the register file and the SPI Shift register. Writing to the register initiates data transmission. Reading the register causes the Shift Register Receive buffer to be read
7.6
7.6.1
I/O PORTs
PORT A Port A is an 8-bit bi-directional I/O Port with internal pull-up resistors.
7.6.1.1
PORT A Alternative Functionality Port A, besides its use as a general-purpose I/O port, is used to support alternate functions. Specifically, serves also as the Address and Data bus of the External Memory Interface AD[0-7]. PORT A I/O Registers
7.6.1.2
PORT A Data Register (PORTA) addr $1B ($3B)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description It is an 8-bit R/W register with zero initial value 0xff. The bits in the Data Direction Register control the direction of the corresponding pin in the PORT A. When bit DDRBx is set, then PBx pin is input, while when DDRBx is cleared PBx is output, x=0...7
64
AT76C713
5665B-USB-04/05
AT76C713
PORT A Data Direction Register (DDRA) addr $1A($3A)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB 0 0 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W R/W R/W The bits in the Data Direction register control the direction of the corresponding pin in the PORT A. When bit DDRAx is set ,then the PAx pin is output, while when DDRAx is cleared, the PAx pin is input (X = 0..7) Description
PORT A Input Pins Address (PINA) addr $19($39)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB
8 bits
Default N/A N/A N/A N/A N/A N/A N/A N/A AVR R R R R R R R R The Port A Input Pins Address (PINA) is not a physical register. This address enables access to the physical voltage value on each port pin. It is a read-only address. The initial value of PINA depends from status of each PORT A pin Description
7.6.2
PORT B PORT B is an 8-bit bi-directional I/O port with internal pull-up resistors.
7.6.2.1
PORT B Alternative Functionality Port B, besides its use as a general-purpose I/O port, is used to support alternate functions. Specifically, the SPI interface, the input capture pin for Timer/Counter1, and the external clocks for the Timers/Counters are implemented through the B Port. When the SPI is enabled, the data direction of port B pins 4..7 is overridden, according to Table 7-6.
Table 7-6.
Port Pin PB0 PB1 PB2 PB3
Port B Pins Alternate Functions
Direction (DDRB) (DDRB) (DDRB) (DDRB) SPI Master SPI Slave Alternate Function External clock pin for Timer/Counter0 External clock pin for Timer/Counter1 Input capture pin for Timer/Counter1 ICP: Capture for Timer/Counter 1
ATMEL CONFIDENTIAL
5665B-USB-04/05
65
ATMEL CONFIDENTIAL
Table 7-6.
Port Pin PB4 PB5 PB6 PB7 (DDRB) Output Input Output
Port B Pins Alternate Functions
Direction Input Input Output/Hi-Z Input Alternate Function nSS (SPI slave select input) MOSI (SPI bus master output/slave input) MISO (SPI bus master input/slave output) SCK (SPI bus serial clock)
7.6.2.2
PORT B I/O Registers
PORT B Data Register (PORTB) addr $18 ($38)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB 0 0 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W R/W R/W It is an 8-bit R/W register with a 0 initial value 0xff. The bits in the Data Direction register control the direction of the corresponding pin in PORT B When bit DDRBx is set, then PBx pin is input, while when DDRBx is cleared, the PBx is output (x = 0...7) Description
PORT B Data Direction Register (DDRB) addr $17 ($37)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB 0 0 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W R/W R/W The bits in the Data Direction register control the direction of the corresponding pin in PORT B. When bit DDRBx is set, then the PBx pin is output, while when DDRBx is cleared, the PBx pin is input (X = 0..7) Description
66
AT76C713
5665B-USB-04/05
AT76C713
PORT B Input Pins Address (PINB) addr $16 ($36)
Bit 7 6 5 4 3 2 1 0 LSB Field MSB N/A N/A N/A N/A N/A N/A N/A N/A
8 bits
Default AVR R R R R R R R R The Port B Input Pins address (PINB) is not a physical register. This address enables access to the physical voltage value on each port pin. It is a read-only address. The initial value of PINB depends from status of each PORT B pin Description
7.6.3
PORT C PORT C is a 8-bit Output Port with internal pull-up resistors.
7.6.3.1
PORT C Alternative Functionality In addition to functioning as a general-purpose I/O port, PORT C is used to support alternate functions. Specifically, it is used as the Address bus A[8-14]and ALE of the external memory interface. PORT C I/O Regsiters
7.6.3.2
PORT C Data Register (PORTC) addr $15 ($35)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description It is an 8-bit R/W register with zero initial value 0xff. The bits in the Data Direction register control the direction of the corresponding pin in the PORT C When bit DDRBx is set, then PBx pin is input, while when DDRBx is cleared PBx is output, x = 0...7
PORT C Data Direction Register addr $14 ($34)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description The bits in the Data Direction register controls the direction of the corresponding pin in the PORT C When bit DDRCx is set, then PCx pin is output, while when the DDRCx is cleared, the PCx pin is input (x = 0..7)
ATMEL CONFIDENTIAL
5665B-USB-04/05
67
ATMEL CONFIDENTIAL
PORT C Input Pins Address (PINC) addr $13 ($33)
Bit 7 6:1 0 LSB Field MSB N/A N/A N/A
8 bits
Default AVR R R R Description The Port C Input Pins address (PINC) is not a physical register. This address enables access to the physical voltage value on each port pin. It is a read-only address. The initial value of PINC depends on the status of each PORT C pin
7.6.4
PORT D PORT D is an 8-bit bi-directional I/O port with internal pull-up resistors.
7.6.4.1
PORT D Alternative Functionality In addition to functioning as a general-purpose I/O port, PORT D is used to support alternate functions. Specifically, it offers the signals of UART0, as shown in Table 7-7. Also, when the UART0 is enabled, the data direction of the port D pins is overridden, according to Table 7-7. PORT D pins use the special pad "Vdd for PORTD" for a power supply.
Table 7-7.
Port Pin PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7
Port D Pins Alternate Functions
Direction Input Output Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Alternate Function Serial Receive In UART0 Serial Transmit Out UART0 nRTS, UART0 Ready To Send nCTS, UART0 Clear To Send nDSR, UART0 Data Set Ready nDTR, UART0 Data Terminal Ready nCD, UART0 Carrier Detect nRI, UART0 Ring Indicator
7.6.4.2
PORT D I/O Registers
PORT D Data Register (PORTD) addr $12 ($32)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description It is an 8-bit R/W register with zero initial value 0xff. The bits in the Data Direction register control the direction of the corresponding pin in the PORT D. When bit DDRBx is set, then PBx pin is input, while when DDRBx is cleared PBx is output (x = 0...7)
68
AT76C713
5665B-USB-04/05
AT76C713
PORT D Data Direction Register addr $11 ($31)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description The Data Direction register controls the direction of the corresponding pin in the PORT D When bit DDRDx is set, then the PDx pin is input, while when DDRDx is cleared, the PDx pin is output (x = 0...7)
PORT D Input Pins Address (PIND) addr $10 ($30)
Bit 7 6:1 0 LSB Field MSB
8 bits
Default N/A N/A N/A AVR R R R Description The Port D Input Pins address (PIND) is not a physical register. This address enables access to the physical voltage value on each port pin. It is a read-only address. The initial value of PIND depends on the status of each PORT D pin
7.6.5
PORT E Port E is an 8-bit bi-directional I/O port with internal pull-up resistors at pins PE0, PE1, and PE4..7, and internal pull-down resistors at pins PE2 and PE3.
7.6.5.1
PORT E Alternative Functionality In addition to functioning as a general-purpose I/O port, PORT E is also used to support alternate functions. Specifically, serves also as the Tx/Rx signals of UART1, as external interrupts and read/write signals for the External Memory Interface. When an alternative function is enabled, the data direction of port E pins is overridden, according to Table 7-8.
Table 7-8.
Port Pin PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7
Port E Pins Alternate Functions
Direction Input Output (DDRE) (DDRE) (DDRE) (DDRE) Output Output Alternate Function Serial Receive In UART1 Serial Transmit Out UART1 INT0: Edge triggered or level sensitive interrupt with pull-down INT1: Edge triggered or level sensitive interrupt with pull-down INT2: Edge triggered or level sensitive interrupt with pull-up INT3: Edge triggered or level sensitive interrupt with pull-up nWR: Write signal for the external memory interface nRD: Read signal for the external memory interface
ATMEL CONFIDENTIAL
5665B-USB-04/05
69
ATMEL CONFIDENTIAL
7.6.5.2 PORT E I/O Registers
PORT E Data Register (PORTE) addr $0A ($2A)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description The bits in the Data Direction register control the direction of the corresponding pin in the PORT E When bit DDRBx is set, then PBx pin is input, while when DDRBx is cleared PBx is output, x = 0...7
PORT E Data Direction Register (DDRE) addr $09 ($29)
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description The bits in the Data Direction register control the direction of the corresponding pin in the PORT E When bit DDREx is set, then PEx pin is output, When DDREx is cleared, the PEx pin is input (x = 0..7).
PORT E Input Pins Address (PINE) addr $08 ($28)
Bit 7 6:1 0 LSB Field MSB
8 bits
Default N/A N/A N/A AVR R R R Description The Port E Input Pins address (PINE) is not a physical register. This address enables access to the physical voltage value on each port pin. It is a read-only address. The initial value of PINE depends from status of eachPORT E pin
8. Memory Space (Register Description)
8.1 USB Register Set
The USB appears to the AVR to be just another peripheral. The USB register file is mapped to the SRAM space. Table 8-1 summarizes the USB cell specific registers.
Table 8-1.
USB Register Set
Address $F000 $F001 $F002 $F003 $F004 $F005 Default 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b Function Sleep mode control Master interrupt enable Master interrupt status Reset status Pair addressing enable DMA address Low
Register SLP_MODE IRQ_EN IRQ_STAT RES_STAT PAIR_EN USB_DMA_ADL
70
AT76C713
5665B-USB-04/05
AT76C713
Table 8-1. USB Register Set (Continued)
Address $F006 $F007 $F008 $F009 $F00A $F0A8 $F0A9 $F0AA $F0AB $F0AC $F0AD $F0AE $F0AF $F0B8 $F0B9 $F0BA $F0BB $F0BC $F0BD $F0BE $F0BF $F0C8 $F0C9 $F0CA $F0CB $F0CC $F0CD $F0CE $F0CF $F0D8 $F0D9 $F0DA $F0DB $F0DC $F0DD $F0DE Default 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b 00000000b x1110000b x1110000b x1110000b x1110000b x1110000b x1110000b x1110000b Function DMA address High DMA packet length requested DMA target Endpoint address DMA packet length transferred DMA enable FIFO Byte Count 7 register [10:8] FIFO Byte Count 6 register [10:8] FIFO Byte Count 5 register [10:8] FIFO Byte Count 4 register [10:8] FIFO Byte Count 3 register [10:8] FIFO Byte Count 2 register [10:8] FIFO Byte Count 1 register [10:8] FIFO Byte Count 0 register [10:8] FIFO Byte Count 7 register [7:0] FIFO Byte Count 6 register [7:0] FIFO Byte Count 5 register [7:0] FIFO Byte Count 4 register [7:0] FIFO Byte Count 3 register [7:0] FIFO Byte Count 2 register [7:0] FIFO Byte Count 1 register [7:0] FIFO Byte Count 0 register [7:0] FIFO 7 Data register FIFO 6 Data register FIFO 5 Data register FIFO 4 Data register FIFO 3 Data register FIFO 2 Data register FIFO 1 Data register FIFO 0 Data register Endpoint7 Control and Status register Endpoint6 Control and Status register Endpoint5 Control and Status register Endpoint4 Control and Status register Endpoint3 Control and Status register Endpoint2 Control and Status register Endpoint1 Control and Status register Register USB_DMA_ADH USB_DMA_LEN USB_DMA_EAD USB_DMA_PLT USB_DMA_EN FBYTE_CNT7_H FBYTE_CNT6_H FBYTE_CNT5_H FBYTE_CNT4_H FBYTE_CNT3_H FBYTE_CNT2_H FBYTE_CNT1_H FBYTE_CNT0_H FBYTE_CNT7_L FBYTE_CNT6_L FBYTE_CNT5_L FBYTE_CNT4_L FBYTE_CNT3_L FBYTE_CNT2_L FBYTE_CNT1_L FBYTE_CNT0_L FDR7 FDR6 FDR5 FDR4 FDR3 FDR2 FDR1 FDR0 ECSR7 ECSR6 ECSR5 ECSR4 ECSR3 ECSR2 ECSR1
ATMEL CONFIDENTIAL
5665B-USB-04/05
71
ATMEL CONFIDENTIAL
Table 8-1. USB Register Set (Continued)
Address $F0DF $F0E8 $F0E9 $F0EA $F0EB $F0EC $F0EC $F0EE $F0EF $F0F1 $F0F2 $F0F3 $F0F5 $F0F7 $F0F9 $F0FA $F0FB $F0FC $F0FD Default x1110000b 0xxx0000b 0xxx0000b 0xxx0000b 0xxx0000b 0xxx0000b 0xxx0000b 0xxx0000b 0xxx0000b 00000000b 00000000b xxx00000b xxxxx000b 00000000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b xxxxx000b Function Endpoint0 Control and Status register Endpoint7 Control register Endpoint6 Control register Endpoint5 Control register Endpoint4 Control register Endpoint3 Control register Endpoint2 Control register Endpoint1 Control register Endpoint0 Control register Function Endpoint Ping-pong register Function Address register USB Interrupt Enable register USB Interrupt Acknowledge register USB Interrupt Status register Suspend/Resume Interrupt Enable register Suspend/Resume register Global State register Frame Number Low register Frame Number High register
Register ECSR0 ECR7 ECR6 ECR5 ECR4 ECR3 ECR2 ECR1 ECR0 ENDPPGPG FADDR UIER UIAR UISR SPRSIE SPRSR GLB_STATE FRM_NUM_L FRM_NUM_H
SLP_MODE (Sleep Mode Control Register) addr: $F000
Bit 7:6 5 4:0 Field Reserved SLP Reserved R/W
8 bits
AVR Description Reserved and set to 0 If set, put the USB Controller in sleep mode Reserved and set to 0
IRQ_EN (USB Interrupt Mask Register) addr: $F001
Bit 7 6 Field Reserved INT_EN
8 bits
AVR R/W R/W Description Reserved and set to 0 When this bit is high, enables the USB protocol handler to cause an interrupt (see UISR and IRQ_STAT[6])
72
AT76C713
5665B-USB-04/05
AT76C713
Bit 5:2 Field Reserved AVR R/W Description Reserved and set to 0 If this bit is high, an interrupt is generated when the USB enters suspend mode A USB device enters in suspend mode only when requested by the USB Host through bus inactivity for at least 3 ms If this bit is high, an interrupt is generated when the USB enters resume mode. A J-to-K state change on the USB port signal resume
1
SUSP_INT_EN
R/W
0
RSM_INT_EN
R/W
IRQ_STAT (USB Interrupt Status Register) The IRQ_STAT register is automatically cleared on each read access. addr: $F002
Bit 7 6 5:4 3 Field Reserved INT Reserved USB_RST
8 bits
AVR R R R R Description Reserved and set to 0 Interrupt from the USB protocol handler. When this bit is high, then at least one bit of UISR is set Reserved and set to 0 This bit is high, while the USB bus remains in reset state. This bit can be accessed also by using the RES_STAT register, avoiding to clear the IRQ_STAT When this bit is high, the USB has exited from the suspend mode When this bit is high, the USB has entered the suspend mode When this bit is high, the USB host controller has sent a Reset request (USB bus entered the reset state)
2 1 0
nSUSP pSUSP pUSB_RST
R R R
RES_STAT (Reset Status) addr: $F003
Bit 7:4 3 2:0 Field Reserved USB_RST Reserved
8 bits
AVR R R R Description Reserved and set to 0 This bit is high while the USB bus remains in reset state Reserved and set to 0
ATMEL CONFIDENTIAL
5665B-USB-04/05
73
ATMEL CONFIDENTIAL
PAIR_EN (Pair Addressing Enable) addr: $F004
Bit 7:4 Field Reserved
8 bits
AVR R Description Reserved and set to 0 By setting any of these bits, a pair of EPs is formed of one IN and one OUT. For example, if UPA[1] is set, the EP1 should be configured as an OUT EP, while the EP4 as an IN EP: UPA[1]: EP4 has the same USB physical address with EP1 UPA[2]: EP5 has the same USB physical address with EP2 UPA[3]: EP6 has the same USB physical address with EP3 Reserved and set to 0
3:1
UPA[3:1]
R/W
0
Reserved
R
USB_DMA_ADL (DMA Address Low) addr: $F005
Bit 7:0 Field UDA[7-0]
8 bits
AVR R/W Description The least significant byte of the target address at the Data Memory that the DMA controller will use
USB_DMA_ADH (DMA Address High) addr: $F006
Bit 7 6:0 Field Reserved UDA[14-8]
8 bits
AVR R R/W Description Reserved and set to 0 These are seven bits along with the eight bits of the USB_DMA_ADL, form the target address UDA[14-0] at the Data Memory that the DMA will use
USB_DMA_LEN (DMA Packet Length) addr: $F007
Bit 7:0 Field PLEN[7-0]
8 bits
AVR R/W Description The AVR writes the number of bytes for the next DMA
74
AT76C713
5665B-USB-04/05
AT76C713
USB_DMA_EAD (DMA Target Endpoint Address) addr: $F008
Bit Field
8 bits
AVR Description The AVR writes the offset byte of the FDRx address, depending on the Endpoint that is going to send or has received the data: The following Endpoints with the corresponding offset bytes are supported by the DMA channels: FDR1: $CE FDR2: $CD FDR3: $CC FDR4: $CB FDR5: $CA FDR6: $C9 FDR7: $C8
7:0
EAD[7:0]
R/W
USB_DMA_PLT (DMA Packet Length Transferred) addr: $F009
Bit 7:0 Field TPL[7:0]
8 bits
AVR R/W Description Returns the number of bytes transferred during the last DMA
USB_DMA_EN (DMA Enable Register) addr: $F00A
Bit 7:2 1 0 Field Reserved USB_RDMA _EN USB_TDMA_ EN
8 bits
AVR R R/W R/W Description Reserved and set to 0 Enables Receive DMA (for OUT EPs). This bit is automatically cleared after the end of the DMA Enables Transmit DMA (for IN EPs). This bit is automatically cleared after the end of the DMA
FBYTE_CNTx_H (FIFO Byte Count High Register) Each Endpoint has a register that stores the number of bytes to be sent or that was received by the USB H/W. The maximum data packet supported is 1024 bytes length for isochronous Endpoints. addr: See Table 8-1
Bit 7:3 2:0 Field Reserved BYTECNT[10:8] AVR Reserved R/W Description Reserved Length of data packet in FIFO
ATMEL CONFIDENTIAL
5665B-USB-04/05
75
ATMEL CONFIDENTIAL
FBYTE_CNTx_L (FIFO Byte Count Low Register) addr: See Table 8-1
Bit 7:0 Field BYTECNT[7:0} AVR R/W Description Length of data packet in FIFO
FDR (FIFO Data Registers 0 -7) FIFO Data registers are dual function buffer registers. Received data are read by the processor from the Endpoint's FIFO through these data registers. In the transmit mode, the processor writes to the FIFO though this register. addr: See Table 8-1
Bit 7:0 Field FIFO DATA [7:0]
8 bits
AVR R/W Description Data to be written to FIFO or data to be read from the FIFO
ECSR (Endpoint Control and Status Registers 0 - 7) addr: See Table 8-1
Bit Field AVR
8 bits
Description This bit is set by the processor to indicate to the USB H/W the direction of a control transfer 0 = control write. No data stage 1 = control read This bit is used by Control Endpoints only and is used by FW to indicate the direction of a control transfer. It is written by the FW after it receives a RX SETUP interrupt. The H/W uses this bit to determine the status phase of a control transfer This bit indicates that the processor has placed the last data packet in FIFO0, or that the processor has processed the last data packet it expects from the Host This bit is used only by Control Endpoints together with bit 1 (TX Packet Ready) to signal the USB H/W to go to the STATUS phase after the packet currently residing in the FIFO is transmitted After the H/W completes the STATUS phase it will interrupt the processor without clearing this bit CAUTION: Because the Data End bit signals "END OF TRANSACTION", any other Endpoint controller bit set after the DATA END is not considered by the Ping-pong controller., which is why Tx_Packet Ready should be set before DATA END This bit is set by the processor to indicate a stalled Endpoint. The H/W will send a STALL handshake as a response to the next IN or OUT token The processor sets this bit if it wants to force a STALL if an unsupported request is received or if the Host continues to ask for data after the data is exhausted. This bit should be set at the end of any data phase or setup phase
7
Control Direction
R
6
Data End
R
5
Force Stall
R
76
AT76C713
5665B-USB-04/05
AT76C713
Bit Field AVR Description This bit indicates that the processor has loaded the FIFO with a packet of data. This bit is cleared by the H/W after the USB Host acknowledges the packet. For ISO Endpoints, this bit is cleared unconditionally after the data is sent This bit is used for the following operations :
* Control read transactions by a Control Endpoint
TX Packet Ready
4
R/C
* IN transactions with DATA1 PID to complete the status phase for a Control Endpoint, when this bit is 0, but bit Data End (bit 4) is 1 * By a BULK IN or ISO IN or INT IN Endpoint
The processor should write into the FIFO only if this bit is cleared. After it has completed writing the data, it should set this bit. The data can be of 0 length. For a Control Endpoint, the processor should write to the FIFO only when bit 6 (TX Packet Requested) is set. The H/W clears this bit after it receives an ACK. If the interrupt is enabled, clearing this bit by the H/W causes an interrupt to the processor
3
Stall Snd
W
The USB H/W sets this bit after a STALL is sent to the Host. The firmware uses this bit when responding to a USB GetStatus Request This bit indicates End of data stage for the Control Endpoint only The USB H/W sets this bit when it receives a valid setup packet from the Host. This bit is used by Control Endpoints only to signal to the processor that the USB H/W has received a valid SETUP packet and that the data portion of the packet is stored in the FIFO. The H/W will clear all other bits in this register and will set the RX SETUP. If the corresponding interrupt is enabled, the processor will be interrupted when the RX SETUP is set. After the completion of reading the data from the FIFO, the firmware should clear this bit This bit indicates that the USB H/W has decoded an OUT token and that the data is in the FIFO. The USB H/W sets this bit after it has stored the data of an OUT transaction in the FIFO. When this bit is set, the H/W will NAK all OUT tokens. For Control Endpoints only, bit 7 of this register, Enable Control Write, has to be set for the H/W to accept the OUT data. The USB H/W will not overwrite the data in the FIFO except for an early USB Setup Request. Bit RX OUT Packet is used for the following operations:
2
RX SETUP
W
1
RX OUT Packet
W
* Control write transactions by a Control Endpoint * OUT transaction with DATA1 PID to complete the status phase of a controlEndpoint * By a BULK OUT or ISO OUT or INT OUT Endpoint
Setting this bit causes an interrupt to the processor if the interrupt is enabled. The firmware clears this bit after the FIFO is read The H/W sets this bit to indicate to a Control Endpoint that it has received an ACK handshake from the Host. This bit is used by H/W in a Control Endpoint to signal to the processor that it has successfully completed certain transactions. TX Complete is set at the completion of a:
0
TX Complete
R
* Control read data stage * Status stage without data stage * Status stage after a control write transaction
ATMEL CONFIDENTIAL
5665B-USB-04/05
77
ATMEL CONFIDENTIAL
ECR (Endpoint Control Registers 0 -7) addr: See Table 8-1
Bit 7 6 5:4 3 2 Field EPEDS Reserved Reserved DTGLE EPDIR
8 bits
AVR R R Reserved and set to 0 W R Data Toggle. Identifies DATA0 or DATA1 packets Endpoint Direction Only applicable for non-Control Endpoints (0 = Out, 1 = In) Endpoint Type These bits represent the type of the Endpoint as follows: Bit1 Bit0 Type 0 0 Control 0 1 Isochronous 1 0 Bulk 1 1 Interrupt Description Endpoint Enable/Disable (0 = Disable Endpoint, 1 = Enable Endpoint) Reserved
1:0
EPTYPE
R
ENDPPGPG (Endpoint Ping-Pong Enable Register) addr: $F0F1
Bit 7 6 5 4 3 2 1 0 Field Reserved PG PG 6 EN PG PG 5 EN PG PG 4 EN PG PG 3 EN PG PG 2 EN PG PG 1 EN PG PG 0 EN R R R R R R R Enable Endpoint 6 Ping-pong Enable Endpoint 5 Ping-pong Enable Endpoint 4 Ping-pong Enable Endpoint 3 Ping-pong Enable Endpoint 2 Ping-pong Enable Endpoint 1 Ping-pong Enable Endpoint 0 Ping-Pong
8 bits
AVR Description
78
AT76C713
5665B-USB-04/05
AT76C713
FADDR (Function Address Register) addr: $F0F2 Table 1.
Bit 7 Field FEN AVR R Function Enable Description The FIU contains an address register that contains the function address assigned by the Host. The Function Address register must be programmed by the processor once it has received a SET_ADDRESS command from the Host and completed the status phase of the transaction. After power up or reset, this register will contain the value of 0x00. The Function Enable bit (FEN) allows the firmware to enable or disable the function Endpoints. The firmware will set this bit after receipt of a reset through the USB H/W. Once this bit is set, the USB H/W passes packets to and from the Host
8 bits
6:0
FADD[6:0]
R
Function address
UIER (USB Interrupt Enable Register) addr: $F0F3
Bit 7 6 5 4 3 2 1 0 Field SOF IE EP6 IE EP5 IE EP4 IE EP3 IE EP2 IE EP1 IE EP0 IE AVR R R R R R R R R Enable SOF Interrupt Enable Endpoint 6 Interrupt Enable Endpoint 5 Interrupt Enable Endpoint 4 Interrupt Enable Endpoint 3 Interrupt Enable Endpoint 2 Interrupt Enable Endpoint 1 Interrupt Enable Endpoint 0 Interrupt The bits in this register have the following meaning: 1 = Enable interrupt 0 = Disable interrupt
8 bits
Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
79
ATMEL CONFIDENTIAL
UIAR (USB Interrupt Acknowledge Register) addr: $F0F5
Bit 7 6 5 4 3 2 1 0 Field Reserved EP6 INTA EP5 INTA EP4 INTA EP3 INTA EP2 INTA EP1 INTA EP0 INTA W W W W W W W Endpoint 6 Interrupt Acknowledge Endpoint 5 Interrupt Acknowledge Endpoint 4 Interrupt Acknowledge Endpoint 3 Interrupt Acknowledge Endpoint 2 Interrupt Acknowledge Endpoint 1 Interrupt Acknowledge Endpoint 0 Interrupt Acknowledge The bits in this register are used to indirectly clear the bits of the UISR. A bit in the UISR is cleared if a 1 is written in the corresponding bit of UIAR AVR
8 bits
Description
UISR (USB Interrupt Status Register) addr: $F0F7
Bit 7 6 5 4 3 2 1 0 Field Reserved EP6 INT EP5 INT EP4 INT EP3 INT EP2 INT EP1 INT EP0 INT W W W W W W W Endpoint 6 Interrupt Endpoint 5 Interrupt Endpoint 4 Interrupt Endpoint 3 Interrupt Endpoint 2 Interrupt Endpoint 1 Interrupt Endpoint 0 Interrupt
8 bits
AVR Description The function interrupt bits will be set by the H/W whenever the following bits in the corresponding Endpoint's Control and Status register are modified by the USB H/W: RX OUT Packet is set (Control and OUT Endpoints) TX Packet Ready is cleared (Control and IN Endpoints) RX SETUP is set (Control Endpoints only) TX Complete is set (Control Endpoints only)
80
AT76C713
5665B-USB-04/05
AT76C713
SPRSIE (Suspend/Resume Interrupt Enable Register) addr: $F0F9
Bit 7:4 3 2 1 0 Field Reserved SOF IE EXTRSM IE RCVDRSM IE SUSP IE R R R R Enable SOF Interrupt Enable External Resume Signaling Interrupt 1 = enable 0 = disable Enable BUS Resume Signaling Interrupt 1 = enable 0 = disable Enable Suspend Signaling Interrupt 1 = enable 0 = disable
8 bits
AVR Description
SPRSR (Suspend/Resume Register) addr: $F0FA
Bit 7:4 3 Field Reserved SOF INT R/W Start Of Frame Interrupt. Firmware clears this bit to acknowledge the SOF interrupt. Received External Resume. The USB H/W sets this bit to denote an External Resume Interrupt. If RMWUPE =1, a RESUME signal is send in USB BUS. Firmware clears this bit to acknowledge the EXT RSM interrupt. Received Resume. The USB H/W sets this bit when a USB resume signaling is detected at its port. Firmware clears this bit to acknowledge the RCVD RSM interrupt. Suspend. The USB H/W sets this bit when it detects no SOF for 3ms. The USB macro enters in SUSPEND MODE, the processor has to go in SLEEP mode.Firmware clears this bit to acknowledge the SUSP interrupt.
8 bits
AVR Description
2
EXT RSM
R/W
1
RCVD RSM
R/W
0
SUSP
R/W
GLB_STATE (Global State Register) addr: $F0FB
Bit 7:4 3 Field Reserved RSMINPR W
8 bits
AVR Description Reserved Set by the H/W when a Resume is send in the USB bus during Remote Wake-up feature (13 ms)
ATMEL CONFIDENTIAL
5665B-USB-04/05
81
ATMEL CONFIDENTIAL
Bit 2 Field RMWUPE AVR R Description Remote Wake-up Enable. This bit is set if the Host enables the function's remote wake-up feature Configured. This bit is set by the firmware after a valid SET_CONFIGURATION request is received. It is cleared by a reset or by a SET_CONFIGURATION with a value of 0 Function Address Enable. This bit is set by firmware after the status phase of a SET_ADRESS request transaction. The Host will use the new address starting at the next transaction
1
CONFG
R
0
FADD Enable
R
FRM_NUM_L (Frame Number Low Register) addr: $F0FC
Bit 7:0 Field FCL[7:0]
8 bits
AVR W Description This is the lower 8-bits of the 11 bit frame number of SOF packet
FRM_NUM_H (Frame Number High Register) addr: $F0FD
Bit 7:3 2:0 Field Reserved FCH[10:8] W
8 bits
AVR Description Reserved and set to 0 This is the upper 3 bits of the 11 bit frame number of SOF packet
8.2
UART Register Set
The base address for UART0 registers is $F200 and for UART1 registers is $F300. Each read or write access of the UART registers consumes at least 2 CPU cycles, since the UART core clock is asynchronous and fixed to 14.769 MHz. The register file and its fields are briefly presented in Table 26. A more detailed description is provided in the following sections.
Table 8-2.
Addr A[3:0]
UART Register File and Register Fields
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
General Register Set 0000 DLAB = 0 00000 DLAB = 0 RHR THR MSB MSB LSB LSB
82
AT76C713
5665B-USB-04/05
AT76C713
Table 8-2.
0001 DLAB = 0
UART Register File and Register Fields (Continued)
Enable Modem Status Interrupt Interrupt ID Bit 2 DMA Mode Enable Rx Line Status Interrupt Interrupt ID Bit 1 Tx FIFO Reset Enable THR Ready Interrupt Interrupt ID Bit 0 Rx FIFO Reset Word Length Bit 1 RTS Overrun Error Delta DSR Enable Rx Data Available Interrupt Not Interrupt Pending FIFO Enable Word Length Bit 0 DTR Rx Data Available Delta CTS LSB
IER
0
0
0
0
0010
IIR
FIFO Enabled Rx FIFO Trigger MSB Divisor Latch Access (DLAB) 0 Error in Rx FIFO CD MSB
FIFO Enabled Rx FIFO Trigger LSB
0
0
0010
FCR
0
0
0011
LCR
Set Break
Stick Parity 0 THR Ready DSR
Even Parity Loopback Break Interrupt CTS
Enable Parity OUT2 Framing Error Delta CD
Number of Stop Bits OUT1 Parity Error Trailing Edge RI
0100 0101 0110 0111
MCR LSR MSR SCR
0 Transmitte r Empty RI
Special Register Set 0000 DLAB = 1 0001 DLAB = 1 1000 DLL DLH MSB MSB Output pins in Loopback Tx FIFO Disable nCD pin Direction MSB MSB Send Address Transmitte r Empty nRI pin Direction Start Time-out Control THR Ready nDSR pin Direction Restart Time-out THR Ready bit Control nCTS pin Direction Tx Reset Rx Reset Tx Disable LSB LSB Rx Disable Multidrop nDTR pin Direction LSB LSB
XR1
1001
XR2
0 nOut2 pin Direction
0 nOut1 pin Direction
0 nRTS pin Direction
1010 1011 1100
MDR RTO TTG
Receive Holding Register (RHR) addr: $0000
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R R R This bit holds the received byte Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
83
ATMEL CONFIDENTIAL
Transmit Holding Register (THR) addr: $0000
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR W W W This bit holds the byte to be transmitted Description
Interrupt Enable Register (IER) addr: $0001
Bit 7:4 Field -- MSI: Enable Modem Status Interrupt RLSI: Enable Receive Line Status Interrupt TRI: Enable THR Ready Interrupt RDAI: Enable RX Data Available Interrupt 0
8 bits
Default AVR R/W Description --
3
0
R/W
If this bit is set, it enables the MODEM status interrupt (MSR[7:4])
2
0
R/W
If this bit is set, it enables the line status interrupt (LSR[4:1])
1
0
R/W
If this bit is set, it enables the THR ready interrupt (LSR[5])
0
0
R/W
If this bit is set, it enables the Rx data available interrupt. It also enables the time-out interrupt when the time-out counter is enabled (in FIFO mode or if RTO is not 0, see XR1[5] and RTO)
Interrupt Identification Register (IIR) addr: $0010
Bit 7:6 5:4 3 Field FIFOEN: FIFO Enabled -- ID2
8bits
Default 0 0 0 AVR R R R Description These two bits are set when FCR[0] is set -- Interrupt ID Bit 2
84
AT76C713
5665B-USB-04/05
AT76C713
Bit 2 1 0 Field ID1 ID0 NIP:Not Interrupt Pending Default 0 0 0 AVR R R R Description Interrupt ID Bit 1 Interrupt ID Bit 0 When this bit is in logic 0, then an interrupt is pending and the IIR[3..1] bits may be used for interrupt type identification. When this bit is in logic 1, no interrupt is pending
Table 8-3.
Priority Highest
UART Interrupt Priority
ID2 0 ID1 1 ID0 1 Interrupt Source (Event) Receiver Line Status (LSR[3..1] not 0) Received Data Available Interrupt Reset Control Reading LSR Reading all the data from the Receive Holding Register or the Rx FIFO Reading the RHR or receiving a new word from SIN pin Reading IIR or writing to THR
0
1
0
1 0
1 0
0 1
Time-out Indication Transmitter Holding Register Ready Modem Status (when any bit in MSR[7..4] changes from `0' to `1').
Lowest
0
0
0
Reading MSR
FIFO Control Register (FCR) addr: $0010
Bit 7 Field RCVR1 0
8 bits
Default AVR W Description RCVR trigger bits. These bits indicate the minimum number of bytes required in the receive FIFO to generate a receive ready interrupt. The trigger level is shown from the following table
6
RCVR0
0
W
Bit 7 0 0 1 1 --
Bit 6 0 1 0 1
Trigger Level (Words) 1 4 8 14
5:4
-- RDMA: DMA Mode select
0
W
3
0
W
When FIFOs are disabled (FCR[0] is low), this bit is forced to 0. When set to logic 1, the DMA is in burst mode allowing transfers until the Rx FIFO has been emitted or the Tx FIFO has been filled. When it is cleared to 0, the DMA is in single mode and the words are read one word at a time
ATMEL CONFIDENTIAL
5665B-USB-04/05
85
ATMEL CONFIDENTIAL
Bit 2 Field TRS:Tx FIFO reset FRS:Rx 1 Default 0 AVR W Description When this bit is set, it resets the transmit FIFO
FIFO reset
FEN:FIFO enable
0
W
When this bit is set, it resets the receive FIFO When this bit is set, it enables the 16-byte receive and transmit FIFOs. When this bit is cleared, the FIFOs are disabled and reset
0
0
W
Line Control Register (LCR) addr: $0011
Bit Field DLAB: Divisor Latch Access
8 bits
Default AVR Description This bit must be set to logic 1 during a read or write operation in order to access the Divisor Latches. Resetting this bit to 0 allows access to RHR, THR, and IER If this bit is set, then it causes a break condition to to be transmitted to the receiving UART. The SOUT pin is forced to the spacing state (logic 0). Resetting to logic 0 stops the break condition. The break control bit acts only on SOUT pin and has no effect on the transmitter logic. Note that UART waits before starting the break condition command for the complete transmission of the word in the transmit shift register. There is no need for software synchronization When the Parity Enable and the Parity Stick bits are set to logic 1, then the Even Parity bit controls the transmitted parity value. By resetting the Even Parity bit to logic 0, the parity bit is transmitted and checked as 1. By setting the Even Parity bit to logic 1, the parity bit is transmitted and checked as 0 When the Enable Parity bit is a 1 and the Stick Parity bit is a 0, then by setting to the Even Parity bit o 1 an even number of logic 1s is transmitted or checked in the data word bits and the Parity bit. When Even Parity bit is reset to logic 0, an odd number of 1s are transmitted or checked By setting this bit to logic 1, a parity bit is transmitted or checked. Resetting this bit to 0, no parity bit is transmitted or checked
7
0
R/W
6
SBRK: Set Break
0
R/W
5
SPAR: Stick Parity
0
R/W
4
EVPAR: Even Parity
0
R/W
3
ENPAR: Enable Parity
0
R/W
86
AT76C713
5665B-USB-04/05
AT76C713
Bit Field Default AVR Description This bit determines the number of stop bits according to the following table: SB: Number of Stop Bits
2
0
R/W
Bit 2 0 1 1
Word Length any 5 6, 7, 8
Number of Stop Bits 1 1,5 2
1
WL1: Word Length
0
R/W
These bits determine the word length according to the following table
0
WL0: Word Length
0
R/W
Bit 1 0 0 1 1
Bit 0 0 1 0 1
Word Length (Bits) 5 6 7 8
Modem Control Register (MCR) addr: $0100
Bit 7:5 4 3 2 1 0 Field -- LB: Loopback OUT2 OUT1 RTS DTR 0 0 0 0 0 0
8 bits
Default AVR R/W R/W R/W R/W R/W R/W If this bit is set, it enables the loopback mode. This bit cannot be set to logic 1 if the value of MDR is not $F0 The compliment value of the bi-directional pin nOUT2 The compliment value of the bi-directional pin nOUT1 The compliment value of the bi-directional pin nRTS The compliment value of the bi-directional pin nDTR Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
87
ATMEL CONFIDENTIAL
Line Status Register (LSR) addr: $0101
Bit Field ERF: Error in RX FIFO TE: Transmitter Empty Default
8 bits
AVR Description If the FIFOs are disabled, this bit is a 0. If the FIFOs are enabled, this bit indicates that at least one word in the Rx FIFO has its Parity Error, Framing Error, or Break Indication bits high If set, this bit indicates that both the Transmit Shift register and Transmit Holding register, or the Tx FIFO if Tx FIFO is enabled, are empty If set, this bit indicates that the THR is ready to accept a new word for transmission. This bit is set when a word is transferred from the THR into the Tx Shift register. This bit is reset concurrently with the loading of the THR by the core. If the Tx FIFO is enabled (FCR[0] = 1, XR2[7] = 0), the function of this bit is controlled by XR2[4]. If XR2[4] is 0, then this bit is set when the Tx FIFO is empty; it is cleared when at least 1 word is written to the Tx FIFO. If XR2[4] is 1, then this bit is set when the Tx FIFO is not full If set, this bit indicates a Break Interrupt that the receive data input is held in the spacing state (logic 0) for longer than a full word transmission time.In FIFO mode, this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic 0 whenever the core reads the LSR If set, this bit indicates a framing error. The received word in RHR does not have the correct stop bit. In FIFO mode, this error is associated with the word at the top of the Rx FIFO which is equivalent to RHR. This bit is reset to a logic 0 whenever the core reads the LSR If set, this bit indicates a parity error. The received word in RHR does not have the correct parity bit. In FIFO mode, this error is associated with the word at the top of the FIFO which is equivalent to RHR. This bit is reset to a logic 0 whenever the core reads the LSR If set, this bit indicates an overrun error, that is, the data in RHR was not read by the core before the next word was transferred into the RHR, thereby destroying the previous word. In FIFO mode, an overrun error will occur only after the Rx FIFO is full and the next word has been completely received in the Shift register. The word in the shift register is overwritten, but it is not transferred to the Rx FIFO. The overrun error is indicated to the core as soon as it happens. This bit is reset to a logic 0 whenever the core reads the LSR If set, this bit indicates that there is data available in the RHR. This bit resets to logic 0 by reading all of the data from the Receive Holding Register or the Rx FIFO
7
0
R
6
0
R
5
THRR: Transmit Holding Register ready
0
R
4
BI: Receive Break Interrupt
0
R
3
FE: Framing Error
0
R
2
PE:Parity Error
0
R
1
OE:Overrun Error
0
R
0
RDA: Receive Holding Register Ready
0
R
88
AT76C713
5665B-USB-04/05
AT76C713
Modem Status Register (MSR) addr: $0110
Bit 7 Field CD
8 bits
Default 0 AVR R/W Description The compliment of the bi-directional Carrier Detect nCD I/O pin. If MCR[4] is set (loopback mode), then this bit is equivalent to nOUT2 pin The compliment of the bi-directional Ring Indicator nRI I/O pin. If MCR[4] is set (loopback mode),then this bit is equivalent to nOUT1 pin The compliment of the bi-directional Data Set Ready nDSR I/O pin. If MCR[4] is set (loopback mode), then this bit is equivalent to nDTR pin The compliment of the bi-directional Clear To Send nCTS I/O pin. If MCR[4] is set (loopback mode), then this bit is equivalent to nRTS pin This bit indicates that the nCD pin has changed state since the last time it was read by the core This bit indicates that the nRI pin has changed from a low to a high state since the last time it was read by the core This bit indicates that the nDSR pin has changed states since the last time it was read by the core This bit indicates that the nCTS pin has changed states since the last time it was read by the core
6
RI
0
R/W
5
DSR
0
R/W
4
CTS DCD: Delta Carrier Detect indicator TRI: Trailing Edge of Ring Indicator DDSR: Delta Data Set Ready indicator DCTS: Delta Clear To Send indicator
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Scratch-pad Register (SCR) addr: $0111
Bit 7 6:1 0 LSB Field MSB
8 bits
Default 0 0 0 AVR R/W R/W R/W A scratch-pad register which holds data temporarily. Doe not effect the UART Description
Divisor Latch Register, Low Byte (DLL) addr: $0000
Bit 7 6:1 0 LSB Field MSB
8 bits
Default 0 0 0 AVR R/W R/W R/W Baud rate generator division ratio low byte Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
89
ATMEL CONFIDENTIAL
Divisor Latch Register, High Byte (DLH) addr: $0001
Bit 7 6:1 0 LSB Field MSB 0 0 0
8 bits
Default AVR R/W R/W R/W Description Baud rate generator division ratio high byte The main UART clock, from the system clock generator, is divided by the 16-bit number contained in DLL and DLH, to provide the UART clock (which is 16 times the actual serial data rate)
Extra Register 1 (XR1) addr: $1000
Bit Field OPL:Output pins in Loopback
8 bits
Default AVR Description If this bit is set in loopback mode (MCR[4] is set), then the SOUT, nOUT2, nOUT1, nRTS, and nDTR pins are not forced to logic 1. Instead, these pins operate normally (echo). If the loopback mode is disabled, then this bit has no effect Effective in multidrop mode only (see XR2[0]). If set, the next word will be transmitted with the parity bit (in multidrop mode, this is called address bit) forced at logic 1 This bit controls the start operation of the time-out counter. If set in logic 0, then it operates in 16550 compatible mode. If set in logic 1, the time-out counter starts whenever RTO is not 0 (see and RTO) Writing a logic 1 resets the time-out counter. This bit resets to logic 0 automatically Writing a logic 1 resets the transmit path (and Tx FIFO). This bit resets to logic 0 automatically Writing a logic 1 resets the receive path (and Rx FIFO). This bit resets to logic 0 automatically If this bit is set, it disables the transmit path If this bit is set, it disables the receive path
7
0
R/W
6
SA:Send Address STOC: Start Timeout Control RTO: Restart Time-out TxR: Tx Reset RxR: Rx Reset TxDis: Tx Disable RxDis: Rx Disable
0
R/W
5
0
R/W
4
0
R/W
3 2 1 0
0 0 0 0
R/W R/W R/W R/W
Note:
When XR1 and XR2 registers are both $00, then the UART operates in 16550 compatible mode.
90
AT76C713
5665B-USB-04/05
AT76C713
Extra Register 2 (XR2) addr: $1001
Bit 7 Field TxFD:Tx FIFO Disable
8 bits
Default 0 AVR R/W Description If this bit is set, it disables the Tx FIFO. So, if FCR[0] and XR2[7] are both set, then only the Rx FIFO is enabled This bit is equivalent to LSR[6]. It can be used to check if the transmitter is empty without resetting the error bits in LSR This bit is equivalent to LSR[5]. It can be used to check if the THR is ready to load data without resetting the line status bits in LSR Functional only if Tx FIFO is enabled. If set in logic 0, then the LSR[5] (and XR2[5]) bit indicates that Tx FIFO is empty (THRR bit is 1) or that it has at least one word waiting for transmission (THRR bit is 0). Setting this bit to logic 1, then LSR[5] (and XR2[5]) bit indicates that Tx FIFO is not full (THRR bit is 1) or that it is full (THRR bit is 0) -- If set, this bit enables the multidrop mode. In this case, the Parity Error Bit in LSR is set when data is detected with the parity bit at logic 1 to identify an address word. If the received parity bit is detected low, then the Parity Error bit is not set. The transmitter sends an address word (with the parity bit set) when the Send Address bit (XR1[6]) is set. Setting the XR1[6] the next word written to THR will be transmitted as an address and any transmitted word after this will have the parity bit cleared
6
TE:Transmitter Empty
THRR: THR Ready
0
R/W
5
0
R/W
4
THRRC:THR Ready Bit Control
0
R/W
3:1
--
0
R/W
0
MDM: Multidrop Mode
0
R/W
Note:
When XR1 and XR2 registers are both $00, then the UART operates in 16550 compatible mode.
Modem Direction Register (MDR) addr: $1010
Bit 7 6 5 4 Field nCDD:nCD pin Direction nRID:nRI pin Direction nDSRD:nDSR pin Direction nCTSD:nCTS pin Direction nOUT2D:nOU T2 pin Direction
8 bits
Default 1 1 1 1 AVR R/W R/W R/W R/W Description If this bit is set, the nCD pin is configured as input If this bit is set, the nRI pin is configured as input If this bit is set, the t nDSR pin is configured as input If this bit is set, the nCTS pin is configured as input
3
0
R/W
If this bit is set, the nOUT2 pin is configured as input
ATMEL CONFIDENTIAL
5665B-USB-04/05
91
ATMEL CONFIDENTIAL
Bit 2 Field nOUT1D:nOU T1 pin Direction nRTSD:nRTS pin Direction nDTRD:nDTR pin Direction Default 0 AVR R/W Description If this bit is set. the nOUT1 pin is configured as input
1 0
0 0
R/W R/W
If this bit is set, the nRTS pin is configured as input If this bit is set, the nDTR pin is configured as input
Receiver Time-out Register (RTO) addr: $1011
Bit 7 6 5 4 3 2 1 Field MSB Default 0 0 1 0 0 0 0
8 bits
AVR R/W R/W R/W R/W R/W R/W R/W Description This register contains the maximum bit periods, for which the UART will wait the next word to arrive. Whenever the time-out counter expires, then a Time-out Indication Interrupt will be issued The XR1[5] Start Time-out Control bit selects the Start Timeout and RTO load mechanism. If the XR1[5] bit is reset to 0 (16550 compatible mode), then the RTO loads the value 4 times the word length + 12 on each LCR write operation. After reset, the word length is 5 bits and the RTO is $20. The timeout counter will then start counting down only in FIFO mode (FCR[0] is set) and if the Rx FIFO holds at least 1 word. If XR1[5] is set to 1, then the time-out function is available and in FIFO disabled mode. The RTO value does not change with LCR write operations. The time-out counter will start counting down whenever the RTO is not $00 and the RHR is loaded. In all cases core has immediate access at the contents of the RTO. The Time-out counter resets when a new word is completely received and transferred at the Receive Holding register or when the XR1[4] bit is forced to logic 1. If XR1[5] is reset to 0, time-out counter resets and on a RHR read access from core
0
LSB
0
R/W
Transmitter Time Guard Register (TTG) addr: $1100
Bit 7 6:1 0 LSB Field MSB Default 0 0 0
8 bits
AVR R/W R/W R/W Description The value of this register indicates the delay (in bit periods) that an active transmitter has to interpose between two consecutive word transmissions
92
AT76C713
5665B-USB-04/05
AT76C713
Table 8-4. Baud Rate Generation Example (UART Clock = 14,769 MHz)
User Devisor (16*clk) Decimal 100 200 400 600 1200 2400 4800 9600 14400 19200 28800 38400 57600 76800 115200 153600 230400 307200 460800 921600 9216 4608 2304 1536 768 384 192 96 64 48 32 24 16 12 8 6 4 3 2 1 Hex 2400 1200 900 600 300 180 C0 60 40 30 20 18 10 0C 08 06 4 03 02 01 UBM Value Hex 24 12 09 06 03 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 UBL Value Hex 00 00 00 00 00 80 C0 60 40 30 20 18 10 0C 08 06 04 03 02 01
Output Baud Rate
8.3
Memory Access Interface Register Set
Memory Bank Map Register (MEMMAP) addr: $F800
Bit 7 6:1 0 LSB Field MSB Default 0 0 1
8 bits
AVR R/W R/W R/W Utilizing the MEMMAP register, it is possible to resize the two memory spaces Description
ATMEL CONFIDENTIAL
5665B-USB-04/05
93
ATMEL CONFIDENTIAL
DMA External Memory Interface Control Register A (DMA_EMICRA) addr: $F801
Bit 7 6 5 4 3 2 1 0 Field RW1 RW0 RM1 RM0 WW1 WW0 WM1 WM0 Default 0 0 0 0 0 0 0 0
8 bits
AVR R/W R/W R/W R/W R/W R/W R/W R/W Description Read Wait States: These bits control the wait states inserted in the corresponding (read, write, and ALE) signals Read Mode Select: These bits control the mode (waveform) of the corresponding (read, write, and ALE) signals Write Wait States:These bits control the wait states inserted in the corresponding (read, write, and ALE) signals Write Mode Select: These bits control the mode (waveform) of the corresponding (read, write, and ALE) signals
DMA External Memory Interface Control Register B (DMA_EMICRB) addr: $F802
Bit 7 6 5 4 3 2 1 Field AW1 AW0 AM1 AM0 -- -- EMD0 Default 0 0 0 0 0 0 0
8 bits
AVR R/W R/W R/W R/W R/W These bits are reserved and must be remain always in 0 value R/W R/W External Memory Device Select: These bits select the external memory interface mode according to the following table: EMD1 0 EMD0 0 1 0 1 External Memory Interface Mode FIFO Reserved Demultiplexed Multiplexed Description ALE Wait States: These bits control the wait states inserted in the corresponding (read, write, and ALE) signals ALE Mode Select: These bits control the mode (waveform) of the corresponding (read, write, and ALE) signals
0
EMD1
0
R/W
0 1 1
94
AT76C713
5665B-USB-04/05
AT76C713
9. Errata
1. Stack Pointer is 11-bits wide The Stack Pointer is 11-bits wide. Problem Fix/Workaround Keep the stack below the address $07FF. 2. DDRB initial value The boostrap ROM code, after accessing the external SPI memory and remmaping to the final code, leaves the DDRB register to $10 value (instead of $00). The result is to have the "PB4/nSS" pin as output and set to 0 value ( because PORTB = $00). Problem fix/workaround Set the correct value of the DDRB register according to the given system configuration. 3.USB "setup" packet In some cases the USB controller might not respond to a "setup" packet if the previous USB packet was a "status-in" and the firmware performed an action while servicing the packet. Problem fix/workaround The firmware must wait for the next "SOF" packet before servicing the "status-in" packet. The "Set Address" is the only USB standard request that needs this special treatment. 4. IIR and MSR UART registers The IIR Register indicates when any bit in MSR[7..4] is changed from 0 to 1 but it does not indicate a transition from 1 to 0. Problem fix/workaround The firmware needs to poll the MSR register in order to detect if any bit in MSR[7..4] changes its value from 1 to 0. 5.Unserved UART Tx Interrupt Request The problem arises when both Receive (Rx) and Transmit (Tx) IRQs are enabled and both Rx and Tx IRQs are pending. In that case the firmware detects the Rx IRQ when it reads the IIR. This IIR read though, may erroneously clear the Tx IRQ. Thus, the firmware loses the Tx IRQ, which is never served. Problem Fix / Workaround The UART Interrupt Service Routine (ISR) must examine and serve a potential Tx IRQ, independently from the IIR value. For example, the ISR can use either the LSR[5] or the XR2[5] bits to check for pending Tx IRQs.
ATMEL CONFIDENTIAL
5665B-USB-04/05
95
ATMEL CONFIDENTIAL
10. Electrical Specifications
10.1 Absolute Maximum Ratings
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature ......................................-40C to 85C Storage Temperature ........................................-65C to 150C Voltage on Any Pin with Respect to Ground ..... 0V to Maximum Operating Voltage Maximum Operating Voltage ............................................ 3.6V
10.2
10.2.1
D.C. Characteristics
Power Supply
Parameter Core Supply Voltage Periphery Supply Voltage USB Supply Voltage Analog Power Supply Low Level Input Voltage High Level Input Voltage Low Level Output Voltage IOL = 0mA IOL = 2mA High Level Output Voltage IOH = 0mA IOH = 2mA PVDD - 0.2 PVDD - 0.4 Condition Min 1.65 CVDD 3.0 1.65 -0.3 2.0 Type 1.8 3.3 3.3 1.8 Max 1.95 CVDD + 1.5, 3.6 max 3.6 1.95 +0.8 PVDD + 0.3 0.2 0.4 Unit V V V V V V V V V V
Symbol CVDD PVDD PVDD_USB PAVDD VIL VIH VOL
VOH
10.2.2
Pull-up Circuit (where pin = 0V)
Condition Min 129A (PVDD = 3.0V) 30A (PVDD = 1.65V) Max 322A (PVDD = 3.6V) 92A (PVDD = 1.95V)
Current Current
PVDD = 3.3V PVDD = 1.8V
10.2.3
Pull-down Circuit (where pin = PVDD)
Condition Current Current PVDD = 3.3V PVDD = 1.8V Min 110A (PVDD = 3.0V) 27A (PVDD = 1.65V) Max 356A (PVDD = 3.6V) 106A (PVDD = 1.95V)
96
AT76C713
5665B-USB-04/05
AT76C713
10.2.4 USB Signals: DP, DM
Code VT+ VTVhys Parameter High Level Input Voltage Low Level Input Voltage Hysteresis pu33b11f 1.8 0.8 0.2 Unit V V V
10.2.5
Oscillator Signals: OSC
Parameter Supply Voltage Condition See Standard Operating Conditions Below rms value, 10 KHz to 10 MHz @16 MHz 8 40 With Crystal Defined Below 0.9 12 Min 1.65 Typ 1.8 Max 1.95 Unit V
Symbol PAVDD
Vdd
idd on Freq Duty Ton Pon ESR Cm Cshunt Cload Idd stdby
Supply Ripple Current Consumption Operating Frequency Duty Cycle Startup Time Drive Level Equivalent Serie Resistance Motional Capacitance Shunt Capacitance Load Capacitance Standby Current Consumption
30 1.6 16 60 2 150
mV MA MHz % ms W fF pF pF A
@16 MHz 5
80 9 7
Max. External Capacitors:40pF onosc = 0
15
20 1
10.3
Ordering Information
Device AT76C713
Ordering Code AT76C713
Package 100 lead TQFP
ATMEL CONFIDENTIAL
5665B-USB-04/05
97
ATMEL CONFIDENTIAL
11. Packaging Information
D1
D
XX
e
E1
CO
E
U NT
RY
b
Bottom View Top View
COMMON DIMENSIONS (Unit of Measure = mm)
A2
SYMBOL A1 A2
MIN 0.05 0.95
NOM
MAX 0.15
NOTE 6
1.00 16.00 BSC 14.00 BSC 16.00 BSC 14.00 BSC 0.50 BSC
1.05
A1 L1
D D1 E E1 e b L1 0.17
2, 3
Side View
2, 3
0.22 1.00 REF
0.27
4, 5
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. The top package body size may be smaller than the bottom package size by as much as 0.15 mm. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 are maximum plastic body size dimensions, including mold mismatch. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08 mm. Dambar cannot be located on the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm for 0.4 and 0.5 mm pitch packages. 5. These dimensions apply to the flat section of the lead between 0.10 mm and 0.25 mm from the lead tip. 6. A1 is defined as the distance from the seating place to the lowest point on the package body. 11/30/01
R
2325 Orchard Parkway San Jose, CA 95131
TITLE 100T1, 100-lead (14 x 14 x 1.0 mm Body), Thin Plastic Quad Flat Pack (TQFP)
DRAWING NO. 100T1
REV. A
98
AT76C713
5665B-USB-04/05
AT76C713
Table of Contents
Features............................................................................................................. 1 1 2 3 Overview ................................................................................................... 2 AT76C713 Functional Diagram ............................................................... 3 Pin Diagram .............................................................................................. 4
3.1100-pin TQFP Package .............................................................................................4
4 5 6
Pin Summary - Pin Assignment ............................................................. 5 Signal Description ................................................................................... 6 Functional Description ............................................................................ 9
6.1Bootstrap ROM and Programming Modes ................................................................9 6.2AVR Core ................................................................................................................12 6.3Oscillator and Clock Generator ...............................................................................13 6.4Memory Map ...........................................................................................................14 6.5Memory Access Interface ........................................................................................15 6.6USB DMA Controller ...............................................................................................19 6.7USB Controller ........................................................................................................20 6.8UART0, UART1 .......................................................................................................28 6.9IrDA 1.0 Codec ........................................................................................................30 6.10Watchdog Timer ....................................................................................................31 6.11Serial Peripheral Interface (SPI) ............................................................................31 6.12JTAG Interface and On-chip Debug System .........................................................34 6.13IEEE 1149.1 (JTAG) Boundary-scan ....................................................................38
7
I/O Space (Register Description) .......................................................... 45
7.1Timers/Counters ......................................................................................................54 7.2Timer/Counter 0 and Timer/Counter 2 .....................................................................55 7.3Timer/Counter 1 ......................................................................................................59 7.4Watchdog Timer ......................................................................................................62 7.5SPI Interface ............................................................................................................63 7.6I/O PORTs ...............................................................................................................64
8
Memory Space (Register Description) ................................................. 70
8.1USB Register Set ....................................................................................................70 8.2UART Register Set ..................................................................................................82 8.3Memory Access Interface Register Set ...................................................................93 i
5665B-USB-04/05
9
Errata ....................................................................................................... 95
10 Electrical Specifications ........................................................................ 96
10.1Absolute Maximum Ratings ...................................................................................96 10.2D.C. Characteristics ..............................................................................................96 10.3Ordering Information .............................................................................................97
11 Packaging Information .......................................................................... 98
ii
AT76C713
5665B-USB-04/05
Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Atmel Operations
Memory
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314
RF/Automotive
Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759
Regional Headquarters
Europe
Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500
Microcontrollers
2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60
Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom
Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80
Asia
Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369
ASIC/ASSP/Smart Cards
Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743
Japan
9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581
Literature Requests
www.atmel.com/literature
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL'S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL'S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel's products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
(c) Atmel Corporation 2005. All rights reserved. Atmel (R), logo and combinations thereof, AVR (R) and DataFlash are registered trademarks, and Everywhere You Are SM are the trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
Printed on recycled paper.
5665B-USB-04/05

▲Up To Search▲

Price & Availability of AT76C713

	To Download AT76C713 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .