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CDB4396/7
Evaluation Board for CS4396 and CS4397
Features Description
The CDB4396/7 evaluation board is an excellent means for quickly evaluating the CS4396 or CS4397 24bit192 kHz D/A converters. The board accepts SPDIF and SACD inputs and, with an analog output interface, presents line level signals via RCA connectors. Evaluation requires an analog signal analyzer and a digital signal source.
lDemonstrates recommended layout and
grounding arrangements lCS8414 receives AES/EBU, S/PDIF, & EIAJ340 Compatible Digital Audio lSupports 32kHz - 192kHz PCM Audio and SACD Audio lRequires only a digital signal source for a The CS8414 digital audio receiver I.C. provides the syscomplete Digital-to-Analog Converter system tem timing and data signals necessary to operate the Digital-to-Analog converter and will accept AES/EBU, lIncluded Wall Mount power supply
SPDIF and EIAJ compatible audio data. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development in PCM and DSD modes. ORDERING INFORMATION CDB4396C.0 CDB4397C.0
I
Evaluation Board Evaluation Board
BLOCK DIAGRAM
POWER SUPPLY REGULATION CS8414
ANALOG FILTER INPUT SELECTOR
CS4396/7
ANALOG FILTER
EXT. PCM/DSD
MODE SELECTOR
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 2000 (All Rights Reserved)
DEC `00 DS288DB1B1 1
CDB4396/7
TABLE OF CONTENTS
1. CDB4396C.0 SYSTEM OVERVIEW ......................................................................................... 3 2. CS4396 AND CS4397 DIGITAL TO ANALOG CONVERTER ................................................. 3 3. CS8414 DIGITAL AUDIO RECEIVER ...................................................................................... 3 4. EXTERNAL DIGITAL AUDIO DATA AND DSD INPUT PORT .............................................. 3 5. MODE CONTROL ..................................................................................................................... 3 6. AUTOMATIC MODE SWITCHING ........................................................................................... 3 7. OUTPUT FILTER ...................................................................................................................... 4 8. POWER SUPPLIES ................................................................................................................. 4 9. GROUNDING AND POWER SUPPLY DECOUPLING ............................................................ 4 10. CS4396/CS4397 MODE SETTINGS (SW2) ........................................................................... 5
LIST OF FIGURES
Figure 1. System Schematic ........................................................................................................... 7 Figure 2. Output Stage Schematic .................................................................................................. 8 Figure 3. Power Supply ................................................................................................................... 9 Figure 4. Component Placement................................................................................................... 10 Figure 5. Top - Layer 1 .................................................................................................................. 11 Figure 6. Layer 2 ........................................................................................................................... 12 Figure 7. Layer 3 ........................................................................................................................... 13 Figure 8. Layer 4 ........................................................................................................................... 14 Figure 9. Layer 4 ........................................................................................................................... 14
LIST OF TABLES
Table 1. Single Speed (16 to 50 kHz) Digital Interface Format Options.......................................... 5 Table 2. Single Speed (16 to 50 kHz) De-Emphasis Options ......................................................... 5 Table 3. Double Speed (50 to 100 kHz) Sample Rate Mode Options ............................................. 5 Table 4. Quad Speed(100 to 200 kHz) Sample Rate Mode Options .............................................. 5 Table 5. 8x Interpolated Input Mode Options (CS4397 only) .......................................................... 5 Table 6. Direct Stream Digital Options (CS4397 only) ................................................................... 5 Table 7. SWITCH S2 MODE SETTINGS TABLE............................................................................ 6 Table 8. AUTOMATIC MODE OPERATION SETTINGS ................................................................ 6
Contacting Cirrus Logic Support
For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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DS288DB1B1
CDB4396/7
1. CDB4396C.0 SYSTEM OVERVIEW
PMD100 or PMD200. Notice that the board has provisions for terminating this input port for proper signal integrity using resistors R20 through R24. The board also features automatic mode switching between this port and the SPDIF port when used with a SACD player. See Section 6- "Automatic Mode Switching" for a complete description of this feature.
The CDB4396C.0 evaluation board is an excellent means of quickly evaluating the CS4396 or CS4397 24 bit - 192 kHz audio D/A converters. The evaluation board features a CS8414 digital audio input interface receiver, an analog output buffer/filter, and on board power supply regulation to be used with a supplied AC Wall Mount power supply. The CS8414 provides an easy interface to 32 kHz to 96 kHz digital audio signal sources. The evaluation board also allows the user to supply external PCM data and DSD data through a 10-pin header for system development.
5. MODE CONTROL
The board utilizes a Dip Switch, "S2" to allow the user to select various operational modes of the CS4396 or CS4397. These modes include selection of the Digital Interface Format, De-emphasis, Sample Rate modes, Internal-External Digital Audio Data, PCM-DSD Automatic Mode Switching, 64x - 128x DSD Data, +3 V/+5 V Digital Supply voltage selection, and Mute control. See Tables 1 through 8 for a complete description of how the switch settings set the different operating modes of the CS4396/7. To manually set the CS4396/7 modes, set S2 position 7 to open and use S2 positions 1 through 5 to set the various modes. To set the board into "Automatic Mode Switching" set the S2 position 7 to the closed position. See Table 8 for PCM-DSD settings that are set in Automatic Mode by circuitry U2, U3, U4, U7. When using the CS4397 with a DSD source, two input clock frequencies are possible, either 64 or 128x and are selectable by S2 position 8 The DSD clock mode, 256fs or 384fs is selectable by resistor stuffing option R19. The external mute circuitry is enabled by setting S2 position 10 to closed.
2. CS4396 AND CS4397 DIGITAL TO ANALOG CONVERTER
Please refer to either the CS4396 or CS4397 product datasheet for a complete detailed description of these components.
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 1. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 datasheet.
4. EXTERNAL DIGITAL AUDIO DATA AND DSD INPUT PORT
The evaluation board has been designed to allow interfacing to external systems via the 10-pin header, JP1. This header allows the evaluation board to accept externally generated clocks and data. The port is activated by setting the "MODE" Control Switch " S2" position 6 "INT/EXT" switch to the closed position. This port accepts PCM data, DSD data or data from an external 8X interpolator such as an HDCD
DS288DB1B1
6. AUTOMATIC MODE SWITCHING
The board features an automatic PCM or DSD input data switching mode for use with an external SACD player. When used with an external SACD player that has both a SPDIF output connected to J1 (U5) and DSD data output connected to the JP1 port, will allow the board to switch automatically between the two.
3
CDB4396/7
Theory of operation - When an SACD player switches from playing a CD to a DSD disc, the SPDIF output data is disabled, the internal circuitry (U6, U2, U3, U4, U7) detects loss of an SPDIF source and automatically switches the Digital Data Input path (U8) to the DSD input port JP1. This feature can also be controlled from an external control signal by removing R60 and inputting a control signal into JP2. Logic low = PCM mode, Logic high = DSD mode. (For use only with the CS4397) ation board can also be powered by an external lab power supply by connecting +12 vdc to connector J8, and -12 vdc to connector J10. J9 is the Ground connection. Up to 13 volts is allowed before reverse voltage protection diodes D3 and D4 will clamp the input voltage. The CDB4396C.0 uses separate voltage regulation for the digital control circuitry and for the digital power section and analog section for the CS4396 CS4397. The digital power for the CS4396 CS4397 is user selectable by switch S2 position 9. The (default) open position sets the voltage regulator VREG2 to +5.0 volts, the closed position sets the voltage regulator to +3.3 volts.
7. OUTPUT FILTER
The CDB4396C.0 output filter is a single op-amp circuit that combines a balanced to single-ended converter and 2-pole output filter. This topology was chosen to demonstrate a low-cost design implementation, however, the trade-off is a slightly compromised noise performance. Other output circuit topologies are available that optimize noise and distortion but at a higher cost. The circuit was designed such that the user can select between DC coupled or AC coupled modes. To select AC coupling, remove Jumpers J2, J4, J5 and J7. The board also allows the user to test other opamps by replacing the socketed op-amps with ones of their choice. Also surface mount op-amps can be tested by removing the socketed op-amps and soldering down the surface mount versions to SKT1X, SKT3X or SKT2X. This may involve the need to remove socket pins 2,3,4 on SKT1 and SKT3 and pins 1,2,3 on SKT2 to get the IC body to mount flush.
9. GROUNDING AND POWER SUPPLY DECOUPLING
For the user to be able to realize the high performance capabilities of the CS4396/7, it is recommended to pay careful attention to PC board layout, grounding, and placement of the power supply and decoupling capacitors. It is recommended when doing the PC board layout to use one ground plane underneath the part and for this ground plane to be the analog ground plane. The digital ground pin connection (pin 9) should tie to the analog ground plane and to the digital ground plane. This should be the "star" ground connection of the analog and digital ground planes. Please review the attached PC board photo plots for an example of the suggested grounding method. It is also recommended to pay careful attention to the placement of the decoupling capacitors tied to VREF (pin 28). This pin requires a very low impedance path to ground at high frequencies as this pin draws high frequency current pulses at 6 MHz. It is important to place the .01 uF capacitor and 100 uF capacitor right next to the pin. Keep the connecting trace as short as possible. A low ESR electrolytic or tantalum for the 100 uF is recommended.
8. POWER SUPPLIES
The CDB4396C.0 comes supplied with an external 14 VAC Wall Mount power supply for convenience in setup, and to make measurements easier by eliminating ground loop problems between lab power supplies and measurement equipment. The external 14 VAC voltage supplied at J11 is rectified, filtered and regulated to produce 12 volts by regulators U13 and U14. The CDB4396A.0 evalu-
4
DS288DB1B1
CDB4396/7
10. CS4396/CS4397 MODE SETTINGS (SW2)
M4 0 0 0 0 M1 (DIF1) 0 0 1 1 M0 (DIF0) 0 1 0 1 DESCRIPTION Left Justified, up to 24-bit data I2S, up to 24-bit data Right Justified, 16-bit Data Right Justified, 24-bit Data
Table 1. Single Speed (16 to 50 kHz) Digital Interface Format Options
M3 (DEM1) 0 0 1 1
M2 (DEM0) 0 1 0 1
DESCRIPTION 32 kHz De-Emphasis 44.1 kHz De-Emphasis 48 kHz De-Emphasis De-Emphasis Disabled Table 2. Single Speed (16 to 50 kHz) De-Emphasis Options
M4 1 1 1 1
M3 1 1 1 1
M2 1 1 1 1
M1 0 0 1 1
M0 0 1 0 1
DESCRIPTION Left Justified up to 24-bit data, Format 0 I2S up to 24-bit data, Format 1 Right Justified 16-bit data, Format 2 Right Justified 24-bit data, Format 3
Table 3. Double Speed (50 to 100 kHz) Sample Rate Mode Options
M4 1 1 1 1
M3 1 1 1 1
M2 0 0 0 0
M1 0 0 1 1
M0 0 1 0 1
DESCRIPTION Left Justified up to 24-bit data, Format 0 I2S up to 24-bit data, Format 1 Right Justified 16-bit data, Format 2 Right Justified 24-bit data, Format 3
Table 4. Quad Speed(100 to 200 kHz) Sample Rate Mode Options
M4 1 1
M3 0 0
M2 0 0
M1 0 (DIR) 0 (DIR)
M0 0 1
DESCRIPTION Right Justified 20-bit data Right Justified 24-bit data
Table 5. 8x Interpolated Input Mode Options (CS4397 only)
M4 1 1
M3 0 0
M2 1 1
M1 0 (DSD_R) 0 (DSD_R)
M0 0 1
DESCRIPTION 64x Oversampled DSD 128x Oversampled DSD
Table 6. Direct Stream Digital Options (CS4397 only)
DS288DB1B1
5
CDB4396/7
SWITCH S2
POSITION 1 MO - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK POSITION 2 M1 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK POSITION 3 M2 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK POSITION 4 M3 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK POSITION 5 M4 - OPEN = 1 NOTE: SWITCH MUST BE OPEN FOR AUTO MODE TO WORK POSITION 6 INT/EXT - SETS THE INPUT MUX TO THE CS8414 OR TO JP1 - OPEN=CS8414 POSITION 7 PCM/DSD-SETS THE BOARD TO AUTO MODE-SWITCHES BETWEEN PCM AND DSD-OPEN=DISABLED POSITION 8 64/128X - SETS THE CLOCK MODE FOR DSD - OPEN =128X POSITION 9 +3V/+5V - SETS THE DIGITAL POWER SUPPLY TO +3 OR +5 VOLTS - OPEN = +5V POSITION 10 MUTE - ENABLES THE EXTERNAL MUTE CIRCUITRY - OPEN = DISABLED DEFAULT ALL SWITCHES IN OPEN POSITION
Table 7. SWITCH S2 MODE SETTINGS TABLE
- MODE TABLE AUTO SWITCHING PCM M1 = 0 DSD M1=DSD_R M0 = 1 M0 = 1 M2 = 1 M2 = 0 M3 = 1 M3 = 0 M4 = 0 M4 = 1 LRCLK = 0 = 256FS LRCLK = 1 = 384FS
Table 8. AUTOMATIC MODE OPERATION SETTINGS
6
DS288DB1B1
+5V
5 3 5 3 5 3 5
.
.
.
.
.
.
.
(L=PCM) 2 R60 0 RES_0805 5%
-
+
.
.
.
1
1
1
VCC
3 C2
.1UF 0805 +5V 1 2 3 4 5 6 7 8 9 10 11 12 13 14
U6 28 C ERR 27 CD/F1 CE/F2 26 CC/F0 SDATA 25 CB/E2 ERF 24 CA/E1 M1 23 /C0/E0 M0 22 VDD VA+ 21 DGND AGND 20 RXP FILT 19 RXN MCK 18 FSYNC M2 17 SCK M3 16 CS12/FCK SEL 15 U CBL
GREEN LED SPDIF ENABLED
PCM/DSD +5V
(L=ENABLE)
PCM/DSD
PCM/DSD
PCM/DSD +5VA
SPDIF IN
OUT
1 .01UF 0805 C3 .1UF 0805
L2 47UH VD+3/+5 VD+3/+5 C5 .1UF 0805 C6 10UF CSP_3528 R6 10K RES_0603 5% R9 10K RES_0603 5% R11 10K RES_0603 5% R12 10K RES_0603 5% R13 10K RES_0603 5% R15 10K RES_0603 5% R18 10K RES_0603 5% S1 PTS645TL50 DAC RESET R7 10K RES_0603 5% C7 .1UF 0805 U1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 R10 100 RES_0603 5% 3 1
5
1
U5 TORX173
C1
RESET PIN?
D1
U7 NC7SZ125
.
1K INT/EXT 4 R2 RES_0805 5%
2
-
+
1K M1 4 R3 RES_0805 5% U2 NC7SZ125
2
-
+
1K M4 4 R4 RES_0805 5% U3 NC7SZ125
.
47UH
R1 560 RES_0805 5%
VCC
GND
VCC
GND
VCC
GND
VCC
GND
3
L1
1 2
CASE2 CASE1 GND2 GND1
6 5 4 2
.
1
5
3
(L=PCM) U10 NC7SZ374 1 2 3 CP /OE GND VCC D Q C22 6 5 4 VD+3/+5 C21 .1UF 0805 INT/EXT R17 10K RES_0603 5% 2
5% 5% /MUTE C20 .1UF 0805 5% 1
.
.
VCC
GND
5
-
+
4
/INT/EXT
Q1 MMBT2907A L
3
2
3
5
.
.
DS288DB1B1
+5V J1 C8 2 .01UF R16 0805 75 RES_0805 5% CS8414-CS
HDR1 SPDIF/DSD VD+3/+5 VD+3/+5 VD+3/+5 VD+3/+5
/INT/EXT 2
-
+
1K M3 4 R5 RES_0805 5% U4 NC7SZ125
R70 1.0K RES_0603 1%
SEE NOTE #1
SPDIF IN
.
VD+3/+5
R8 470 C4 .068UF RES_0805 0805 5% S2 1 2 3 4 VD+3/+5 5 6 7 8 9 /MUTE 10
4 2 +5VA
R71 1.0K RES_0603 1%
20 19 18 17 16 15 14 13 12 11
(DEFAULT = OPEN) M0 M1 M2 M3 M4 INT/EXT PCM/DSD 64/128X +3V/+5V +3V/+5V /MUTE_CNTRL
(DSD CLK MODE) LOW = 256fs HIGH = 384fs JP1 2 4 6 Input8 10 1 3 5 7 9 SDATA LRCLK SCK MCLK DSD_R
R19 N.S. RES_0805 5%
Input Mux/Level Shifter 3 4 7 8 11 14 17 18 21 22 1 12 R23 N.S. 5% R24 N.S. 5% A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 B0-4 GND 2 B0 5 B1 6 B2 9 B3 10 B4 15 B5 16 B6 19 B7 20 B8 23 B9 13 B5-9 24 VCC VD+3/+5 R25 1K 5% R26 1K 5% R27 1K 5% R28 1K 5% C18 10UF C19 .01UF MCLK SCK LRCLK SDATA M1
ON
C9 .01UF CSN_0603 VREF FILT + FILT CM OUT AOUT L AOUT L+ VA AGND1 AOUT R+ AOUT R AGND2 /MUTE C C/H /MUTE
C10 100UFSMT 25V
External Digital Audio IIs/DSD
/RST M4 (AD0/CS) M3 (AD1/CDIN) M2 (SCL/CCLK) M0 (SDA/CDOUT) DGND1 VDD1 VDD2 DGND2 MCLK SCLK LR(CLK MODE) SDATA (DSD_L) M1 (DSD_R)
C11 .01UF CSN_0603
C12 100UFSMT 25V
CM AOUT_LEFTAOUT_LEFT+ C13 .01UF C14 10UF CSP_3528
AOUT_RIGHT+ AOUT_RIGHT/MUTE_CNTRL +5VA
VD+3/+5 CS4397KS L3 47UH S3 PTS645TL50 DAC MUTE VD+3/+5 +5VA C15 C16 .01UF 10UF CSP_3528
HDR5X2 R20 N.S. 5% R21 N.S. 5% R22 N.S. 5%
U8 QS3384 (L=CONNECT) VD+3/+5
C17 .1UF 0805
R30 100 3 1 4 2
R29 10K
R31 10K
MUT E R33 10K RES_0603 5%
NC7SZ04
U9
.1UF VD+3/+5
0805 1 2 3 2
U11 IN2 GND IN1 SEL VCC OUT 6 5 4
(H=IN2) 64/128X
- MODE TABLE AUTO SW ITCHING
PCM M0 M1 M2 M3 M4 = = = = = 1 0 1 1 0 DSD
NOTE 1: USE THESE RESISTORS F USING I PCM AND DSD MODES
-12V
GND
VCC
4
+
-
VD+3/+5 NC7SZ157 C23 .1UF 0805
U12
NC7SZ04
M0 = 1 M1 = DSD_R M2 = 1 M3 = 0 M4 = 1 lrclk = 0 = 256fs lrclk = 1 = 384fs
CDB4396/7
Figure 1. System Schematic 7
`
`
1
2
100UF 25V C29 AOUT_L EFT+ 100UF 25V 1 2
RN55 1% R40 1K RN55 1%
C27 5600PF
4 1 8
C32 5600PF
R43 1K RN55 1%
C33 1500PF
2
RN55 1%
C30 .1UF 0805
MUT E OS 1
MUTE
-12 V C34 .1UF
R42 1K 0805 5%
1 Q2 2SC3 326
C31 5600PF
1
RN55 1% C28 470PF R41 499
7 5
RN55 1%
3
3
.
`
J4 JUMPER SKT2 L_O UT LL+ -12V 1 2 3 4 1 2 3 4 C35 .1UF 0805 R44 1K J5 JUMPER ` ` RN55 1% C36 1 2 R47 1K RN55 1% R50 1K RN55 1% C44 5600PF R53 1K RN55 1% C39 5600PF R48 499 RN55 1% R51 499 RN55 1% C42 .1UF C45 1500PF 0805 -12 V 1500PF C37 .1UF +12V OS 4 7 5 0805 2 3 ~ 6 MUTE 4 1 8 OS 3 R52 1K 0805 5% SKT3 LT1028 R45 N.S. OS 3 0805 1% -12 V OS 4 R46 N.S. 0805 1% R49 560 RN55 1 2 Q3 2SC3326 C43 5600PF 0805 8 7 6 5 SKT 8 7 6 5 +12V R_OUT RR+
`
C41 AOUT_RIG HT+ 100UF 25V 1 2
3
`
J7 JUMPER
`
NOTE: THE CIRCUIT IS SHOWN DC COUPLED. TO MAKE AC COUPLED -REMOVE JUMPERS J2, J4, J5, J7 DC OFFSET CAN BE ADJUSTED FOR BY ADDING RESISTORS R35, R36 AND R45, R46
1
.
8
R34 1K OS 1 J2 JUMPER RN55 1% C24 1500PF C25 .1UF 0805 2 OS 2 +12V OS 2 SKT1 LT1028 6 R39 560 2 R36 N.S. 0805 1% J3 . OS 1 LL+ -12 V SKT1X 1 1 2 2 3 3 4 4 8 7 +12V L_OU T 6 5 OS 2 R35 N.S. 0805 1% -12 V
NOTE: THE FILTER OP-AMPS ARE DUAL FOOTPRINT - DIP8 AND SO-8 SINGLE AND DUAL OP-AMPS ARE SUPPORTED
C26 AOUT_LE FT-
R37 1K
R38 499
~
8 7 6 5
DUAL_FTPRN T
SKT2X L_OU T1 L2 L+ 3 -12 4 V 1 2 3 4 8 7 6 5 +12V 8 7 R_OUT R6 R+ 5
DUAL_FTPRN T
SKT3X OS 3 RR+ -12 V 1 2 3 4 1 2 3 4 8 7 6 5 8 +12V 7 6 R_OUT OS 4 5
DUAL_FTPRN T
C38 AOUT_RIGHT 100UF 25V
C40 470PF
J6 1% 2 .
CDB4396/7
DS288DB1B1
Figure 2. Output Stage Schematic
ADJ
OUT TAB IN
ADJ
OUT TAB IN
1
2 4 3
1
1
1
1
VD+3/+ 5 -12 V R55 TB D 5% R56 330 1% C46 47UF 25V R57 110 1% C49 10UF CSP_ 3528 C50 10UF CSP_ 3528 R59 330 C51 RES_ 0805 47UF 1% 25V R54 110 1%
2 4 3
ADJ
OUT TAB IN
VOUT
2
ADJ
D5 1N4003T J11 3 2 1 POWERJAC K
C54 4700UF 25V
VIN
1
1
2
3
2 4 3
21
1
1
2
3
VOUT
ADJ
VIN
DS288DB1B1
+12V C52 100UF 25V
J8 +12VDC
J9 GND
J10 -12VDC
VREG 2 LT1117 SO T223
VREG 1 LT1117 SO T223
+12V
+12V
+5VA C47 10UF CSP_3 528 R58 560 RES_0 805 5% D2 GREEN LED POWE R C48 10UF CSP_ 3528
D3 2 P6K E13 1 2
D4 1 P6K E13
C53 100UF 25V
+3V/+ 5V
+3V/+ 5V
U13 LM 317T VREG 3 LT1117 SO T223
+20V
CDB4396/7
+12V
+5V +20V R66 R65 330 110 C62 RES_0 80510UF 1% 1% CSP_3 528 C60 10UF CSP_3 528 C61 10UF CSP_3 528
D6 1N4003T C55 4700UF 25V R63 953 1% -20 V C56 47UF 25V R61 110 1%
+12V
C57 10UF CSP_ 3528
U14 LM 337T
-12 V -20 V
R64 953 1%
C58 47UF 25V
R62 110 1%
C59 10UF CSP_3 528
CDB4396/7
Figure 3. Power Supply 9
10
CDB4396/7
DS288DB1B1
Figure 4. Component Placement
DS288DB1B1
CDB4396/7
Figure 5. Top - Layer 1 11
CDB4396/7
12
DS288DB1B1
Figure 6. Layer 2
CDB4396/7
DS288DB1B1
Figure 7. Layer 3 13
CDB4396/7
14
DS288DB1B1
Figure 8. Layer 4
* Notes *

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