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CDB4340/41 Evaluation Board for CS4340 and CS4341
Features
l Demonstrates
Description
The CDB4340/41 evaluation board is an excellent means for quickly evaluating the CS4340/41 family of 24-bit, stereo D/A converters. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the CS4341 and a power supply. Analog outputs are provided via RCA phono jacks for both channels. The CS8414 digital audio receiver I.C. provides the system timing necessary to operate the Digital-to-Analog converters and will accept AES/EBU, S/PDIF, and EIAJ340 compatible audio data. The evaluation board may also be configured to accept external timing signals for operation in a user application during system development. ORDERING INFORMATION CDB4340, CDB4341 Evaluation Board
recommended layout and grounding arrangements l CS8414 Receives AES/EBU, S/PDIF, & EIAJ-340 Compatible Digital Audio l Digital and Analog Patch Areas l Requires only a digital signal source and power supplies for a complete Digital-toAnalog-Converter system
I/O for Clocks and Data
Control Port
Mute Circuit
CS8414 Digital Audio Interface
CS4340/41
Analog Filter
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 1999 (All Rights Reserved)
NOV `99 DS297DB3 1
CDB4340/41
TABLE OF CONTENTS
1. 2. 3. 4. 5. 6. 7. 8. 9. CDB4340/41 SYSTEM OVERVIEW ............................................................... 3 CS4340/41 DIGITAL TO ANALOG CONVERTER ......................................... 3 CS8414 DIGITAL AUDIO RECEIVER ............................................................ 3 CS8414 DATA FORMAT ................................................................................ 3 ANALOG OUTPUT FILTER ........................................................................... 4 INPUT/OUTPUT FOR CLOCKS AND DATA ................................................. 4 POWER SUPPLY CIRCUITRY ....................................................................... 4 GROUNDING AND POWER SUPPLY DECOUPLING .................................. 4 CDB4341 CONTROL PORT SOFTWARE ..................................................... 4
LIST OF FIGURES
Figure 1. System Block Diagram and Signal Flow .............................................. 8 Figure 2. CS4340/41 ........................................................................................... 9 Figure 3. Analog Output Passive Filter .............................................................. 10 Figure 4. External Mute Circuit .......................................................................... 11 Figure 5. CS8414 Digital Audio Receiver Connections ..................................... 12 Figure 6. Digital Audio Inputs ............................................................................ 13 Figure 7. MCLK Divider and Voltage Level Converter ...................................... 14 Figure 8. Control Port Interface ......................................................................... 15 Figure 9. Reset Circuitry .................................................................................... 16 Figure 10. Power Supply ................................................................................... 17 Figure 11. I/O for Clocks and Data .................................................................... 18 Figure 12. Silkscreen Top ................................................................................. 19 Figure 13. Top Side ........................................................................................... 20 Figure 14. Bottom Side ...................................................................................... 21
LIST OF TABLES
Table 1. CS8414 Supported Formats.................................................................... 3 Table 2. System Connections ............................................................................... 5 Table 3. CDB4340 Jumper Selectable Options..................................................... 5 Table 4. CDB4341 (I2C Mode) Jumper Selectable Options.................................. 6 Table 5. CDB4341 (SPI Mode) Jumper Selectable Options ................................. 7
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
I 2 C is a registered trademark of Philips Semiconductors.
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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CDB4340/41
1. CDB4340/41 SYSTEM OVERVIEW
The CDB4340/41 evaluation board is an excellent means of quickly evaluating the CS4340/41. The CS8414 digital audio interface receiver provides an easy interface to digital audio signal sources including the majority of digital audio test equipment. The evaluation board also allows the user to supply clocks and data through a 10-pin header for system development. The CDB4340/41 schematic has been partitioned into 10 schematics shown in Figures 2 through 11. Each partitioned schematic is represented in the system diagram shown in Figure 1. Notice that the the system diagram also includes the interconnections between the partitioned schematics. formation mode. The information displayed by the LED's can be decoded by consulting the CS8414 data sheet. It is likely that the de-emphasis control for the CS4340 will be erroneous and produce an incorrect audio output if the Error Information Switch is activated and the CS4340 is in the internal serial clock mode. Encoded sample frequency information can be displayed provided a proper clock is being applied to the FCK pin of the CS8414. When an LED is lit, this indicates a "1" on the corresponding pin located on the CS8414. When an LED is off, this indicates a "0" on the corresponding pin. Neither the L or R option of CSLR/FCK should be selected if the FCK pin is being driven by a clock signal. The evaluation board has been designed such that the input can be either optical or coax (see Figure 6). However, both inputs cannot be driven simultaneously.
2. CS4340/41 DIGITAL TO ANALOG CONVERTER
A description of the CS4340 is included in the CS4340 data sheet. A description of the CS4341 is included in the CS4341 data sheet.
4. CS8414 DATA FORMAT
The CS8414 data format can be set with jumpers M0, M1, M2, and M3, as described the CS8414 datasheet. The format selected must be compatible with the data format of the CS4340 or CS4341, shown in the CS4340 and CS4341 datasheets. Please note that the CS8414 does not support all the possible modes of the CS4340 or CS4341, see Table 1 for details. The default settings for M0-M3 on the evaluation board are given in Tables 3-5.
CS4341 CS4340 CS8414 External Internal Format Format Format SCLK SCLK 0 2 Yes Yes 1 0 2 Yes No 2 1 0 No Yes 3 2 Unsupported 4 Unsupported 5 3 5 Yes No 6 6 Yes Yes 7 0 2 Yes No Table 1. CS8414 Supported Formats
3. CS8414 DIGITAL AUDIO RECEIVER
The system receives and decodes the standard S/PDIF data format using a CS8414 Digital Audio Receiver, Figure 4. The outputs of the CS8414 include a serial bit clock, serial data, left-right clock (FSYNC), de-emphasis control and a 256 Fs master clock. The operation of the CS8414 and a discussion of the digital audio interface are included in the CS8414 Datasheet. During normal operation, the CS8414 operates in the Channel Status mode where the LED's display channel status information for the channel selected by the CSLR/FCK jumper. This allows the CS8414 to decode the de-emphasis bit from the digital audio interface for control of the CS4340 de-emphasis filter. When the Error Information Switch is activated, the CS8414 operates in the Error and Frequency in-
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CDB4340/41
5. ANALOG OUTPUT FILTER
The evaluation board includes a pair of single pole passive filters. The passive filters, Fig. 3, have a corner frequency of approximately 95 kHz with JP3 and JP6 installed and 190 kHz without JP3 and JP6. supply voltages, VCCA and VCCB, to the Voltage Level Converter (LVXC4245) must remain within 2.25 Volts of each other in order to maintain proper operation.
8. GROUNDING AND POWER SUPPLY DECOUPLING
The CS4340/41 requires careful attention to power supply and grounding arrangements to optimize performance. Figure 10 details the power distribution used on this board. The CDB4340/41 ground plane is split to control the digital return currents in order to minimize digital interference. The decoupling capacitors are located as close to the CS4340/41 as possible. Extensive use of ground plane fill on both the analog and digital sections of the evaluation board yields large reductions in radiated noise.
6. INPUT/OUTPUT FOR CLOCKS AND DATA
The evaluation board has been designed to allow the interface to external systems via the 10-pin header, J9. This header allows the evaluation board to accept externally generated clocks and data. The schematic for the clock/data I/O is shown in Figure 11. The 74HC243 transceiver functions as an I/O buffer where jumpers HDR1-HDR6 determine if the transceiver operates as a transmitter or receiver. A transmit function is implemented with the HDR1-HDR6 jumpers in the 8414 position. LRCK, SDATA, and SCLK from the CS8414 will be outputs on J9. The transceiver operates as a receiver with jumpers HDR1-HDR6 in the EXTERNAL position. MCLK, LRCK, SDATA and SCLK on J9 become inputs.
9. CDB4341 CONTROL PORT SOFTWARE
The CDB4341 is shipped with Windows based software for interfacing with the CS4341 control port via the DB25 connector, P1. The software can be used to communicate with the CS4341 in either SPI or I2C mode; however, in SPI mode the CS4341 registers are write-only. Run SETUP.EXE from the distribution diskette to install the software. Further documentation for the software is available on the distribution diskette. The documentation is available in the plain text format file, README.TXT.
7. POWER SUPPLY CIRCUITRY
Power is supplied to the evaluation board by three binding posts (GND, +5V, +3V/+5V) (see Figure 10). The +5V input supplies power to the +5 Volt digital circuitry (VA+5, VD+5, VDPC+5), while the +3V/+5V input supplies power to the Voltage Level Converter and the CS4340/41 for evaluation in either +3 or +5 Volt mode. Note, the
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CDB4340/41
CONNECTOR +5 V +3V/+5V GND Digital input Optical input J9 Parallel Port Control I/O AOUTA AOUTB
INPUT/OUTPUT input input input input input input/output input/output input/output output output + 5 Volt power
SIGNAL PRESENT + 3 Volt or + 5 Volt power for the CS4340/41 and the Voltage Level Converter ground connection from power supply digital audio interface input via coax digital audio interface input via optical I/O for master, serial, left/right clocks and serial data parallel connection to PC for SPI/I2C control port signals I/O for SPI/I2C control port signals channel A analog output with single-pole passive filter channel B analog output with single-pole passive filter
Table 2. System Connections
JUMPER CSLR/FCK M0 M1 M2 M3 SCLK DEM_8414 HDR1-6 HDR 7 HDR 8 MCLK HDR15 HDR16 HDR17 ENCTRL
PURPOSE Selects channel for CS8414 channel status information CS8414 mode selection
POSITION HI *LO *Low *High *Low *Low INT *EXT *8414 DEM *8414 EXT *ON OFF *ON OFF *x1 /2 HI *LOW HI *LOW HI *LOW Enable *Disable
FUNCTION SELECTED See CS8414 Datasheet for details See CS8414 Datasheet for details
Selects SCLK Mode Selects source of de-emphasis control Selects source of clocks and audio data Enables the external mute for AOUTA Enables the external mute for AOUTB Selects High-Rate or Base-Rate Modes DIF1 DIF0 DEM0 Enables/Disables parallel port
Internal SCLK Mode External SCLK Mode CS8414 de-emphasis De-emphasis input static low Selects CS8414 as source Digital I/O header becomes an source Mute Enabled Mute Disabled Mute Enabled Mute Disabled Selects Base-Rate Mode Selects High-Rate Mode See CS4340 Datasheet for details See CS4340 Datasheet for details See CS4340 Datasheet for details Invalid for CS4340 Disables parallel port
Table 3. CDB4340 Jumper Selectable Options *Default setting from factory
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CDB4340/41
JUMPER CSLR/FCK M0 M1 M2 M3 SCLK DEM_8414 HDR1-6 HDR 7 HDR 8 MCLK HDR15 HDR16 HDR17 ENCTRL
PURPOSE Selects channel for CS8414 channel status information CS8414 mode selection
POSITION HI *LO *Low *High *Low *Low INT *EXT *8414 DEM *8414 EXT *ON OFF *ON OFF *x1 /2 *HI LOW *HI LOW HI *LOW *Enable Disable
FUNCTION SELECTED See CS8414 Datasheet for details See CS8414 Datasheet for details
Selects SCLK Mode Selects source of de-emphasis control Selects source of clocks and audio data Enables the external mute for AOUTA Enables the external mute for AOUTB Selects High-Rate or Base-Rate Modes SCL Pull-Up SDA Pull-Up AD0 Enables/Disables parallel port
Internal SCLK Mode External SCLK Mode "Don't Care" for CS4341 Selects CS8414 as source Digital I/O header becomes an source Mute Enabled Mute Disabled Mute Enabled Mute Disabled Selects Base-Rate Mode Selects High-Rate Mode SCL pulled high Invalid for I2C mode SDA pulled high Invalid for I2C mode "Don't Care" for Control Port Mode Enables parallel port Disables parallel port (must use HDR14)
Table 4. CDB4341 (I2C Mode) Jumper Selectable Options *Default setting from factory Notes: The CDB4341 evaluation board is shipped from the factory configured for I2C mode.
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CDB4340/41
JUMPER CSLR/FCK M0 M1 M2 M3 SCLK DEM_8414 HDR1-6 HDR 7 HDR 8 MCLK HDR15 HDR16 HDR17 ENCTRL
PURPOSE Selects channel for CS8414 channel status information CS8414 mode selection
POSITION HI *LO *Low *High *Low *Low INT *EXT *8414 DEM *8414 EXT *ON OFF *ON OFF *x1 /2 *HI LOW *HI LOW HI *LOW *Enable Disable
FUNCTION SELECTED See CS8414 Datasheet for details See CS8414 Datasheet for details
Selects SCLK Mode Selects source of de-emphasis control Selects source of clocks and audio data Enables the external mute for AOUTA Enables the external mute for AOUTB Selects High-Rate or Base-Rate Modes CCLK Pull-up or Pull-down CDIN Pull-up or Pull-down CS Pull-up Enables/Disables parallel port
Internal SCLK Mode External SCLK Mode "Don't Care" for CS4341 Selects CS8414 as source Digital I/O header becomes an source Mute Enabled Mute Disabled Mute Enabled Mute Disabled Selects Base-Rate Mode Selects High-Rate Mode "Don't Care" for SPI mode "Don't Care" for SPI mode "Don't Care" for Control Port Mode Enables parallel port Disables parallel port (must use HDR14)
Table 5. CDB4341 (SPI Mode) Jumper Selectable Options *Default setting from factory Notes: When in SPI mode, it is not possible to read the control registers of the CS4341. The CDB4341 evaluation board is shipped from the factory configured for I2C mode.
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CDB4340/41
I/O for Clocks and Data Fig 11 Digital Audio Input Fig 6 RXN RXP CS8414 Digital Audio Receiver Connections Fig 5 MCLK LRCK SCLK SDATA Reset Circuit Fig 9 Voltage MCLK LRCK Level Converter SCLK SDATA Fig 7
Control Port Interface Fig 8
CS4340/41 Fig 2
Passive Analog Filter Fig 3
External Mute Circuit Fig 4
Figure 1. System Block Diagram and Signal Flow
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MUTEC
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C44 3.3UF TP5 MUTEC
ALP
FERRITE_BEAD L1 1
RST SDATA-A DEM1/SCLK-A LRCK-A MCLK-A DIF1/SCL/CCLK-A DIF0/SDA/CDIN DEM0/AD0/CS-A VA+3/+5
R10 499 R13 499 R14 499 R41 49.9 R40 200 R39 200
2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
C17 .1UF X7R U7
/RST MUTEC SDATA AOUTA SCLK VA CS4341 LRCK AGND MCLK AOUTB SCL/CCLK REF_GND SDA/CDIN VCOM AD0//CS FILT+ 16 15 14 13 12 11 10 9
C23 10UF
AGND
3.3UF TP4
ARP
C43
CS4341_KS 1UF C20 X7R C34 .1UF 1UF C21 X7R C35
AGND
.1UF
CDB4340/41
Figure 2. CS4340/41
9
10
MUTEA
HDR1X2 HDR7 1 2
R18
ALP
J4 CON_RCA_RA 560 C18 1500PF COG
JP3 1
R28 10K
C6 1500PF COG
2
3 4 NC
AOUTLP A
AGND
AGND AGND
HDR1X2 HDR8 1 2
MUTEB
R17
ARP
J3 CON_RCA_RA 560 C22 1500PF COG
JP6 1
R29 10K
C5 1500PF COG
2
3 4 NC
AOUTRP B
AGND
CDB4340/41
AGND AGND
Figure 3. Analog Output Passive Filter
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VA+3/+5
2 1
MMUN2111LT1 Q3
3
MUTEA
MUTEB
Q1 2SC2878 R25 2K
3
2 3
2
3
MUTEC
1
Q4 MMUN2211LT1
2
Q2 2SC2878
1
1
AGND
AGND
R31
AGND
2K
CDB4340/41
Figure 4. External Mute Circuit
11
1 2 3
1 2 3
VA+5
C1 10UF
VA
HDR1X3 HDR3
GND
1 2 3 HDR1X3 HDR2
1 2 3
SCLK
LRCK
GND
1 2 3
12
HDR1X3 HDR5
MCLK
HDR1X3 HDR4
VD1
HDR1X3 M0 1 2 M0 3 HDR1X3 M1 1 2 M1 3 HDR1X3 M2 1 2 M2 3 HDR1X3 M3 1 2 8414_M 3 HDR1X3 CSLR/FCK 1 2 CSLR/FCK 3
R11
VD1
10 .1UF X7R 1UF
1 2 3 4 5 6 7 8 9 10 11 12 13 14
HDR1X3 HDR1
C26 C16 .1UF
VD+5
RN3 560
SDATA
C27
U2 C VERF CD/F1 CE/F2 CC/F0 SDATA CB/E2 ERF CA/E1 M1 /C0/E0 M0 VD+ VA+ DGND AGND RXP FILT RXN MCK FSYNC M2 SCK M3 CS12/FCK SEL U CBL CS8414
28 27 26 25 24 23 22 21 20 19 18 17 16 15
.1UF X7R
CS8414_M0
VD+5
14
C31 VCC
1
U8
D1 LED_RECT 2
GND
1UF C32
CS8414_M1
SN74HC04N
D3 LED_RECT 4 3
VA
CS8414_M2
RXP RXN CSLR/FCK
R9 470
C33
.068UF X7R
GND
D5 LED_RECT
6
5
CSLR/FCK
8414_DEM
D6 LED_RECT 8 9
SW_B3W_1100 S4
D4 LED_RECT 10 11
GND
R6 47.5K
HDR1X3 8414_DEM 1 DEM 2 3 8414 HDR1X3 EXT_INT_SCLK 1 INT 2 3 EXT
R7 47.5K
TP10
ERROR & FREQ
D2 12 LED_RECT 13
8414_DEM
VD1
7
GND
DEM1/SCLK SCLK
INT/EXT SCLK
GND
CDB4340/41
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Figure 5. CS8414 Digital Audio Receiver Connections
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DIGITAL INPUT
J5
CON_RCA_RA
1
OPTICAL INPUT
OPT1 C11
6
C10
1 2 3 4
NC
3 4
RXN
R30 .01UF 75
5
RXP
.01UF C9 .01UF L4 47UH
2
VD+5
GND
TORX173
GND
CDB4340/41
Figure 6. Digital Audio Inputs
13
Q1 /Q1 Q2 /Q2 GND
5 6 9 8
1 2 3
VD+5 VD+5 VD+5 VD+5 GND
4 3 2 1 10 11 12 13
VCC /SET1 CLOCK1 DATA1 /RST1 /SET2 CLOCK2 DATA2 /RST2
14
VD+5
J20 HDR1X3
MCLK SDATA DEM1/SCLK LRCK DIF1/SCL/CCLK DEM0/AD0/CS
19 1 2 3 4 5 6 7 8 9
/G DIR A1 A2 A3 A4 A5 A6 A7 A8
VCC B1 B2 B3 B4 B5 B6 B7 B8 GND
20
HRM
BRM MCLK-B
18 17 16 15 14 13 12 11 10
SDATA-A DEM1/SCLK-A LRCK-A MCLK-A DIF1/SCL/CCLK-A DEM0/AD0/CS-A
7
MC74HC74AN
GND
SN74VHC245DW
VD+5
GND
C15 .1UF GND
AGND
14
VA+3/+5 MCLK
U5 U1 C14 .1UF
CDB4340/41
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Figure 7. MCLK Divider and Voltage Level Converter
1K 1K 1K 1K 1K 1K
R2 R3 R5 R4 R8 R12
1 14 2 15 3 16 4 17 5 18 6 19 7 20 8 21 9 22 10 23 11 24 12 25 13
LATCH ENCTRL
VCC GND
GND
20 10
VDPC+5
VA+3/+5
SN74HC574N C4
.1UF
2K
2K
2K
R16
R20
GND
HDR4X2 HDR14 1 2 3 4 5 6 7 8
R22
2K
2K
DIF1/SCL/CCLK DIF0/SDA/CDIN DEM0/AD0/CS
2K
R19
R21
GND GND
Figure 8. Control Port Interface
R23
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VDPC+5
DB25M_RA P1
C7
VDPC+5
SN74HCT125N
6 5
GND PC0
.1UF VCC
2 14
U6
3
U6
LATCH
12 11
SN74HCT125N GND
71
SN74HCT125N
13
GND
4
GND
U6
U3
1 11 2 3 4 5 6 7 8 9
/OC CLK 1D 2D 3D 4D 5D 6D 7D 8D 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q
19 18 17 16 15 14 13 12 10
DIF1/SCL/CCLK
SN74HCT125N
9 8
DIF0/SDA/CDIN
U6
DEM0/AD0/CS
VDPC+5
GND
HDR1X3 HDR15 1 2 3 HDR1X3 HDR16 1 2 3 HDR1X3 HDR17 1 2 3
VDPC+5
HDR1X3 HDR18 1 2 3
ENCTRL
CDB4340/41
GND
15
C29 3.3UF
R27
100
AGND
AGND
S1 SW_B3W_1100
16
VA+3/+5
R1 200K
BAT85
D7
RST
CDB4340/41
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Figure 9. Reset Circuitry
C8
.1UF
L2 FB
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+5V
CON_BANANA
GND
CON_BANANA
+3V/+5V
CON_BANANA
J6 Z1
J7 P6KE6V8P
J1
P6KE6V8P
Z2
C12 47UF
C2 47UF
C25
VA+5
.1UF
C3
.1UF
VA+3/+5
L3 FB C13 47UF
AGND
GND
GND
10UF C19 VDPC+5
CDB4340/41
VD+5
Figure 10. Power Supply
17
18
7 8 9 10 11
U4 74HC243 GND B4 B3 B2 B1 VCC A4 A3 A2 A1 GBA /GAB
6 5 4 3 13 1 9 7 5 3 1 10 8 6 4 2 MCLK SCLK LRCK SDATA
GND MCLK SCLK LRCK SDATA VD+5
J9 HDR5X2
14
GND
C24 .1UF
GND
DIGITAL I/O
8414 EXTERNAL CLK SOURCE HDR1X3 HDR6
1 2 3
GND
VD+5
CDB4340/41
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Figure 11. I/O for Clocks and Data
CDB4340/41
Figure 12. Silkscreen Top
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19
CDB4340/41
Figure 13. Top Side
20
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CDB4340/41
Figure 14. Bottom Side
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