View CS5361REV10_978022.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Back
CS5361 Battery Charger Buck Controller
The CS5361 is a high voltage step down controller that provides a simple way to build a battery charger suited for various types of batteries. With an operating range of up to 30 V, it can be used to charge a multiple number of cells from a DC voltage, as is supplied by high AC-DC adapter voltages. Proprietary I2 architecture ensures full control over both Average and Peak charging currents. Independent voltage loop allows for precision regulation of the battery voltage. Average current outer control loop provides tight regulation and easy loop compensation while pulse by pulse inner control provides for fast response. The CS5361 is designed to provide a high performance, full-featured battery charger that is simple to use. A 4.2 V reference with 0.8% tolerance can be used to implement 1.0% accurate output voltages. It also features an additional pulse-by-pulse current limit input to allow for fast output current control. The CS5361 operates over a 7.0 V to 30 V range and is available in a 16 lead surface mount narrow body. Features * Switching Regulator Controller - Synchronous Buck Regulator Topology for High Efficiency - Top Side P-Channel Allows High Input Voltage and Requires No Charge Pump - Pulse-by-Pulse Inner Control Loop for Fast Response - Programmable Peak Current Limit - True Current Soft Start - Clamped Gate-to-Source Voltage * Oscillator - Constant Frequency Design - 100 kHz to 500 kHz Adjustable Frequency * System Power Management - Programmable UVLO - 2.0 A Sleep Mode Current (Typical) - Bias Mode Uses Top Switch to Connect Battery to Load - 4.2 V 0.8% Reference Output - Thermal Shutdown
http://onsemi.com
16 1
SO-16 D SUFFIX CASE 751B
PIN CONNECTIONS AND MARKING DIAGRAM
1 ENABLE/UVLO OSC VREF(IN) LGND ICOMP VREF IAVG VCOMP 16 GATE(H) VCC GATE(L) PGND IS+ IS- IPEAK VFB
A = Assembly Location YY, Y = Year WW, W = Work Week
ORDERING INFORMATION
Device CS5361GD16 CS5361GDR16 Package SO-16 SO-16 Shipping 48 Units/Rail 2500 Tape & Reel
5361 YYWWA
(c) Semiconductor Components Industries, LLC, 2001
1
October, 2001 - Rev. 10
Publication Order Number: CS5361/D
CS5361
VIN 18.5 V to 24.5 V 1.0 F C5 R7
Q3 VOUT 16.8 V
CIN 10
R3 40.2 k 1% VCC GATE(H) Q1 L1 CS5361 33 H Q2 GATE(L) R4 EN/UVL 12.7 k 1% IS+ IS- D1 R1 75 k 0.1% CO 10 R2 24.9 k 0.1% RSENSE 0.05 1%
OSC 330 k C3 Rc 1.0 k C2 100 p VCOMP VREF(IN) R5 4.12 k 1% R6 6.04 k 1% VREF IAVG IPEAK C1 0.1 0.022 ICOMP
C4
0.1
VFB
Shutdown
Figure 1. Application Diagram, 16.8 V/2.0 A Four Cell Lithium-Ion Battery Charger with High Side Current Sensing
http://onsemi.com
2
CS5361
MAXIMUM RATINGS*
Rating Operating Junction Temperature Lead Temperature Soldering: Storage Temperature Range Package Thermal Resistance: Junction-to-Case, RJC Junction-to-Ambient, RJA ESD Susceptibility (Human Body Model) 1. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Reflow: (SMD styles only) (Note 1) Value 150 230 peak -65 to +150 28 115 2.0 Unit C C C C/W C/W kV
MAXIMUM RATINGS
Pin Name IC Power Input Positive Current Sense Input Negative Current Sense Input Shutdown and UVLO Input Average Current Loop Set Point Peak Current Loop Set Point Voltage Feedback Input Reference Voltage Input Voltage Loop Compensation Pin High-Side FET Driver Low-Side FET Driver Current Loop Compensation Pin Power Ground Logic Ground Reference Voltage Output Oscillator Pin Pin Symbol VCC IS+ IS- Enable/UVLO IAVG IPEAK VFB VREF(IN) VCOMP GATE(H) GATE(L) ICOMP PGND LGND VREF OSC VMAX 30 V 30 V 30 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 6.0 V 30 V 15 V 6.0 V 0V 0V 6.0 V 6.0 V VMIN -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -0.3 V -2.0 V for 50 ns -0.3 V -2.0 V for 50 ns -0.3 V 0V 0V -0.3 V -0.3 V ISOURCE N/A 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 2.0 A Peak 200 mA DC 2.0 A Peak 200 mA DC 1.0 mA 2.0 A Peak 200 mA DC 200 mA DC 50 mA 10 mA ISINK 2.0 A Peak 50 mA DC 1.0 mA 1.0 mA 10 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 1.0 mA 2.0 A Peak 200 mA DC 2.0 A Peak 200 mA DC 1.0 mA N/A N/A 50 mA 10 mA
http://onsemi.com
3
CS5361
ELECTRICAL CHARACTERISTICS (0C < TA < 70C; 0C < TJ < 115C; 7.0 V < VCC < 30 V; CGATE(H) = CGATE(L) =
1.0 nF, CREF = 0.1 F, CVCC = 0.1 F, CICOMP = 0.1 F; unless otherwise specified.) Characteristic Voltage Error Amplifier VFB Bias Current VCOMP Source Current VCOMP Sink Current Open Loop DC Gain Transconductance (Gm) Output Impedance PSRR @ 1.0 kHz CMRR @ 1.0 kHz Input Voltage Offset VCOMP Max Voltage VCOMP Min Voltage GATE(H) and GATE(L) High Voltage (AC) Low Voltage (AC) Rise Time Note 2 Note 2 For VCC > 10 V: Note 2 1.0 V < GATE(L) < 3.0 V, VCC - 8.0 V < GATE(H) < VCC - 1.0 V; For 7.0 V < VCC < 10 V: 1.0 V < GATE(L) < VCC - 1.0 V, 1.0 V < GATE(H) < VCC 1.0 V For VCC > 10 V: Note 2 3.0 V > GATE(L) > 1.0 V, VCC - 1.0 V > GATE(H) < VCC - 8.0 V; For 7.0 V < VCC < 10 V: VCC - 1.0 V > GATE(L) < 1.0 V, VCC - 1.0 V > GATE(H) > 1.0 V VCC - GATE(H) < 2.0 V, GATE(L) > 2.0 V Note 2 GATE(L) < 2.0 V, VCC - GATE(H) > 2.0 V Note 2 - - IGATE(H) = 100 A - IGATE(H) = 10 A to GND in Bias mode GATE(H) = VCC - 5.0 V VCC - 0.5 - - VCC 0 40 - 0.5 80 V V ns Note 2 Note 2 Note 2 1.0 V to 5.0 V VREF(IN) = 3.3 V, VFB = 3.2 V VREF(IN) = 3.3 V, VFB = 3.4 V VFB = 0 V VCOMP = 0.5 V to 3.3 V; VFB = 0.9 V VCOMP = 0.5 V to 3.3 V; VFB = 1.1 V Note 2 - - 68 60 60 0.6 1.4 60 80 -5.0 3.9 - 0.1 100 100 80 1.2 8.3 85 110 - 5.0 0.1 0.27 170 160 100 2.1 47.6 - - 6.5 6.5 0.2 A A A dB mA/V M dB dB mV V V Test Conditions Min Typ Max Unit
Fall Time
-
40
80
ns
GATE(H) to GATE(L) Delay GATE(L) to GATE(H) Delay GATE(L) Clamp to GND GATE(H) Clamp to VCC GATE(H) Sleep Clamp GATE(L) Resistance to GND GATE(H) Bias Clamp GATE(H) Bias Current
40 15 4.0 -15 - 20 13 3.0
80 60 5.0 -12 VCC - 0.7 50 16 10
110 80 6.0 -10 VCC - 1.0 100 20 20
ns ns V V V k V A
2. Guaranteed by design, not 100% production tested.
http://onsemi.com
4
CS5361
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 115C; 7.0 V < VCC < 30 V; CGATE(H) = CGATE(L) = 1.0 nF, CREF = 0.1 F, CVCC = 0.1 F, CICOMP = 0.1 F; unless otherwise specified.)
Characteristic Oscillator Switching Frequency Switching Frequency Switching Frequency Bias Threshold Positive Bias Threshold Negative Bias Threshold Hysteresis Bias Input Current Average Current Error Amplifier IAVG Bias Current ICOMP Source Current ICOMP Sink Current Set Point Open Loop DC Gain Transconductance (Gm) Output Impedance PSRR @ 1.0 kHz ICOMP Max Voltage ICOMP Min Voltage Current Sense Amplifier IS+, IS- Bias Current Input Offset DC Gain Gain Bandwidth (-3.0 dB) Propagation Delay PSRR @ 1.0 kHz CMRR @ 1.0 kHz Input Common Mode Range Input Differential Mode Range Peak Current Comparator Set Point IPEAK Bias Current IPEAK = 3.0 V, Duty Cycle = 50% IPEAK = 0 V 90 - 100 0.3 110 1.0 mV A Note 3 IS- = IS+ = 0 V to VCC (20 V max) IS- = 0 to VCC IS- = 1.0 V to VCC Note 3 Note 3 Note 3 Note 3 - -5.0 -8.0 23 3.5 - 60 80 0 0 1.0 - 25 5.5 70 85 100 - - 5.0 7.0 27 - 105 - - VCC 125 A mV V/V MHz ns dB dB V mV IAVG = 0 V ICOMP = 0.5 V to 3.3 V ICOMP = 0.5 V to 3.3 V IAVG = 0.25V, 7.0 V < VCC < 24 V IAVG = 2.5 V, 7.0 V < VCC < 24 V Note 3 Note 3 Note 3 Note 3 VI(AVG) = 3.3 V, IS+ = IS- = 0V VI(AVG) = 0 V, IS+ = 0.2 V, IS- = 0 V - 18 18 2.0 90 60 0.2 5.0 60 3.9 - 0.2 25 25 10 100 80 0.3 33 80 5.0 0.1 1.0 32 32 16.5 110 100 0.7 143 - 6.5 0.2 A A A mV mV dB mA/V M dB V V OSC = 5.0 V 960 k from OSC to GND 330 k from OSC to GND 185 k from OSC to GND - - - 80 240 420 2.5 2.25 150 - 100 300 500 2.75 2.5 250 - 120 360 635 3.0 2.75 350 1.0 kHz kHz kHz V V mV A Test Conditions Min Typ Max Unit
3. Guaranteed by design, not 100% production tested.
http://onsemi.com
5
CS5361
ELECTRICAL CHARACTERISTICS (continued) (0C < TA < 70C; 0C < TJ < 115C; 7.0 V < VCC < 30 V; CGATE(H) = CGATE(L) = 1.0 nF, CREF = 0.1 F, CVCC = 0.1 F, CICOMP = 0.1 F; unless otherwise specified.)
Characteristic PWM Comparator Transient Response ICOMP Input Resistance Slope Compensation Oscillator Duty Cycle Minimum Pulse Width Enable/UVLO Management Enable Input Threshold Input Resistance Input Bias Current Reference Output VREF Output Voltage VREF Short Circuit Current Thermal Protection Over Temperature Trip Point Thermal Shutdown Hysteresis General Electrical Specifications VCC Operating Current (Non-Switching) VCC Sleep Current VCC Bias Mode Current VCOMP = ICOMP = 0 V ENABLE/UVLO = 0V; 7.0 V < VCC < 20 V; TA = 25C ENABLE/UVLO = 0 V - - - 17 2.0 50 30 5.0 75 mA A A Note 4 Note 4 125 - 150 25 175 - C C 0 mA < IV(REF) < 1.0 mA VREF = 0V 4.166 3.0 4.2 6.0 4.234 10 V mA Note 4 VENABLE/UVLO = 2.75 V - 2.25 10 - 2.5 50 0.1 2.75 80 1.0 V k A Note 4 Note 4 Note 4 Note 4 - - 200 0.8 85 - 50 500 1.0 90 150 - 800 1.2 95 200 ns V % ns Test Conditions Min Typ Max Unit
4. Guaranteed by design, not 100% production tested.
http://onsemi.com
6
CS5361
PACKAGE PIN DESCRIPTION
Package Pin # SO-16 1 2 3 4 5 6 7 8 9 10 Pin Symbol ENABLE/UVLO OSC VREF(IN) LGND ICOMP VREF IAVG VCOMP VFB IPEAK Function Shutdown input. Connect to VIN through a resistor divider to program minimum operating voltage. Pull below 2.5 V to shut down the IC. Oscillator pin. Place resistor to GND to set the switching frequency. Enters bias mode when pulled above 2.75 V and the ENABLE/UVLO Input is low (PFET turned ON). Reference input of the voltage error amplifier. Connect to the built-in or external reference. Logic Ground. IC Substrate Connection. Current feedback compensation network. 4.2 V Reference output voltage. Capable of sourcing 3.0 mA. Average current control loop input. Voltage at this pin sets average output current. Voltage feedback compensation network. Voltage feedback pin. Connect a resistor divider between output and this pin to set output voltage. Peak current control loop input. This input is used to set peak value of the inductor ripple current. This pin can override average current loop setting. It can be used for fast current control. Negative input of the current sense amplifier. Positive input of the current sense amplifier. Power Ground. Low-Side FET Driver. This pin is capable of delivering peak currents of 1.0 A. Input power supply pin or VCC bias. High-Side FET Driver. This pin is capable of delivering peak currents of 1.0 A.
11 12 13 14 15 16
IS- IS+ PGND GATE(L) VCC GATE(H)
http://onsemi.com
7
CS5361
Reset Dominant PULSE OSC OSC Negative RAMP 0 to -200 A VCOMP VREF(IN) VFB ICOMP IAVG + - Rail-to-Rail Low Vos. High Speed + - 500 5k - + PWM Comp + - 50 k 2.5 V ENABLE/ UVLO EN V REF =4.2 V Thermal Shutdown PGND + - Voltage Error Amp. + - Bias COMP S R QN NONOVR GATE(L) GATE(H)
2.5 V VCC
VREF
Avg. Current Amp. x 25 Current Sense Amp.
IS+ IS-
IPEAK
- +
x1 Peak Current Buffer Amp.
2.5 V + - LGND
Figure 2. Block Diagram
http://onsemi.com
8
CS5361
APPLICATIONS INFORMATION THEORY OF OPERATION
Overview
The CS5361 battery charger controller has been designed with the flexibility to charge several types of batteries, such as Lithium Ion, Nickel Cadmium, Nickel Metal Hydride and Lead Acid. The differences in chemistry between different battery types result in differing charge requirements. Lithium Ion batteries are charged with a constant voltage, current limit supply. When the battery voltage is low, the charger operates in constant current mode. When the battery voltage reaches 4.2 V, the current begins to taper off and the charger enters into constant voltage mode until the current essentially reaches zero. Nickel Cadmium and Nickel Metal Hydride batteries can be charged with a constant current profile. Lead Acid batteries are charged with a constant voltage, current limiting supply or with a constant-current supply. For a battery charger with the capability to charge all those battery types, at least two operation modes are required: constant current mode and constant voltage mode. Synchronous operation enables designs with greater than 94% efficiency to be realized.
Control Method
- PWM +
GATE(H) GATE(L)
RAMP Current Sense + Error - + IAVG - Inductor Current
Sense Resistor
Figure 3. I2 Control Scheme
1. Current Control I2 control scheme is employed to regulate the charging current. The sense resistor senses the inductor current. A low offset, high speed Current Sense amplifier with rail-to-rail inputs amplifies the voltage across the sense resistor. The output of the amplifier (ISENSE), which is proportional to the inductor current, is used as feedback for two control loops. The DC level is used by the outer loop and is fed to the Average Current Error Amplifier. The Error Amplifier compares ISENSE to an externally set reference voltage IAVG and generates a PWM control voltage ICOMP. Charger designers can use the ICOMP pin to design the compensation for the Average Current Amplifier. The current ripple is used as the ramp signal of the PWM comparator. I2 control has inherent compensation for duty cycle in response to line voltage or load changes. Changes in line and load conditions affect the inductor current. Because the ramp signal of the PWM comparator is generated from the inductor current, the duty cycle can be adjusted on a pulse by pulse basis. Since the fast PWM control loop handles transient response, a high gain, low bandwidth error amplifier can be used to improve DC accuracy, stability and noise immunity.
2. Voltage Control Current mode voltage control method is used to regulate the voltage. The VFB pin monitors the battery voltage. A resistor divider is used to scale the voltage down to the reference level set at the VREF(IN) pin. CS5361 provides a 4.2 V 0.8%reference voltage which can obviate the need for a resistor network if charging a single 4.2 V cell. VFB and VREF(IN) are the two inputs of the Voltage Error Amplifier. The output VCOMP is compared with the ramp signal, which is generated from the inductor current, to adjust the duty cycle. Similar to ICOMP, VCOMP provides user with compensation capability.
Start-Up
CS5361 provides a controlled startup of regulator output current and voltage through the Error Amplifiers and external compensation networks. The capacitor at the ICOMP output provides true current soft start. As the capacitor charges up, the Average Current Error Amplifier signal increases. The output current of the regulator ramps up in a controlled manner. The compensation network at VCOMP has the similar function, which will prevent instantaneous switching of the output voltage.
Oscillator
The battery charger controller is designed for constant frequency operation. The user can adjust the switching frequency from 100 kHz to 500 kHz by connecting a resistor from the OSC pin to GND. This function simplifies the
http://onsemi.com
9
CS5361
selection of external components and allows the user freedom to choose switching frequency.
Gate Drivers GATE(H) and GATE(L) Error Amplifier Compensation
In synchronous buck operation, GATE(H) and GATE(L) drive the high-side P-channel MOSFET and the low-side N-channel MOSFET respectively. The advantage of this circuit is that no charge pump is required. The low-side FET (the synchronous rectifier) behaves like a diode but has a smaller voltage drop and improves the efficiency. A 60 ns nonoverlap dead time is added between the time when the high-side FET is turned off and when the synchronous rectifier is turned on, and vice versa. This function effectively prevents crowbar currents during switching transitions.
Gate Voltage Clamps
The outputs of the Average Current Error Amplifier and the Voltage Error Amplifier are available to users. Users have the freedom to design the compensation network to improve the dynamic characteristics such as transient response time, over/undershoot, and loop stability.
Enable/Under-Voltage Lockout
Internal clamps prevent driving the external power MOSFET gate voltages to levels higher than required for complete enhancement. This improves converter efficiency by reducing gate rise time, fall time, and the losses associated with the charge and discharge of gate capacitance.
Bias Mode
The input voltage of the charger must remain above a certain level in order to work. Control is required to ensure that the charger will not start to operate without sufficient voltage. Under-Voltage Lockout provides this protection with a comparator, which compares the input to 2.5 V. The output of the comparator enables the charger's reference voltage, which in turn controls startup of the charger. The comparator's output also controls the high-side MOSFET so that the batteries will power the load when the charger is shut off. This pin also provides the function of manual shutdown by bringing the pin below 2.5 V. Chip current in the shutdown mode is only 2.0 A.
Peak Current Control
When the battery is fully charged, the charger can be shut down externally by pulling the ENABLE/UVLO pin low. When the part is off and the OSC pin is pulled above 2.75 V, the charger will enter into Bias Mode. In Bias mode, the high-side PFET turns on and connect the battery to the load so that the battery starts discharging to the load.
100% Duty Cycle
The maximum duty cycle of the CS5361 is 100%. This feature is useful when the input voltage is marginally higher than the output voltage. If the battery voltage is very close to the input line voltage, the controller will simply go to 100% duty cycle.
Slope Compensation
In both current and voltage controls, the sensed inductor current signal is used as the ramp of the PWM comparator to afford fast response to line and load variations. An artificial ramp signal with negative slope generated by the oscillator is added to the two negative inputs (VCOMP and ICOMP) of the PWM comparator to be compared with the ramp generated by the inductor current. The output of the PWM comparator is used to control the duty cycle. This method helps stabilize the system over the whole operation duty cycle range as well as minimize response time to output current changes.
The Peak Current Buffer Amplifier compares the current control signal (the output of the Average Current Error Amplifier) with a preset reference voltage, which can be set externally at pin IPEAK. When output of the Error Amplifier exceeds the limit, the output of the Peak Current Buffer Amplifier goes low and clamps current control signal. Therefore, the peak current control can override the average current control. In laptop computer systems, fast reducing the charge current is required to prevent overloading the input supply when the computer switches into active mode from sleep mode. On the other hand, a trickle charging mode is required in many battery chargers either to prevent over-discharged or fully charged cells from being damaged by constant-current charging. The current for trickle charging is usually much lower than that of constant-current charging. The Peak Current Control can be utilized to implement trickle charging mode without changing the setting of the average charging current.
Input Current Limiting
An input current limiting function can be implemented externally using a dual op-amp, a sense resistor and several resistors and capacitors. The first op-amp is configured into a differential amplifier. The second op-amp compares the amplified input current signal with a reference voltage. The output is used to clamp the ICOMP pin voltage when input current exceeds the limit. See Figure 9 for detailed implementation.
http://onsemi.com
10
CS5361
Constant Current Constant Voltage Shutoff Bias Mode
VCC
VREF
4.2 V
Battery Voltage
16.8 V
Battery Current
2.0 A
0A
VCOMP Inductor Current
ICOMP
GATE(H)

GATE(L) ENABLE/ UVLO
2.5 V
2.5 V 2.5 V
OSC
: Nonoverlap Time
Figure 4. Key Operation Waveforms
DESIGN GUIDELINES
1. Selection of the Output Inductor
The peak current should not saturate the core of the inductor.
2. Selection of Output Capacitor
The value of the output inductor can be calculated based on the inductor ripple current requirement:
L + (1.0 * D) TSVOUT DIL
(1)
Both the output voltage ripple and the inductor current ripple determine the value of the output capacitance. The required minimum is given by:
C + 0.125 DILTS DVOUT
(3)
where VOUT is the output voltage; TS is the period of one switching cycle; IL is the peak-to-peak inductor ripple current given by design specification; and D is the duty cycle. Because both duty cycle and the output voltage change during charging operation, the designer should determine the maximum product of (1.0 - D) and VOUT to calculate the inductance. The peak inductor current is given by:
DI IL,PEAK + IO ) L 2.0
(2)
The capacitor ESR (Equivalent Series Resistance) of the capacitor also needs to be small enough to meet the ripple requirement.
ESRMAX + DVOUT DIL
(4)
If the ESR obtained from the above equation is smaller than the ESR specified in the capacitor manufacturer's data
http://onsemi.com
11
CS5361
sheet; several capacitors should be paralleled. The number of capacitors is determined by:
Number of Capacitors + ESRPER CAP ESRMAX
(5)
RSENSE v 125 mV IPEAK
(8)
After the value of current sense resistor is determined, the resistor divider for current setting can be designed.
R6 + IOUT R5 ) R6 RSENSE 25 4.2 V
3. Design of Resistor Divider for Voltage Sensing
Because the internal reference voltage is 4.2 V, which is equal to the voltage of one Lithium Ion battery cell, we have:
1.0 R2 + R1 ) R2 Cell Count
where IOUT is the target value of the output current. The maximum bias current of the Current Error Amplifier is 1.0 mA. The voltage across the resistor divider is 4.2 V. If we choose R5 + R6 = 10 k, we have
42 + 420 mA >> 1.0 mA 10 kW
The maximum input bias current of the Voltage Error Amplifier is 1.0 A, the resistor divider current should be much higher than that to ensure that there is sufficient bias current. For 4-cell charger, the output voltage is 16.8 V. If we choose R1 + R2 = 100 k, then
16.8 V + 168 mA >> 1.0 mA 100 kW
Therefore,
R6 + 10 kW 25 IOUT RSENSE , 4.2 V
(9)
R5 + 10 kW * R6
Therefore,
R2 + 100 kW , R1 + 100 kW * R2 Cell Count
(6)
6. Design of Average Current Compensation Network
R1 and R2 must be 0.1% precise resistors to meet the 1.0% overall charge voltage accuracy.
4. Design of Resistor Divider for Enable/Under-Voltage Lockout
The resistor divider should be so designed that the controller can be enabled at the required minimum input voltage.
R4 + 2.5 V R3 ) R4 VIN,MIN
As mentioned before, there are two feedback loops in the I2 control scheme. The slow outer loop provides tight regulation and easy loop compensation. The fast inner loop handles the transient response on a pulse-by-pulse basis. The design of the compensation network is based on the control-to-output transfer function with closed inner current feedback loop. In this case, "control" is the output of the Average Current Error Amplifier (ICOMP) and "output" is the inductor current. The approximate control-to-output transfer function for the Buck converter is given by:
1.0 ) sC (ESR ) R) IL [ ICOMP RI(1.0 ) sCR) 1.0 ) s (wnQ) ) s2 wn2
(10)
The maximum bias current for this pin is also 1.0 A. The sum of R3 and R4 can also be chosen as 100 k, so
R4 + 100 kW 2.5 V , R3 + 100 kW * R4 VIN,MIN 5. Selection of Current Sense Resistor and Resistor Divider for Current Setting
(7)
where RI is the current sense gain, n is half of the switching frequency and
Q+ p[(1.0 ) Se Sn) 1.0 (1.0 * D) * 0.5]
(11)
The tolerance of the current sense resistor affects the accuracy of current regulation, so a sense resistor with 1.0% tolerance should be used. Since the Current Sense Amplifier is a high-speed, low voltage rail-to-rail amplifier, the value of the current sensing resistor should satisfy the following condition:
IPEAK RSENSE v 125 mV
where 125 mV is the differential mode input range of the Current Sense Amplifier. Therefore,
where Se is the slope of the external ramp signal and Sn is the inductor current up slope. The transfer function is a third-order system with a double pole at half of the switching frequency and a low frequency pole. Because ESR of the output capacitor is usually very small compared to load resistor R, the zero and the low frequency pole can cancel out each other. The system degrades to second-order. The compensation design for such a system becomes very easy. A single integrator pole gives the system high DC gain and makes it crossover with -1.0 slope. The Bode plot of the
http://onsemi.com
12
CS5361
closed loop control-to-output transfer function without and with compensation is shown in Figure 5.
R(1.0 ) sC ESR) VOUT [ VCOMP RI(1.0 ) sCR) 1.0 ) s (wnQ) ) s2 wn2
(15)
dB Without Compensation -1
fs/2
-2
f
Compare the above expression with equation (9), the transfer function of current mode voltage control has same poles as I2 control. The difference is the zero. For I2 control, the zero is determined by both ESR of the output capacitor and the load resistor and can be cancel out the low frequency pole. But for current mode voltage control, the zero is a high frequency ESR zero. The low frequency pole cannot be cancelled. So the system is third-order. The Bode plot of the control-to-output transfer function with closed current loop is illustrated in Figure 6
dB
With Compensation
-3 -1 Double Pole f ESR Zero -2 Low Freq. Pole
Figure 5. Bode Plot of Control-to-Output Transfer Function
If a transconductance amplifier is used as the error amplifier, the integrator pole can be implemented by connecting a capacitor from the amplifier output to the ground. The compensation gain is given by:
FC(s) + G (sCCOMP)
(12)
Figure 6. Bode Plot
where G is the transconductance of the amplifier. The total loop gain is
T(s) + RI G (13) sCCOMP 1.0 ) s (wnQ) ) s2 wn2
For a transconductance error amplifier, a possible compensation network is shown in Figure 7. The compensation network has two poles and one zero.
VFB VREF(IN) - + R1 C2 C1 VCOMP
The value of the compensation capacitor CCOMP can be calculated if the crossover frequency is known. Generally, the crossover frequency should be chosen well below the switching frequency. We can choose
fCO + 1 6 fS
Figure 7. Compensation Network
So
CCOMP + RI G 2.0pfCO
(14)
The compensation gain is given by:
F(s) + (C1 ) C2) G (1.0 ) sR1C1) (16) s[1.0 ) sR1C1C2 (C1 ) C2)]
7. Design of Voltage Compensation Network
For voltage, "control" is referred to the output of the Voltage Error Amplifier (VCOMP) and "output" is the output voltage. The control-to-output transfer function with closed current loop is given by:
The integrator pole will give the system high DC gain. Use the zero to compensate the excessive phase delay caused by the low frequency pole of the control-to-output transfer function. The other pole of the compensation network should be placed around the ESR zero to make sure the amplitude decrease fast after the 0 dB crossover.
http://onsemi.com
13
CS5361
Q3 VIN 18.5 to 24.5 V
C5 10
R3 40.2 k VCC GATE(H) Q1 L1 10 H Q2 D1 R4 C7 10 R1 75 k 1%
VOUT 16.8 V
R7 OSC 330 k C3 0.1 R8 1.0 k C2 1000 p C1 0.1 ICOMP VCOMP
CS5361 GATE(L) VREF(IN) VREF EN/UVL 12.7 k IS+ IS- IAVG IPEAK PGND VFB LGND
C4 0.1 R5 69.8 k 1%
Li_Ion Battery Pack R2 24.9 k 1% C6 10
R6 29.4 k 1%
R11 0.025 1% VOUT_RTN Shutdown
VIN_RTN R9 430 k R10 70 k Q5 NPN R13 470 Q4 NPN
R12 470 IPEAK 5.0 V Bias
D2 Diode
Figure 8. Additional Application Diagram, 16.8 V/2.0 A Four Cell Lithium-Ion Battery Charger with Low Side Current Sensing
http://onsemi.com
14
CS5361
C8 1.0 F Load R15 500 VIN 18.5 to 24.5 V D2 R14 0.025 D3 C7 1.0 R7 OSC 330 k C3 0.1 R8 C1 0.1 1.0 k C2 1000 p ICOMP VCOMP CS5361 GATE(L) R4 C4 0.1 Bias +5.0 V R6 60.4 k 1% R9 430 k R5 41.2 k 1% IAVG IPEAK PGND VREF(IN) VREF EN/UVL 12.7 k IS+ IS- VFB LGND R2 24.9 k 1% C6 10 Q2 D1 R1 75 k 1% Li_Ion Battery Pack C5 10 R3 40.2 k VCC GATE(H) Q1 L1 33 H R11 0.05 R16 500
VOUT 16.8 V
U1
VIN_RTN
R10 70 k Q5 NPN R13 470 Q4 NPN R12 470
VOUT_RT Shutdown IPEAK
R19 560 k R17 10 k R18 10 k R20 560 k + U1A R21 10 k U1B LM2903 D4
R22 10 k
+ -
LM2903 R23 560 k C9 1.0 nF
Figure 9. Additional Application Diagram, 16.8 V/2.0 A Four Cell Lithium-Ion Battery Charger with High Side Current Sensing and Input Current Limiting
http://onsemi.com
15
CS5361
PACKAGE DIMENSIONS
-A-
16 9
SO-16 D SUFFIX CASE 751B-05 ISSUE J
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019
-B-
1 8
P
8 PL
0.25 (0.010)
M
B
S
G F
K C -T-
SEATING PLANE
R
X 45 _
M D
16 PL M
J
0.25 (0.010)
TB
S
A
S
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada JAPAN: ON Semiconductor, Japan Customer Focus Center 4-32-1 Nishi-Gotanda, Shinagawa-ku, Tokyo, Japan 141-0031 Phone: 81-3-5740-2700 Email: r14525@onsemi.com ON Semiconductor Website: http://onsemi.com For additional information, please contact your local Sales Representative.
http://onsemi.com
16
CS5361/D

▲Up To Search▲

Price & Availability of CS5361REV10

	To Download CS5361REV10 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .