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DAC7731
DAC 773 1
SBAS249 - DECEMBER 2001
16-Bit, Voltage Output, Serial Input DIGITAL-TO-ANALOG CONVERTER
FEATURES
q LOW POWER: 150mW MAXIMUM q +10V INTERNAL REFERENCE q UNIPOLAR OR BIPOLAR OPERATION q SETTLING TIME: 5s to 0.003% FSR q 16-BIT MONOTINICITY, -40C TO +85C q 10V, 5V, OR +10V CONFIGURABLE VOLTAGE OUTPUT q RESET TO ZERO OR MID-SCALE q DOUBLE-BUFFERED DATA INPUT q DAISY-CHAIN FEATURE FOR MULTIPLE DAC7731s ON A SINGLE BUS q SMALL SSOP-24 PACKAGE
DESCRIPTION
The DAC7731 is a 16-bit Digital-to-Analog Converter (DAC) which provides 16 bits of monotonic performance over the specified operating temperature range and offers a +10V internal reference. Designed for automatic test equipment and industrial process control applications, the DAC7731's output swing can be configured in a 10V, 5V, or +10V range. The flexibility of the output configuration allows the DAC7731 to provide both unipolar and bipolar operation by pin strapping. The DAC7731 includes a high-speed output amplifier with a maximum settling time of 5s to 0.003% FSR for a 20V full-scale change and only consumes 100mW (typical) of power. The DAC7731 features a standard 3-wire, SPI-compatible serial interface with double buffering to allow asynchronous updates of the analog output as well as a serial data output line for daisy-chaining multiple DAC7731's. A user programmable reset control forces the DAC output to either min-scale (0000H) or mid-scale (8000H), overriding both the input and DAC register values. The DAC7731 is available in a SSOP-24 package and three performance grades specified to operate from -40C to +85C.
APPLICATIONS
q PROCESS CONTROL q ATE PIN ELECTRONICS q CLOSED-LOOP SERVO CONTROL q MOTOR CONTROL q DATA ACQUISITION SYSTEMS
VDD VSS VCC REFADJ REFOUT REFIN
VREF ROFFSET Buffer
REFEN RSTSEL RST LDAC SCLK CS Control Logic
+10V Reference
RFB2
RFB1
SJ SDO SDI Enable Input Register DAC Register DAC VOUT
AGND
DGND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2001, Texas Instruments Incorporated
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ABSOLUTE MAXIMUM RATINGS(1)
VCC to VSS ........................................................................... -0.3V to +32V VCC to AGND ...................................................................... -0.3V to +16V VSS to AGND ...................................................................... -16V to +0.3V AGND to DGND ................................................................... -0.3V to 0.3V REFIN to AGND .............................................................. 0V to VCC - 1.4V VDD to DGND ........................................................................ -0.3V to +6V Digital Input Voltage to DGND ................................. -0.3V to VDD + 0.3V Digital Output Voltage to DGND .............................. -0.3V to VDD + 0.3V Operating Temperature Range ........................................ -40C to +85C Storage Temperature Range ......................................... -65C to +150C Junction Temperature (TJ Max) .................................................... +150C NOTE: (1) Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability.
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PRODUCT DAC7731E PACKAGE-LEAD SSOP-24 PACKAGE DESIGNATOR(1) DB SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING DAC7731E ORDERING NUMBER(2) DAC7731E DAC7731E/1K DAC7731EB DAC7731EB/1K DAC7731EC DAC7731EC/1K TRANSPORT MEDIA, QUANTITY Rails, 60 Tape and Reel,1000 Rails, 60 Tape and Reel, 1000 Rails, 60 Tape and Reel, 1000
"
DAC7731EB
"
SSOP-24
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DB
"
-40C to +85C
"
DAC7731EB
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DAC7731EC
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SSOP-24
"
DB
"
-40C to +85C
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DAC7731EC
"
"
"
"
"
NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. (2) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces of "DAC7731EC/1K" will get a single 1000-piece Tape and Reel.
ELECTRICAL CHARACTERISTICS
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = -15V, VDD = +5V, Internal refience enabled, unless otherwise noted. DAC7731E PARAMETER ACCURACY Linearity Error (INL) TA = 25C Differential Linearity Error (DNL) Monotonicity Offset Error Offset Error Drift Gain Error Gain Error Drift PSRR (VCC or VSS) ANALOG OUTPUT(1) Voltage Output(2) 14 2 With Internal REF With External REF With Internal REF At Full-Scale +11.4/-4.75 +11.4/-11.4 +11.4/-6.4 5 0.1 0.4 0.25 200 0.25 0.1 CONDITIONS MIN TYP MAX 6 5 4 15 0.15 7 10.04 9.975 10 10.025 7 MIN DAC7731EB TYP MAX 4 3 2 16 MIN DAC7731EC TYP MAX 3 2 1 UNITS
15 50 0 to 10 10 5
10
LSB LSB LSB Bits % of FSR ppm/C % of FSR % of FSR ppm/C ppm/V V V V mA pF mA
Output Current Output Impeadance Maximum Load Capacitance Short-Circuit Current Short-Circuit Duration
AGND 9.96
0.1 200 15 Indefinite 10 400 15
REFERENCE Reference Output REFOUT Impedance REFOUT Voltage Drift REFOUT Voltage Adjustment(3) REFIN Input Range(4) REFIN Input Current REFADJ Input Range Absolute Max Value that can be applied is VCC REFADJ Input Impedance VREF Output Current VREF Impedance
25 4.75 0
VCC - 1.4 10 10 50

V ppm/C mV V nA V k mA
-2 1
+2

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ELECTRICAL CHARACTERISTICS (Cont.)
All specifications at TA = TMIN to TMAX, VCC = +15V, VSS = -15V, VDD = +5V, Internal reference enabled, unless otherwise noted. DAC7731E PARAMETER DYNAMIC PERFORMANCE Settling Time to 0.003% CONDITIONS 20V Output Step RL = 5k, CL = 200pF, with external REFOUT to REFIN filter(5) at 10kHz |IH| < 10A |IL| < 10A IOH = -0.8mA IOL = 1.6mA 0.7 * VDD 0.3 * VDD 3.6 0.4 +4.75 +11.4 -15.75 -15.75 +5.0 +5.25 +15.75 -11.4 -4.75 6 150 +85 MIN TYP 3 MAX 5 MIN DAC7731EB TYP MAX MIN DAC7731EC TYP MAX UNITS s
Digital Feedthrough Output Noise Voltage DIGITAL INPUT VIH VIL DIGITAL OUTPUT VOH VOL POWER SUPPLY VDD VCC VSS IDD ICC ISS Power TEMPERATURE RANGE Specified Performance
2 100

nV-s nV/Hz V V V V V V V V A mA mA mW mW C

Bipolar Operation Unipolar Opeation Unloaded Unloaded No Load, Ext. Reference No Load, Int. Reference
-4
100 4 -2.5 85 100

-40
Specifications same as grade to the left. NOTES: (1) With minimum VCC/VSS requirements, internal reference enabled. (2) Please refer to the "Theory of Operation" section for more information with respect to output voltage configurations. (3) See Figure 11 for gain and offset adjustment connection diagrams when using the internal reference. (4) The minimum value for REF IN must be equal to the greater of VSS +14V and +4.75V, where +4.75V is the minimum voltage allowed. (5) Reference low-pass filter values: 100k, 1.0F (see Figure 14).
PIN CONFIGURATION
Top View SSOP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 NAME VCC REFOUT REFIN REFADJ VREF DESCRIPTION Positive Analog Power Supply Internal Reference Output Reference Input Internal Reference Trim. (Acts as a gain adjustment input when the internal reference is used.) Buffered Output from REFIN, can be used to drive external devices. Internally, this pin directly drives the DAC's circuitry. Offsetting Resistor Analog ground Feedback Resistor 2, used to configure DAC output range. Feedback Resistor 1, used to configure DAC output range. Summing Junction of the Output Amplifier DAC Voltage Output Digital Power Supply Digital Ground Reserved, Connect to DGND No Connection VOUT reset; active LOW, depending on the state of RSTSEL, the DAC register is either reset to midscale or min-scale. DAC register load control, rising dege triggered. Data is loaded from the input register to the DAC register. Serial Data Input. Data is latched into the input register on the rising edge of SCLK. Serial Data Output, delayed 16 SCLK clock cycles. Chip Select, Active LOW Serial Clock Input Reset Select; determines the action of RST. If HIGH, RST will reset the DAC register to mid-scale. If LOW, RST will reset the DAC register to min-scale. Enables internal +10V reference (REFOUT), active LOW. Negative Analog Power Supply
VCC REFOUT REFIN REFADJ VREF ROFFSET AGND RFB2 RFB1 SJ VOUT VDD
1 2 3 4 5 6 DAC7731 7 8 9 10 11 12
24 VSS 23 REFEN 22 RSTSEL 21 SCLK 20 CS 19 SDO 18 SDI 17 LDAC 16 RST 15 NC 14 TEST 13 DGND
6 7 8 9 10 11 12 13 14 15 16
ROFFSET AGND RFB2 RFB1 SJ VOUT VDD DGND TEST NC RST
17 18 19 20 21 22
LDAC SDI SDO CS SCLK RSTSEL
23 NOTE: (1) RST, LDAC, SDI, CS and SCK are Schmitt-triggered inputs. 24
REFEN VSS
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TIMING CHARACTERISTICS
VCC = +15V, VSS = -15V, VDD = 5V; RL = 2k to AGND; CL = 200pF to AGND; all specifications -40C to +85C, unless otherwise noted. DAC7731 PARAMETER tWH tWL tSDI tHDI tSCS tHSC tDDO tHDO tDDOZ tWCSH tWLDL tWLDH tSLD tDLD tSCLK tSRS tHRS tWRL tS DESCRIPTION SCLK HIGH Time SCLK LOW Time Setup Time: Data in valid before rising SCLK Hold Time: Data in valid after rising SCLK Setup Time: CS falling edge before first rising SCLK Hold Time: CS rising edge after 16th rising SCLK Delay Time: CS Falling Edge to Data Out valid, CL = 20pF on SDO Hold Time: Data Out valid after SCLK rising edge, CL 20pF on SDO Delay Time: CS rising edge to SDO = High Impedance CS HIGH Time LDAC LOW Time LDAC HIGH Time Setup Time: 16th Rising SCLK Before LDAC Rising Edge Delay Time: LDAC rising edge to first SCLK rising edge of next transfer cycle. Setup Time: CS High before falling SCLK edge following 16th rising SCLK edge Setup Time: RSTSEL Valid Before RST LOW Hold Time: RSTSEL valid after RST HIGH RST LOW Time DAC VOUT Settling Time MIN 25 25 5 20 15 0 50 50 70 50 20 20 15 15 5 0 20 30 5 TYP MAX UNITS ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s
INTERFACE TIMING
tSCS CS tWH SCLK tSDI SDI tDDO tHDO SDO A15 A14 A13 B15 1 2 tHDI B14 B13 tWL 16 tSCLK tHCS tWCSH
B0
C15
C14
C13
C12
Word B tDDOZ A0 tDLD Word A tWLDL tWLDH tSLD tS B15
Word C B14 B13 B12
Word B
LDAC
VOUT 0.003% of FSR Error Bands
RESET TIMING
tSRS RSTSEL tHRS RST +FS VOUT (RSTSEL = LOW) -FS +FS VOUT (RSTSEL = HIGH) -FS Mid-Scale tWRL tS Min-Scale
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TYPICAL CHARACTERISTICS
TA = +25C (unless otherwise noted).
6 4 2 0 -2 -4 -6
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE 6 4 2 0 -2 -4 -6
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
INL (LSB)
Bipolar Configuration: VOUT = -10V to +10V TA = 85C, Internal Reference Enabled
INL (LSB)
Bipolar Configuration: VOUT = -10V to +10V TA = 25C, Internal Reference Enabled
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
DNL (LSB)
Error (mV)
6 4 2 0 -2 -4 -6
LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs DIGITAL INPUT CODE
DNL (LSB)
1.00 0.75 0.50
OFFSET ERROR vs TEMPERATURE
INL (LSB)
VOUT = -10 to +10V VOUT = 0 to +10V
Bipolar Configuration: VOUT = -10V to +10V TA = -40C, Internal Reference Enabled
0.25 0.00 -0.25 -0.50 -0.75 -1.00 -40
2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
DNL (LSB)
-15
10
35
60
85
Temperature (C)
0.000 -0.010 -0.020 -0.030
GAIN ERROR vs TEMPERATURE
4.4 4.3 4.2
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE Bipolar Configuration: VOUT = -10V to +10V Internal Reference Enabled, TA = 25C
Ext. Ref, Unipolar Mode: VOUT = 0 to +10V
Ext. Ref, Bipolar Mode: VOUT = -10 to +10V
ICC (mA)
Error (%)
-0.040 -0.050 -0.060 -0.070 -0.080 -0.090 -0.100 -40 -15
Int. Ref, Unipolar Mode: VOUT = 0 to +10V
4.1 4.0 3.9
Int. Ref, Bipolar Mode: VOUT = -10 to +10V Load = 200pF, 2k 10 35 60 85
3.8 3.7 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
Temperature (C)
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
3.4 3.3 3.2
VCC SUPPLY CURRENT vs DIGITAL INPUT CODE Bipolar Configuration: VOUT = -10V to +10V External Reference, REFEN = 5V, TA = 25C
-1.50
VSS SUPPLY CURRENT vs DIGITAL INPUT CODE
-1.75
ICC (mA)
3.0 2.9
ISS (mA)
3.1
-2.00
-2.25
-2.50
2.8 2.7 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
Bipolar Configuration: VOUT = -10V to +10V TA = 25C -2.75 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code
7 6 5 4
SUPPLY CURRENT vs TEMPERATURE Load Current Excluded VCC = +15V, VSS = -15V Bipolar VOUT Configuration: -10V to +10V
1800 1600 1400 1200
IDD (A)
SUPPLY CURRENT vs LOGIC INPUT VOLTAGE TA = 25C, Transition Shown for a Single Input (Applies to CS, SCLK,DIN and LDAC inputs)
ICC, ISS (mA)
3 2 1 0 -1 -2 -3 -40
ICC
1000 800 600 400
ISS
200 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
-15
10
35
60
85
Temperature (C)
VLOGIC (V)
100 90 80 70
Frequency
HISTOGRAM OF VCC CURRENT CONSUMPTION Bipolar Output Configuration Internal Reference Enabled Code = 5555H
Frequency
100 90 80 70 60 50 40 30 20 10 0 -3.50
HISTOGRAM OF VSS CURRENT CONSUMPTION Bipolar Output Configuration Internal Reference Enabled Code = 5555H
60 50 40 30 20 10 0 3.000 3.500 4.000 ICC (mA) 4.500 5.000
-3.00
-2.50 ISS (mA)
-2.00
-1.50
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
10 0 -10 -20
PSRR (dB)
POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at VOUT) Bipolar Configuration: 10V VOUT Code 8000H -VSS, VCC = 15V + 1Vp-p VDD = 5V + 0.5Vp-p
10 0 -10 -20
PSRR (dB)
POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at VOUT) Bipolar Configuration: 10V VOUT, Code FFFFH -VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p
VSS VCC
-30 -40 -50 -60 -70 -80 0.1K VDD 1K 10K 100K 1M 10M VSS VCC
-30 -40 -50 -60 -70 -80 0.01K 0.1K
VDD
1K
Frequency (Hz)
10K 100K Frequency (Hz)
1M
10M
INTERNAL REFERENCE START-UP
10.015 10.010 10.005
INTERNAL REFERENCE OUTPUT vs TEMPERATURE
VCC (5V/div)
15V 0V
REFOUT (V)
10.000 9.995 9.990
REFOUT (2V/div)
10V
0V Time (2ms/div)
9.985 -40
-15
10
35
60
85
Temperature (C)
11.0
REFOUT VOLTAGE vs LOAD Loaded to VCC VCC = +15V
12 8 4
OUTPUT VOLTAGE vs RLOAD Source
10.5
REFOUT (V)
10.0
VOUT (V)
0 -4
9.5
9.0 Loaded to AGND 8.5 1 10 100 REFOUT LOAD(k) 1K
Sink -8 -12 0.0 0.1 1.0 RLOAD (k) 10.0 100.0
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
10 0 -10 -20
POWER-SUPPY REJECTION RATIO vs FREQUENCY (Measured at REFOUT) Internal Reference Enabled -VSS, VCC = 15V + 1Vp-p, VDD = 5V + 0.5Vp-p
Output Noise (nV/Hz)
900 800 700 600 500 400 300 200 100
OUTPUT NOISE vs FREQUENCY Unipolar Configuration, Internal Reference Enabled
PSRR (dB)
VCC
-30 -40 -50 -60 -70 -80 1 10 100 1K 10K Frequency (Hz) 100K 1M 10M VSS VDD
Code FFFFH
Code 0000H
0 0.01K
0.1K
1K
10K 100K Frequency (Hz)
1M
10M
800 700
OUTPUT NOISE vs FREQUENCY Bipolar Configuration: 10V, Internal Reference Enabled
BROADBAND NOISE
Output Noise (nV/rtHz)
500 400 Code 0000H 300 200 100 0 0.01K Code 8000H Code FFFFH
VOUT (V, 50V/div)
1M 10M
600
Internal Reference Enabled Filtered with 1.6Hz Low-Pass Code FFFFH, Bipolar 10V Configuration 10kHz Measurement BW Time (100s/div)
0.1K
1K
10K 100K Frequency (Hz)
UNIPOLAR FULL-SCALE SETTLING TIME
BIPOLAR FULL-SCALE SETTLING TIME
Large-Signal Output (5V/div)
Large-Signal Output (5V/div)
Small-Signal Error (150V/div)
Small-Signal Error (300V/div)
Unipolar Configuration: VOUT = 0 to +10V Zero-Scale to +Full-Scale Change 5k, 200pF Load Time (2s/div)
Bipolar Configuration: VOUT = -10 to +10V -Full-Scale to +Full-Scale 5k, 200pF Load Time (2s/div)
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TYPICAL CHARACTERISTICS (Cont.)
TA = +25C (unless otherwise noted).
UNIPOLAR FULL-SCALE SETTLING TIME
BIPOLAR FULL-SCALE SETTLING TIME
Small-Signal Error (150V/div) Small-Signal Error (300V/div) Large-Signal Output (5V/div) Large-Signal Output (5V/div) Unipolar Configuration: VOUT = 0V to +10V +Full-Scale to Zero-Scale Change 5k, 200pF Load Time (2s/div) Bipolar Configuration: VOUT = -10 to +10V +Full-Scale to -Full-Scale 5k, 200pF Load Time (2s/div)
MID-SCALE GLITCH Code 8000H to 7FFFH Bipolar Configuration: 10V VOUT
MID-SCALE GLITCH Code 7FFFH to 8000H Bipolar Configuration: 10V VOUT
VOUT (V, 100mV/div)
VOUT (V, 100mV/div)
Time (1s/div)
Time (1s/div)
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THEORY OF OPERATION
The DAC7731 is a voltage output, 16-bit DAC with a +10V built-in internal reference. The architecture is an R-2R ladder configuration with the three MSB's segmented, followed by an operational amplifier that serves as a buffer, as shown in Figure 1. The output buffer is designed to allow userconfigurable output adjustments giving the DAC7731 output voltage ranges of 0V to +10V, -5V to +5V, or -10V to +10V. Please refer to Figures 2, 3, and 4 for pin configuration information.
The digital input is a serial word made up of the DAC code (MSB first) and is loaded into the DAC register using the LDAC input pin. The converter can be powered from 12V to 15V dual analog supplies and a +5V logic supply. The device offers a reset function, which immediately sets the DAC output voltage and DAC register to min-scale (code 0000H) or mid-scale (code 8000H). The data I/O and reset functions are discussed in more detail in the following sections.
REFADJ
REFOUT
REFIN
VREF R/4
ROFFSET RFB2
Buffer +10V Internal Reference R R/2 R/2
RFB1 R/4 SJ
VOUT 2R 2R 2R 2R 2R 2R 2R 2R 2R R/4
VREF AGND
FIGURE 1. DAC7731 Architecture.
VCC DAC7731 0.1F 1F 1 2 3 4 5 6 7 8 9 VCC REFOUT REFIN REFADJ VREF ROFFSET AGND RFB2 RFB1 VSS REFEN RSTSEL SCLK CS SDO SDI LDAC RST NC TEST DGND 24 23 22 21 20 19 18 17 16 15 14 13 Control/Data Bus 1F 0.1F VSS
VCC DAC7731 0.1F 1F 1 2 3 4 5 6 7 8 9 VCC REFOUT REFIN REFADJ VREF ROFFSET AGND RFB2 RFB1 VSS REFEN RSTSEL SCLK CS SDO SDI LDAC RST NC TEST DGND 24 23 22 21 20 19 18 17 16 15 14 13 Control/Data Bus 1F 0.1F VSS
10 SJ (0V to +10V) VDD 11 VOUT 12 VDD
10 SJ (-5V to +5V) VDD 11 VOUT 12 VDD
0.1F
1F
0.1F
1F
FIGURE 2. Basic Operation: VOUT = 0V to +10V.
FIGURE 3. Basic Operation: VOUT = -5V to +5V.
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VCC DAC7731 0.1F 1F 1 2 3 4 5 6 7 8 9 VCC REFOUT REFIN REFADJ VREF ROFFSET AGND RFB2 RFB1 VSS REFEN RSTSEL SCLK CS SDO SDI LDAC RST NC TEST DGND 24 23 22 21 20 19 18 17 16 15 14 13 Control/Data Bus 1F 0.1F VSS
REFSEL 1 0
ACTION Internal Reference disabled; REFOUT = High Impedance Internal Reference enabled; REFOUT = +10V
TABLE I. REFEN Action.
DIGITAL INTERFACE
Table II shows the input data format for the DAC7731 and Table III illustrates the basic control logic of the device. The serial interface consists of a chip select input (CS), serial data clock input (SCLK), serial data input (SDI), serial data output (SDO), and load control input (LDAC). An asynchronous reset input (RST), which is active LOW, is provided to simplify startup conditions, periodic resets, or emergency resets to a known state, depending on the status of the reset select (RSTSEL) signal. Please refer to the "DAC Reset" section for additional information regarding the reset operation.
ANALOG OUTPUT DIGITAL INPUT Unipolar Configuration Unipolar Straight Binary Zero (0V) Zero + 1LSB : 1/2 Full-Scale 1/2 Full-Scale + 1LSB : Full-Scale (VREF - 1LSB) Bipolar Configuration Bipolar Offset Binary -Full-Scale (-VREF or -VREF/2) -Full-Scale + 1LSB : Bipolar Zero Bipolar Zero + 1LSB : +Full-Scale (+VREF - 1LSB or +VREF/2 - 1LSB)
10 SJ (-10V to +10V) VDD 11 VOUT 12 VDD
0.1F
1F
FIGURE 4. Basic Operation: VOUT = -10V to +10V.
ANALOG OUTPUTS
The output amplifier can swing to within 1.4V of the supply rails, specified over the -40C to +85C temperature range. This allows for a 10V DAC voltage output operation from 12V supplies with a typical 5% tolerance. When the DAC7731 is configured for a unipolar, 0V to 10V output, a negative voltage supply is required. This is due to internal biasing of the output stage. Please refer to the "Electrical Characteristics" table for more information. The minimum and maximum voltage output values are dependent upon the output configuration implemented and reference voltage applied to the DAC7731. Please note that VSS (the negative power supply) must be in the range of -4.75V to -15.75V for unipolar operation. The voltage on VSS sets several bias points within the converter and is required in all modes of operation. If VSS is not in one of these two configurations, the bias values may be in error and proper operation of the device is not ensured.
0x0000 0x0001 : 0x8000 0x8001 : 0xFFFF
TABLE II. DAC7731 Data Format.
CONTROL STATUS CS RST RSTSEL LDAC SCLK H L L X X X H H H H H L L X X X X X H L X X X X X X X X L X X X
COMMAND ACTION Shift Register is disabled on the serial bus. Enable SDO pin from High Impedance; enables shift operation and I/O bus (SCLK, SDI, SDO). Serial Data Shifted into Input Register Serial Data Shifted into Input Register(1) Data in Input Register is Loaded into DAC Register. Resets Input and DAC Registers to mid-scale. Resets Input and DAC Registers to min-scale.
REFERENCE INPUTS
The DAC7731 provides a built-in +10V voltage reference and on-chip buffer to allow external component reference drive. To use the internal reference, REFEN must be LOW, enabling the reference circuitry of the DAC7731 (as shown in Table I) and the REFOUT pin must be connected to REFIN. This is the input to the on-chip reference buffer. The buffer's output is provided at the VREF pin. In this configuration, VREF is used to setup the DAC7731 output amplifier into one of three voltage output modes as discussed earlier. VREF can also be used to drive other system components requiring an external reference. The internal reference of the DAC7731 can be disabled when use of an external reference is desired. When using an external reference, the reference input, REFIN, can be any voltage between 4.75V (or VSS + 14V, whichever is greater) and VCC - 1.4V.
NOTE: (1) In order to avoid unwanted shifting of the input register by an additional bit, care must be taken that a rising edge on CS only occurs when SCLK is HIGH.
TABLE III. DAC7731 Logic Truth Table. The DAC code is provided via a 16-bit serial interface, as shown in Table II. The digital input word makes up the digital code to be loaded into the data input register of the device. A typical data transfer and DAC output update takes place as follows: Once CS is active (LOW), the DAC7731 is enabled on the serial bus and the 16-bit serial data transfer can begin. The serial data is shifted into the device on each rising SCLK edge until all 16 bits are transferred (1 bit per 1 rising SCLK edge). Once received, the data in the input register is loaded into the DAC register upon reception of a rising edge on the LDAC input (load command). This action updates the analog output, VOUT, to the desired voltage specified by the digital input word. A rising edge
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on LDAC is completely asynchronous to the serial interface of the device and can occur at any time. Care must be taken to ensure that the entire 16 bits of data are loaded into the input register before issuing a LDAC active edge. Additional load commands will have no effect on the DAC output if the data in the input register is unchanged between rising LDAC edges. When CS is returned HIGH, the rising edge on CS must occur when SCLK is HIGH. Application of a rising CS edge when SCLK is LOW will cause one additional shift in the serial input shift register, corrupting the desired input data.
Byte transfer mode is especially useful when an 8-bit host is communicating with the DAC. Data transfer can occur without requiring an additional general purpose I/O pin to control the CS input of the DAC in cycles of 16 clocks. A HIGH state on CS stops data from coming into and out of the internal shift register. This provides byte-wide support for 8-bit host processors. Figure 5 is an example of the timing cycle of such a data transfer. The remaining data transfer mode accepted by the DAC7731 is continuous transfer. The CS of the DAC7731 can be tied LOW or held LOW by the controller for an indefinite number of serial clock cycles. Each clock cycle will transfer data into the DAC via SDI and out of the DAC on SDO. Care must be taken that the LDAC signal to the DAC(s) is timed correctly so that valid data is transferred into the DAC register on each rising LDAC edge. ("Valid data" refers to the serial data latched on each of the 16 rising SCLK edges prior to the occurrence of a rising LDAC signal.) The rising edge of LDAC must occur before the first rising SCLK edge of the following 16-bit transfer. Figure 6 shows continuous transfer timing.
TIMING CONSIDERATIONS
The flexible interface of the DAC7731 can operate under a number of different scenarios as is required by a host controller. Critical timing for a 16-bit data transfer cycle is shown in the Interface Timing section of the Timing Characteristics. While this is the most common method of writing to the DAC7731, the device accepts two additional modes of data transfer from the host. These are byte transfer mode and continuous transfer mode.
16-Bit Data Word CS Most Significant Byte Least Significant Byte
SCLK
1
2
8
9
10
16
SDI
B15
B14
B13
B8
B7
B6
B0
Byte 1, Word N SDO A15 A14 A13 Byte 1, Word N - 1 LDAC A8 A7
Byte 2, Word N A6 Byte 2, Word N - 1 A0
FIGURE 5. Byte-Wide Data Write Cycle.
CS
SCLK
1
2
16
1
2
16
1
2
SDI
B15
B14
B1
B0
C15
C14
C1
C0
D15
D14
Word N SDO A15 A14 A1 A0 B15 B14
Word N + 1 B1 B0 C15
Word N + 2 C14
Word N - 1 LDAC
Word N
Word N + 1
FIGURE 6. Continuous Transfer Control.
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DAISY-CHAINING USING SDO
Multiple DAC7731's can be connected to a single serial port by attaching each of their control inputs in parallel and daisychaining the SDO and SDI I/O's of each device. The SDO output of the DAC7731 is active when CS is LOW and can be left unconnected when not required for use in a daisychain configuration. Once a data transfer cycle begins, new data is shifted into SDI and data currently residing in the shift register (from previous cycle, power-up, or reset command) is presented on SDO, MSB first. One data transfer cycle for each DAC7731 is required to update all devices in the chain. The first data cycle written into the chain will arrive at the last DAC7731 on the final cycle of the data transfer. Upon completion of the required number of data transfer cycles (one cycle per device), each DAC voltage output is updated with a rising edge on the LDAC inputs. Figure 8 shows the required timing to properly update two
DAC7731's in a daisy-chained configuration, as shown in Figure 7.
DAC RESET
The RST and RSTSEL inputs control the reset of the analog output. The reset command is level triggered by a low signal on RST. Once RST is LOW, the DAC output will begin settling to the mid-scale or min-scale code depending on the state of the RSTSEL input. A HIGH value on RSTSEL will cause VOUT to reset to the mid-scale code (8000H) and a LOW value will reset VOUT to min-scale (8000H). A change in the state of the RSTSEL input while RST is LOW will cause a corresponding change in the reset command selected internally and consequently change the output value of VOUT of the DAC. Note that a valid reset signal also resets the input register of the DAC to the value specified by the state of RSTSEL.
From Host Controller To next DAC7731
DAC7731 1 2 3 4 5 6 7 8 9 VCC REFOUT REFIN REFADJ VREF ROFFSET AGND RFB2 RFB1 VSS REFEN RSTSEL SCLK CS SDO SDI LDAC RST NC TEST DGND 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 VCC REFOUT REFIN REFADJ VREF ROFFSET AGND RFB2 RFB1
DAC7731 VSS REFEN RSTSEL SCLK CS SDO SDI LDAC RST NC TEST DGND 24 23 22 21 20 19 18 17 16 15 14 13
10 SJ 11 VOUT 12 VDD
10 SJ 11 VOUT 12 VDD
First Device in Chain
Second Device in Chain
FIGURE 7. DAC7731 Daisy-Chain Schematic.
Both DAC VOUT's are updated LSBs latched SCLK 1 2 16 1 2 LSBs latched 16
CS LDAC First Data Transfer Cycle SDI A15 A14 A0 B15 B14 B1 B0
Previous cycle word from host (to DAC7731 B SDI) SDO X X X A15 A14 A1 A0
FIGURE 8. DAC7731 Daisy-Chain Timing for Figure 7.
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APPLICATIONS
GAIN AND OFFSET CALIBRATION
The architecture of the DAC7731 is designed in such a way as to allow for easily configurable offset and gain calibration using a minimum of external components. The DAC7731 has built-in feedback resistors and output amplifier summing points brought out of the package in order to make the absolute calibration possible. Figures 9 and 10 illustrate the relationship of offset and gain adjustments for the DAC7731 in a unipolar configuration and in a bipolar configuration, respectively.
should be at +10V - 1LSB for the 0V to +10V or 10V output range and +5V - 1LSB for the 5V output range. Figure 11 shows the generalized external offset and gain adjustment circuitry using potentiometers.
DAC7731
REFADJ ROFFSET AGND
RFB2
RFB1 9
Optional Gain Adjust
VREF
4
5
6
7
(+VREF) + Full Scale 1LSB
Full Scale Range Analog Output
Optional Offset Adjust Gain Adjust Rotates the Line (Other Connections Omitted for Clarity) R1 RS RPOT2 + VOADJ -
8
RPOT1
10 SJ
ISJ
Input = 0000 H
Input = FFFF H
Zero Scale (AGND)
FIGURE 11. Generalized External Calibration Circuitry for Gain and Symmetrical Offset Adjustment. OFFSET ADJUSTMENT Offset adjustment is accomplished by introducing a small current into the summing junction (SJ) of the DAC7731. The voltage at SJ, or VSJ, is dependent on the output configuration of the DAC7731. See Table IV for the required pin strapping for a given configuration and the nominal values of VSJ for each output range.
REFERENCE OUTPUT PIN STRAPPING CONFIGURATION CONFIGURATION ROFFSET RFB1 RFB2 VSJ(1)
Digital Input
Offset Adjust Translates the Line
FIGURE 9. Relationship of Offset and Gain Adjustments for VOUT = 0V to +10V Output Configuration.
(+VREF or +VREF/2) + Full Scale 1LSB Input = 0000H
Analog Output
Gain Adjust Rotates the Line
Full Scale Range
Internal Reference Offset Adjust Translates the Line External Reference
0V to +10V -10V to +10V -5V to +5V
+5V to VREF to VOUT to VOUT NC NC to VOUT +3.333V to AGND to VOUT to VOUT +1.666V VREF/2 VREF/3 VREF/6
to VREF to VOUT to VOUT 0V to VREF -VREF to VREF NC NC to VOUT -VREF/2 to VREF/2 to AGND to VOUT to VOUT
Input = 8000H
Input = FFFF H
NOTE: (1) Voltage measured at VSJ for a given configuration.
TABLE IV. Nominal VSJ versus VOUT and Reference Configuration. The current level required to adjust the DAC7731's offset can be created by using a potentiometer divider as shown in Figure 11 Another alternative is to use a unipolar DAC in order to apply a voltage, VOADJ, to the resistor RS. A 2uA current range applied to SJ will ensure offset adjustment coverage of the 0.1% maximum offset specification of the DAC7731. When in a unipolar configuration (VSJ = 5V), only a single resistor, RS, is needed for symmetrical offset adjustment with a 0V to 10V VOADJ range. When in one of the two bipolar configurations, VSJ is either +3.333V (10V range) or +1.666V (5V range), and circuit values chosen to match those given in Table V will provide symmetrical offset adjust. Please refer to Figure 11 for component configuration.
- Full-Scale (-VREF OR -VREF/2) Digital Input
FIGURE 10. Relationship of Offset and Gain Adjustments for VOUT = -10V to +10V Output Configuration. (Same Theory Applies for VOUT = -5V to +5V.) When calibrating the DAC's output, offset should be adjusted first to avoid first order interaction of adjustments. In unipolar mode, the DAC7731's offset is adjusted from code 0000H and for either bipolar mode, offset adjustments are made at code 8000H. Gain adjustment can then be made at code FFFFH for each configuration, where the output of the DAC
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OUTPUT RPOT2 CONFIGURATION 0V to +10V -10V to +10V -5V to +5V 10K 10K 10K
R1
RS
ISJ RANGE 2A 2.2A 1.7A
NOMINAL OFFSET ADJUSTMENT 25mV 55mV 21mV
REFOUT Adjustment (mV)
0 5K 20K
2.5M 1.5M 1M
40 30 20 10 0 -10 -20 -30 -40 0 2
REFOUT ADJUST RANGE Typical REFOUT Adjustment Range
TABLE V. Recommended External Component Values for Symmetrical Offset Adjustment (VREF = 10V).
Minimum REFOUT Adjustment Range
Figure 12 illustrates the typical minimum offset adjustment ranges provided by forcing a current at SJ for a given output voltage configuration.
4
6
8
10
REFADJ (V)
50 Offset Adjustment at VOUT (mV) OFFSET ADJUST RANGE typ -10V to +10V VOUT Configuration 25 typ 0 min (75% of typ) -25 0V to 10V and -5V to +5V VOUT Configuration min (75% of typ)
FIGURE 13. Internal Reference Adjustment Transfer Characteristic.
VOLTAGE AT REFADJ REFADJ = 0V REFADJ = 5V or NC(1) REFADJ = 10V NOTE: "NC" is "Not Connected"
REFOUT VOLTAGE 10V + 25mV (min) 10V 10V - 25mV (max)
TABLE VI. Minimum Internal Reference Adjustment Range.
-50 -2 -1 0 ISJ (A) 1 2
NOISE PERFORMANCE
Increased noise performance of the DAC output can be achieved by filtering the voltage reference input to the DAC7731. Figure 14 shows a typical internal reference filter schematic. A low-pass filter applied between the REFOUT and REFIN pins can increase noise immunity at the DAC and output amplifier. The REFOUT pin can source a maximum of 50A so care should be taken in order to avoid overloading the internal reference output.
FIGURE 12. Offset Adjustment Transfer Characteristic.
GAIN ADJUSTMENT
When using the internal reference of the DAC7731, gain adjustment is performed by adjusting the device's internal reference voltage via the reference adjust pin, REFADJ. The effect of a reference voltage change on the gain of the DAC output can be seen in the generic equation (for unipolar configuration): VOUT = VREFIN * (N/65536) Where N is represented in decimal format and ranges from 0 to 65535. REFADJ can be driven by a low impedance voltage source such as a unipolar, 0V to +10V DAC or a potentiometer (less than 100k), see Figure 11. Since the input impedance of REFADJ is typically 50k, the smaller the resistance of the potentiometer, the more linear the adjustment will be. A 10k potentiometer is suggested if linearity of the reference adjustment is of concern. When the DAC7731's internal reference is not used, gain adjustments can be made via trimming the external reference applied to the DAC at REFIN. This can be accomplished through using a potentiometer, unipolar DAC, or other means of precision voltage adjustment to control the voltage presented to the DAC7731 by the external reference. Figure 13 and Table VI summarize the range of adjustment of the internal reference via REFADJ.
DAC7731 Low-Pass Reference Filter 1.0F 100k 1 2 3 4 5 6 7 8 9 VCC REFOUT REFIN REFADJ VREF ROFFSET AGND RFB2 RFB1 VSS REFEN RSTSEL SCLK CS SDO SDI LDAC RST NC TEST DGND 24 23 22 21 20 19 18 17 16 15 14 13
10 SJ 11 VOUT 12 VDD
(Other connections omitted for clarity.)
FIGURE 14. Filtering the Internal Reference.
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LAYOUT
A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. The DAC7731 offers separate digital and analog supplies, as it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more important it will become to separate the analog and digital ground and supply planes at the device. Since the DAC7731 has both analog and digital ground pins, return currents can be better controlled and have less effect on the DAC output error. Ideally, AGND would be connected directly to an analog ground plane and DGND to the digital ground plane. The analog ground plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system.
The voltages applied to VCC and VSS should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. In addition, a 1F to 10F bypass capacitor in parallel with a 0.1F bypass capacitor is strongly recommended for each supply input. In some situations, additional bypassing may be required, such as a 100F electrolytic capacitor or even a "Pi" filter made up of inductors and capacitors-all designed to essentially low-pass filter the analog supplies, removing any high frequency noise components.
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PACKAGE DRAWING
DB (R-PDSO-G**)
28 PINS SHOWN 0,65 28 0,38 0,22 15 0,15 M
MSSO002D - JANUARY 1995 - REVISED SEPTEMBER 2000
PLASTIC SMALL-OUTLINE
0,15 NOM 5,60 5,00 8,20 7,40
Gage Plane 1 A 14 0- 8 0,25 0,95 0,55
Seating Plane 2,00 MAX 0,05 MIN 0,10
PINS ** DIM A MAX
14
16
20
24
28
30
38
6,50
6,50
7,50
8,50
10,50
10,50
12,90
A MIN
5,90
5,90
6,90
7,90
9,90
9,90
12,30 4040065 /D 09/00
NOTES: A. B. C. D.
All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0,15. Falls within JEDEC MO-150
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Copyright 2001, Texas Instruments Incorporated

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