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DAC908
DAC 908
DAC9 08
SBAS109B - JUNE 2003
8-Bit, 165MSPS DIGITAL-TO-ANALOG CONVERTER
TM
FEATURES
q SINGLE +5V OR +3V OPERATION q HIGH SFDR: 5.04MHz Output at 100MSPS: 67dBc q LOW GLITCH: 3pV-s q LOW POWER: 170mW at +5V q INTERNAL REFERENCE: Optional Ext. Reference Adjustable Full-Scale Range Multiplying Option
APPLICATIONS
q MEDICAL INSTRUMENTATION Ultrasound (DBF) q VIDEO, DIGITAL TV q WAVEFORM GENERATION Direct Digital Synthesis (DDS) Arbitrary Waveform Generation (ARB) q TEST INSTRUMENTATION q COMMUNICATIONS
For noncontinuous operation of the DAC908, a power-down mode results in only 45mW of standby power. The DAC908 comes with an integrated 1.24V bandgap reference and edge-triggered input latches, offering a complete converter solution. Both +3V and +5V CMOS logic families can be interfaced to the DAC908. The reference structure of the DAC908 allows for additional flexibility by utilizing the on-chip reference, or applying an external reference. The full-scale output current can be adjusted over a span of 2mA to 20mA, with one external resistor, while maintaining the specified dynamic performance. The DAC908 is available in the SO-28 and TSSOP-28 packages.
+VA DAC908 LSB Switches Segmented Switches IOUT IOUT BYP BW +VD
DESCRIPTION
The DAC908 is a high-speed, Digital-to-Analog Converter (DAC) offering an 8-bit resolution option within the SpeedPlus family of high-performance converters. Featuring pin compatibility among family members, the DAC900, DAC902, and DAC904 provide a component selection option to an 10-, 12-, and 14-bit resolution, respectively. All models within this family of DACs support update rates in excess of 165MSPS with excellent dynamic performance, and are especially suited to fulfill the demands of a variety of applications. The advanced segmentation architecture of the DAC908 is optimized to provide a high Spurious-Free Dynamic Range (SFDR) for single-tone, as well as for multi-tone signals--essential when used for the transmit signal path of communication systems. The DAC908 has a high impedance (200k) current output with a nominal range of 20mA and an output compliance of up to 1.25V. The differential outputs allow for both a differential or singleended analog signal interface. The close matching of the current outputs ensures superior dynamic performance in the differential configuration, which can be implemented with a transformer. Utilizing a small geometry CMOS process, the monolithic DAC908 can be operated on a wide, single-supply range of +2.7V to +5.5V. Its low power consumption allows for use in portable and batteryoperated systems. Further optimization can be realized by lowering the output current with the adjustable full-scale option.
FSA REFIN
Current Sources
INT/EXT Latches +1.24V Ref. 8-Bit Data Input AGND CLK D7...D0 DGND PD
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright (c) 2002-2003, Texas Instruments Incorporated
www.ti.com
ABSOLUTE MAXIMUM RATINGS
+V A to AGND ........................................................................ -0.3V to +6V +V D to DGND ........................................................................ -0.3V to +6V AGND to DGND ................................................................. -0.3V to +0.3V +V A to +VD ............................................................................................................. -6V to +6V CLK, PD to DGND ..................................................... -0.3V to VD + 0.3V D0-D7 to DGND ......................................................... -0.3V to VD + 0.3V IOUT, IOUT to AGND ........................................................ -1V to VA + 0.3V BW, BYP to AGND ..................................................... -0.3V to VA + 0.3V REFIN, FSA to AGND ................................................. -0.3V to VA + 0.3V INT/EXT to AGND ...................................................... -0.3V to VA + 0.3V Junction Temperature .................................................................... +150C Case Temperature ......................................................................... +100C Storage Temperature .................................................................... +125C
ELECTROSTATIC DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE DRAWING NUMBER 217 SPECIFIED TEMPERATURE RANGE -40C to +85C PACKAGE MARKING DAC908U ORDERING NUMBER(1) DAC908U DAC908U/1K DAC908E DAC908E/2K5 TRANSPORT MEDIA Rails Tape and Reel Rails Tape and Reel
PRODUCT DAC908U
PACKAGE SO-28
"
DAC908E
"
TSSOP-28
"
360
"
-40C to +85C
"
DAC908E
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K5 indicates 2500 devices per reel). Ordering 2500 pieces of "DAC908E/2K5" will get a single 2500-piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT DAC908U DAC908E DEMO BOARD ORDERING NUMBER DEM-DAC90xU DEM-DAC908E COMMENT Populated evaluation board without DAC. Order sample of desired DAC90x model separately. Populated evaluation board including the DAC908E.
ELECTRICAL CHARACTERISTICS
At TA = full specified temperature range, +VA = +5V, +VD = +5V, differential transformer coupled output, 50y doubly terminated, unless otherwise specified. DAC908U/E PARAMETER RESOLUTION OUTPUT UPDATE RATE Output Update Rate (fCLOCK) Full Specified Temperature Range, Operating STATIC Differential Nonlinearity (DNL) Integral Nonlinearity (INL) DYNAMIC PERFORMANCE Spurious-Free Dynamic Range (SFDR) fOUT = 1.0MHz, fCLOCK = 25MSPS fOUT = 2.1MHz, fCLOCK = 50MSPS fOUT = 5.04MHz, fCLOCK = 50MSPS fOUT = 5.04MHz, fCLOCK = 100MSPS fOUT = 20.2MHz, fCLOCK = 100MSPS fOUT = 25.3MHz, fCLOCK = 125MSPS fOUT = 41.5MHz, fCLOCK = 125MSPS fOUT = 27.4MHz, fCLOCK = 165MSPS fOUT = 54.8MHz, fCLOCK = 165MSPS Spurious-Free Dynamic Range within a Window fOUT = 2.1MHz, fCLOCK = 50MSPS fOUT = 5.04MHz, fCLOCK = 100MSPS Total Harmonic Distortion (THD) fOUT = 2.1MHz, fCLOCK = 50MSPS fOUT = 5.04MHz, fCLOCK = 100MSPS fOUT = 20.2MHz, fCLOCK = 100MSPS ACCURACY(1) 2.7V to 3.3V 4.5V to 5.5V Ambient, TA TA = +25C fCLOCK = 25MSPS, fOUT = 1.0MHz TA = +25C To Nyquist 64 70 69 67 67 61 57 51 58 52 70 69 -72 -66 -60 dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc dBc 125 165 -40 -0.5 -0.5 CONDITIONS MIN TYP 8 165 200 +85 0.25 0.25 +0.5 +0.5 MAX UNITS Bits MSPS MSPS C LSB LSB
2MHz Span 4MHz Span
2
DAC908
SBAS109B
ELECTRICAL CHARACTERISTICS (Cont.)
At TA = +25C, +VA = +5V, +V D = +5V, differential transformer coupled output, 50 doubly terminated, unless otherwise specified. DAC908U/E PARAMETER DYNAMIC PERFORMANCE (Cont.) Output Settling Time(2) Output Rise Time(2) Output Fall Time(2) Glitch Impulse DC-ACCURACY Full-Scale Output Range(3) (FSR) Output Compliance Range Gain Error Gain Error Gain Drift Offset Error Offset Drift Power-Supply Rejection, +VA Power- Supply Rejection, +VD Output Noise Output Resistance Output Capacitance REFERENCE Reference Voltage Reference Tolerance Reference Voltage Drift Reference Output Current Reference Input Resistance Reference Input Compliance Range Reference Small-Signal Bandwidth(4) DIGITAL INPUTS Logic Coding Latch Command Logic High Voltage, VIH Logic Low Voltage, VIL Logic High Voltage, VIH Logic Low Voltage, VIL Logic High Current, IIH(5) Logic Low Current, IIL Input Capacitance POWER SUPPLY Supply Voltages +VA +VD Supply Current(6) IVA IVA, Power-Down Mode IVD Power Dissipation Power Dissipation, Power-Down Mode Thermal Resistance, JA SO-28 TSSOP-28 CONDITIONS MIN TYP MAX UNITS
to 0.1% 10% to 90% 10% to 90%
30 2 2 3 2.0 -1.0 -10 -10 -0.025 0.1 -0.2 -0.025 +0.2 +0.025 50 200 12 +1.24 5 50 10 1 0.1 1.3 Straight Binary Rising Edge of Clock 5 0 3 0 20 20 5 1.25 20.0 +1.25 +10 +10 +0.025
ns ns ns pV-s mA V %FSR %FSR ppmFSR/C %FSR ppmFSR/C %FSR/V %FSR/V pA/Hz k pF V % ppmFSR/C A M V MHz
All Bits High, IOUT With Internal Reference With External Reference With Internal Reference With Internal Reference With Internal Reference
1 2 120
IOUT = 20mA, RLOAD = 50 IOUT, IOUT to Ground
+VD +VD +VD +VD +VD +VD
= = = = = =
+5V +5V +3V +3V +5V +5V
3.5 2
1.2 0.8
V V V V A A pF
+2.7 +2.7
+5 +5 24 1.1 8 170 50 45 75 50
+5.5 +5.5 30 2 15 230
V V mA mA mA mW mW mW C/W C/W
+5V, IOUT = 20mA +3V, IOUT = 2mA
NOTES: (1) At output IOUT, while driving a virtual ground. (2) Measured single-ended into 50 Load. (3) Nominal full-scale output current is 32x IREF; see Application Section for details. (4) Reference bandwidth depends on size of external capacitor at the BW pin and signal level. (5) Typically 45A for the PD pin, which has an internal pull-down resistor. (6) Measured at fCLOCK = 50MSPS and f OUT = 1.0MHz.
DAC908
SBAS109B
3
PIN CONFIGURATION
Top View SO, TSSOP
PIN DESCRIPTIONS
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 DESIGNATOR Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 NC NC NC NC NC NC PD DESCRIPTION Data Bit 1 (D7), MSB Data Bit 2 (D6) Data Bit 3 (D5) Data Bit 4 (D4) Data Bit 5 (D3) Data Bit 6 (D2) Data Bit 7 (D1) Data Bit 8 (D0), LSB No Connection No Connection No Connection No Connection No Connection No Connection Power Down, Control Input; Active HIGH. Contains internal pull-down circuit; may be left unconnected if not used. Reference Select Pin; Internal (= 0) or External (= 1) Reference Operation. Reference Input/Ouput. See Applications section for further details. Full-Scale Output Adjust Bandwidth/Noise Reduction Pin: Bypass with 0.1F to +VA for Optimum Performance. Analog Ground Complementary DAC Current Output DAC Current Output Bypass Node: Use 0.1F to AGND Analog Supply Voltage, 2.7V to 5.5V No Connection Digital Ground Digital Supply Voltage, 2.7V to 5.5V Clock Input
(MSB) Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 (LSB) Bit 8 NC
(1)
1 2 3 4 5 6 7 DAC908 8 9
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CLK +VD DGND NC(1) +VA BYP IOUT IOUT
16
INT/EXT REF IN FSA BW
AGND BW FSA REFIN INT/EXT PD
20 21 22 23 24 25 26 27 28 AGND IOUT IOUT BYP +VA NC DGND +V D CLK 17 18 19
NC(1) 10 NC(1) 11 NC NC NC
(1) (1) (1)
12 13 14
NOTE: (1) NC pins should be left unconnected or grounded.
TYPICAL CONNECTION CIRCUIT
+5V 0.1F +VA DAC908 FSA REFIN RSET 0.1F Current Sources LSB Switches Segmented MSB Switches BW +VD IOUT IOUT BYP 0.1F 50 20pF 50 20pF 1:1 +5V
INT/EXT PD Latches +1.24V Ref. 8-Bit Data Input AGND CLK D7.......D0 DGND
4
DAC908
SBAS109B
TIMING DIAGRAM
t2 CLOCK t1
tS
Data changes
t
H
Data changes
Stable, Valid
D13 - D0
Data
t PD
t SET
Iout or Iout
SYMBOL t1 t2 tS tH tPD tSET
DESCRIPTION Clock Pulse HIGH Time Clock Pulse LOW Time Data Setup Time Data Hold Time Propagation Delay Time Output Settling Time to 0.1%
MIN
TYP 3 3 1.0 1.5 1 30
MAX
UNITS ns ns ns ns ns ns
DAC908
SBAS109B
5
TYPICAL CHARACTERISTICS: VD = VA = +5V
At TA = +25C, differential transformer coupled output, 50y doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
SFDR vs fOUT AT 25MSPS 85 80 75 -6dBFS 70 65 60 55 0 2.0 4.0 6.0 8.0 Frequency (MHz) 10.0 12.0 85 80 75 70 65 60
SFDR vs fOUT AT 50MSPS
SFDR (dBc)
SFDR (dBc)
-6dBFS
0dBFS
0dBFS 55 0 5.0 10.0 15.0 Frequency (MHz) 20.0 25.0
SFDR vs fOUT AT 100MSPS 85 80 75 85 80 75
SFDR vs fOUT AT 125MSPS
SFDR (dBc)
70 65 60 55 50 45 0 10.0 20.0 30.0 Frequency (MHz) 40.0 50.0 0dBFS -6dBFS
SFDR (dBc)
70 65 60 55 0dBFS 50 45 0 10.0 20.0 30.0 40.0 Frequency (MHz) 50.0 60.0 -6dBFS
SFDR vs fOUT AT 165MSPS 80 75 70
80 75 70
SFDR vs IOUTFS and fOUT AT 100MSPS 2.1MHz 5.04MHz 10.1MHz 20.2MHz
X X
SFDR (dBc)
SFDR (dBc)
65 60 55 0dBFS 50 45 40 0 10.0 20.0
-6dBFS
65 60 55 50 45 40
X
40.4MHz
X
30.0 40.0 50.0 Frequency (MHz)
60.0
70.0
80.0
2
5 IOUTFS (mA)
10
20
6
DAC908
SBAS109B
TYPICAL CHARACTERISTICS: VD = VA = +5V (Cont.)
At TA = +25C, differential transformer coupled output, 50y doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
THD vs fCLOCK AT fOUT = 2.1MHz -70 -75 2HD
SFDR (dBc)
85 80 75
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
-80
THD (dBc)
2.1MHz 70 65 60
X X X X
3HD -85
X X
5.04MHz
X X X
-90 -95 -100 0 25
X X
20.2MHz
55
4HD
50 45 -40
50 100 fCLOCK (MSPS)
125
150
-20
0
25 50 Temperature (C)
70
85
SINGLE-TONE OUTPUT SPECTRUM 10 0 -10 fCLOCK = 50MSPS fOUT = 2.1MHz SFDR = 69dBc Amplitude = 0dBFS 10 0 -10
SINGLE-TONE OUTPUT SPECTRUM
Magnitude (dBm)
-30 -40 -50 -60 -70 -80 -90 0 5 10
Magnitude (dBm)
-20
-20 -30 -40 -50 -60 -70 -80 -90
fCLOCK = 100MSPS fOUT = 5.04MHz SFDR = 67dBc Amplitude = 0dBFS
15
20
25
0
5
10
15
20
25
30
35
40
45
50
Frequency (MHz)
Frequency (MHz)
SINGLE-TONE OUTPUT SPECTRUM 10 0 -10 fCLOCK = 125MSPS fOUT = 25.3MHz SFDR = 57dBc Amplitude = 0dBFS
Magnitude (dBm)
-20 -30 -40 -50 -60 -70 -80 -90 0 12.5 25.0
37.5
50.0
62.5
Frequency (MHz)
DAC908
SBAS109B
7
TYPICAL CHARACTERISTICS: VD = VA = +3V
At TA = +25C, differential transformer coupled output, 50y doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
SFDR vs fOUT AT 25MSPS 85 80 75 -6dBFS 70 65 0dBFS 60 55 0 2.0 4.0 6.0 8.0 Frequency (MHz) 10.0 12.0 60 85 80 75 70 65
SFDR vs fOUT AT 50MSPS
SFDR (dBc)
SFDR (dBc)
0dBFS
-6dBFS 55 0 5.0 10.0 15.0 Frequency (MHz) 20.0 25.0
SFDR vs fOUT AT 100MSPS 85 80 75 -6dBFS 85 80 75
SFDR vs fOUT AT 125MSPS
SFDR (dBc)
70 65 60 55 0dBFS 50 45 0 10.0 20.0 30.0 Frequency (MHz) 40.0 50.0
SFDR (dBc)
70 65 -6dBFS 60 55 50 45 0 10.0 20.0 30.0 40.0 Frequency (MHz) 50.0 60.0 0dBFS
SFDR vs fOUT AT 165MSPS 80 75 70 -6dBFS
80 75 70
SFDR vs IOUTFS and fOUT AT 100MSPS, 0dBFS 2.1MHz 5.04MHz 10.1MHz 20.2MHz
SFDR (dBc)
65 60 55 0dBFS 50 45 40 0 10.0 20.0 30.0 40.0 50.0 Frequency (MHz) 60.0 70.0 80.0
SFDR (dBc)
65 60 55
X
50 45 40 2
X
X
40.4MHz
X
5 IOUTFS (mA)
10
20
8
DAC908
SBAS109B
TYPICAL CHARACTERISTICS: VD = VA = +3V (Cont.)
At TA = +25C, differential transformer coupled output, 50y doubly terminated, and SFDR up to Nyquist, unless otherwise noted.
THD vs fCLOCK AT fOUT = 2.1MHz -70 2HD -75 -80
THD (dBc)
85 80 75
SFDR vs TEMPERATURE AT 100MSPS, 0dBFS
2.1MHz 5.04MHz
X X X X X X X
SFDR (dBc)
70 65 60 55 50 45 -40
-85 -90 -95 -100 0 25
3HD
20.2MHz
4HD
50 100 fCLOCK (MSPS)
125
150
-20
0
25 50 Temperature (C)
70
85
DAC908
SBAS109B
9
APPLICATION INFORMATION
THEORY OF OPERATION The architecture of the DAC908 uses the current steering technique to enable fast switching and a high update rate. The core element within the monolithic DAC is an array of segmented current sources that are designed to deliver a fullscale output current of up to 20mA, as shown in Figure 1. An internal decoder addresses the differential current switches each time the DAC is updated and a corresponding output current is formed by steering all currents to either output summing node, IOUT or IOUT. The complementary outputs deliver a differential output signal that improves the dynamic performance through reduction of even-order harmonics, common-mode signals (noise), and double the peak-to-peak output signal swing by a factor of two, compared to singleended operation. The segmented architecture results in a significant reduction of the glitch energy, and improves the dynamic performance (SFDR) and DNL. The current outputs maintain a very high output impedance of greater than 200ky. The full-scale output current is determined by the ratio of the internal reference voltage (1.24V) and an external resistor, RSET. The resulting IREF is internally multiplied by a factor of 32 to produce an effective DAC output current that can range from 2mA to 20mA, depending on the value of RSET. The DAC908 is split into a digital and an analog portion, each of which is powered through its own supply pin. The digital section includes edge-triggered input latches and the decoder logic, while the analog section comprises the current source array with its associated switches and the reference circuitry.
+3V to +5V Digital
DAC TRANSFER FUNCTION The total output current, IOUTFS, of the DAC908 is the summation of the two complementary output currents: IOUTFS = IOUT + IOUT (1)
The individual output currents depend on the DAC code and can be expressed as: IOUT = IOUTFS * (Code/256) IOUT = IOUTFS * (255 - Code/256) (2) (3)
where `Code' is the decimal representation of the DAC data input word. Additionally, IOUTFS is a function of the reference current IREF, which is determined by the reference voltage and the external setting resistor, RSET. IOUTFS = 32 * IREF = 32 * VREF /RSET (4)
In most cases the complementary outputs will drive resistive loads or a terminated transformer. A signal voltage will develop at each output according to: VOUT = IOUT * RLOAD VOUT = IOUT * RLOAD (5) (6)
+3V to +5V Analog 0.1F
Bandwidth Control DAC908 Full-Scale Adjust Resistor +VA BW +VD IOUT FSA Ref Input REFIN 0.1F INT/EXT Ref Buffer Ref Control Amp PMOS Current Source Array LSB Switches Segmented MSB Switches BYP IOUT 1:1 VOUT
RSET 2k
400pF
50 0.1F
20pF
50
20pF
Latches and Switch Decoder Logic
PD Power Down (internal pull-down)
+1.24V Ref AGND Analog Ground CLK Clock Input 8-Bit Data Input D7...D0 DGND
Digital Ground
NOTE: Supply bypassing not shown.
FIGURE 1. Functional Block Diagram of the DAC908.
10
DAC908
SBAS109B
The value of the load resistance is limited by the output compliance specification of the DAC908. To maintain specified linearity performance, the voltage for IOUT and IOUT should not exceed the maximum allowable compliance range. The two single-ended output voltages can be combined to find the total differential output swing:
VOUTDIFF= VOUT - VOUT = (2 * Code- 255) * IOUTFS*RLOAD (7) 256
IOUT and IOUT. Furthermore, using the differential output configuration in combination with a transformer will be instrumental for achieving excellent distortion performance. Common-mode errors, such as even-order harmonics or noise, can be substantially reduced. This is particularly the case with high output frequencies and/or output amplitudes below full-scale. For those applications requiring the optimum distortion and noise performance, it is recommended to select a full-scale output of 20mA. A lower full-scale range down to 2mA may be considered for applications that require a low power consumption, but can tolerate a reduced performance level.
INPUT CODE (D7 - D0) 1111 1111 1000 0000 0000 0000 IOUT 20mA 10mA 0mA IOUT 0mA 10mA 20mA
ANALOG OUTPUTS The DAC908 provides two complementary current outputs, IOUT and IOUT. The simplified circuit of the analog output stage representing the differential topology is shown in Figure 2. The output impedance of 200k || 12pF for IOUT and IOUT results from the parallel combination of the differential switches, along with the current sources and associated parasitic capacitances.
TABLE I. Input Coding vs Analog Output Current. OUTPUT CONFIGURATIONS
+VA DAC908
The current output of the DAC908 allows for a variety of configurations, some of which are illustrated below. As mentioned previously, utilizing the converter's differential outputs will yield the best dynamic performance. Such a differential output circuit may consist of an RF transformer (see Figure 3) or a differential amplifier configuration (see Figure 4). The transformer configuration is ideal for most applications with ac coupling, while op amps will be suitable for a DC-coupled configuration. The single-ended configuration (see Figure 6) may be considered for applications requiring a unipolar output voltage. Connecting a resistor from either one of the outputs to ground will convert the output current into a ground-referenced voltage signal. To improve on the DC linearity an I-to-V converter can be used instead. This will result in a negative signal excursion and, therefore, requires a dual supply amplifier. DIFFERENTIAL WITH TRANSFORMER
IOUT RL
IOUT RL
FIGURE 2. Equivalent Analog Output. The signal voltage swing that may develop at the two outputs, IOUT and IOUT, is limited by a negative and positive compliance. The negative limit of -1V is given by the breakdown voltage of the CMOS process, and exceeding it will compromise the reliability of the DAC908, or even cause permanent damage. With the full-scale output set to 20mA, the positive compliance equals 1.25V, operating with +VD = 5V. Note that the compliance range decreases to about 1V for a selected output current of IOUTFS = 2mA. Care should be taken that the configuration of DAC908 does not exceed the compliance range to avoid degradation of the distortion performance and integral linearity. Best distortion performance is typically achieved with the maximum full-scale output signal limited to approximately 0.5V. This is the case for a 50 doubly-terminated load and a 20mA full-scale output current. A variety of loads can be adapted to the output of the DAC908 by selecting a suitable transformer while maintaining optimum voltage levels at
Using an RF transformer provides a convenient way of converting the differential output signal into a single-ended signal while achieving excellent dynamic performance (see Figure 3). The appropriate transformer should be carefully selected based on the output frequency spectrum and impedance requirements. The differential transformer configuration has the benefit of significantly reducing common-mode signals, thus improving the dynamic performance over a wide range of frequencies. Furthermore, by selecting a suitable impedance ratio (winding ratio), the transformer can be used to provide optimum impedance matching while controlling the compliance voltage for the converter outputs. The model shown in Figure 3 has a 1:1 ratio and may be used to interface the DAC908 to a 50 load. This results in a 25 load for each of the outputs, IOUT and IOUT. The output signals are ac coupled and inherently isolated because of the transformer's magnetic coupling.
DAC908
SBAS109B
11
As shown in Figure 3, the transformer's center tap must be connected to ground to enable the necessary DC-current flow for both outputs. Some applications may require a solid termination, in which case a differential resistor, RDIFF, may be inserted as shown. Note that this will reduce the available signal power by approximately one half.
of the resistors typically sets the limit for the achievable common-mode rejection. An improvement can be obtained by fine tuning resistor R4. This configuration typically delivers a lower level of ac performance than the previously discussed transformer solution because the amplifier introduces another source of distortion. Suitable amplifiers should be selected based on their slew-rate, harmonic distortion, and output swing capabilities. High-speed amplifiers like the OPA680 or OPA687 may be considered. The ac performance of this circuit may be improved by adding a small capacitor, CDIFF, between the outputs IOUT and IOUT, as shown in Figure 4. This will introduce a real pole to create a low-pass filter in order to slewlimit the DACs fast output signal steps, which otherwise could drive the amplifier into slew-limitations or into an overload condition; both would cause excessive distortion. The difference amplifier can easily be modified to add a level shift for applications requiring the single-ended output voltage to be unipolar, i.e., swing between 0V and +2V. DUAL TRANSIMPEDANCE OUTPUT CONFIGURATION The circuit example of Figure 5 shows the signal output currents connected into the summing junction of the OPA2680, which is set up as a transimpedance stage, or I-to-V converter. With this circuit, the DAC's output will be kept at a virtual ground, minimizing the effects of output impedance variations, and resulting in the best DC linearity (INL). However, as mentioned previously, the amplifier may be driven into slew-rate limitations, and produce unwanted distortion. This may occur especially at high DAC update rates.
IOUT DAC908 Optional RDIFF IOUT 50 50
ADT1-1WT (Mini-Circuits) 1:1
RL
FIGURE 3. Differential Output Configuration Using an RF Transformer. DIFFERENTIAL CONFIGURATION USING AN OP AMP If the application requires a DC-coupled output, a difference amplifier may be considered, as shown in Figure 4. Four external resistors are needed to configure the voltage-feedback op amp OPA680 as a difference amplifier performing the differential to single-ended conversion. Under the shown configuration, the DAC908 generates a differential output signal of 0.5Vp-p at the load resistors, RL. The resistor values shown were selected to result in a symmetric 25 loading for each of the current outputs since the input impedance of the difference amplifier is in parallel to resistors RL, and should be considered.
R2 402 R1 200 IOUT DAC908 IOUT CDIFF R3 200 RL 28.7 OPA680 VOUT
+5V 50
1/2 OPA2680
DAC908 RF1 CF1
-VOUT = IOUT * RF
IOUT
CD1
RF2
-5V +5V R4 402
IOUT CD2 CF2
RL 26.1
FIGURE 4. Difference Amplifier Provides Differential to Single-Ended Conversion and DC-Coupling.
50
1/2 OPA2680
-VOUT = IOUT * RF
-5V
The OPA680 is configured for a gain of two. Therefore, operating the DAC908 with a 20mA full-scale output will produce a voltage output of 1V. This requires the amplifier to operate off of a dual power supply (5V). The tolerance
FIGURE 5. Dual, Voltage-Feedback Amplifier OPA2680 Forms Differential Transimpedance Amplifier.
12
DAC908
SBAS109B
The DC gain for this circuit is equal to feedback resistor RF. At high frequencies, the DAC output impedance (CD1, CD2) will produce a zero in the noise gain for the OPA2680 that may cause peaking in the closed-loop frequency response. CF is added across RF to compensate for this noise-gain peaking. To achieve a flat transimpedance frequency response, the pole in each feedback network should be set to:
INTERNAL REFERENCE OPERATION The DAC908 has an on-chip reference circuit that comprises a 1.24V bandgap reference and a control amplifier. Grounding pin 16, INT/EXT, enables the internal reference operation. The full-scale output current, IOUTFS, of the DAC908 is determined by the reference voltage, VREF, and the value of resistor RSET. IOUTFS can be calculated by: IOUTFS = 32 * IREF = 32 * VREF / RSET (10)
1 GBP = 2 R F C F 4 R F C D
(8)
with GBP = Gain Bandwidth Product of OPA which will give a corner frequency f-3dB of approximately:
GBP 2 R F C D
As shown in Figure 7, the external resistor RSET connects to the FSA pin (Full-Scale Adjust). The reference control amplifier operates as a V-to-I converter producing a reference current, IREF, which is determined by the ratio of VREF and RSET, as shown in Equation 10. The full-scale output current, IOUTFS, results from multiplying IREF by a fixed factor of 32.
CCOMPEXT +5V 0.1F
f - 3 dB =
(9)
The full-scale output voltage is defined by the product of IOUTFS * RF, and has a negative unipolar excursion. To improve on the ac performance of this circuit, adjustment of RF and/or IOUTFS should be considered. Further extensions of this application example may include adding a differential filter at the OPA2680's output followed by a transformer, in order to convert to a single-ended signal. SINGLE-ENDED CONFIGURATION Using a single load resistor connected to the one of the DAC outputs, a simple current-to-voltage conversion can be accomplished. The circuit in Figure 6 shows a 50 resistor connected to IOUT, providing the termination of the further connected 50 cable. Therefore, with a nominal output current of 20mA, the DAC produces a total signal swing of 0V to 0.5V into the 25 load.
DAC908 IREF = VREF RSET FSA REFIN RSET 2k 0.1F INT/EXT Ref Control Amp
BW
+VA
Current Sources CCOMP 400pF
+1.24V Ref.
FIGURE 7. Internal Reference Configuration. Using the internal reference, a 2k resistor value results in a 20mA full-scale output. Resistors with a tolerance of 1% or better should be considered. Selecting higher values, the converter output can be adjusted from 20mA down to 2mA. Operating the DAC908 at lower than 20mA output currents may be desirable for reasons of reducing the total power consumption, improving the distortion performance, or observing the output compliance voltage limitations for a given load condition. It is recommended to bypass the REFIN pin with a ceramic chip capacitor of 0.1F or more. The control amplifier is internally compensated, and its small signal bandwidth is approximately 1.3MHz. To improve the ac performance, an additional capacitor (CCOMPEXT) should be applied between the BW pin and the analog supply, +VA, as shown in Figure 7. Using a 0.1F capacitor, the small-signal bandwidth and output impedance of the control amplifier is further diminished, reducing the noise that is fed into the current source array. This also helps shunting feedthrough signals more effectively, and improving the noise performance of the DAC908. 13
IOUTFS = 20mA IOUT DAC908 IOUT 25 50
VOUT = 0V to +0.5V
50
FIGURE 6. Driving a Doubly-Terminated 50 Cable Directly. Different load resistor values may be selected as long as the output compliance range is not exceeded. Additionally, the output current, IOUTFS, and the load resistor may be mutually adjusted to provide the desired output signal swing and performance.
DAC908
SBAS109B
EXTERNAL REFERENCE OPERATION The internal reference can be disabled by applying a logic HIGH (+VA) to pin INT/EXT. An external reference voltage can then be driven into the REFIN pin, which in this case functions as an input, as shown in Figure 8. The use of an external reference may be considered for applications that require higher accuracy and drift performance, or to add the ability of dynamic gain control. While a 0.1F capacitor is recommended to be used with the internal reference, it is optional for the external reference operation. The reference input, REFIN, has a high input impedance (1M) and can easily be driven by various sources. Note that the voltage range of the external reference should stay within the compliance range of the reference input (0.1V to 1.25V). DIGITAL INPUTS The digital inputs, D0 (LSB) through D7 (MSB) of the DAC908 accepts standard-positive binary coding. The digital input word is latched into a master-slave latch with the rising edge of the clock. The DAC output becomes updated with the following falling clock edge (refer to the specification table and timing diagram for details). The best performance will be achieved with a 50% clock duty cycle, however, the duty cycle may vary as long as the timing specifications are met. Additionally, the setup and hold times may be chosen within their specified limits. All digital inputs are CMOS compatible. The logic thresholds depend on the applied digital supply voltage such that they are set to approximately half the supply voltage; Vth = +VD/2 (20% tolerance). The DAC908 is designed to operate over a supply range of 2.7V to 5.5V.
POWER-DOWN MODE The DAC908 features a power-down function which can be used to reduce the supply current to less than 9mA over the specified supply range of 2.7V to 5.5V. Applying a logic High to the PD pin will initiate the power-down mode, while a logic Low enables normal operation. When left unconnected, an internal active pull-down circuit will enable the normal operation of the converter. GROUNDING, DECOUPLING AND LAYOUT INFORMATION Proper grounding and bypassing, short lead length, and the use of ground planes are particularly important for high frequency designs. Multilayer pc-boards are recommended for best performance since they offer distinct advantages such as minimization of ground impedance, separation of signal layers by ground layers, etc. The DAC908 uses separate pins for its analog and digital supply and ground connections. The placement of the decoupling capacitor should be such that the analog supply (+VA) is bypassed to the analog ground (AGND), and the digital supply bypassed to the digital ground (DGND). In most cases 0.1uF ceramic chip capacitors at each supply pin are adequate to provide a low impedance decoupling path. Keep in mind that their effectiveness largely depends on the proximity to the individual supply and ground pins. Therefore, they should be located as close as physically possible to those device leads. Whenever possible, the capacitors should be located immediately under each pair of supply/ ground pins on the reverse side of the pc-board. This layout approach will minimize the parasitic inductance of component leads and pcb runs.
CCOMPEXT +5V 0.1F
DAC908 IREF = VREF RSET FSA External Reference REFIN Ref Control Amp
BW
+VA
Current Sources CCOMP 400pF
RSET
+5V
INT/EXT
+1.24V Ref.
FIGURE 8. External Reference Configuration.
14
DAC908
SBAS109B
Further supply decoupling with surface mount tantalum capacitors (1uF to 4.7uF) may be added as needed in proximity of the converter. Low noise is required for all supply and ground connections to the DAC908. It is recommended to use a multilayer pcboard utilizing separate power and ground planes. Mixed signal designs require particular attention to the routing of the different supply currents and signal traces. Generally, analog supply and ground planes should only extend into analog signal areas, such as the DAC output signal and the reference signal. Digital supply and ground planes must be confined to areas covering digital circuitry, including the digital input lines connecting to the converter, as well as the clock signal. The analog and digital ground planes should be joined together at one point underneath the DAC. This can be realized with a short track of approximately 1/8" (3mm).
The power to the DAC908 should be provided through the use of wide pcb runs or planes. Wide runs will present a lower trace impedance, further optimizing the supply decoupling. The analog and digital supplies for the converter should only be connected together at the supply connector of the pc-board. In the case of only one supply voltage being available to power the DAC, ferrite beads along with bypass capacitors may be used to create an LC filter. This will generate a low-noise analog supply voltage that can then be connected to the +VA supply pin of the DAC908. While designing the layout, it is important to keep the analog signal traces separate from any digital line, in order to prevent noise coupling onto the analog signal path.
DAC908
SBAS109B
15
PACKAGE DRAWINGS
16
DAC908
SBAS109B
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