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MOTOROLA SEMICONDUCTOR TECHNICAL DATA
Order this document by DSP56005/D Rev. 1
DSP56005
Advance Information
24-bit Digital Signal Processor
The DSP56005 is an MPU-style general purpose Digital Signal Processor (DSP), composed of an efficient 24-bit digital signal processor core, program and data memories, various peripherals, and support circuitry. The 56000-Family-compatible DSP core is fed by a large program RAM, two independent data RAMs, and two data ROMs with sine and arc-tangent tables. Like the DSP56002, the DSP56005 contains a Serial Communication Interface (SCI), Synchronous Serial Interface (SSI), parallel Host Interface (HI), a 24-bit timer/event counter, and On-Chip Emulation (OnCETM) port. Features of the DSP56005 include the large on-chip program memory, five Pulse Width Modulators (PWM), a watchdog timer, and an address decode pin for external peripherals. This combination of features, illustrated in Figure 1, makes the DSP56005 a cost-effective, high-performance solution for many DSP and control applications, especially in high-performance motor control, optical disk drives and audio processing.
14 Pulse Width Modul.
(5)
1 24-bit Timer / Event Counter
6 Sync. Serial (SSI) or I/O
3 Serial Comm. (SCI) or I/O
15 Host Interface (HI) or I/O Program Memory 4608 x 24 RAM 96 x 24 ROM
(boot)
16-bit Bus 24-bit Bus X Data Memory 256 x 24 RAM 256 x 24 ROM
(sine)
Watchdog Timer
Y Data Memory 256 x 24 RAM 256 x 24 ROM
(arc-tangent)
24-bit 56000 DSP Core
Internal Data Bus Switch OnCE Port PLL Clock Gen. 5 4 IRQ
Address Generation Unit
PAB XAB YAB GDB PDB XDB YDB
External Address Bus Switch External Data Bus Switch
Address 16
Data 24
Interrupt Control
Program Decode Controller
Program Address Generator
Program Control Unit 5
Data ALU 24 x 24 + 56 56-bit MAC Two 56-bit Accumulators
Bus Control
Control 6
Figure 1
DSP56005 Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
(c) MOTOROLA INC., 1995
Introduction DSP56005 Features
DSP56005 Features
Digital Signal Processing Core
* Efficient, object code compatible, 24-bit 56000-Family DSP engine -- -- -- -- -- -- -- -- -- -- -- -- -- Up to 25 Million Instructions per Second (MIPS) - 40 ns instruction cycle at 50 MHz Up to 150 Million Operations per Second (MOPS) at 50 MHz Executes a 1024-point complex Fast Fourier Transform (FFT) in 59,898 clocks Highly parallel instruction set with unique DSP addressing modes Two 56-bit accumulators including extension byte Parallel 24 x 24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles) Double precision 48 x 48-bit multiply with 96-bit result in 6 instruction cycles 56-bit Addition/subtraction in 1 instruction cycle Fractional arithmetic with support for multiprecision arithmetic Hardware support for block-floating point FFT Hardware nested DO loops Zero-overhead fast interrupts (2 instruction cycles) Four 24-bit internal data buses and three 16-bit internal address buses for simultaneous accesses to one program and two data memories
Memory
* On-chip Harvard architecture permitting simultaneous accesses to program and two data memories * 4608 x 24-bit on-chip program RAM and 96 x 24-bit bootstrap ROM * Two 256 x 24-bit on-chip data RAMs * Two 256 x 24-bit on-chip data ROMs containing sine and arc-tangent tables * External memory expansion with 16-bit address and 24-bit data buses * Bootstrap loading from external data bus, Host Interface, or Serial Communications Interface
Peripheral and Support Circuits
* Byte-wide Host Interface (HI) with Direct Memory Access (DMA) support * Synchronous Serial Interface (SSI) to communicate with codecs and synchronous serial devices * Serial Communication Interface (SCI) for full-duplex asynchronous communications * Five Pulse Width Modulators (PWM) -- Three with alternate outputs; two with open drain or TTL outputs -- 9- to 16-bit data width -- Alternate outputs independently selectable as active-high or active-low * 24-bit timer/event counter also generates and measures digital waveforms * 16-bit Watchdog timer
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Introduction DSP56005 Features Product Documentation
* On-chip peripheral registers memory mapped in data memory space * Double buffered peripherals * Up to 25 general purpose I/O pins * Five external interrupt request pins * On-Chip Emulation (OnCE) port for unobtrusive, processor speed-independent debugging * Software-programmable, Phase-Locked Loop (PLL) based frequency synthesizer for the core clock * External peripheral address decode signal
Miscellaneous Features
* Power-saving Wait and Stop modes * Fully static, HCMOS design for operating frequencies from 50 MHz down to DC * 144-pin Thin Quad Flat Pack (TQFP) surface-mount package; 20 x 20 x 1.4 mm * 5 V Power supply
Product Documentation
More detailed documentation is available describing the DSP56005. The three documents listed in Table 1 are required for a complete description of the DSP56005 and are necessary to properly design with the part. Documentation is available from a local Motorola distributor or semiconductor sales office, or through a Motorola Literature Distribution Center. Table 1 Additional DSP56005 Documentation
Document Name DSP56000 Family Manual DSP56005 User's Manual DSP56005 Data Sheet Description Detailed description of the 56000-family architecture and the 24-bit core processor and instruction set Detailed description of memory, peripherals, and interfaces Electrical and timing specifications, and pin and package descriptions Order Number DSP56KFAMUM/AD DSP56005UM/AD DSP56005/D
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DSP56005 Data Sheet
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Introduction Product Documentation
Related Documentation
Table 2 lists additional documentation relevant to the DSP56005. Table 2 DSP56005 Related Documentation
Document Name Motorola's 16-, 24-, and 32-bit Digital Signal Processing Families Digital Sine-Wave Synthesis Digital Stereo 10-band Graphic Equalizer Fractional and Integer Arithmetic Implementation of Fast Fourier Transforms Implementation of PID Controllers Description Overview of all of the DSP product families. Application Report. Uses the DSP56001 look-up table. Application Report. Includes code and circuitry; features the DSP56001. Application Report. Includes code. Application Report. Comprehensive FFT algorithms and code for DSP56001, DSP56156, and DSP96002. Application Report. PWM using the SCI timer and three phase output using modulo addressing. Application Report. Theory and code; features the DSP56001. Application Report. Comprehensive example using the DSP56001. Application Report. Features the DSP56ADC16; improving resolution with half-band filters Application Report. Features the DSP56001 Application Report. Interfaces for pseudo static RAM, dynamic RAM, ISA bus, Host Application Report. Circuit, code, FIR filter design for two voice band CODECs connecting to the SSI Application Report. Theory and code; features the DSP56001/002 Application Report. Adaptive control using reference models; generalized predictive control; includes code Order Number BR1105/D APR1/D APR2/D APR3/D APR4/D
APR5/D
Convolutional Encoding and Viterbi Decoding with a V.32 Modem Trellis Example Implementing IIR/FIR Filters Principles of Sigma-Delta Modulation for A-to-D Converters Full-Duplex 32-kbit/s CCITT ADPCM Speech Coding DSP56001 Interface Techniques and Examples Twin CODEC Expansion Board for the DSP56000 ADS Conference Bridging in the Digital Telecommunications Environment Implementation of Adaptive Controllers
APR6/D
APR7/D APR8/D
APR9/D APR11/D APR12/D
APR14/D APR15/D
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DSP56005 Data Sheet
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Introduction Product Documentation
Table 2 DSP56005 Related Documentation (Continued)
Document Name Calculating Timing Requirements of External SRAM PC Media Hardware Reference Design Version 4.0 Low Cost Controller for DSP56001 G.722 Audio Processing Minimal Logic DRAM Interface Logarithmic/Linear Conversion Routines Dr. BuB Bulletin Board DSP Development Tools Third Party Compendium Description Application Report. Determination of SRAM speed for optimum performance Application Report. Audio, telephony, and entertainment board design Application Report. Circuit and code to connect two DSP56001s to an MC68008 Application Report. Theory and code using SB-ADPCM Application Report. 1M x 480 ns DRAM, 1 PAL, code Application Report. -law and A-law companding routines for PCM mono-circuits Flyer. Motorola's electronic bulletin board where free DSP software is available Overview of Motorola's hardware and software development tools Brochures from companies selling hardware and software that supports Motorola DSPs Flyer. Motorola's program supporting Universities in DSP research and education Technical Training Schedule Textbook by Mohamed El-Sharkawy; 398+ pages. (This is a charge item.) Order Number APR16/D APR19/D APR402/D APR404/D APR405/D ANE408/D BR297/D DSPTOOLSP/D DSP3RDPTYPAK/D
University Support Program Technical Training Schedule
BR382/D BR348/D Prentice-Hall, 1990; ISBN 0-13-767138-5
Real Time Signal Processing Applications with Motorola's DSP56000 Family
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DSP56005 Data Sheet
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Introduction Contents Conventions
Data Sheet Contents
This data sheet contains: * * * * * Pin Descriptions . . . . . . . . . . . . . . . . . . . Electrical Specifications . . . . . . . . . . . . . Pin-out and Package. . . . . . . . . . . . . . . . Design Considerations . . . . . . . . . . . . . . Ordering Information. . . . . . . . . . . . . . . 9 21 Left 77 87
Data Sheet Conventions
This data sheet uses the following conventions: * OVERBARS are used to indicate a signal that is active when pulled to ground (see Table 3) e.g. the HREQ pin is active when pulled to ground. Therefore, references to the HREQ pin will always have an overbar. * The word "assert" (see Table 3) means that a high true (active high) signal is pulled high to VCC or that a low true (active low) signal is pulled low to ground. * The word "deassert" (see Table 3) means that a high true signal is pulled low to ground or that a low true signal is pulled high to VCC. Table 3 High True / Low True Signal Conventions
Signal/Symbol PIN PIN PIN PIN
NOTES: 1. 2. 3. PIN is a generic term for any pin on the chip. Ground is an acceptable low voltage level. See the DC electrical specifications for the range of acceptable low voltage levels (typically a TTL logic low). VCC is an acceptable high voltage level. See the DC electrical specifications for the range of acceptable high voltage levels (typically a TTL logic high).
Logic State True False True False
Signal State Asserted Deasserted Asserted Deasserted
Voltage Ground VCC VCC Ground
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DSP56005 Data Sheet
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Introduction Pin Groupings
Pin Groupings
The input and output signals of the DSP56005 are organized into function groups as shown in Table 4 and as illustrated in Figure 2.
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DSP56005 Data Sheet
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Introduction Pin Functions
DSP56005
D0-D23 VCCD GNDD A0-A15 PS DS X/Y EXTP VCCA GNDA RD WR External Data Bus Host Interface (HI) H0-H7 HA0-HA2 HR/W HEN HREQ HACK VCCH GNDH RXD TXD SCLK VCCS GNDS SC0-SC2 SCK SRD STD TIO PWAP0 - PWAP2 PWAN0 - PWAN2 PWAC0 - PWAC2 PWACLK PWB0, PWB1 PWBC PWBCLK VCCW GNDW
External Address Bus Serial Communication Interface (SCI)
VCCC GNDC
External Bus Control
Synchronous Serial Interface (SSI) Timer/ Event Counter Pulse Width Modulator A (PWMA0-2)
MODA/IRQA MODB/IRQB MODC/NMI IRQC IRQD RESET VCCQ GNDQ DSI/OS0 DSCK/OS1 DSO DR EXTAL XTAL VCCCK GNDCK
Interrupt/ Mode Control Pulse Width Modulator B (PWMB0-1)
On-Chip Emulator (OnCE) Port Phase-Locked Loop (PLL) Clock Oscillator PCAP PINIT CKOUT VCCP GNDP
Figure 2 DSP56005 Pin Functions
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DSP56005 Data Sheet
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Pin Descriptions Address and Data Bus Bus Control
Pin Descriptions
The DSP56005 is available in a 144 TQFP. The pins are organized into the functional groups indicated in Table 4. The signals are discussed in the paragraphs that follow. All unused inputs should have pull-up resistors for two reasons: 1. floating inputs draw excessive power 2. floating input can cause erroneous operation For example, during reset, all signals are three-stated. A pull-up resistor in the 50 k range should be sufficient. Also, for future enhancements, all reserved "no connect" (NC), pins should be left unconnected.
Bus Control
The bus control signals are three-stated during reset and may require pull-up resistors to prevent erroneous operation.
PS (Program Memory Select) -- three-state, active low output This output is asserted only when external program memory is referenced (see Table 5). PS timing is the same as the A0-A15 address lines. If the external bus is not used during an instruction cycle, PS is driven high. PS is three-stated during hardware reset. DS (Data Memory Select) -- three-state, active low output This three-state output is asserted only when external data memory is referenced (see Table 5). If the external bus is not used during an instruction cycle, DS is driven high. DS is three-stated during hardware reset. X/Y (X/Y Select) -- three-state output. This three-state output selects which external data memory space (X or Y) is referenced by DS (see Table 5). X/Y is three-stated during hardware reset. RD (Read Enable) -- three-state, active low output. This output is asserted during external memory read cycles. When RD is asserted, the data bus pins D0-D23 become inputs, and an external device is enabled onto the data bus. When RD is deasserted, the external data is latched inside the DSP. When RD is asserted, it qualifies the A0-A15, PS and DS pins. RD can be connected directly to the OE pin of a static RAM or ROM. RD is three-stated during hardware reset.
Address and Data Bus
The Port A address and data bus signals control the access to external memory. These signals are three-stated during reset unless noted otherwise, and may require pull-up resistors to minimize power consumption and to prevent erroneous operation. A0-A15 (Address Bus) -- three-state, outputs. A0-A15 specify the address for external program and data memory accesses. If there is no external bus activity, A0-A15 remain at their previous values. A0-A15 are three-stated during hardware reset. D0-D23 (Data Bus) -- three-state, bidirectional input/outputs. Data for external memory I/O is presented on D0-D23. If there is no external bus activity, D0-D23 are three-stated. D0-D23 are also three-stated during hardware reset.
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DSP56005 Data Sheet
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Pin Descriptions Bus Control HI
WR (Write Enable) -- three-state, active low output. This output is asserted during external memory write cycles. When WR is asserted, the data bus pins D0-D23 become outputs, and the DSP puts data on the bus. When WR is deasserted, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15, PS and DS pins. WR can be connected directly to the WE pin of a static RAM. WR is three-stated during hardware reset. EXTP (External Peripheral) -- active low output. The EXTP pin is an output asserted whenever the external Y memory I/O space (Y:$FFC0-$FFFF) is accessed. This signal simplifies generating peripheral enable signals. No additional circuitry is needed if only one external peripheral is used. For most applications, no more than one decode chip is needed and, as a result, decode delays are minimized. Using the Y memory I/O space allows the MOVEP instruction to be used to send and to receive data. Using the MOVEP instruction may allow the entire I/O routine to fit in a fast interrupt. EXTP is three-stated during hardware reset.
Host Interface
The following paragraphs discuss the host interface signals, which provide a convenient connection to another processor. H0-H7 (Host Data Bus) -- bidirectional. This bidirectional data bus is used to transfer data between the host processor and the DSP. This bus is an input unless enabled by a host processor read. It is high impedance when HEN is deasserted. H0-H7 may be programmed as Port B general purpose parallel I/O pins called PB0-PB7 when the Host Interface (HI) is not being used. These pins are configured as GPIO input pins during hardware reset. HA0-HA2 (Host Address) -- input.* These inputs provide the address selection for each HI register and must be stable when HEN is asserted. HA0-HA2 may be programmed as Port B general purpose parallel I/O pins called PB8-PB10 when the HI is not being used. These pins are configured as GPIO input pins during hardware reset.
*Note that these pins can be inputs or outputs when programmed as general purpose I/O.
Table 5 Program and Data Memory Select Encoding PS 1 1 1 0 0 0 1 DS 1 0 0 1 1 0 1 X/Y 1 1 0 1 0 X 0
External Memory Reference
No Activity X Data Memory on Data Bus Y Data Memory on Data Bus Program Memory on Data Bus (Not an Exception) External Exception Fetch: Vector or Vector +1 (Development Mode Only) Reserved Reserved
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DSP56005 Data Sheet
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Pin Descriptions HI SCI
HR/W (Host Read/Write) -- input.* This input selects the direction of data transfer for each host processor access. If HR/W is high and HEN is asserted, H0-H7 are outputs, and DSP data is transferred to the host processor. If HR/W is low and HEN is asserted, H0-H7 are inputs and host data is transferred to the DSP when HEN is deasserted. When HEN is asserted, HR/W must be stable. HR/W may be programmed as a general purpose I/O pin called PB11 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. HEN (Host Enable) -- active low input.* This input enables a data transfer on the host data bus. When HEN is asserted and HR/W is high, H0-H7 becomes an output and DSP data may be latched by the host processor. When HEN is asserted and HR/W is low, H0-H7 is an input and host data is latched inside the DSP when HEN is deasserted. Normally a chip select signal derived from host address decoding and an enable clock is connected to the Host Enable. HEN may be programmed as a general purpose I/O pin called PB12 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. HREQ (Host Request) -- active low output.* This open-drain output signal is used by the DSP to request service from the host processor. HREQ may be connected to a host processor interrupt request pin, a DMA controller transfer request pin, or a control input to external circuitry. HREQ is asserted when an enabled request occurs in the HI. HREQ is
deasserted when the enabled request is cleared or masked, DMA HACK is asserted, or the DSP is reset. HREQ may be programmed as a general purpose I/O pin (not open-drain) called PB13 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. HACK (Host Acknowledge) -- active low input.* This input has two functions: * to provide a host acknowledge signal for DMA transfers * to control handshaking and to provide a host interrupt acknowledge compatible with MC68000 family processors If programmed as a host acknowledge signal, HACK may be used as a data strobe for HI DMA data transfers. If programmed as an MC68000 host interrupt acknowledge, HACK enables the HI Interrupt Vector Register (IVR) onto the host data bus H0-H7 if the Host Request HREQ output is asserted. In this case, all other HI control pins are ignored and the HI state is not affected. HACK may be programmed as a general purpose I/O pin called PB14 when the HI is not being used. This pin is configured as a GPIO input pin during hardware reset. NOTE: HACK should always be pulled high when not in use.
Serial Communication Interface (SCI)
RXD (Receive Data) -- input.* This input receives byte-oriented data and transfers the data to the SCI receive shift register. Input data is sampled on the 11
*Note that these pins can be inputs or outputs when programmed as general-purpose I/O.
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DSP56005 Data Sheet
Pin Descriptions SCI SSI
positive or the negative edge of the receive clock, depending on how the SCI control register is programmed. RXD may be programmed as a general-purpose I/O pin called PC0 when it is not being used as an SCI pin. This pin is configured as a GPIO input pin during hardware reset. TXD (Transmit Data) -- output.* This output transmits serial data from the SCI transmit shift register. Data changes on the negative edge of the transmit clock. This output is stable on the positive or the negative edge of the transmit clock, depending on how the SCI control register is programmed. TXD may be programmed as a general-purpose I/O pin called PC1 when the SCI TXD function is not being used. This pin is configured as a GPIO input pin during hardware reset. SCLK (SCI Serial Clock) -- bidirectional. This bidirectional pin provides an input or output clock from which the transmit and/or receive baud rate is derived in the asynchronous mode, and from which data is transferred in the synchronous mode. SCLK may be programmed as a general-purpose I/O pin called PC2 when the SCI SCLK function is not being used. This pin is configured as a GPIO input pin during hardware reset.
termined by whether the SSI is in synchronous or asynchronous mode. In synchronous mode, this pin is used for serial flag I/O. In asynchronous mode, this pin receives clock I/O. SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. SC0 may be programmed as a general-purpose I/O pin called PC3 when the SSI SC0 function is not used. This pin is configured as a GPIO input pin during hardware reset. SC1 (Serial Control 1) -- bidirectional. The SSI uses this bidirectional pin to control flag or frame synchronization. This pin's function is determined by whether the SSI is in synchronous or asynchronous mode. In asynchronous mode, this pin is frame sync I/O. For synchronous mode with continuous clock, this pin is serial flag SC1 and operates like the SC0. SC0 and SC1 are independent serial I/O flags but may be used together for multiple serial device selection. SC1 may be programmed as a general-purpose I/O pin called PC4 when the SSI SC1 function is not being used. This pin is configured as a GPIO input pin during hardware reset. SC2 (Serial Control 2) -- bidirectional. The SSI uses this bidirectional pin to control frame synchronization only. As with SC0 and SC1, its function is defined by the SSI operating mode. SC2 may be programmed as a general-purpose I/O pin called PC5 when the SSI SC2 function is not being used. This pin is configured as a GPIO input pin during hardware reset. SCK (SSI Serial Clock) -- bidirectional. This bidirectional pin provides the serial bit rate clock for the SSI when only one clock is being used. SCK may be
Synchronous Serial Interface (SSI)
SC0 (Serial Control 0) -- bidirectional. This bidirectional pin's function is de*These pins can be input or output when programmed as general-purpose I/O.
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DSP56005 Data Sheet
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Pin Descriptions SSI TIMER PWMA
programmed as a general-purpose I/O pin called PC6 when it is not needed as an SSI pin. This pin is configured as a GPIO input pin during hardware reset. SRD (SSI Receive Data) -- input.* This input pin receives serial data into the SSI receive shift register. SRD may be programmed as a general-purpose I/O pin called PC7 when the SRD function is not being used. This pin is configured as a GPIO input pin during hardware reset. STD (SSI Transmit Data) -- output.* This output pin transmits serial data from the SSI transmit shift register. STD may be programmed as a general-purpose I/O pin called PC8 when the STD function is not being used. This pin is configured as a GPIO input pin during hardware reset.
Pulse Width Modulator A (PWMA)
Pulse Width Modulator A is a set of three 16-bit signed two's complement fractional data pulse width modulators and has 10 dedicated external pins. These pulse width modulators are independent of the PWMB modulators. PWAP0 - PWAP2 (Pulse Width Modulator A Positive) -- output. These three pins are the positive outputs for the three PWMA modulators (PWMA0, PWMA1, and PWMA2). When a positive two's complement number is loaded in one of the three PWMA Count Registers, an output signal will be generated on the respective pin (e.g., loading PWACR0 with a positive two's complement number will generate an output on PWAP0). When a negative two's complement number is loaded in a PWMA Count Register, PWAP0-PWAP2 will be at its inactive logic level (as defined by the polarity bits in the PWMA Control/Status Register 1). These pins are driven at their inactive logic level (as defined by the polarity bits in the Control/Status Register 1) when the individual PWM modulator (PWMA0, PWMA1, or PWMA2) is not enabled. During hardware reset, these pins are driven to a high logic level. PWAN0 - PWAN2 (Pulse Width Modulator A Negative) -- output. These three pins are the negative outputs for the three PWMA modulators (PWMA0, PWMA1, and PWMA2). When a negative two's complement number is loaded in one of the three PWMA Count Registers, an output signal will be generated on the respective pin (e.g. loading PWACR0 with a negative two's
Timer/Event Counter
TIO (Timer/Event Counter Input/Output) -- bidirectional. The TIO pin provides an interface to the Timer/Event Counter module. When the module functions as an external event counter or is used to measure an external pulse width/signal period, the TIO is used as an input. When the module functions as a timer, the TIO is an output and the signal on the TIO pin is the timer pulse. When not used by the timer module, the TIO can act as a general purpose I/O pin. Reset disables the TIO pin and causes it to be three-stated.
* These pins can be input or output when programmed as general purpose I/O. MOTOROLA
DSP56005 Data Sheet
13
Pin Descriptions PWMA PWMB
complement number will generate an output on PWAN0). When a positive two's complement number is loaded in a PWMA Count Register, the N-output (PWAN0PWAN2) of this PWMA block will be at its inactive logic level (as defined by the polarity bits in the PWMA Control/Status Register 1). These pins are driven at their inactive logic level (as defined by the polarity bits in the Control/Status Register 1) when the individual PWM modulator (PWMA0, PWMA1, or PWMA2) is not enabled. During hardware reset, these pins are driven to a high logic level. PWAC0 - PWAC2 (Pulse Width Modulator A Carrier) -- input. These three pins are inputs that provide the external carrier signals for the three PWMAs (PWMA0, PWMA1 and PWMA2). When the carrier source for the respective PWMA block is programmed to be external, the modulator starts operation at each rising edge of its carrier signal. While a PWMA block is either disabled, or is enabled and programmed to operate with the internal carrier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. PWACLK (Pulse Width Modulator A Clock) -- input. This input increments the prescaler which connects to the three PWMA blocks and increments the counter in each these blocks. If all of the PWMA blocks are either disabled, or are programmed to use the internal clock, the internal input buffer is disconnected from the pin and no external pull-up is necessary.
Pulse Width Modulator B (PWMB)
Pulse Width Modulator B is a pair 16-bit positive fractional data pulse width modulators and has four dedicated external pins. These two pulse width modulators are independent of the PWMA modulators. PWBC (Pulse Width Modulator B Carrier) -- input. This pin is an input that provides the external carrier signals for the two PWMB blocks (PWMB0 and PWMB1). When the carrier source for these blocks is programmed to be external, these blocks start operation at each rising edge of this signal. While a PWMB block is either disabled, or is enabled and programmed to operate with the internal carrier, its respective internal input buffer is disconnected from the pin and no external pull-up is necessary. PWB0-PWB1(Pulse Width Modulator B Output) -- active low output. These two pins are the outputs for pulse width modulators PWMB0 and PWMB1. These pins are either open drain or driven at TTL levels depending on the programming of PWBCSR1 bit 14 (WBR0). These pins are also in the high-impedance state or in a high logic state (depending on the value of the bit WBO in PWBCSR1) when PWMB0 and PWMB1 are disabled. During hardware reset, these pins are in the high-impedance state. PWBCLK (Pulse Width Modulator B Clock) -- input. This input increments the prescaler which increments the counter connected to the two PWMB blocks. While both PWMB blocks are disabled, the internal input buffer is disconnected from the pin and no external pull-up
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DSP56005 Data Sheet
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Pin Descriptions PWMB OnCE Port
is necessary. While the PWMB blocks are programmed to use the internal clock, the internal input buffer is disconnected from the pin and no external pull-up is necessary.
On-Chip Emulation (OnCETM) Port
The following paragraphs describe the pins associated with the OnCE Port controller and its serial interface. DSI/OS0 (Debug Serial Input/Chip Status 0) -- bidirectional. The DSI/OS0 pin, when an input, is the pin through which serial data or commands are provided to the OnCE port controller. The data received on the DSI pin will be recognized only when the DSP has entered the debug mode of operation. Data must have valid TTL logic levels before the serial clock falling edge. Data is always shifted into the OnCE serial port most significant bit (MSB) first. When the DSP is not in the debug mode, the DSI/OS0 pin provides information about the chip status if it is an output and used in conjunction with the OS1 pin. When switching from output to input, the pin is three-stated. During hardware reset, this pin is defined as an output and it is driven low. NOTE: To avoid possible glitches, an external pull-down resistor should be attached to this pin. DSCK/OS1(Debug Serial Clock/Chip Status 1) -- bidirectional. The DSCK/OS1 pin, when an input, is the pin through which the serial clock is supplied to the OnCE port. The serial clock provides pulses required to shift data into and
out of the OnCE serial port. Data is clocked into the OnCE port on the falling edge and is clocked out of the OnCE serial port on the rising edge. If the DSCK/OS1 pin is an output and used in conjunction with the OS0 pin, it provides information about the chip status when the DSP is not in the debug mode. The debug serial clock frequency must be no greater than 1/8 of the processor clock frequency. The pin is three-stated when it is changing from input to output. During hardware reset, this pin is defined as an output and is driven low. NOTE: To avoid possible glitches, an external pull-down resistor should be attached to this pin. DSO (Debug Serial Output) -- output. The debug serial output provides the data contained in one of the OnCE port controller registers as specified by the last command received from the command controller. The most significant bit (MSB) of the data word is always shifted out of the OnCE serial port first. Data is clocked out of the OnCE Port serial port on the rising edge of DSCK. The DSO pin also provides acknowledge pulses to the external command controller. When the chip enters the debug mode, the DSO pin will be pulsed low to indicate (acknowledge) that the OnCE Port is waiting for commands. After receiving a read command, the DSO pin will be pulsed low to indicate that the requested data is available and the OnCE Port serial port is ready to receive clock pulses in order to deliver the data. After receiving a write command, the DSO pin will be pulsed low to indicate that the OnCE serial port is ready to receive the data to be written;
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15
Pin Descriptions OnCE Port Power and Ground
after the data is written, another acknowledge pulse will be provided. During hardware reset and when idle, the DSO pin is held high. DR (Debug Request) -- active low input. The debug request input provides a means of entering the debug mode of operation. This pin, when asserted, will cause the DSP to finish the current instruction being executed, to save the instruction pipeline information, to enter the debug mode, and to wait for commands to be entered from the debug serial input line. While the DSP is in the debug mode, the user can reset the OnCE Port controller by asserting DR, waiting for an acknowledge from DSO, and then deasserting DR. It may be necessary to reset the OnCE Port controller in cases where synchronization between the OnCE Port controller and external circuitry is lost. Asserting DR when the DSP is in the Wait or the Stop state, and keeping it asserted until an acknowledge pulse in the DSP is produced, sends the DSP into the debug mode. After receiving the acknowledge, DR must be deasserted before sending the first OnCE Port command. Power and Ground NOTE: To avoid possible glitches, an external pull-up resister should be attached to this pin The power and ground pins are presented in the following paragraphs. There are ten sets of power and ground pins (see Table 25). In accordance with good engineering practice, VCC should be bypassed to ground (as needed) by a 0.1 F capacitor located as close as possible to the chip package. The two circuits where this bypassing is most important are the PLL and the core processor internal logic circuits.
Power
These VCC pins provide power to the circuits listed in Table 25, "DSP56005 Power Supply Pins," on page 77. The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail. VCCP (PLL Circuit Power). This pin supplies a quiet power source to the Phase-Locked Loop (PLL) to provide greater frequency stability. The voltage should be well regulated and the pin should be provided with an extremely low impedance path to the power rail. VCCP should be bypassed to GNDP by a 0.1 F capacitor located as close as possible to the chip package.
Ground
These pins provide grounds for the circuits listed in Table 25, "DSP56005 Power Supply Pins," on page 77. The pins should be provided with an extremely low impedance path to ground. GNDP (PLL Circuit Ground). This pin supplies a quiet ground source to the PLL to provide greater frequency stability. The pin should be provided with an extremely low impedance path to ground. VCCP should be bypassed to GNDP by a 0.1 F capacitor located as close as possible to the chip package.
Interrupt and Mode Control
The interrupt and mode control pins select the chip's operating mode as it comes out of hardware reset and receive interrupt requests from external sources after reset.
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DSP56005 Data Sheet
MOTOROLA
Pin Descriptions Interrupt and Mode Control
MODA/IRQA (Mode Select A/External Interrupt Request A) -- input. This input pin has three functions: * to work with the MODB and MODC pins to select the chip's initial operating mode * to allow an external device to request a DSP interrupt after internal synchronization * to turn on the internal clock generator when the DSP in the Stop processing state, causing the chip to resume processing MODA is read and internally latched in the DSP when the processor exits the reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODA pin changes to the external interrupt request IRQA. The chip operating mode can be changed by software after reset. The IRQA input is a synchronized external interrupt request. It may be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQA will generate multiple interrupts also increases. While the DSP is in the Stop processing state, asserting IRQA gates on the oscillator and, after a clock stabilization delay, enables clocks to the processor and peripherals. Hardware reset causes this input to act as MODA.
MODB/IRQB (Mode Select B/External Interrupt Request B) -- input. This input pin has two functions: * to work with the MODA and MODC pins to select the chip's initial operating mode * to allow an external device to request a DSP interrupt after internal synchronization MODB is read and internally latched in the DSP when the processor exits the reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODB pin changes to the external interrupt request IRQB. The chip operating mode can be changed by software after reset. The IRQB input is a synchronized external interrupt request. It may be programmed to be level sensitive or negative edge triggered. When the signal is edge triggered, triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQB will generate multiple interrupts also increases. Hardware reset causes this input to act as MODB. MODC/NMI (Mode Select C/Non-Maskable Interrupt Request) -- edge triggered input. This input pin has two functions: * to work with the MODA and MODB pins to select the chip's initial operating mode * to allow an external device to request a DSP interrupt after internal synchronization
MOTOROLA
DSP56005 Data Sheet
17
Pin Descriptions Interrupt and Mode Control Clock, Oscillator, and PLL
MODC is read and internally latched in the DSP when the processor exits the reset state. MODA, MODB, and MODC select the initial chip operating mode. Several clock cycles after leaving the reset state, the MODC pin changes to the non-maskable interrupt request, NMI. The chip operating mode can be changed by software after reset. The NMI input is a negative-edge triggered external interrupt request. This is a level 3 interrupt that can not be masked out. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on NMI will generate multiple interrupts also increases. Hardware reset causes this input to act as MODC. IRQC (External Interrupt Request C) -- edge triggered input. This negative edge triggered input allows an external device to request a DSP interrupt after internal synchronization. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQC will generate multiple interrupts also increases. IRQD (External Interrupt Request D) -- edge triggered input. This negative edge triggered input allows an external device to request a DSP interrupt after internal synchronization. Triggering occurs at a voltage level and is not directly related to the fall time of the interrupt signal. However, as the fall time of the interrupt signal increases, the probability that noise on IRQD will
generate multiple interrupts also increases. RESET (Reset) -- input. This input is a direct hardware reset of the processor. When RESET is asserted, the DSP is initialized and placed in the reset state. A Schmitt trigger input is used for noise immunity. When the reset pin is deasserted, the initial chip operating mode is latched from the MODA, MODB, and MODC pins. The chip also samples the PINIT pin and writes its status into the PEN bit of the PLL Control Register. When the chip comes out of the reset state, deassertion occurs at a voltage level and is not directly related to the rise time of the RESET signal. However, the probability that noise on RESET will generate multiple resets increases with increasing rise time of the RESET signal.
Clock, Oscillator, and PLL
The following pins are dedicated to the PLL, clock, and oscillator operation. CKOUT (Output Clock) -- output. This output pin provides a 50% duty cycle output clock synchronized to the internal processor clock when the PLL is enabled and locked. When the PLL is disabled, the output clock at CKOUT is derived from, and has the same frequency and duty cycle as, EXTAL. NOTE: If the PLL is enabled and the multiplication factor is less than or equal to 4, then CKOUT is synchronized to EXTAL. (For information on the DSP56005's PLL multiplication factor, see Section 3.5 -- DSP56005 Phase-Locked Loop Configuration in the DSP56005 User's Manual.
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DSP56005 Data Sheet
MOTOROLA
Pin Descriptions Clock, Oscillator, and PLL
EXTAL (External Clock/Crystal) -- input. This pin may be used in one of two ways: * driven from an external clock * interface the internal crystal oscillator input to an external crystal circuit If the PLL is enabled, this pin is internally connected to the on-chip PLL. The PLL can multiply the frequency on the EXTAL pin to generate the internal DSP clock. The PLL output is divided by two to produce a four-phase instruction cycle clock, with the minimum instruction time being two PLL output clock periods. If the PLL is disabled, EXTAL is divided by two to produce the four-phase instruction cycle clock. XTAL (Crystal) -- output. This output connects the internal crystal oscillator output to an external crystal. If an external clock is used, XTAL should not be connected. It may be disabled through
software control using the XTLD bit in the PLL control register. PCAP (PLL Filter Capacitor) -- input. This input is used to connect a high quality external capacitor needed for the PLL filter. The capacitor should be as close as possible to the chip with heavy, short traces connecting one terminal of the capacitor to PCAP and the other terminal to VCCP. PINIT (PLL Initialization) -- input. During the assertion of hardware reset, the value at the PINIT input pin is written into the PEN bit of the PLL control register. When high, the PEN bit enables the PLL by causing it to derive the internal clocks from the PLL voltage controlled oscillator output. When the bit is clear, the PLL is disabled and the chip's internal clocks are derived from the clock connected to the EXTAL pin. After hardware reset is deasserted, the PINIT pin is ignored.
MOTOROLA
DSP56005 Data Sheet
19
Pin Descriptions

20
DSP56005 Data Sheet
MOTOROLA
Electrical Characteristics
Electrical Specifications
The preliminary DC/AC electrical specifications are generated from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. The DSP56005 is fabricated in high density CMOS with TTL compatible inputs and outputs.
Table 6 Maximum Ratings (GND = 0Vdc) Rating
Supply Voltage All Input Voltages Current Drain per Pin Excluding
Symbol
VCC VIN I
Value
-0.3 to +7.0 GND - 0.5 to VCC + 0.5 10
Unit
V V mA C C
VCC and GND
Operating Temperature Range Storage Temperature TJ Tstg -40 to +105 -55 to +150
Table 7 Thermal Characteristics of the TQFP Package Thermal Resistance
Junction to Ambient Junction to Case
Symbol
JA JC
Value
49 8
Rating
C/W C/W
NOTE: This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (e.g., either GND or VCC).
MOTOROLA
DSP56005 Data Sheet
21
DC Electrical Characteristics
DC Electrical Characteristics
VCC = 5.0 Vdc 10%; TJ = -40 to +105C
Table 8 DC Electrical Characteristics Characteristics
Supply Voltage Input High Voltage
Symbol
VCC
Min
4.5
Typ
5.0
Max
5.5
Unit
V
* Except EXTAL, RESET, MODA, MODB, MODC * EXTAL * RESET * MODA, MODB, MODC
Input Low Voltage
VIH VIHC VIHR VIHM
2.0 4.0 2.5 3.5
-- -- -- --
VCC VCC VCC VCC
V V V V
* Except EXTAL, MODA, MODB, MODC * EXTAL * MODA, MODB, MODC
Input Leakage Current
VIL VILC VILM IIN
-0.5 -0.5 -0.5 -1
-- -- -- --
0.8 0.6 2.0 1
V V V A
EXTAL, RESET, MODA/IRQA, MODB/IRQB, MODC/NMI
Three-State (Off-State) Input Current (@ 2.4V / 0.4V) Output High Voltage (IOH = -0.4 mA) Output Low Voltage (IOL = 3.2 mA; HREQ IOL = 6.7 mA, TXD IOL = 6.7 mA) Internal Supply Current 5.5 V, 50 MHz (See Note 3) ITSI VOH VOL -10 2.4 -- -- -- -- 10 -- 0.4 A V V
* in Wait Mode (See Note 1) * in Stop Mode (See Note 1)
PLL Supply Current (See Note 4) Clockout Supply Current (See Note 5) Input Capacitance (See Note 2)
ICCI ICCW ICCS
-- -- -- -- --
125 25 2 TBD TBD 10
TBD TBD TBD TBD TBD --
mA mA A mA mA pF
CIN
--
NOTES: 1. 2. 3. 4. 5. In order to obtain these results, all inputs must be terminated (i.e., not allowed to float). Periodically sampled and not 100% tested Power Consumption in the Design Considerations section describes how to calculate the external supply current. Values given are for PLL enabled. Values given are for CKOUT enables.
22
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Internal Clocks
AC Electrical Characteristics
The timing waveforms in the AC Electrical Characteristics are tested with a VIL maximum of 0.5V and a VIH minimum of 2.4V for all pins, except EXTAL, RESET, MODA, MODB, and MODC. These five pins are tested using the input levels set forth in DC Electrical Characteristics. AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. DSP56005 output levels are measured on the production test machine with VOL and VOH reference levels set at 0.8V and 2.0V respectively.
Internal Clocks
For each occurrence of TH, TL, TC or ICYC substitute with the numbers given in Table 9:
Table 9 Internal Clocks Characteristics
Internal Operation Frequency Internal Clock High Period
Symbol
f TH ETH
Expression
- with PLL disabled - with PLL enabled and MF 4
(See Note 1)
(Min) 0.48 x ETC x DF/MF (Max) 0.52 x ETC x DF/MF (See Note 2) (Min) 0.467 x ETC x DF/MF (Max) 0.533 x ETC x DF/MF TL ETL (See Note 1)
- with PLL enabled and MF > 4
Internal Clock Low Period
- with PLL disabled - with PLL enabled and MF 4
(Min) 0.48 x ETC x DF/MF (Max) 0.52 x ETC x DF/MF (Min) 0.467 x ETC x DF/MF (Max) 0.533 x ETC x DF/MF
- with PLL enabled and MF > 4
Internal Clock Cycle Time Instruction Cycle Time
TC ICYC
ETC x DF/MF 2 x TC
(See Note 1)
NOTES: 1. 2. The "E" in ETH, ETL, and ETC means external. MF is the PCTL Multiplication Factor bits (MF0 - MF11). DF is the PCTL Division Factor bits (DF0 - DF3).
MOTOROLA
DSP56005 Data Sheet
23
AC Electrical Characteristics Clock
Clock
The DSP56005 system clock may be derived from the on-chip crystal oscillator as shown in Figure 3, or it may be externally supplied. An externally supplied square wave voltage source should be connected to EXTAL, leaving XTAL physically unconnected (see Figure 4) to the board or socket. The rise and fall time of this external clock should be 3 ns maximum. When using a crystal to provide a clock input, the frequency must be greater than 500 kHz. This restriction does not apply when providing an external clock to the EXTAL pin.
XTAL R
EXTAL
EXTAL R1 C1
XTAL R2
C
XTAL1
C
L1
C2
XTAL1*
C3
Fundamental Frequency Crystal Oscillator Suggested Component Values R = 680 k 10% C = 20 pF 20%
3rd Overtone Crystal Oscillator Suggested Component Values R1 = 470 k 10% R2 = 330 10% C1 = 0.1 F 20% C2 = 26 pF 20% C3 = 20 pF 10% L1 = 2.37 H 10% XTAL = 50 MHz, AT cut, 20 pF load, 50 max series resistance NOTES:
1. *3rd overtone crystal. 2. The suggested crystal source is ICM, # 471163 - 50.00 (50 MHz 3rd overtone, 20 pF load). 3. R2 limits crystal current. 4. Reference Benjamin Parzen, The Design of Crystal and Other Harmonic Oscillators, John Wiley & Sons, 1983.
NOTES:
1. The suggested crystal source is ICM, # 433163 - 4.00 (4 MHz fundamental, 20 pF load) 2. To reduce system cost, a ceramic resonator may be used instead of the crystal. Suggested source: Murata-Erie #CST4.00MGW040 (4 MHz fundamental)
Figure 3 Crystal Oscillator Circuits
24
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Clock
VILC EXTAL ETH
1 3
Midpoint VIHC ETL
2
ETC
4
NOTE: The midpoint is VILC + 0.5 (VIHC - VILC).
Figure 4 External Clock Timing
Table 10 Clock Operation 50 MHz Num Characteristics
Frequency of Operation (EXTAL Pin) 1 Clock Input High (See Note) ETH 9.34 8.5 235500 235500 409600 819200 ns ns
Symbol Min
f 0
Unit Max
50 MHz
* with PLL disabled (46.7% - 53.3% duty cycle) * with PLL enabled (42.5% - 57.5% duty cycle)
2 Clock Input Low (See Note)
* with PLL disabled (46.7% - 53.3% duty cycle) * with PLL enabled (42.5% - 57.5% duty cycle)
3 Clock Cycle Time
ETL
9.34 8.5
ns ns
* with PLL disabled * with PLL enabled
4 Instruction Cycle Time = ICYC = 2 x TC (See Note)
ETC
20 20
ns ns
* with PLL disabled * with PLL enabled
ICYC
40 40
ns ns
NOTE: External Clock Input High and External Clock Input Low are measured at 50% of the input transition.
MOTOROLA
DSP56005 Data Sheet
25
AC Electrical Characteristics PLL
Phase-Locked Loop (PLL)
Table 11 Phase-Locked Loop Characteristics Characteristics
VCO frequency when PLL enabled PLL external capacitor (PCAP pin to VCCP)
Expression
MF x Ef (See Notes 1,2) MF x Cpcap (See Note 4) @ MF < 4 @ MF > 4
Min
10
Max
f (See Note 3) MF x 480 MF x 970
Unit
MHz
MF x 340 MF x 380
pF
NOTES: 1. 2. 3. 4. The "E" in Ef, ETH, ETL, and ETC means external. MF is the PCTL Multiplication Factor bits (MF0 - MF11). DF is the PCTL Division Factor bits (DF0 - DF3). The maximum VCO frequency is limited to the internal operation frequency. Cpcap is the value of the PLL capacitor (connected between PCAP pin and VCCP) for MF=1. The recommended value for Cpcap is 400 pF for MF 4 and 540 pF for MF > 4.
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DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing
Reset, Stop, Mode Select, and Interrupt Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Loads
WS = Number of wait states (1 WS = TC) programmed into external bus access using BCR (WS = 0 - 15)
Table 12 Reset, Stop, Mode Select, and Interrupt Timing 50 MHz Num
9
Characteristics Min
Delay from RESET Assertion to Address High Impedance (periodically sampled and not 100% tested) Minimum Stabilization Duration * Internal Oscillator PLL Disabled (See Note 1) * External Clock PLL Disabled (See Note 2) * External Clock PLL Enabled (See Note 2) Delay from Asynchronous RESET Deassertion to First External Address Output (Internal Reset Deassertion) Synchronous Reset Setup Time from RESET Deassertion to CKOUT Falling Edge Synchronous Reset Delay Time from the CKOUT Falling Edge to the First External Address Output Mode Select Setup Time Mode Select Hold Time Minimum Edge-Triggered Interrupt Request Assertion Width Minimum Edge-Triggered Interrupt Request Deassertion Width Delay from IRQA, IRQB, NMI Assertion to External Memory Access Address Out Valid * Caused by First Interrupt Instruction Fetch * Caused by First Interrupt Instruction Execution Delay from IRQA, IRQB, NMI Assertion to General Purpose Transfer Output Valid caused by First Interrupt Instruction Execution Delay from Address Output Valid caused by First Interrupt Instruction Execute to Interrupt Request Deassertion for Level Sensitive Fast Interrupts (See Note 3) Delay from RD Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts (See Note 3) Delay from WR Assertion to Interrupt Request Deassertion for Level Sensitive Fast Interrupts * WS = 0 * WS > 0 (See Note 3) -- 75000 x TC 25 x TC 2500 x TC 8 x TC
Unit Max
26 -- -- -- 9 x TC + 20 TC 8 x TC + 6 -- -- -- -- ns ns ns ns ns
10
11 12 13 14 15 16 16a 17
8.5 8 x TC 21 0 13 13
ns ns ns ns ns ns
5 x TC + TH 9 x TC + TH
-- --
ns ns
18
11 x TC + TH -- --
-- 2 TC + TL + (TC x WS) - 23 2TC + (TC x WS) - 21
ns ns ns
19
20 21
-- --
2 x TC - 21 TC + TL + (TC x WS) - 21
ns ns
MOTOROLA
DSP56005 Data Sheet
27
AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing
Table 12 Reset, Stop, Mode Select, and Interrupt Timing Num
22
(continued)
50 MHz Characteristics Min
Delay from General-Purpose Output Valid to Interrupt Request Deassertion for Level Sensitive Fast Interrupts If Second Interrupt Instruction is: * Single Cycle * Two Cycles (See Note 3) Synchronous Interrupt Setup Time from IRQA, IRQB, NMI Assertion to the CKOUT transition #2 Synchronous Interrupt Delay Time from the CKOUT transition #2 to the First External Address Output Valid caused by the First Instruction Fetch after coming out of Wait State Duration for IRQA Assertion to Recover from Stop State Delay from IRQA Assertion to Fetch of First Interrupt Instruction (when exiting `Stop') * Internal Crystal Oscillator Clock, OMR bit 6 = 0 * Stable External Clock, OMR bit 6 = 1 * Stable External Clock, PCTL bit 17 = 1 (See Note 1) Duration of Level Sensitive IRQA Assertion to ensure interrupt service (when exiting `Stop') * Internal Crystal Oscillator Clock, OMR bit 6 = 0 * Stable External Clock, OMR bit 6 = 1 * Stable External Clock, PCTL bit 17 = 1 (See Note 1) Delay from Level Sensitive IRQA Assertion to Fetch of First Interrupt Instruction (when exiting `Stop') * Internal Crystal Oscillator Clock, OMR bit 6 = 0 * Stable External Clock, OMR bit 6 = 1 * Stable External Clock, PCTL bit 17= 1 (See Note 1)
Unit Max
-- -- 10
TL - 31 (2 x TC) + TL - 31 TC
ns ns ns
23 24
13 x TC + TH 12
13 x TC + TH + 6 --
ns ns
25 26
65548 x TC 20 x TC 13 x TC
-- -- --
ns ns ns
27
65534 x TC + TL 6 x TC + TL 12
-- -- --
ns ns ns
28
65548 x TC 20 x TC 13 x TC
-- -- --
ns ns ns
NOTES: 1. A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: * after power-on reset, and * when recovering from Stop mode. During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 x TC is typically allowed to assure that the oscillator is stable before executing programs. 2. Circuit stabilization delay is required during reset when using an external clock in two cases: * after power-on reset, and * when recovering from Stop mode. 3. When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timings 19 through 22 apply to prevent multiple interrupt service. To avoid these timing restrictions, the deassertive edge-triggered mode is recommended when using fast interrupt. Long interrupts are recommended when using level-sensitive mode.
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DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing
VIHR RESET
10 9 11
A0-A15
First Fetch
Figure 5 Reset Timing
CKOUT
12
RESET
13
A0-A15, DS, PS X/Y
Figure 6 Synchronous Reset Timing
VIHR RESET
14 15
VIHM MODA, MODB MODC VILM
VIH VIL IRQA, IRQB, NMI
Figure 7 Operating Mode Select Timing
MOTOROLA
DSP56005 Data Sheet
29
AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing
IRQA, IRQB NMI
16
IRQA, IRQB NMI
16A
Figure 8 External Interrupt Timing (Negative Edge-Triggered)
A0-A15
First Interrupt Instruction Execution/Fetch
RD
20
WR
21 19
17
IRQA IRQB NMI a) First Interrupt Instruction Execution
General Purpose I/O
18 22
IRQA IRQB NMI b) General Purpose I/O
Figure 9 External Level-Sensitive Fast Interrupt Timing
30
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Reset, Stop, Mode Select, and Interrupt Timing
CKOUT
T0, T2
T1, T3
23
IRQA, IRQB NMI
24
A0-A15, DS PS, X/Y
Figure 10 Synchronous Interrupt from Wait State Timing
25
IRQA
26
A0-A15, DS PS, X/Y
First Instruction Fetch
Figure 11 Recovery from Stop State Using IRQA
IRQA
27
28
A0-A15, DS PS, X/Y
First IRQA Interrupt Instruction Fetch
Figure 12 Recovery from Stop State Using IRQA Interrupt Service
MOTOROLA
DSP56005 Data Sheet
31
AC Electrical Characteristics Host I/O Timing
Host I/O Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Load Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications.
Table 13 Host I/O Timing 50 MHz Num
31
Characteristics Min
HEN/HACK Assertion Width (See Note 1) * CVR, ICR, ISR, RXL Read * IVR, RXH/M Read * Write HEN/HACK Deassertion Width (See Note 1) * Between Two TXL Writes (See Note 2) * Between Two CVR, ICR, ISR, RXL Reads (See Note 3) Host Data Input Setup Time Before HEN/HACK Deassertion Host Data Input Hold Time After HEN/HACK Deassertion HEN/HACK Assertion to Output Data Active from High Impedance HEN/HACK Assertion to Output Data Valid HEN/HACK Deassertion to Output Data High Impedance (See Note 5) Output Data Hold Time After HEN/HACK Deassertion (See Note 6) HR/W Low Setup Time Before HEN Assertion HR/W Low Hold Time After HEN Deassertion HR/W High Setup Time to HEN Assertion HR/W High Hold Time After HEN/HACK Deassertion HA0-HA2 Setup Time Before HEN Assertion HA0-HA2 Hold Time After HEN Deassertion DMA HACK Assertion to HREQ Deassertion (See Note 4) TC + 31 26 13 13 2 x TC + 31 2 x TC + 31 4 3 0 -- -- 2.5 0 3 0 3 0 3 3
Unit Max
-- -- -- -- -- -- -- -- -- 26 18 -- -- -- -- -- -- -- 45 ns
32
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
33 34 35 36 37 38 39 40 41 42 43 44 45
32
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Host I/O Timing
Table 13 Host I/O Timing (Continued) 50 MHz Num
46
Characteristics Min
DMA HACK Deassertion to HREQ Assertion (See Notes 4, 5) * for DMA RXL Read * for DMA TXL Write * all other cases Delay from HEN Deassertion to HREQ Assertion for RXL Read (See Notes 4, 5) Delay from HEN Deassertion to HREQ Assertion for TXL Write (See Notes 4, 5) Delay from HEN Assertion to HREQ Deassertion for RXL Read, TXL Write (See Notes 4, 5)
Unit Max
TL + TC + TH TL + TC 0 TL + TC + TH TL + TC
-- -- -- -- --
ns ns ns ns ns
47 48 49
3
58
ns
NOTES: 1. 2. 3. 4. 5. 6. See Host Port Use Considerations in the Design Considerations section of this data sheet. This timing must be adhered to only if two consecutive Writes to the TXL are executed without polling TXDE or HREQ. This timing must be adhered to only if two consecutive reads from one of these registers are executed without polling the corresponding status bits or HREQ. HREQ is pulled up by a 1k resistor. Specifications are periodically sampled and not 100% tested. May decrease to 0 ns for future versions.
MOTOROLA
DSP56005 Data Sheet
33
AC Electrical Characteristics Host I/O Timing
HREQ (Output)
31
32
HACK (Input)
41 42
HR/W (Input)
36 35 38 37
H0-H7 (Output)
Data
Valid
Figure 13 Host Interrupt Vector Register (IVR) Read
34
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Host I/O Timing
HREQ (Output)
49 47
HEN (Input)
RXH Read
31 43 32 44
RXM Read
RXL Read
HA2-HA0 (Input)
Address Valid
41 42
Address Valid
Address Valid
HR/W (Input)
36 37 38
H0-H7 (Output)
35
Data Valid
Data Valid
Data Valid
Figure 14 Host Read Cycle (Non-DMA Mode)
MOTOROLA
DSP56005 Data Sheet
35
AC Electrical Characteristics Host I/O Timing
HREQ (Output)
49 48
HEN (Input)
TXH Write
31 43 32
TXM
TXL
44
HA2-HA0 (Input) HR/W (Input)
Address Valid
39 40
Address Valid
Address Valid
33
34
H0-H7 (Input)
Data Valid
Data Valid
Data Valid
Figure 15 Host Write Cycle (Non-DMA Mode)
HREQ (Output)
45 31 32 46 46 46
HACK (Input)
36 35
RXH Read
RXM Read
37 38
RXL Read
H0-H7 (Output)
Data Valid
Data Valid
Data Valid
Figure 16 Host DMA Read Cycle
36
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Host I/O Timing
HREQ (Output)
45 31 32 46 46
HACK (Input)
TXH Write
33
TXM Write
TXL Write
34
H0-H7 (Input)
Data Valid
Data Valid
Data Valid
Figure 17 Host DMA Write Cycle
MOTOROLA
DSP56005 Data Sheet
37
AC Electrical Characteristics SCI Timing
Serial Communication Interface (SCI) Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Load, tSCC = Synchronous Clock Cycle Time (for internal clock, tSCC is determined by the SCI clock control register and TC). The minimum tSCC value is 8 x TC.
Table 14 SCI Synchronous Mode Timing 50 MHz Num
55 56 57 58 59 60 61 62 63 64 65 66
Characteristics Min
Synchronous Clock Cycle -- tSCC Clock Low Period Clock High Period < intentionally blank > Output Data Setup to Clock Falling Edge (Internal Clock) Output Data Hold After Clock Rising Edge (Internal Clock) Input Data Setup Time Before Clock Rising Edge (Internal Clock) Input Data Not Valid Before Clock Rising Edge (Internal Clock) Clock Falling Edge to Output Data Valid (External Clock) Output Data Hold After Clock Rising Edge (External Clock) Input Data Setup Time Before Clock Rising Edge (External Clock) Input Data Hold Time After Clock Rising Edge (External Clock) 8 x TC tSCC/2 - 10.5 tSCC/2 - 10.5 -- tSCC/4 + TL - 26 tSCC/4 -TL - 8 tSCC/4 + TL + 23 -- -- TC + 3 16 21
Unit Max
-- -- -- -- -- -- -- tSCC/4 + TL - 5.5 32.5 -- -- -- ns ns ns -- ns ns ns ns ns ns ns ns
Table 15 SCI Asynchronous Mode Timing -- 1X Clock 50 MHz Num
67 68 69 70 71 72
Characteristics Min
Asynchronous Clock Cycle - tACC Clock Low Period Clock High Period < intentionally blank > Output Data Setup to Clock Rising Edge (Internal Clock) Output Data Hold After Clock Rising Edge (Internal Clock) 64 x TC tACC/2 -11 tACC/2 -11 -- tACC/2 -51 tACC/2 -51
Unit Max
-- -- -- -- -- -- ns ns ns -- ns ns
38
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics SCI Timing
Internal Clock
55 57
SCLK (Output)
59
56
60
TXD
Data Valid
61 62
RXD
Data Valid
External Clock
55 57
SCLK (Input)
63
56
64
TXD
Data
Valid
65
66
RXD
Data Valid
Figure 18 SCI Synchronous Mode Timing
MOTOROLA
DSP56005 Data Sheet
39
AC Electrical Characteristics SCI Timing
67 68 69
1X SCLK (Output)
71 72
TXD
Data Valid
NOTE:
In the wire-OR mode, TXD can be pulled up by 1 K
Figure 19 SCI Asynchronous Mode Timing
40
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics SSI Timing
Synchronous Serial Interface (SSI) Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105CL = 50 pF + 2 TTL Load, tSSICC = SSI clock cycle time TXC (SCK Pin) = Transmit Clock RXC (SC0 or SCK Pin) = Receive Clock FST (SC2 Pin) = Transmit Frame Sync FSR (SC1 or SC2 Pin) = Receive Frame Sync i ck = Internal Clock x ck = External Clock g ck = Gated Clock i ck a = Internal Clock, Asynchronous Mode (Asynchronous implies that TXC and RXC are two different clocks) i ck s = Internal Clock, Synchronous Mode (Synchronous implies that TXC and RXC are the same clock) bl = bit length wl = word length
Table 16 SSI Timing 50 MHz Num
80 81 82 83 84 85 86 87
Characteristics Min
Clock Cycle-tSSICC (See Note 1) Clock High Period Clock Low Period < intentionally blank > SRD Rising Edge to FSR Out (bl) High SRD Rising Edge to FSR Out (bl) Low SRD Rising Edge to FSR Out (wl) High RXC Rising Edge to FSR Out (wl) Low 4 x TC 3 x TC tSSICC/2 - 10.8 TC + TL tSSICC/2 - 10.8 TC + TL -- -- -- -- -- -- -- -- --
Case Max
-- -- -- -- -- -- -- 40.8 25.8 35.8 25.8 35.8 20.8 35.8 20.8 i ck x ck i ck x ck i ck x ck -- x ck i ck a x ck i ck a x ck i ck a x ck i ck a
Unit
ns ns ns -- ns ns ns ns
MOTOROLA
DSP56005 Data Sheet
41
AC Electrical Characteristics SSI Timing
Table 16 SSI Timing (Continued) 50 MHz Num
88
Characteristics Min
Data In Setup Time Before RXC (SCK in Synchronous Mode) Falling Edge Data In Hold Time After RXC Falling Edge FSR Input (bl) High Before RXC Falling Edge FSR Input (wl) High Before RXC Falling Edge FSR Input Hold Time After RXC Falling Edge Flags Input Setup Before RXC Falling Edge Flags Input Hold Time After RXC Falling Edge TXC Rising Edge to FST Out (bl) High TXC Rising Edge to FST Out (bl) Low TXC Rising Edge to FST Out (wl) High TXC Rising Edge to FST Out (wl) Low TXC Rising Edge to Data Out Enable from High Impedance TXC Rising Edge to Data Out Valid -- TXC Rising Edge to Data Out High Impedance (See Note 2) TXC Falling Edge to Data Out High Impedance (See Note 2) FST Input (bl) Setup Time Before TXC Falling Edge FST Input (wl) to Data Out Enable from High Impedance -- -- -- 0.8 18.3 -- 3.3 15.8 13 18 3.3 0.8 17.4 3.3 18.3 18.3 3.3 0.8 16.7 18.3 3.3 -- -- -- -- -- -- -- -- --
Case Max
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 31.6 15.8 33.3 18.3 30.8 18.3 33.3 18.3 33.3 + TH 20.8 33.3 + TH 22.4 35.8 20.8 TC + TH x ck i ck a i ck s x ck i ck x ck i ck a x ck i ck a x ck i ck x ck i ck s x ck i ck s x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck x ck i ck g ck x ck i ck
Unit
ns
89 90 91 92 93 94 95 96 97 98 99 100 101 101A 102 103
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
-- 30.8
42
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics SSI Timing
Table 16 SSI Timing (Continued) 50 MHz Num
104 105 106
Characteristics Min
FST Input (wl) Setup Time Before TXC Falling Edge FST Input Hold Time After TXC Falling Edge Flag Output Valid After TXC Rising Edge 0.8 20.0 18.3 3.3 -- --
Case Max
-- -- -- -- 32.5 20.8 x ck i ck x ck i ck x ck i ck
Unit
ns ns ns
NOTES: 1. 2. For Internal Clock, External Clock Cycle is defined by ICYC and SSI control register. Periodically sampled, and not 100% tested.
MOTOROLA
DSP56005 Data Sheet
43
AC Electrical Characteristics SSI Timing
80
81
TXC (Input/Output)
95
82
96
FST (Bit) Out
97 98
FST (Word) Out
100 99 100 101A 101
Data Out
102 105
First Bit
Last Bit
FST (Bit) In
103 104 105
FST (Word) In
106
(See Note)
Flags Out
NOTE:
In the Network mode, output flag transitions can occur at the start of each time slot within the frame. In the Normal mode, the output flag state is asserted for the entire frame period.
Figure 20 SSI Transmitter Timing
44
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics SSI Timing
80
81
SRD (Input/Output)
84
82
85
FSR (Bit) Out
86 87
FSR (Word) Out
88 89 First 90 92 Bit Last Bit
Data In
FSR (Bit) In
91 92
FSR (Word) In
93
94
Flags In
Figure 21 SSI Receiver Timing
MOTOROLA
DSP56005 Data Sheet
45
AC Electrical Characteristics External Bus Asynchronous Timing
External Bus Asynchronous Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Load WS = Number of Wait States, Determined by BCR Register (WS = 0 to 15)
Capacitance Derating
The DSP56005 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y, EXTP) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications.
Table 17 External Bus Asynchronous Timing 50 MHz Num
120
Characteristics Min
Address Valid to WR Assertion
Unit Max
-- -- -- -- ns
* WS = 0 * WS > 0
121 WR Assertion Width
TL-6 TC-6 TC WS x TC+TL TH-6 TH-4 0 TH-7 (See Note 1) TL-0.8 WS x TC+TL-0.8 TH TC+TL-6 ((WS+1)x TC)+TL-6 0
ns
* WS = 0 * WS > 0
122 123 WR Deassertion to Address Not Valid WR Assertion to Data Out Active
-- -- --
ns ns
* WS = 0 From High Impedance * WS > 0
124 Data Out Hold Time from WR Deassertion (the maximum specification is periodically sampled, and not 100% tested) Data Out Setup Time to WR Deassertion
TH-2.5 (See Note 2)
ns
125
* WS = 0 * WS > 0
126 127 RD Deassertion to Address Not Valid Address Valid to RD Deassertion
ns
-- --
ns ns
* WS = 0 * WS > 0
128 Input Data Hold Time to RD Deassertion
--
ns
46
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics External Bus Asynchronous Timing
Table 17 External Bus Asynchronous Timing (Continued) 50 MHz Num
130
Characteristics Min
Address Valid to Input Data Valid
Unit Max
ns -- -- TL-6 -- -- TC-7 TC-4 TC-4 TC+TH-4 TC-4 TC+TH-4 TC+TL-9.5 ((WS+1) x TC)+TL-9.5 -- TC-7.5 ((WS+1) x TC)7.5 -- -- -- -- ns ns ns ns ns ns
* WS = 0 * WS > 0
131 132 Address Valid to RD Assertion RD Assertion to Input Data Valid
* WS = 0 * WS > 0
133 134 135 WR Deassertion to RD Assertion RD Deassertion to RD Assertion WR Deassertion to WR Assertion
* WS = 0 * WS > 0
136 RD Deassertion to WR Assertion
--
* WS = 0 * WS > 0
ns ns
NOTES: 1. 2. WR Deassertion to the end of valid data. WR Deassertion to data high impedance.
MOTOROLA
DSP56005 Data Sheet
47
AC Electrical Characteristics External Bus Asynchronous Timing
A0-A15, DS, PS, X/Y (See Note)
127 131 129 126 134
RD
120 135 122 121 133 136 132 123 125 130 128 124
WR
D0-D23
Data
Out
Data In
NOTE:
During Read-Modify-Write instructions, the address lines do not change state.
Figure 22 External Bus Asynchronous Timing
48
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics External Bus Synchronous Timing
External Bus Synchronous Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Load
Capacitance Derating
The DSP56005 External Bus Timing Specifications are designed and tested at the maximum capacitive load of 50 pF, including stray capacitance. Typically, the drive capability of the External Bus pins (A0-A15, D0-D23, PS, DS, RD, WR, X/Y, EXTP) derates linearly at 1 ns per 12 pF of additional capacitance from 50 pF to 250 pF of loading. Port B and C pins derate linearly at 1 ns per 5 pF of additional capacitance from 50 pF to 250 pF of loading. Active low lines should be "pulled up" in a manner consistent with the AC and DC specifications.
Table 18 External Bus Synchronous Timing 50 MHz Num Characteristics Min
140 141 CKOUT Falling Edge to Address Valid CKOUT Rising Edge to WR Assertion --
Unit Max
6.2 4.4 TH+4.4 9.1 3.9 3.4 5.4 -- -- -- -- 9.7 3.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* WS=0 (See Note 1) * WS>0
142 143 144 145 146 147 148 149 170 CKOUT Rising Edge to WR Deassertion CKOUT Rising Edge to RD Assertion CKOUT Rising Edge to RD Deassertion CKOUT Falling Edge to Data-Out Valid CKOUT Falling Edge to Data-Out Invalid (See Note 3) Data-In Valid To CKOUT Rising Edge (Setup) CKOUT Rising Edge to Data-In Invalid (Hold) CKOUT Falling Edge to Address Invalid (See Note 3) EXTAL to CKOUT -- PLL Disabled EXTAL to CKOUT -- PLL Enabled and MF < 5
-- -- 1.3 -- 0 -- 0 3.4 0 0 3 0.3
NOTES: 1. 2. 3. 4. AC timing specifications which are referenced to a device input signal are measured in production with respect to the 50% point of the respective input signal's transition. WS are Wait state values specified in the BCR. CKOUT Falling Edge to data-out invalid (specification T146) and CKOUT Falling Edge to address invalid (specification T149) indicate the time after which data/address are no longer guaranteed to be valid. Timings are given from CKOUT midpoint to VOL or VOH of the corresponding pin(s).
MOTOROLA
DSP56005 Data Sheet
49
AC Electrical Characteristics External Bus Synchronous Timing
T0
T1
T2
T3
T0
T1
T2
T3
T0
CKOUT A0-A15 DS, PS EXTP, X/Y
140 143 149 144
RD
141 142
WR
147 148
D0-D23
145
Data Out
146
Data In
EXTAL
170
NOTE:
During Read-Modify-Write Instructions, the address lines do not change states.
Figure 23 Synchronous Bus Timing
50
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics OnCE Port Timing
OnCETM Port Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Loads
Table 19 OnCE Port Timing 50 MHz Num Characteristics Min
230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 DSCK Low DSCK High DSCK Cycle Time DR Asserted to DSO (ACK) Asserted DSCK High to DSO Valid DSCK High to DSO Invalid DSI Valid to DSCK Low (Setup) DSCK Low to DSI Invalid (Hold) Last DSCK Low to OS0-OS1, ACK Active DSO (ACK) Asserted to First DSCK High DSO (ACK) Assertion Width DSO (ACK) Asserted to OS0-OS1 High Impedance (See Note 2) OS0-OS1 Valid to CKOUT Rising Edge CKOUT Rising Edge to OS0-OS1 Invalid Last DSCK Low of Read Register to First DSCK High of Next Command Last DSCK Low to DSO Invalid (Hold) DR Assertion to CKOUT Rising Edge for Wake Up from Wait State CKOUT Rising Edge to DSO After Wake Up from Wait State DR Assertion Width 40 40 200 5TC -- 3 15 3 3TC + TL 2TC 4TC + TH - 3 -- TC - 21 0 7TC + 10 3 12 17TC
Unit Max
-- -- -- -- 42 -- -- -- -- -- 5TC + 7 0 -- -- -- -- TC ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* to recover from Wait * to recover from Wait and enter DEBUG mode
249 DR Assertion to DSO (ACK) Valid (Enter Debug Mode) after Asynchronous Recovery from Wait State
15 13TC+15 17TC
12TC - 15 -- --
ns
ns
MOTOROLA
DSP56005 Data Sheet
51
AC Electrical Characteristics OnCE Port Timing
Table 19 OnCE Port Timing (Continued) 50 MHz Num
250A
Characteristics Min
DR Assertion Width to Recover from Stop
Unit Max
65548TC + TL 20TC + TL 13TC + TL ns
* Stable External Clock, OMR bit 6 = 0 * Stable External Clock, OMR bit 6 = 1 * Stable External Clock, PCTL bit 17= 1
(See Note 1) 250B DR Assertion Width to Recover from Stop and Enter Debug Mode
15 15 15
* Stable External Clock, OMR bit 6 = 0 * Stable External Clock, OMR bit 6 = 1 * Stable External Clock, PCTL bit 17= 1
(See Note 1) 251 DR Assertion to DSO (ACK) Valid (Enter Debug Mode) after Recovery from Stop State
65549TC + TL 21TC + TL 14TC + TL
-- -- --
ns
* Stable External Clock, OMR bit 6 = 0 * Stable External Clock, OMR bit 6 = 1 * Stable External Clock, PCTL bit 17= 1
(See Note 1)
65553TC + TL 25TC + TL 18TC + TL
-- -- --
ns
NOTES: 1. A clock stabilization delay is required when using the on-chip crystal oscillator in two cases: * after power-on reset * when recovering from stop mode During this stabilization period, TC, TH, and TL will not be constant. Since this stabilization period varies, a delay of 75,000 x TC is typically allowed to assure that the oscillator is stable before executing programs. While it is possible to set OMR bit 6 = 1 when using the internal crystal oscillator, it is not recommended and these specifications do not guarantee timings for that case. The maximum specified is periodically sampled and not 100% tested.
2.
52
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics OnCE Port Timing
DSCK (Input)
230 231 232
Figure 24 OnCE Serial Clock Timing
DR (Input)
233
DSO (Output)
(ACK)
Figure 25 OnCE Acknowledge Timing
DSCK (Input) DSO (Output)
(Last)
(OS1)
(ACK)
236 237 238
DSI (Input)
(OS0) (See Note)
NOTE: High Impedance, external pull-down resistor
Figure 26 OnCE Data I/O To Status Timing
MOTOROLA
DSP56005 Data Sheet
53
AC Electrical Characteristics OnCE Port Timing
DSCK (Input)
(Last) (See Note)
234 235 245
DSO (Output)
NOTE: High Impedance, external pull-down resistor
Figure 27 OnCE Read Timing
OS1 (Output)
241 240
239
(See Note)
(DSCK Input)
DSO (Output)
(DSO Output) (DSI Input)
OS0 (Output)
241
(See Note) 236
237
NOTE:
High Impedance, external pull-down resistor
Figure 28 OnCE Data I/O To Status Timing
54
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics OnCE Port Timing
CKOUT
242
OS0-OS1 (Output)
(See Note)
243
NOTE:
High Impedance, external pull-down resistor
Figure 29 OnCE CKOUT To Status Timing
DSCK (Input) (Next Command)
244
Figure 30 OnCE Read Register to Next Command Timing
CKOUT
T0, T2
T1, T3
248
DR (Input)
246 247
DSO (Output) Figure 31 Synchronous Recovery from Wait State
MOTOROLA
DSP56005 Data Sheet
55
AC Electrical Characteristics OnCE Port Timing
248
DR (Input)
249
DSO (Output)
Figure 32 Asynchronous Recovery from Wait State
DR (Input)
250
251
DSO (Output)
Figure 33 Asynchronous Recovery from Wait State
56
DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics Timer Timing
Timer Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Loads
Table 20 Timer Timing 50 MHz Num Characteristics Min
260 261 262 263 TIO Low TIO High Synchronous Timer Setup Time from TIO (input) Asssertion to CKOUT Rising Edge Synchronous Timer Delay Time from CKOUT Rising Edge to the External Memory Access Address Out Valid Caused by First Interrupt Instruction Execution CKOUT Rising Edge to TIO (output) Assertion CKOUT Rising Edge to TIO (output) Deassertion CKOUT Rising Edge to TIO (General Purpose Output) 2TC+7 2TC+7 10 5TC+TH
Unit Max
-- -- TC -- ns ns ns ns
264 265 266
0 0 0
8 8 8
ns ns ns
TIO
261 260
Figure 34 TIO Timer/ Event Input Restrictions
MOTOROLA
DSP56005 Data Sheet
57
AC Electrical Characteristics Timer Timing
CKOUT
TIO (Input) 262 ADDRESS
263
First Interrupt Instruction Execution
Figure 35 Timer Interrupt Generation
CKOUT
TIO (Output) 264 Figure 36 External Pulse Generation 265
fetch the instruction MOVE X0,X:(R0) ; X0 contains the new value of TIO 266 ; and R0 contains the address of TCSR
CKOUT A0-A15 PS, DS EXTP, X/Y
TIO (Output)
Figure 37 GPIO Output Timing 58 DSP56005 Data Sheet
MOTOROLA
AC Electrical Characteristics PWM Timing
Pulse Width Modulator (PWM) Timing
VCC = 5.0 Vdc 10%, TJ = -40 to +105C, CL = 50 pF + 2 TTL Load WPS WCN ick xck = = = = PWM Prescale Factor PWM Count Internal Clock External Clock
Table 21 PWM Timing 50 MHz Num
280 281 282 283
Characteristics Min
PWM External Clock Low (TWL) PWM External Clock High (TWH) PWM External Clock Cycle (TWC) PWM External Carrier Low TC + 3 TC + 3 2 x TC + 6 2 x TC + 3 x WPS x TC + 14 3 x TC + TWC + TWL +14 3 x TC + 1.5 x WPS x TWC + 14 15 -- 3 x TC 3 x TC 3 x TC --
Case Max
-- -- -- -- -- -- -- 2 x TC+TL+35 ick 2 x TC + 3 x WPS x TC + 35 xck WPS = 1 3 x TC + TWC + TWL + 35 xck WPS > 1 3 x TC + 1.5 x WPS x TWC + 35 2 x TC + TL + 35 ns ick xck WPS = 1 xck WPS > 1
Unit
ns ns ns ns
284 285 286
PWM External Carrier High PWM Clock Rising Edge to PWM Output Assertion PWM Carrier Rising Edge to PWM Output Assertion
ns ns ns
287
PWM Clock Rising Edge to PWM Output Deassertion PWM Output Assertion Time (See Note) Synchronous PWM Rising Edge Clock Setup Time to CKOUT Falling Edge Synchronous PWM Carrier Setup Time to CKOUT Rising Edge CKOUT Rising Edge to PWM Output Assertion for Synchronous Operation PWM Output Assertion Time In Synchronous Operation
ns
288 289
2 x WCN x WPS x TC - 3 WCN x WPS x TWC - TC - 3 12
2 x WCN x WPS x TC + 3 WCN x WPS x TWC + TC + 3 TC - 3
ick xck
ns ns
290
14
TC - 2
ns
291
2 x TC+WPS x TC + 3 2 x TC + TWL + 3 2 x TC + .5 x WPS x TWC + 3 WCN x WPS x TWC - 3
TC + 3 x WPS x TC + 26 ick TC + TWC + TWL + 26 xck WPS = 1 TC + 1.5 x WPS x TWC + 26 xck WPS > 1 WCN x WPS x TWC + 3 ns
ns
292
ns
NOTE:
If WCN=0 then the Output is not asserted at all.
MOTOROLA
DSP56005 Data Sheet
59
Electrical Characteristics PWM Timing
PWACLK PWBCLK
281 280 282
Figure 38 PWM Clock Input Restrictions
PWACn PWBC
284 283
Figure 39 PWM Carrier Input Restrictions
PWACLK PWBCLK
PWACn PWBC PWAPn PWBm
286
285
287
288
Figure 40 PWM Output Asynchronous Operation
60
DSP56005 Data Sheet
MOTOROLA
Electrical Characteristics PWM Timing
CKOUT
289
PWACLK PWBCLK PWACn PWBC PWAPn PWBm
291 292
290
Figure 41 PWM Output Synchronous Operation
MOTOROLA
DSP56005 Data Sheet
61
Pin-out and Package 144-pin TQFP Top View
Pin-out and Package Information
Top and bottom views of the Thin Quad Flat Package (TQFP) are shown in Figure 42 and Figure 43 with their pin-outs.
D0 D1 GNDD D2 D3 VCCD D4 D5 GNDD D6 D7 D8 D9 GNDD D10 D11 VCCD D12 D13 GNDD VCCQ GNDQ D14 D15 D16 D17 GNDD D18 D19 VCCD D20 D21 GNDD D22 D23 IRQD NOTES: 1. "nc" are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 2. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 3. To simplify locating the pins, each fifth pin is shaded in the illustration.
Figure 42 Top View of the DSP56005 144-pin Plastic Thin Quad Flat Package (TQFP) 62 DSP56005 Data Sheet
MOTOROLA
WR RD SRD/PC7 SC1/PC4 GNDS STD/PC8 SC2/PC5 SCK/PC6 VCCS SC0/PC3 TXD/PC1 GNDS RXD/PC0 SCLK/PC2 TIO PWAP0 PWAN0 VCCQ GNDQ PWAC0 GNDW PWAP1 PWAN1 PWAC1 VCCW PWAP2 PWAN2 PWAC2 GNDW PWACLK PWB0 PWB1 PWBC PWBCLK IRQC nc
1
A15 A14 GNDA A13 VCCA A12 A11 A10 GNDA A9 A8 A7 A6 GNDA VCCA A5 GNDQ VCCQ A4 A3 A2 GNDA A1 A0 PS VCCA DS GNDA X/Y EXTP DSI/OS0 DSO DR GNDC DSCK/OS1 VCCC
109
Orientation Mark
(Top View)
37
MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET PINIT VCCP PCAP GNDP XTAL EXTAL HA2/PB10 GNDH VCCQ GNDQ HA1/PB9 HA0/PB8 HACK/PB14 VCCH HEN/PB12 GNDH HR/W/PB11 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5 H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0
73
Pin-out and Package 144-pin TQFP Bottom View
NOTES: 4. "nc" are No Connection pins that are reserved for possible future enhancements. Do not connect these pins to any power, ground, signal traces, or vias. 5. An OVERBAR indicates the signal is asserted when the voltage = ground (active low). 6. To simplify locating the pins, each fifth pin is shaded in the illustration.
Figure 43 Bottom View of the DSP56005 144-pin Plastic Thin Quad Flat Package (TQFP)
nc IRQC PWBCLK PWBC PWB1 PWB0 PWACLK GNDW PWAC2 PWAN2 PWAP2 VCCW PWAC1 PWAN1 PWAP1 GNDW PWAC0 GNDQ VCCQ PWAN0 PWAP0 TIO SCLK/PC2 RXD/PC0 GNDS TXD/PC1 SC0/PC3 VCCS SCK/PC6 SC2/PC5 STD/PC8 GNDS SC1/PC4 SRD/PC7 RD WR
MOTOROLA
DSP56005 Data Sheet
1
MODC/NMI MODB/IRQB MODA/IRQA GNDCK CKOUT VCCCK RESET PINIT VCCP PCAP GNDP XTAL EXTAL HA2/PB10 GNDH VCCQ GNDQ HA1/PB9 HA0/PB8 HACK/PB14 VCCH HEN/PB12 GNDH HR/W/PB11 HREQ/PB13 H7/PB7 H6/PB6 GNDH H5/PB5 H4/PB4 H3/PB3 VCCH H2/PB2 GNDH H1/PB1 H0/PB0
73
IRQD D23 D22 GNDD D21 D20 VCCD D19 D18 GNDD D17 D16 D15 D14 GNDQ VCCQ GNDD D13 D12 VCCD D11 D10 GNDD D9 D8 D7 D6 GNDD D5 D4 VCCD D3 D2 GNDD D1 D0 109
Orientation Mark
(on Top side)
(Bottom View)
37
A15 A14 GNDA A13 VCCA A12 A11 A10 GNDA A9 A8 A7 A6 GNDA VCCA A5 GNDQ VCCQ A4 A3 A2 GNDA A1 A0 PS VCCA DS GNDA X/Y EXTP DSI/OS0 DSO DR GNDC DSCK/OS1 VCCC
63
Pin-out and Package Shipping Tray
Orientation Marks
Top View
5 x 12
Figure 44 DSP56005 144-pin TQFP Shipping Tray
64
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package By General Purpose I/O
MOTOROLA
DSP56005 Data Sheet
65
Pin-out and Package By Pin Number
66
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package By Pin Number
MOTOROLA
DSP56005 Data Sheet
67
Pin-out and Package By Pin Number
68
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package By Signal Name
MOTOROLA
DSP56005 Data Sheet
69
Pin-out and Package By Signal Name
70
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package By Signal Name
MOTOROLA
DSP56005 Data Sheet
71
Pin-out and Package By Signal Name
72
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package Power Supply Pins
MOTOROLA
DSP56005 Data Sheet
73
Pin-out and Package Power Supply Pins
74
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package
MOTOROLA
DSP56005 Data Sheet
75
Pin-out and Package

76
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package
Table 25 DSP56005 Power Supply Pins "005PV" 144-pin TQFP Pin 113 123 134 111 117 122 130 136 144 142 67 69 79 92 103 76 82 89 95 100 106 GNDD Data Bus Buffers VCCC GNDC VCCCK GNDCK VCCD Clock Bus Control Buffers GNDA Address Bus Buffers
Power Supply
Circuit Supplied
VCCA
MOTOROLA
DSP56005 Data Sheet
77
Pin-out and Package
Table 25 DSP56005 Power Supply Pins (Continued) "005PV" 144-pin TQFP Pin 41 52 39 45 50 58 18 57 88 126 19 56 87 125 64 62 25 21 29 9 5 12 GNDS GNDW VCCS Serial Port VCCP GNDP VCCW Pulse Width Modulator PLL GNDQ VCCQ Internal Logic GNDH
Power Supply
Circuit Supplied
VCCH Host Interface Buffers
78
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package
MOTOROLA
DSP56005 Data Sheet
79
Pin-out and Package
S
0.204 (0.008) M T L S - M S
N
S
A
0.508 (0.020) M T L S - M S PIN 1 IDENT 1 144
N
S
J1 J1
108
109
-L-, -M-, -N-
Z VIEW Y
3 PL
NOTES:
B V
1. Dimensioning and tolerancing per ANSI Y14.5M, 1982. 2. Controlling dimension: millimeter. 3. Datum plane -H- is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. Datums -L-, -M- and -N- to be determined at datum plane -H-. 5. Dimensions S and V to be determined at seating plane -T-. 6. Dimensions A and B do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. Dimensions A and B do include mold mismatch and are determined at datum plane -H-. 7. Dimension D does not include dambar protrusion. Allowable dambar protrusion shall be 0.08 (0.003) total in excess of the Ddimension at maximum material condition. MILLIMETERS MIN MAX
19.900 19.900 1.400 0.170 1.350 0.160 0.500 BSC 0.130 0.450 21.900 21.900 0.050 0.250 BSC 0.100 0.100 1.000 REF 0.150 REF 0.150 05 05 0.250 85 85 0.150 0.180 0.750 22.100 22.100 0.150 20.100 20.100 1.600 0.280 1.450 0.270
VIEW Y
36 37 72 73
0.508 (0.020) M T L S - M 0.204 (0.008) M T L S - M E C
S S
N N
S S
-H-
W
G 140 PL
PLATING
0.102 (0.004) -T- SEATING
PLANE
F
VIEW P
INCHES
MIN 0.783 0.783 0.056 0.0067 0.054 0.063 0.197 BSC 0.005 0.018 0.863 0.863 0.002 0.007 0.029 0.870 0.870 0.006 MAX 0.791 0.791 0.062 0.0110 0.057 0.011
J
B1
DIM
A B BASE METAL
D
0.13 (0.005) M T L-M S
C D
NS 12 2 PL A1 1 R1
E F G J K S V W
SECTION J1-J1 144 PL (ROTATED 90)
SEATING PLANE
-HR2
Z A1 B1 C1
0.0098 BSC 0.004 0.004 0.039 REF 0.006 REF 0.006 05 05 0.010 85 85 0.006
VIEW P
K C1 2
R1 R2 1 2
80
DSP56005 Data Sheet
MOTOROLA
Pin-out and Package
Figure 45 DSP56005 144-pin TQFP Mechanical Information
MOTOROLA
DSP56005 Data Sheet
81
Design Considerations Heat Dissipation
Design Considerations
Heat Dissipation
The average chip junction temperature, TJ, in C, can be obtained from: TJ = TA + (PD x JA) (1) outside ambient (CA). These terms are related by the equation: JA = JC + CA (4)
Where: TA = ambient temperature, C JA = package thermal resistance, junction-to-ambient, C/W PD = PINT + PI/O PINT = ICC x VCC watts -- chip internal power PI/O = power dissipation on input and output pins -- user determined
For most applications PI/O < PINT and PI/O can be neglected. An appropriate relationship between PD and TJ (if PI/O is neglected) is: PD = K/(TJ + 273) (2)
JC is device-related and cannot be influenced by the user. However, CA is user-dependent and can be minimized by thermal management techniques such as heat sinks, ambient air cooling, and thermal convection. Thus, good thermal management can significantly reduce CA so that JA approximately equals JC. Values for thermal resistance presented in this document, unless estimated, were derived using the procedure described in Motorola Reliability Report 7843, "Thermal Resistance Measurement Method for MC68XX Microcomponent Devices", and are provided for design purposes only. Thermal measurements are complex and dependent on procedure and setup. User-derived values for thermal resistance may differ.
Note: Table 7, "Thermal Characteristics of the TQFP Package," on page 21 contains the package thermal values for this chip.
Solving equations (1) and (2) for K gives: K = PD x (TA + 273) + PD x JA (3)
Where: K is a constant pertaining to the particular package K can be determined from equation (2) by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving equations (1) and (2) iteratively for any value of TA. The total thermal resistance of a package (JA) can be separated into two components, JC and CA, representing the barrier to heat flow from the semiconductor junction to the package (case) surface (JC) and from the case to the
MOTOROLA
DSP56005 Data Sheet
77
Design Considerations Power, Ground, and Noise Power Consumption
Power, Ground, and Noise
Each DSP56005 VCC pin should be provided with a low-impedance path to the board's supply. Each DSP56005 GND pin should also be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on chip as shown in Table 25, "DSP56005 Power Supply Pins," on page 77. The VCC power supply should be bypassed to GND using at least four 0.1 F by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC and GND should be less than 0.5" per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on this DSP have fast rise and fall times. Printed Circuit Board (PCB) trace lengths should be minimal. This recommendation particularly applies to the address and data buses as well as the RD, WR, IRQA, IRQB, IRQC, IRQD, NMI, HEN, and HACK pins. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Power Consumption
Power dissipation is a key issue in portable DSP applications. This section describes some factors which affect current consumption. This current consumption is described by the formula: I = CxVxf where: C = f= node/pin capacitance frequency of node/pin toggle
V = voltage swing
For example, for a Port A address pin loaded with a 50 pF capacitance and operating at 5.5V with a 40 MHz clock, toggling at its maximum possible rate (which is 10 MHz), the current consumption is: I = 50 x 10-12 x 5.5 x 10 x 106 = 2.75 mA The Maximum Internal Current value (ICCI-max), reflects the maximum possible switching of the internal buses, which is not necessarily a real application case. The Typical Internal Current value (ICCI-typ) reflects the average switching of the internal buses. The following steps are recommended for applications requiring very low current consumption: 1. minimize external memory accesses; use internal memory accesses instead 2. minimize the number of pins which are switching 3. minimize the capacitive load on the pins 4. connect the unused inputs to pull-up or pull-down resistors
78
DSP56005 Data Sheet
MOTOROLA
Design Considerations Host Programming Considerations
Current consumption test code:
org p:RESET jmp org movep move move move move nop rep move rep mov clr move rep mac MAIN p:MAIN #$180000,x:$FFFD #0,r0 #0,r4 #$00FF,m0 #$00FF,m4 #256 r0,x:(r0)+ #256 r4,y:(r4)+ a l:(r0)+,a #30 x0,y0,a x:(r0)+,x0 y:(r4)+,y0 a,p:(r5) TP1 MAIN
2. Overwriting Transmit Byte Registers
The host program should not write to the transmit byte registers, TXH or TXL, unless the TXDE bit is set, indicating that the transmit byte registers are empty. This guarantees that the transmit byte registers will transfer valid data to the HRX register.
3. Synchronization of Status Bits from DSP to Host
HC, HREQ, DMA, HF3, HF2, TRDY, TXDE, and RXDF status bits are set or cleared from inside the DSP and read by the host processor (refer to DSP56005 User's Manual for descriptions of these status bits). The host can read these status bits very quickly without regard to the clock rate used by the DSP, but the state of the bit could be changing during the read operation. Generally, this is not a system problem, since the bit will be read correctly in the next pass of any host polling routine. However, if the host asserts HEN for more than timing number 31 , with a minimum cycle time of timing number 31 + 32 , then these status bits are guaranteed to be stable. Exercise care when reading status bits HF3 and HF2 as an encoded pair. If the DSP changes HF3 and HF2 from 00 to 11, there is a small probability that the host could read the bits during the transition and receive 01 or 10 instead of 11. If the combination of HF3 and HF2 has significance, the host could read the wrong combination. Therefore, read the bits twice and check for consensus.
move jmp TP1 nop jmp
Host Port Considerations
Careful synchronization is required when reading multi-bit registers that are written by another asynchronous system. This is a common problem when two asynchronous systems are connected. The situation exists in the host interface. The following paragraphs present considerations for proper operation.
Host Programming Considerations
1. Unsynchronized Reading of Receive Byte Registers
When reading receive byte registers, RXH or RXL, the host program should use interrupts or poll the RXDF flag which indicates that data is available. This assures that the data in the receive byte registers will be stable.
4. Overwriting the Host Vector
The host program should change the Host Vector register only when the Host Command bit (HC) is clear. This change will guarantee that the DSP interrupt control logic will receive a stable vector.
MOTOROLA
DSP56005 Data Sheet
79
Design Considerations Host Programming Considerations DSP Programming Considerations
5. Cancelling a Pending Host Command Exception
The host processor may elect to clear the HC bit to cancel the host command exception request at any time before it is recognized by the DSP. Because the host does not know exactly when the exception will be recognized (due to exception processing synchronization and pipeline delays), the DSP may execute the host command exception after the HC bit is cleared. For these reasons, the HV bits must not be changed at the same time that the HC bit is cleared.
DSP Programming Considerations
1. Synchronization of Status Bits from Host to DSP
DMA, HF1, HF0, and HCP, HTDE, and HRDF status bits are set or cleared by the host processor side of the interface. These bits are individually synchronized to the DSP clock. (Refer to the DSP56005 User's Manual for descriptions of these status bits.)
2. Reading HF0 and HF1 as an Encoded Pair
Care must be exercised when reading status bits HF0 and HF1 as an encoded pair, i.e., the four combinations 00, 01, 10, and 11 each have significance. A very small probability exists that the DSP will read the status bits synchronized during transition. Therefore, HF0 and HF1 should be read twice and checked for consensus.
6. Variance in the Host Interface Timing
The Host Interface (HI) may vary (e.g. due to the PLL lock time at reset). Therefore, a host which attempts to load (bootstrap) the DSP56005 should first make sure that the part has completed its HI port programming (e.g. by setting the INIT bit in ICR then polling it and waiting it to be cleared, then reading the ISR or by writing the TREQ/RREQ together with the INIT and then polling INIT, ISR, and the HREQ pin).
80
DSP56005 Data Sheet
MOTOROLA
Design Considerations Application Examples
Application Examples
The lowest cost DSP56005 based system is shown in Figure 46. It uses no run time external memory and requires only two chips, the DSP56005 and a low cost EPROM. The EPROM read access time should be less than 300 nanoseconds when the DSP56005 is operating at a clock rate of 50 MHz.
+5 V
DSP56005
DR From Open Collector Buffer MBD301* From Reset Function MBD301* From Open Collector Buffer HACK MODA/IRQA MODC/NMI
2716
PS A0-A10 11 8 CE A0-A10 D0-D7
RESET
D0-D7
MODB/IRQB PINIT NOTES: 1. *These diodes must be Schottky diodes. 2. All resistors are 15 K unless noted otherwise. 3. When in Reset, IRQA, IRQB, and NMI must be deasserted by external peripherals.
Figure 46
No Glue Logic, Low Cost Memory Port Bootstrap -- Mode 1
MOTOROLA
DSP56005 Data Sheet
81
Design Considerations Application Examples
A system with external data RAM memory requires no glue logic to select the external EPROM from bootstrap mode. PS is used to enable the EPROM and DS is used to enable the high speed data memories as shown in Figure 47.
+5 V
DSP56005
RD DR WR
From Open Collector Buffer MBD301*
X/Y A0-A10 MODA/IRQA PS MODC/NMI
HACK
11
10
A0-A9 A10 CS WE OE From Reset Function CE RESET MBD301* A0-A10
2716
D0-D7
2018 (3)
D0-D23 24
From Open Collector Buffer
8 MODB/IRQB D0-D23 PINIT
NOTES: 1. *These diodes must be Schottky diodes. 2. All resistors are 15 K unless noted otherwise. 3. When in Reset, IRQA, IRQB, and NMI must be deasserted by external peripherals.
Figure 47 Port A Bootstrap with External Data RAM -- Mode 1
82
DSP56005 Data Sheet
MOTOROLA
Design Considerations Application Examples
Figure 48 shows the DSP56005 bootstrapping via the Host Port from an MC68000.
+5 V DSP56005
DR HACK From Open Collector Buffer From Reset Function MBD301* From Open Collector Buffer MODA/IRQA MODC/NMI LS09 RESET HR/W H0-H7 HA0-HA2 MODB/IRQB F32 8 3 F32 HEN F32 F32 Address Decode +5 V 1K DTACK R/W D0-D7 A1-A3 LDS AS A4-A23
MC68000
(12.5 MHz)
PINIT NOTES: 1. *These diodes must be Schottky diodes. 2. All resistors are 15 K unless noted otherwise. 3. When in Reset, IRQA, IRQB, and NMI must be deasserted by external peripherals.
Figure 48 DSP56005 Host Bootstrap Example -- Mode 5
MOTOROLA
DSP56005 Data Sheet
83
Design Considerations Application Examples
In Figure 49, the DSP56005 is operated in mode 3 with external program memory at location $E000. The programmer can overlay the high speed on-chip P:RAM with DSP algorithms by using the MOVEM instruction.
+5 V DSP56005
RD DR HACK From Open Collector Buffer MBD301* From Reset Function PS A0-A14 15
MODA/IRQA MODC/NMI
A0-A14
CS
OE
2756 (3)
RESET D0-D23
From Open Collector Buffer
D0-D23 MODB/IRQB
24
PINIT
NOTES: 1. *These diodes must be Schottky diodes. 2. All resistors are 15 K unless noted otherwise. 3. When in Reset, IRQA, IRQB, and NMI must be deasserted by external peripherals.
Figure 49 32K Words of External Program ROM -- Mode 3
84
DSP56005 Data Sheet
MOTOROLA
Design Considerations Application Examples
Figure 50 shows a circuit which waits until VCC on the DSP56005 is at least 4.5 V before initiating a 75,000 x TC oscillator stabilization delay required for the on-chip oscillator (only 25 x TC is required for an external oscillator without the PLL or 2500 x TC for an external oscillator with the PLL enabled). This insures that the DSP is operational and stable before releasing the reset signal.
+5V
2 (2) 1 (1)
R
RESET
CDLY
MC34064 MC33064
+
1.2 VREF
1
U1
tDLY = RCDLY In
1-
VTH VIN - VOL
3 (4)
Where: tDLY = 75,000 TC minimum VIN = 5 V VTH = 2.5 V VOL = 0.4 V CDLY = 1 f 20% TC = 50 ns
Logic Reset
R = 8.2 K 5% fOSC = 20 MHz
NOTES: 1. IRQA, IRQB, and NMI must be driven to the logic levels appropriate for the application. 2. MODA, MODB, and MODC must be driven to the logic levels appropriate for the application.
Figure 50 Reset Circuit Using MC34064/MC33064
MOTOROLA
DSP56005 Data Sheet
85
Design Considerations Application Examples
Figure 51 shows the DSP56005 connected to the bus of an IBM-PC computer. This circuit is complete and does not require external ROM or RAM to load and execute code from the PC. The PAL equations and other details of this circuit are available in the application note entitled "DSP56001 Interface Techniques and Examples" (ARP11/D).
IRQA IRQB 51 DR B30 A27 A26 A25 A24 A23 A22 A17 A11 B14 B13 OSC A04 A05 A06 A07 A08 A09 A14 AEN IOR IOW 1 2 3 4 5 6 7 8 9 10 11 13 23 13 17 16 14 22 21 15 HREQ +5V
External Interrupt Sources
119 MODC/NMI 8 HACK 10 HEN 12 HR/W 121 MODA/IRQA 120 MODB/IRQB 125 RESET
PAL22V10
19
1
DSP56005
OE DIR A02 A03 A04 A05 A06 A07 A08 A09 D07 D06 D05 D04 D03 D02 D01 D00 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 14 15 17 18 19 21 23 24 H7 H6 H5 H4 H3 H2 H1 H0
MC74ACT245
A31 A30 A29
A00 A01 A02
7 HA0 6 HA1 4 HA2
NOTE: Connector is J1 of ISA Bus All series resistors are 15 K Ohms
PINIT
Figure 51 DSP56005 -to- ISA Bus Interface Schematic 86 DSP56005 Data Sheet
MOTOROLA
Ordering Information
Ordering Information
Table 26 lists the pertinent information needed to place an order. Consult a Motorola Semiconductor sales office or authorized distributor to determine availability and to order parts.
Table 26 DSP56005 Ordering Information Part
DSP56005
Supply Voltage
5V
Package Type
Plastic Thin Quad Flat Pack (TQFP)
Pin Count
144
Frequency (MHz)
50
Order Number
DSP56005PV50
MOTOROLA
DSP56005 Data Sheet
87
OnCE is a trademark of Motorola, Inc.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typical", must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and b are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
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