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| S6B0729 102 SEG / 81 COM DRIVER & CONTROLLER FOR 4 GRAY SCALE STN LCD Jun.19. 2001. Ver. 0.1 Contents in this document are subject to change without notice. No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written permission of LCD Driver IC Team. Precautions for Light Light has characteristics to move electrons in the integrated circuitry of semiconductors, therefore may change the characteristics of semiconductor devices when irradiated with light. Consequently, the users of the packages which may expose chips to external light such as COB, COG, TCP and COF must consider effective methods to block out light from reaching the IC on all parts of the surface area, the top, bottom and the sides of the chip. Follow the precautions below when using the products. 1. Consider and verify the protection of penetrating light to the IC at substrate ( board or glass) or product design stage. Always test and inspect products under the environment with no penetration of light. 2. 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X S6B0729 Specification Revision History Version 0.0 0.1 Preliminary specification (short form) Preliminary specification (full set) Content Date June 8, 2001 June 19, 2001 2 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD CONTENTS INTRODUCTION ............................................................................................................................................ 1 FEATURES .................................................................................................................................................... 1 BLOCK DIAGRAM ......................................................................................................................................... 3 PAD CONFIGURATION ......................................................................... A*u! ACC AACC3/4i AOAo 3/4E1/2AIU. PAD Center Coordinates............................................................................................................................... 6 PIN DESCRIPTION ........................................................................................................................................ 6 POWER SUPPLY .................................................................................................................................... 9 LCD DRIVER SUPPLY ............................................................................................................................ 9 SYSTEM CONTROL...............................................................................................................................10 MICROPROCESSOR INTERFACE .........................................................................................................11 LCD DRIVER OUTPUTS .........................................................................................................................13 FUNCTIONAL DESCRIPTION ...................................................................................................................... 14 MICROPROCESSOR INTERFACE .........................................................................................................14 DISPLAY DATA RAM (DDRAM) ..............................................................................................................18 LCD DISPLAY CIRCUITS .......................................................................................................................21 LCD DRIVER CIRCUIT ...........................................................................................................................26 POWER SUPPLY CIRCUITS ..................................................................................................................29 REFERECE CIRCUIT EXAMPLES ..........................................................................................................34 RESET CIRCUIT ....................................................................................................................................36 INSTRUCTION DESCRIPTION ..................................................................................................................... 37 SPECIFICATIONS ........................................................................................................................................ 60 ABSOLUTE MAXIMUM RATINGS ...........................................................................................................60 DC CHARACTERISTICS ........................................................................................................................61 AC CHARACTERISTICS .........................................................................................................................64 REFERENCE APPLICATIONS ..................................................................................................................... 68 MICROPROCESSOR INTERFACE .........................................................................................................68 CONNECTIONS BETWEEN S6B0729 AND LCD PANE L .........................................................................70 3 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD INTRODUCTION The S6B0729 is a driver & controller LSI for 4-level gray scale graphic dot-matrix liquid crystal display systems. It contains 102 segment and 81 common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI) or 8-bit parallel display data and stores in an on-chip display data RAM of 102 x 81 x 2 bits. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components. FEATURES 4-level (White, Light Gray, Dark Gray, Black) Gray Scale Display with PWM and FRC Methods DDRAM data [2n: 2n+1] Gray scale 00 White 01 Light gray 10 Dark gray 11 Dark (Accessible column address, n = 0, 1, 2, ......, 99, 100, 101) Driver Output Circuits - 102 segment outputs / 81 common outputs Applicable Duty Ratios Duty ratio 1/16 ~ 1/80 (ICON disabled) 1/17 ~ 1/81 (ICON enabled) - - - - - - - - - - - - - Various partial display Partial window moving & data scrolling Capacity: 81 x 102 x 2 = 16,524bits Applicable LCD bias 1/4 to 1/10 Maximum display area 81 x 102 On-chip Display Data RAM Microprocessor Interface 8-bit parallel bi-directional interface with 6800-series or 8080-series SPI (serial peripheral interface) available (only write operation) On-chip Low Power Analog Circuit On-chip oscillator circuit Voltage converter (x3, x4, x5) Voltage regulator (temperature coefficient: -0.125%/C, or external input) On-chip electronic contrast control function (64 steps) Voltage follower (LCD bias :1/4 to 1/10) Operating Voltage Range Supply voltage (VDD): 1.8 to 3.3V Converter input voltage(Vci): 2.4 to 3.3 V LCD driving voltage (VLCD = V0 - VSS): 4.0 to 11.0 V 1 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Low Power Consumption - - - 60 Typ. (operation) : Vdd=Vci=2.5V, VLCD=9.004V, x5 boosting, No load 2 Max. (sleep mode) Gold bumped chip or TCP Package Type 2 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD BLOCK DIAGRAM SEG100 SEG101 COMS0 COM39 COM40 COM79 COMS1 SEG99 COM0 SEG0 SEG1 SEG2 : : : : VDD V0 V1 V2 V3 V4 VSS 41 COMMON DRIVER CIRCUITS 102 SEGMENT DRIVER CIRCUITS 41 COMMON DRIVER CIRCUITS DISPLAY DATA CONTROL CIRCUIT V/F CIRCUIT COMMON OUTPUT CONTROLLER CIRCUIT PAGE LINE I/O DISPLAY DATA RAM ADDRESS ADDRESS BUFFER 81X102X2= 16,524 Bits CIRCUIT CIRCUIT VR INTRS REF VEXT V/R CIRCUIT DISPLAY TIMING GENERATOR CIRCUIT COLUMN ADDRESS CIRCUIT OSCILLATOR VCI C1C1+ C2C2+ C3+ C4+ VOUT OSC1 V/C CIRCUIT STATUS REGISTER BUS HOLDER INSTRUCTION REGISTER INSTRUCTION DECODER MPU INTERFACE (PARALLEL & SERIAL) DB0 DB1 DB2 DB3 DB4 DB5 DB6(SCLK) DB7(SID) RW_WR E_RD RS CS1B PS0 PS1 RESETB TESTs Figure 1. Block Diagram 3 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X PIN DESCRIPTION POWER SUPPLY Table 3. Power Supply Pin Description Name VDD VSS I/O Supply Supply Power supply Ground LCD driver supply voltages The voltage determined by LCD pixel is impedance-converted by an operational amplifier for application. Voltages should have the following relationship; V0 V1 V2 V3 V4 VSS When the internal power circuit is active, these voltages are generated as following table according to the state of LCD bias. LCD bias 1/N bias V1 (N-1) / N x V0 V2 (N-2) / N x V0 V3 (2/N) x V0 V4 (1/N) x V0 Description V0 V1 V2 V3 V4 I/O NOTE: N = 4,5,9,10 LCD DRIVER SUPPLY Table 4. LCD Driver Supply Pin Description Name C1C1+ C2C2+ C3+ C4+ V0 VOUT VCl VR I/O O O O O O O I/O I/O I I Description Capacitor 1 negative connection pin for voltage converter Capacitor 1 positive connection pin for voltage converter Capacitor 2 negative connection pin for voltage converter Capacitor 2 positive connection pin for voltage converter Capacitor 3 positive connection pin for voltage converter Capacitor 4 positive connection pin for voltage converter LCD Power supply input / output pin Connect this pin to VSS through capacitor Voltage converter input / output pin Connect this pin to VSS through capacitor Voltage converter input voltage pin V0 voltage adjustment pin It is valid only when on-chip resistors are not used (INTRS = "L") When using internal resistors (INTRS = "H"), open this pin Selects the external VREF voltage via the VEXT pin - REF = "H": using the internal VREF - REF = "L": using the external VREF Externally input reference voltage (VREF) for the internal voltage regulator It is valid only when REF is "L" When using internal voltage regulator, connect to VDD, VSS or open this pin REF I VEXT I 4 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD OSC1 I When using internal clock oscillator, connect a resistor between OSC1 and VDD. 5 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X SYSTEM CONTROL Table 5. System Control Pin Description Name I/O Description Internal resistor select pin This pin selects the resistors for adjusting V0 voltage level - INTRS = "H": use the internal resistors. - INTRS = "L": use the external resistors VR pin and external resistive divider control V0 voltage Test pins Don't use this pin. - TESTs: Open this pin. INTRS I TESTs O 6 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD MICROPROCESSOR INTERFACE Table 6. Microprocessor Interface Pin Description Name RESETB I/O I Description Reset input pin When RESETB is "L", initialization is executed. Parallel / Serial data input select input PS0 PS0 I H L Interface mode Parallel Serial Data / instruction RS RS or None Data DB0 to DB7 SID (DB7) Read / Write E_RD RW_WR Write only Serial clock SCLK (DB6) *NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5 are high impedance and E_RD and RW_WR must be fixed to either "H" or "L". Microprocessor interface select input pin - PS0 = "H" , PS1 = "H": 6800-series parallel MPU interface - PS0 = "H" , PS1 = "L": 8080-series parallel MPU interface - PS0 = "L" , PS1 = "H": 4 pin-SPI MPU interface - PS0 = "L" , PS1 = "L": 3 pin-SPI MPU interface CSB I Chip select input pins Data/instruction I/O is enabled only when CSB is "L". When chip select is non-active, DB0 to DB7 may be high impedance. Register select input pin - RS = "H": DB0 to DB7 are display data - RS = "L": DB0 to DB7 are control data Read / Write execution control pin C68 H RW_WR I L 8080-series /WR MPU type 6800-series RW_WR RW Description Read / Write control input pin - RW = "H" : read - RW = "L" : write Write enable clock input pin The data on DB0 to DB7 are latched at the rising edge of the /WR signal. PS1 I RS I 7 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Table 7. Microprocessor Interface Pin Description (Continued) Name I/O Read / Write execution control pin PS1 MPU Type E_RD Description Read / Write control input pin - RW = "H": When E is "H", DB0 to DB7 are in an output status. - RW = "L": The data on DB0 to DB7 are latched at the falling edge of the E signal. Read enable clock input pin When /RD is "L", DB0 to DB7 are in an output status. Description E_RD I H 6800-series E L 8080-series /RD DB0 to DB7 I/O 8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data bus. When the serial interface selected (PS0 = "L"); - DB0 to DB5: high impedance - DB6: serial input clock (SCLK) - DB7: serial input data (SID) When chip select is not active, DB0 to DB7 may be high impedance. 8 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD LCD DRIVER OUTPUTS Table 8. LCD Driver Output Pin Description Name I/O Description LCD segment driver outputs The display data and the M signal control the output voltage of segment driver. Display data SEG0 to SEG101 H O H L L Power save mode M (Internal) H L H L Segment driver output voltage Normal display V0 VSS V2 V3 VSS Reverse display V2 V3 V0 VSS VSS LCD common driver outputs The internal scanning data and M signal control the output voltage of common driver. Scan data COM0 to COM79 H O H L L Power save mode M (Internal) H L H L Common driver output voltage VSS V0 V1 V4 VSS COMS (COMS1) O Common output for the icons The output signals of two pins are same. When not used, these pins should be left open. NOTE: DUMMY - These pins should be opened (floated). 9 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X FUNCTIONAL DESCRIPTION MICROPROCESSOR INTERFACE Chip Select Input There is CSB pin for chip selection. The S6B0729 can interface with an MPU when CSB is "L". When these pins are set to any other combination, RS, E_RD, and R W_WR inputs are disabled and DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are reset. Parallel / Serial Interface S6B0729 has four types of interface with an MPU, which are two serial and two parallel interfaces. This parallel or serial interface is determined by PS pin as shown in table 9. Table 9. Parallel / Serial Interface Mode Type Parallel PS1 H L H L CSB CSB PS0 H Interface mode 6800-series MPU mode 8080-series MPU mode 4-pin SPI mode 3-pin SPI mode Serial CSB L Parallel Interface (PS0 = "H") The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by PS1 as shown in table 10. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table 11. Table 10. Microprocessor Selection for Parallel Interface PS1 H L CSB CSB CSB RS RS RS E_RD E /RD RW_WR RW /WR DB0 to DB7 DB0 to DB7 DB0 to DB7 MPU bus 6800-series 8080-series Table 11. Parallel Data Transfer Common RS H H L L 6800-series E_RD (E) H H H H RW_WR (RW) H L H L 8080-series E_RD (/RD) L H L H RW_WR (/WR) H L H L Description Display data read out Display data write Register status read Writes to internal register (instruction) NOTE: When E_RD pin is always pulled high for 6800-series interface, it can be used CSB for enable signal. In this case, interface data is latched at the rising edge of CSB and the type of data transfer is determined by signals at RS, RW_WR as in case of 6800-series mode. 10 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD CS1B RS RW E DB Command Write Data Write Status Read Data Read Figure 5. 6800-Series MPU Interface protocol (PS="H", MI="H") CS1B RS /WR /RD DB Command Write Data Write Status Read Data Read Figure 6. 8080-Series MPU Interface Protocol (PS="H", MI="L") Serial Interface (PS0 = "L") When the S6B0729 is active (CSB="L"), serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal 8 -bit shift register and the 3 -bit counter are reset. The display data/command indication may be controlled either via software or the Register Select(RS) Pin, based on the setting of PS1. When the RS pin is used (PS1 = "H"), data is display data when RS is high, and command data when RS is low. When RS is not used (PS1 = "L"), the LCD Driver will receive command from MCU by default. If messages on the data pin are data rather than command, MCU should send Data Direction command(11101000) to control the data direction and then one more command to define the number of data bytes will be write. After these two continuous commands are send, the following messages will be data rather than command. Serial data can be read on the rising edge of serial clock going into DB6 and processed as 8-bit parallel data on the eighth serial clock. And the DDRAM column address pointer will be increased by one automatically. The next bytes after the display data string is handled as command data. 11 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Serial mode 4-Pin SPI mode 3-Pin SPI mode PS0 L L PS1 H L CSB CSB CSB RS Used Not used 4-pin SPI Mode (PS0 = "L" , PS1 = "H") CSB SID DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DB7 DB6 SCLK RS Figure 2. 4-pin SPI Timing (RS is used) 12 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD 3-pin SPI Mode (PS0 = "L" , PS1 = "L") To write data to the DDRAM, send Data Direction Command in 3-pin SPI mode. Data is latched at the rising edge of SCLK. And the DDRAM column address pointer will be increased by one automatically. CSB 0 SCLK 3 Byte (1) 23 0 1 78 15 0 829 830 831 2 Byte (2) 104 Byte Data In (1) SID Page MSB LSB DDC ( No. of DATA (1) Set Page and Column Address. Set Page Address : 1 0 1 1 P3 P2 P1 P0 Set Column Address MSB : 0 0 0 1 0 Y6 Y5 Y4 Set Column Address LSB : 0 0 0 0 Y3 Y2 Y1 Y0 (2) Set DDC(Data Direction Command) and No. of Data Bytes. Set Data Direction Command( For SPI mode Only): 11101 000 Set No. of Data Bytes : D7 D6 D5 D4 D3 D2 D1 D0 (3) This figure is example for 104 Data bytes to be transfered . Figure 3. 3-pin SPI Timing (RS is not used) This command is used in 3-pin SPI mode only. It will be two continuous commands, the first byte controls the data direction and informs the LCD driver the second byte will be number of data bytes will be write. After these two commands sending out, the following messages will be data. If data is stopped in transmitting, it is not valid data. New data will be transferred serially with most significant bit first. NOTE: In spite of transmission of data, if CSB will be disable, state terminates abnormally. Next state is initialized. Busy Flag The Busy Flag indicates whether the S6B0729 is operating or not. When DB7 is "H" in read status operation, this device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor needs not to check this flag before each instruction, which improves the MPU performance. 13 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Data Transfer The S6B0729 uses bus holder and internal data bus for data transfer with the MPU. When writing data from the MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 5. And when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder (dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 6. This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of address sets is executed. Therefore, the data of the specified address cannot be output with the read display data instruction right after the address sets, but can be output at the second read of data. MPU signals RS /WR N D(N) D(N+1) D(N+2) D(N+3) DB0 to DB7 Internal signals /WR N D(N) D(N+1) D(N+2) D(N+3) BUS HOLDER COLUMN ADDRESS N N+1 N+2 N+3 Figure 4. Write Timing 14 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD MPU signals RS /WR /RD DB0 to DB7 N Dummy D(N) D(N+1) D(N+2) Internal signals /WR /RD BUS HOLDER COLUMN ADDRESS N N D(N) N+1 D(N+1) N+2 D(N+2) N+3 Figure 5. Read Timing 15 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X DISPLAY DATA RAM (DDRAM) The Display Data RAM stores pixel data for the LCD. It is 81-row (10 page by 8 bits & icon page by 1 bit) by 102-column addressable array. Each pixel can be selected when the page and column addresses are specified. Data is read from or written to the 8 lines of each page directly through DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD controller operates independently, data can be written into RAM at the same time as data is being displayed without causing the LCD flicker. Page Address Circuit This circuit is for providing a Page Address to D isplay Data RAM shown in figure 8. It incorporates 4 -bit Page Address register changed by only the "Set Page" instruction. Page address 11 is a special RAM area for the icons and display data DB0 is only valid. Line Address Circuit This circuit assigns DDRAM a Line Address corresponding to the first line (COM0) of the display. Therefore, by setting Line Address repeatedly, it is possible to realize the screen scrolling and page switching without changing the contents of on-chip RAM as shown in figure 8. It incorporates 7-bit Line Address register changed by only the initial display line instruction and 7-bit counter circuit. At the beginning of each LCD frame, the contents of register are copied to the line counter which is increased by CL signal and generates the line address for transferring the 102-bit RAM data to the display data latch circuit. 16 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Column Address Circuit Column Address Circuit has an 8-bit preset counter that provides Column Address to the D isplay Data RAM as shown in figure 8. When set Column Address MSB / LSB instruction is issued, 7-bit [Y7:Y1] are set and lowest bit, Y0 is set to "0". Since this address is increased by 1 each a read or write data instruction, microprocessor can access the display data continuously. However, the counter is not increased and locked if a non-existing address above 65H. It is unlocked if a column address is set again by set Column Address MSB / LSB instruction. And the column address counter is independent of page address counter. ADC select instruction makes it possible to invert the relationship between the Column Address and the segment outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the following figure 7. SEG output Column address [Y7:Y1] Internal column address [Y7:Y0] Display data (ADC = 0) LCD panel display SEG 0 00H 00 HEX 1 01 HEX 1 SEG 1 01H 02 HEX 1 03 HEX 0 SEG 2 02H 04 HEX 0 05 HEX 0 SEG 3 03H 06 HEX 0 07 HEX 1 ... ... ... ... ... ... ... ... ... ... SEG 98 62H C4 HEX 1 C5 HEX 0 SEG 99 63H C6 HEX 1 C7 HEX 1 SEG 100 64H C8 HEX 0 C9 HEX 0 SEG 101 65H CA HEX 0 CB HEX 1 Display data (ADC = 1) LCD panel display 0 1 0 0 1 1 1 0 ... ... ... ... 0 1 0 0 1 0 1 1 Figure 7. The Relationship between the Column Address and The Segment Outputs Segment Control Circuit This circuit controls the display data by the display ON / OFF, reverse display ON / OFF and entire display ON / OFF instructions without changing the data in the display data RAM. 17 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Page Address DB3 DB2 DB1 DB0 Data DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 Line Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Initial line register = 08H COM Output COM72 COM73 COM74 COM75 COM76 COM77 COM78 COM79 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 0 0 0 0 Page 0 End = 07H Start = 08H 1/73Duty 1/81Duty 0 0 0 1 Page 1 0 0 1 0 Page 2 0 0 1 1 Page 3 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DB0 Page 7 Page 8 Page9 Page 9 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH Page 10 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63 COM64 COM65 COM66 COM67 COM68 COM69 COM70 COM71 COMS Column Address ADC=0 ADC=1 00 01 02 03 04 05 65 64 63 62 61 60 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 ------------- 60 61 62 63 64 65 05 04 03 02 01 00 Initial start line address = 08H SEG100 SEG101 SEG96 SEG97 SEG98 SEG99 LCD Output Figure 8. Display Data RAM Map 18 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD LCD DISPLAY CIRCUITS FRC (Frame Rate Control) and PWM (Pulse Width Modulation) Function Circuit The S6B0729 incorporates an FRC function and a PWM function circuit to display a 4-level gray scale. The FRC function and PWM utilize liquid crystal characteristics whose transmittance is changed by an effective value of applied voltage. The S6B0729 provides four 4-bit palette-registers to assign the desired gray level. These registers are set by the instructions and the RESETB. - Gray Scale Table of 4 FRC (Frame Rate Control) Gray scale level White Light gray Dark gray Black - MSB (DB7 to DB4) 2nd FR (FR2) 4th FR (FR4) 2nd FR (FR2) 4th FR (FR4) 2nd FR (FR2) 4th FR (FR4) 2nd FR (FR2) 4th FR (FR4) LSB (DB3 to DB0) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) Gray Scale Table of 3 FRC (Frame Rate Control) Gray scale level White Light gray MSB (DB7 to DB4) 2nd FR (FR2) xxxx 2nd FR (FR2) xxxx 2nd FR (FR2) xxxx 2nd FR (FR2) xxxx LSB (DB3 to DB0) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) 1st FR (FR1) 3rd FR (FR3) Dark gray Black 19 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X - Gray Scale Table of 15 PWM (Pulse Width Modulation) Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 4-bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM (on width) 0 (0/15) 1/15 2/15 3/15 4/15 5/15 6/15 7/15 8/15 9/15 10/15 11/15 12/15 13/15 14/15 1 (15/15) Darker Note Brighter - Gray Scale Table of 12 PWM (Pulse Width Modulation) Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 4-bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM (on width) 0 (0/12) 1/12 2/12 3/12 4/12 5/12 6/12 7/12 8/12 9/12 10/12 11/12 1 (12/12) 0/12 0/12 0/12 This area is selected to OFF level (0/12 level) Note Brighter Darker 20 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD - Gray Scale Table of 9 PWM (Pulse Width Modulation) Dec 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Hex 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 4-bits 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 PWM (on width) 0 (0/9) 1/9 2/9 3/9 4/9 5/9 6/9 7/9 8/9 1 (9/9) 0/9 0/9 0/9 0/9 0/9 0/9 This area is selected to OFF level (0/9 level) Note Brighter Darker 21 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Oscillator This is on-chip Oscillator with external resistor. Its frequency is controlled by external resistor between OSC1 and VDD. This oscillator signal is used in the voltage converter and display timing generation circuit. Display Timing Generator Circuit This circuit generates some signals to be used for displaying LCD. The display clock, CL(internal), generated by oscillation clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip RAM is generated in synchronization with the display clock and the display data latch circuit latches the 102-bit display data in synchronization with the display clock. The display data, which is read to the LCD driver, is completely independent of the access to the display data RAM from the microprocessor. The display clock generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an internal common timing signal and start signal to the common driver. The frame signal or the line signal changes the M by setting internal instruction. Driving waveform and internal timing signal are shown in Figure 9. 12 7 12 8 1 2 3 4 5 6 7 8 9 10 11 12 95 96 97 98 99 100 101 102 1 2 3 4 5 6 CL(Internal) FR(Internal) M(Internal) V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS COM0 COM1 SEGn Figure 9. 2-frame AC Driving Waveform (Duty Ratio = 1/102) 22 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD 12 7 12 8 1 2 3 4 5 6 7 8 9 10 11 12 93 94 95 96 97 98 99 100 101 102 1 2 3 4 CL(Internal) FR(Internal) M(Internal) V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS V0 V1 V2 V3 V4 VSS COM0 COM1 SEGn Figure 10. N-Line Inversion Driving Waveform (N = 5, Duty Ratio = 1/102) 23 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X LCD DRIVER CIRCUIT This driver circuit is configured by 81-channel common drivers and 102-channel segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal. COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 VDD M VSS V0 V1 V2 COM0 V3 V4 VSS V0 V1 V2 COM1 V3 V4 VSS V0 V1 V2 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 S E G 0 S E G 1 S E G 2 S E G 3 S E G 4 COM2 V3 V4 VSS V0 V1 V2 SEG0 V3 V4 VSS V0 V1 V2 SEG1 V3 V4 VSS V0 V1 V2 SEG2 V3 V4 VSS Figure 11. Segment and Common Timing 24 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Partial Display on LCD The S6B0729 realizes the Partial Display function on LCD with low-duty driving for saving power consumption and showing the various display duty. To show the various display duty on LCD, LCD driving duty and bias are programmable via the instruction. And, built-in power supply circuits are controlled by the instruction for adjusting the LCD driving voltages ------------------------- COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 Figure 12. Reference Example for Partial Display ------------------------- COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 COM17 COM18 COM19 COM20 COM21 COM22 COM23 Figure 13. Partial Display (Partial Display Duty = 16, Initial COM0 = 0) 25 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X -- COM0 -- COM1 -- COM2 -- COM3 -- COM4 -- COM5 -- COM6 -- COM7 -- COM8 -- COM9 -- COM10 -- COM11 -- COM12 -- COM13 -- COM14 -- COM15 -- COM16 -- COM17 -- COM18 -- COM19 -- COM20 -- COM21 -- COM22 -- COM23 Figure 14. Moving Display (Partial Display Duty = 16, Initial COM0 = 8) 26 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD POWER SUPPLY CIRCUITS The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and voltage follower circuits. They are controlled by power control instruction. For details, refers to "Instruction Description". Table 12 shows the referenced combinations in using Power Supply circuits. Table 12. Recommended Power Supply Combinations User setup Only the internal power supply circuits are used Only the voltage regulator circuits and voltage follower circuits are used Only the voltage follower circuits are used Only the external power supply circuits are used Power control (VC VR VF) 111 V/C circuits ON V/R circuits ON V/F circuits ON VOUT V0 V1 to V4 Open Open Open 011 OFF ON ON External input Open Open 001 000 OFF OFF OFF OFF ON OFF Open Open External input External input Open External input 27 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Voltage Converter Circuits These circuits boost up the electric potential between VCI and Vss to 3, 4, 5 times toward positive side and boosted voltage is outputted from VOUT pin. It is possible to select the lower boosting level in any boosting circuit by "Set DC-DC Step-up" instruction. When the higher level is selected by instruction, VOUT voltage is not valid. [C1 = 1.0 to 4.7 F] Vss VOUT + Vss C1 VOUT + C1 C3+ C1- C3+ VOUT = 3 x VCI C1 C1+ VCI Vss C2+ C2 C4+ + + VOUT = 4 x VCI + + C1 C1 C1- C1+ C2+ C2 C4+ + - C1 C1 VCI Vss Figure 15. Three Times Boosting Circuit Figure 16. Four Times Boosting Circuit Vss VOUT + C1 VOUT = 5 x VCI C3+ C1C1+ C2+ C2 C4+ + + + + C1 C1 C1 C1 VCI Vss Figure 17. Five Times Boosting Circuit 28 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Voltage Regulator Circuits The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of operational-amplifier circuits shown in figure18, it is necessary to be applied internally or externally. For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the paramet er is the value selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta= 25C is shown in Table 13. Rb V0 = (1 + ) x VEV [V] ------ (Eq. 1) Ra (63 - ) VEV = (1 - ) x VREF [V] ------ (Eq. 2) 210 Table 13 . VREF Voltage at Ta = 25C REF 1 0 Temp. coefficient -0.125% / C External input VREF [ V ] 2.1 VEXT VOUT + VEV V0 Rb VR Ra VSS GND Figure 18. Internal Voltage Regulator Circuit 29 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X In Case of Using Internal Resistors, Ra and Rb (INTRS = "H") When INTRS pin is "H", resistor Ra is connected internally between VR pin and VSS, and Rb is connected between V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage". Table 14. Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0) 3-bit data settings (R2 R1 R0) 000 1 + (Rb / Ra) 2.3 001 3.0 010 3.7 011 4.4 100 5.1 101 5.8 110 6.5 111 7.2 Figure19 Shows V0 voltage measured by adjusting internal regulator register ratio (Rb / Ra) and 6-bit electronic volume registers for each temperature coefficient at Ta = 25 C. 16.00 (1, 1, 1) 14.00 12.00 10.00 8.00 6.00 4.00 2.00 0.00 0 8 16 24 32 40 48 56 63 Electronic volume register (0 to 63) Figure19. Electronic Volume Level (Temp. Coefficient = -0.125% / C) (1, 1, 0) (1, 0, 1) (1, 0 ,0) (0, 1, 1) (0, 1, 0) (0, 0, 1) (0, 0, 0) V0 voltage [V] 30 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD In Case of Using External Resistors, Ra and Rb (INTRS = "L") When INTRS pin is "L", it is necessary to connect external regulator resistor Ra between VR and VSS, and Rb between V0 and VR. Example: For the following requirements 1. LCD driver voltage, V0 = 10V 2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0) 3. Maximum current flowing Ra, Rb = 1 uA From Eq. 1 Rb 10 = (1 + ) x VEV [V] ------ (Eq. 3) Ra From Eq. 1 (63 - 32) VEV = (1 - ) x 2.1 = 1.79 [V] ------ (Eq. 4) 210 From requirement 3. 10 = 1 [uA] ------ (Eq. 5) Ra + Rb From equations Eq. 3, 4 and 5 Ra = 1.79 [M] Rb = 8.21 [M] Table 15 Shows the Range of V0 depending on the above Requirements. Table 15. The Range of V0 Electronic volume level 0 V0 8.21 ....... ....... 32 10.00 ....... ....... 63 11.73 Voltage Follower Circuits VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4), and those output impedance are converted by the Voltage Follower for increasing drive capability. Table 16 shows the relationship between V1 to V4 level and each duty ratio. Table 16. The Relationship between V1 to V4 Level and Each Duty Ratio LCD bias 1/N V1 (N-1)/N x V0 V2 (N-2)/N x V0 V3 2/N x V0 V4 1/N x V0 Remarks N = 4,5,9,10 31 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X DISCHARGE CIRCUIT When Power save mode instruction is executed or the voltages(V0,V1,V2,V3,V4) are discharged forcibly by this circuit. power supply switched off, the VLCD 32 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD REFERENCE CIRCUIT EXAMPLES [C1 = 1.0 to 4.7 [F], C2 = 0.47 to 2.0 [F]] When not using internal regulator resistors When using internal regulator resistors V DD INTRS VOUT C1 C1 C1 C1 C1 C3+ C1 C1+ C2+ C2 C4+ VR C2 C2 C2 C2 C2 V SS + + + + + V0 V1 V2 V3 V4 V SS INTRS VOUT C1 C1 C1 C1 C1 Ra C2 C2 C2 C2 C2 + + + + + Rb C3+ C1 C1+ C2+ C2 C4+ VR V0 V1 V2 V3 V4 V SS Figure 20. When Using all LCD Power Circuits (5-Time V/C: ON, V/R: ON, V/F: ON) [C2 = 0.47 to 2.0 [F]] When using internal regulator resistors V DD When not using internal regulator resistors External Power Supply INTRS VOUT C3+ C1C1+ C2+ C2C4+ VR External Power Supply INTRS VOUT C3+ C1C1+ C2+ C2C4+ VR V SS Ra C2 C2 C2 C2 C2 V SS + + + + + Rb C2 C2 C2 C2 C2 V SS - + + + + + V0 V1 V2 V3 V4 V0 V1 V2 V3 V4 Figure 21. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON) 33 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X [C2 = 0.47 to 2.0 [F]] VDD INTRS VOUT C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4 External Power Supply C2 C2 C2 C2 C2 VSS - + + + + + Figure 22. When Using some LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: ON) [C2 = 0.47 to 2.0 [F]] VDD INTRS VOUT C3+ C1C1+ C2+ C2C4+ VR V0 V1 V2 V3 V4 External Power Supply VSS Figure 23. When Not Using any Internal LCD Power Supply Circuits (V/C: OFF, V/R: OFF, V/F: OFF) 34 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD RESET CIRCUIT Setting RESETB to "L" or Reset instruction can initialize internal function. When RESETB becomes "L", following procedure is occurred. Page address: 0 Column address: 0 Read-modify-write: OFF Display ON / OFF: OFF Initial display line: 0 (first) Initial COM0 register: 0 (COM0) Partial display duty ratio: 1/80 Reverse display ON / OFF: OFF (normal) N-line inversion register: 0 (disable) Entire Display ON/OFF: OFF ICON Control register ON/OFF: OFF (ICON disable) Power control register (VC, VR, VF) = (0, 0, 0) DC-DC converter circuit = (0, 0) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 LCD bias ratio: 1/9 COM Scan Direction: 0 ADC Select: 0 Oscillator: OFF Power Save Mode: Release Display Data Length register: 0 (for SPI mode) White mode set: OFF White palette register (WG3, WG2, WG1, WG0) = (0, 0, 0, 0) Light gray mode set: OFF Light gray palette register (LG3, LG2, LG1, LG0) = (0, 0, 0, 0) Dark gray mode set: OFF Dark gray palette register (DG3, DG2, DG1, DG0) = (1, 1, 1, 1) Black mode set: OFF Black palette register (BG3, BG2, BG1, BG0) = (1, 1, 1, 1) FRC, PWM mode: 4FRC, 9PWM When RESET instruction is issued, following procedure is occurred. Page address: 0 Column address: 0 Read-modify-write: OFF Initial display line: 0 (First) Regulator resistor select register: (R2, R1, R0) = (0, 0, 0) Contrast Level: 32 Display Data Length register: 0 (for SPI mode) White mode set: OFF White palette register (WG3, WG2, WG1, WG0) = (0, 0, 0, 0) Light gray mode set: OFF Light gray palette register (LG3, LG2, LG1, LG0) = (0, 0, 0, 0) Dark gray mode set: OFF Dark gray palette register (DG3, DG2, DG1, DG0) = (1, 1, 1, 1) Black mode set: OFF Black palette register (BG3, BG2, BG1, BG0) = (1, 1, 1, 1) FRC, PWM mode: 4FRC, 9PWM While RESETB is "L" or reset instruction is executed, no instruction except read status can be accepted. Reset status appears at DB4. After DB4 becomes "L", any instruction can be accepted. RESETB must be connected to the reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential before used. 35 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X INSTRUCTION DESCRIPTION Table 17. Instruction Table Instruction Read display data Write display data Read status ICON control register ON/OFF Set page address Set column address MSB Set column address LSB Set modify-read Reset modify-read Display ON/OFF Set initial display line register RS 1 1 0 0 0 0 0 0 0 0 0 0 0 Set initial COM0 register 0 0 0 0 0 0 0 0 RW 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BS UY 1 1 0 0 1 1 1 0 x 0 x 0 x 0 x 1 1 1 O N 0 0 0 0 1 1 0 1 S6 1 C6 1 D6 1 x 1 0 0 RS E 1 1 0 0 1 1 1 0 S5 0 C5 0 D5 0 x 1 1 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 x : Don't care Description Read data from DDRAM Write data into DDRAM M0 F 0 P2 Y7 Y3 0 1 1 0 S2 1 C2 0 D2 1 N2 1 1 1 D1 S 1 P1 Y6 Y2 0 1 1 x S1 x C1 x D1 x N1 0 1 0 D0 S CN IO P0 Y5 Y1 0 0 D x S0 x C0 x D0 x N0 0 REV EON Read the internal status ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16 Set page address Set column address MSB Set column address LSB Set modify-read mode release modify-read mode D=0: display OFF D=1: display ON 2-byte instruction to specify the initial display line to realize vertical scrolling 2-byte instruction to specify the initial COM0 to realize window scrolling 2-byte instruction to set partial display duty ratio 2-byte instruction to set N-line inversion register Release N-line Inversion mode REV=0: normal display, REV=1: reverse display EON=0: normal display. EON=1: entire display ON Read data Write data M2 F 0 1 1 0 0 0 0 0 S4 0 C4 0 D4 0 N4 0 0 0 M1 F 0 P3 0 Y4 0 1 1 0 S3 0 C3 1 D3 1 N3 0 0 0 Set partial display duty ratio Set N-line inversion Release N-line inversion Reverse display ON/OFF Entire display ON/OFF 36 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Table 17. Instruction Table (Continued) Instruction Power control Select DC-DC step-up Select regulator resistor Set electronic volume register Select LCD bias RS 0 0 0 0 0 0 RW 0 0 0 0 0 0 DB7 0 0 0 1 x 0 DB6 0 1 0 0 x 1 DB5 1 1 1 0 EV5 0 DB4 0 0 0 0 EV4 1 DB3 1 0 0 0 EV3 0 DB2 VC 1 R2 0 EV2 B2 x DB1 VR DC1 R1 0 EV1 B1 x DB0 VF DC0 R0 1 EV0 B0 x x : Don't care Description Control power circuit operation Select the step-up of the internal voltage converter Select internal resistance ratio of the regulator resistor 2-byte instruction to specify the Reference voltage Select LCD bias COM bi-directional selection SHL=0: normal direction SHL=1: reverse direction SEG bi-directional selection ADC select 0 0 1 0 1 0 0 0 0 ADC ADC=0: normal direction ADC=1: reverse direction Start the built-in oscillator P=0: normal mode P=1: sleep mode Release power save mode Initialize the internal functions 2-byte instruction to specify the number of data bytes. (SPI Mode) No operation Don't use this instruction. SHL select 0 0 1 1 0 0 SHL Oscillator on start Set power save mode Release power save mode Reset Set data direction & display data length(DDL) NOP Test Instruction 0 0 0 0 x x 0 0 0 0 0 0 x x 0 0 1 1 1 1 1 D7 1 1 0 0 1 1 1 D6 1 1 1 1 1 1 1 D5 1 1 0 0 0 0 0 D4 0 1 1 1 0 0 1 D3 0 x 0 0 0 0 0 D2 0 x 1 0 0 1 0 D1 1 x 1 P 1 0 0 D0 1 x 37 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Table 17. Instruction Table (Continued) Instruction RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Description FRC(1:3FRC, 0:4FRC) PWM1 PWM0 0 0 9PWM 0 1 9PWM 1 0 12PWM 1 1 15PWM Set white mode and 1st/2nd frame Set FRC and PWM mode 0 0 1 0 0 1 0 FRC PWM1 PWM0 Set white mode and 1st/2nd frame, set pulse width Set white mode and 3rd/4th frame, set pulse width Set light gray mode and 1st/2nd frame, set pulse width Set light gray mode and 3rd/4th frame, set pulse width Set dark gray mode and 1st/2nd frame, set pulse width Set dark gray mode and 3rd/4th frame, set pulse width Set black mode and 1st/2nd frame, set pulse width Set black mode and 3rd/4th frame, set pulse width 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 WB3 1 WD3 1 LB3 1 LD3 1 DB3 1 DD3 1 BB3 1 BD3 0 WB2 0 WD2 0 LB2 0 LD2 0 DB2 0 DD2 0 BB2 0 BD2 0 WB1 0 WD1 0 LB1 0 LD1 0 DB1 0 DD1 0 BB1 0 BD1 0 WB0 0 WD0 0 LB0 0 LD0 0 DB0 0 DD0 0 BB0 0 BD0 1 WA3 1 WC3 1 LA3 1 LC3 1 DA3 1 DC3 1 BA3 1 BC3 0 WA2 0 WC2 0 LA2 0 LC2 1 DA2 1 DC2 1 BA2 1 BC2 0 WA1 0 WC1 1 LA1 1 LC1 0 DA1 0 DC1 1 BA1 1 BC1 0 WA0 1 WC0 0 LA0 1 LC0 0 DA0 1 DC0 0 BA0 1 BC0 Set white mode and 3rd/4th frame Set light gray mode and 1st/2nd f rame Set light gray mode and 3rd/4th frame Set dark gray mode and 1st/2nd frame Set dark gray mode and 3rd/4th frame Set black mode and 1st/2nd frame Set black mode and 3rd/4th frame 38 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Read Display Data 8-bit data from Display Data RAM specified by the column address and page address can be read by this instruction. As the column address is increased by 1 automatically after each this instruction, the microprocessor can continuously read data from the addressed page. A dummy read is required after loading an address into the column address register. Display Data cannot be read through the serial interface. RS 1 Write Display Data 8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column address and page address. The column address is increased by 1 automatically so that the microprocessor can continuously write data to the addressed page. During auto-increment, the column address wraps to 0 after the last column is written RS 1 RW 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RW 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 Read data Write data Set Page Address Set Column Address Data Write Column = Column + 1 YES Set Page Address Set Column Address Dummy Data Read Column = Column + 1 Data Read Column = Column + 1 YES Data Write Continue ? NO Optional Status Data Read Continue ? NO Optional Status Figure 24. Sequence for Writing Display Data Figure 25. Sequence for Reading Display Data 39 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Read Status Indicates the internal status of the S6B0729 RS 0 RW 1 DB7 BUSY DB6 ON / OFF DB5 RES DB4 MF2 DB3 MF1 DB2 MF0 DB1 DS1 DB0 DS0 Flag BUSY Description The device is busy when internal operation or reset. Any instruction is rejected until BUSY goes Low. 0: chip is active, 1: chip is being busy Indicates display ON / OFF status 0: display OFF, 1: display ON Indicates the initialization is in progress by RESET signal. 0: chip is active, 1: chip is being reset Manufacturer ID, MF2 MF1 MF0 = [0 0 0] Display size ID, DS1 DS0 = [1 0] ON / OFF RESET MF DS ICON Control Register ON/OFF This instruction makes ICON enable or disable. By default, ICON display is disabled (ICON= 0). When ICON control register is set to "1", ICON display is enabled and page address is set to "16". Then user can write data for icons. It is impossible to set the page address to "16" by Set Page Address instruction. Therefore, when writing data for icons, ICON control register ON instruction would be used to set the page address to "16". When ICON control register is set to "0", ICON display is disabled. RS RW DB7 DB6 DB5 DB4 0 DB3 0 DB2 0 DB1 1 DB0 ICON 0 0 1 0 1 ICON=0: ICON disable (default) ICON=1: ICON enable & set the page address to 16 40 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Set Page Address Sets the Page Address of display data RAM from the microprocessor into the page address register. Any RAM data bit can be accessed when its Page Address and column address are specified. Along with the column address, the Page Address defines the address of the display RAM to write or read display data. Changing the Page A ddress doesn't effect to the display status. Set Page Address instruction can not be used to set the page address to "10". Use ICON control register ON/OFF instruction to set the page address to "10". RS 0 P3 0 0 : 1 1 RW 0 P2 0 0 : 0 0 DB7 1 P1 0 0 : 0 1 DB6 0 P0 0 1 : 1 0 DB5 1 DB4 1 DB3 P3 Page 0 1 : 9 10 DB2 P2 DB1 P1 DB0 P0 Set Column Address Sets the Column Address of display RAM from the microprocessor into the column address register. Along with the Column Address, the Column Address defines the address of the display RAM to write or read display data. When the microprocessor reads or writes display data to or from display RAM, Column Addresses are automatically increased. Set Column Address MSB RS 0 RW 0 DB7 0 DB6 0 DB5 0 DB4 1 DB3 0 DB2 Y7 DB1 Y6 DB0 Y5 Set Column Address LSB RS RW DB7 0 Y7 0 0 : 1 1 0 Y6 0 0 : 1 1 0 Y5 0 0 : 0 0 DB6 0 Y4 0 0 : 0 0 DB5 0 Y3 0 0 : 1 1 DB4 0 Y2 0 0 : 0 0 DB3 Y4 Y1 0 1 : 0 1 DB2 Y3 DB1 Y2 DB0 Y1 Column address [Y7:Y1] 0 1 : 100 101 41 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Set Modify-Read This instruction stops the automatic increment of the column address by the read display data instruction, but the column address is still increased by the write display data instruction. And it reduces the load of microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This mode is canceled by the reset Modify-Read instruction. RS 0 Reset Modify-Read This instruction cancels the Modify-Read mode, and makes the column address return to its initial value just before the set Modify-Read instruction is started. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 0 Set Page Address Set Column Address (N) Set Modify-read Dummy Read Data Read Data Process Data Write NO Change Completed? YES Reset Modify-read Return Column Address (N) Figure 26. Sequence for Cursor Display 42 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Display ON / OFF Turns the display ON or OFF. This command has priority over Entire Display On/Off and Reverse Display On/Off. Commands are accepted while the display is off, but the visual state of the display does not change. RS RW DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 1 DB1 1 DB0 DON 0 0 DON = 1: display ON DON = 0: display OFF Set Initial Display Line Register Sets the line address of display RAM to determine the initial display line using 2-byte instruction. The RAM display data is displayed at the top of row(COM0) of LCD panel. The 1 Instruction RS 0 nd st RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 0 DB1 x DB0 x The 2 Instruction RS RW 0 S6 0 0 0 : 1 1 1 : 1 0 S5 0 0 0 : 0 0 0 : 1 DB7 x S4 0 0 0 : 0 0 1 : 1 DB6 S6 S3 0 0 0 : 1 1 0 : 1 DB5 S5 S2 0 0 0 : 1 1 0 : 1 DB4 S4 S1 0 0 1 : 1 1 0 : 1 DB3 S3 S0 0 1 0 : 0 1 0 : 1 DB2 S2 DB1 S1 Line address 0 1 2 : 78 79 DB0 S0 Setting Initial Display Line Start 1 st Instruction (2-byte Instruction for Mode Setting) 2nd Instruction (2-byte Instruction for R egister Setting) Setting Iinitial Display L ine End Figure 27. The Sequence for Setting the Initial Display Line 43 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Set Initial COM0 Register Sets the initial row (COM) of the LCD panel using the 2-byte instruction. By using this instruction, it is possible to realize the window moving without the change of display data. The 1 Instruction RS 0 nd st RW 0 DB7 0 DB6 1 DB5 0 DB4 0 DB3 0 DB2 1 DB1 x DB0 x The 2 Instruction RS RW 0 0 DB7 x DB6 C6 DB5 C5 DB4 C4 DB3 C3 DB2 C2 DB1 C1 DB0 C0 C6 0 0 0 0 : 1 1 1 1 C5 0 0 0 0 : 0 0 0 0 C4 0 0 0 0 : 0 0 0 0 C3 0 0 0 0 : 1 1 1 1 C2 0 0 0 0 : 1 1 1 1 C1 0 0 1 1 : 0 0 1 1 C0 0 1 0 1 : 0 1 0 1 Initial COM0 COM0 COM1 COM2 COM3 : COM76 COM77 COM78 COM79 Setting Initial COM0 Start st 1 Instruction (M ode Setting) nd 2 Instruction (Initial COM0 Setting) Setting Initial COM0 End Figure 28. Sequence for Setting the Initial COM0 44 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Set Partial Display Duty Ratio Sets the duty ratio within range of 16 to 80 (ICON disabled) or 17 to 81 (ICON enabled) to realize partial display by using the 2-byte instruction. The 1 Instruction RS RW 0 nd st DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 0 DB1 x DB0 x 0 The 2 Instruction RS RW 0 0 DB7 x DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0 D6 0 : 0 0 0 : 1 1 1 : 1 D5 0 : 0 0 0 : 0 0 0 : 1 D4 0 : 0 1 1 : 0 1 1 : 1 D3 0 : 1 0 0 : 1 0 0 : 1 D2 0 : 1 0 0 : 1 0 0 : 1 D1 0 : 1 0 0 : 1 0 0 : 1 D0 0 : 1 0 1 : 1 0 1 : 1 Selected partial duty ratio (ICON disabled) Selected partial duty ratio (ICON enabled) No operation No operation 1/16 1/17 : 1/79 1/80 No operation 1/17 1/18 : 1/80 1/81 No operation Setting Partial Display Start 1st Instruction (Mode Setting) 2nd Instruction (Partial Display Duty Setting) Setting Partial Display End Figure29. Sequence for Setting Partial Display 45 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Set N-line Inversion Register Sets the inverted line number within range of 3 to 33 to improve the display quality by controlling the phase of the internal LCD AC signal (M) by using the 2-byte instruction. The DC-bias problem could be occurred if K is even number. So, we recommend customers to set K to be odd number. K : D/N D : The number of display duty ratio (D is selectable by customers) N : N for N-line inversion (N is selectable by customers). The 1 Instruction RS RW 0 nd st DB7 0 DB6 1 DB5 0 DB4 0 DB3 1 DB2 1 DB1 x DB0 x 0 The 2 Instruction RS RW 0 0 DB7 x DB6 x DB5 x DB4 N4 DB3 N3 DB2 N2 DB1 N1 DB0 N0 N4 0 0 0 0 : 1 1 1 N3 0 0 0 0 : 1 1 1 N2 0 0 0 0 : 1 1 1 N1 0 0 1 1 : 0 1 1 N0 0 1 0 1 : 1 0 1 Selected n-line inversion 0-line inversion (frame inversion) 3-line inversion 4-line inversion 5-line inversion : 31-line inversion 32-line inversion 33-line inversion Setting N -L i n e Inversion Start 1 2 nd st Instruction (M o d e S etting) Instruction ( N -L i n e Inversion S etting) Setting N- Li n e Inversion E nd Figure 30. Sequence for N-line Inversion Release N-line Inversion Returns to the frame inversion condition from the n-line inversion condition. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 0 46 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Reverse Display ON / OFF Reverses the display status on LCD panel without rewriting the contents of the display data RAM. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 1 DB0 REV REV 0 (normal) 1 (reverse) DDRAM data = "00" - White White ("00") Dark ("11") DDRAM data = "01" - Light gray Light gray ("01") Dark gray ("10") DDRAM data = "10" - Dark gray Dark gray ("10") Light gray ("01") DDRAM data = "11" - Dark Dark ("11") White ("00") Entire Display ON / OFF Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time, the contents of the display data RAM are held. This instruction has priority over the Reverse Display ON / OFF instruction. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 1 DB1 0 DB0 EON EON 0 (normal) 1 (entire) DDRAM data = "00" - White White ("00") Dark ("11") DDRAM data = "01" - Light gray Light gray ("01") Dark ("11") DDRAM data = "10" - Dark gray Dark gray ("10") Dark ("11") DDRAM data = "11" - Dark Dark ("11") Dark ("11") Power Control Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal power supply functions can be used simultaneously. RS 0 RW 0 DB7 0 DB6 0 DB5 1 DB4 0 DB3 1 DB2 VC DB1 VR DB0 VF VC 0 1 VR VF Status of internal power supply circuits Internal voltage converter circuit is OFF Internal voltage converter circuit is ON 0 1 0 1 Internal voltage regulator circuit is OFF Internal voltage regulator circuit is ON Internal voltage follower circuit is OFF Internal voltage follower circuit is ON 47 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Select DC-DC Step-up Selects one of 3 DC-DC step-up to reduce the power consumption by this instruction. It is very useful to realize the partial display function. RS 0 RW 0 DB7 0 DB6 1 DB5 1 DB4 0 DB3 0 DB2 1 DB1 DC1 DB0 DC0 DC1 0 0 1 DC0 0 1 0 Selected DC-DC converter circuit 3 times boosting circuit 4 times boosting circuit 5 times boosting circuit Select Regulator Resistor Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator section in power supply circuit. Refer to the table 14. RS 0 R2 0 0 0 0 1 1 1 1 RW 0 R1 0 0 1 1 0 0 1 1 DB7 0 R0 0 1 0 1 0 1 0 1 DB6 0 DB5 1 DB4 0 DB3 0 1+ (Rb / Ra) 2.3 3.0 3.7 4.4 5.1 5.8 6.5 7.2 DB2 R2 DB1 R1 DB0 R0 48 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Set Electronic Volume Register Consist of 2-byte Instructions st nd The 1 instruction set Reference Voltage mode, the 2 one updates the contents of reference voltage register. After second instruction, Reference Voltage mode is released. The 1 Instruction: Set Reference Voltage Select Mode RS 0 The 2 nd st RW 0 DB7 1 DB6 0 DB5 0 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 Instruction: Set Reference Voltage Register RW 0 EV4 0 0 : : 1 1 DB7 x EV3 0 0 : : 1 1 DB6 x EV2 0 0 : : 1 1 DB5 EV5 EV1 0 0 : : 1 1 DB4 EV4 EV0 0 1 : : 0 1 DB3 EV3 DB2 EV2 DB1 EV1 DB0 EV0 RS 0 EV5 0 0 : : 1 1 Reference voltage parameter () 0 1 : : 62 63 Setting Reference Voltage Start 1 Instruction for Mode Setting 2nd Instruction for Register Setting Setting Reference Voltage End st Figure 31. Sequence for Setting the Electronic Volume 49 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Select LCD Bias Selects LCD bias ratio of the voltage required for driving the LCD. RS 0 RW 0 DB7 0 DB6 1 DB5 0 DB4 1 DB3 0 DB2 B2 DB1 B1 DB0 B0 B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 LCD bias 1/4 1/5 1/61/7 1/8 1/9 1/10 1/10 SHL Select COM output scanning direction is selected by this instruction which determines the LCD driver output status. RS 0 RW 0 DB7 1 DB6 1 DB5 0 DB4 0 DB3 SHL DB2 x DB1 x DB0 x x : Don't care SHL = 0: normal direction (COM0 COM79) SHL = 1: reverse direction (COM79 COM0) ADC Select Changes the relationship between RAM column address and segment driver. The direction of segment driver output pins could be reversed by software. This makes IC layout flexible in LCD module assembly. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 ADC ADC = 0: normal direction (SEG0 SEG101) ADC = 1: reverse direction (SEG101 SEG0) 50 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Oscillator ON Start This instruction enables the built-in oscillator circuit. RS 0 RW 0 DB7 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 1 DB0 1 Power Save The S6B0729 enters the Power Save status to reduce the power consumption to the static power consumption value and returns to the normal operation status by the following instructions. Set Power Save Mode RS RW DB7 0 0 1 P = 0: normal mode P = 1: sleep mode Release Power Save Mode RS RW DB7 0 0 1 DB6 0 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 P DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 0 DB0 1 Set Power Save Mode (Sleep Mode) Sleep Mode Oscillator Circuits: OFF LCD Power Supply Circuits: OFF All COM / SEG Output Level: VSS Consumption Current < 2uA Release Power Save Mode (Sleep Mode) Figure 32. Power Save Routine 51 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Reset This instruction Resets initial display line, column address, page address, and common output status select to their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD power supply, which is initialized by the RESETB pin. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 0 Set Data Direction & Display Data Length (3-Pin SPI Mode) Consists of 2 bytes instruction. This command is used in 3-Pin SPI mode only(PS0 = "L" and PS1 = "L"). It will be two continuous commands, the first byte control the data direction(write mode only) and inform the LCD driver the second byte will be number of data bytes will be write. When RS is not used, the Display Data Length instruction is used to indicate that a specified number of display data bytes are to be transmitted. The next byte after the display data string is handled as command data. The 1 Instruction: Set Data Direction (Only Write Mode) RS x nd st RW x DB7 1 DB6 1 DB5 1 DB4 0 DB3 1 DB2 0 DB1 0 DB0 0 The 2 Instruction: Set Display Data Length (DDL) Register RW x DB7 D7 DB6 D6 DB5 D5 DB4 D4 DB3 D3 DB2 D2 DB1 D1 DB0 D0 RS x D7 0 0 0 : 1 1 1 NOP No operation RS 0 D6 0 0 0 : 1 1 1 D5 0 0 0 : 1 1 1 D4 0 0 0 : 1 1 1 D3 0 0 0 : 1 1 1 D2 0 0 0 : 1 1 1 D1 0 0 1 : 0 1 1 D0 0 1 0 : 1 0 1 Display Data Length 1 2 3 : 254 255 256 RW 0 DB7 1 DB6 1 DB5 1 DB4 0 DB3 0 DB2 0 DB1 1 DB0 1 52 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Test Instruction This instruction is for testing IC. Please do not use it. RS 0 RW 0 DB7 1 DB6 1 DB5 1 DB4 1 DB3 x DB2 x DB1 x DB0 x Set PWM & FRC mode Selects 3/4 FRC and 9 / 12 / 15 PWM RS 0 RW 0 DB7 1 DB6 0 DB5 0 DB4 1 DB3 0 DB2 FRC DB1 PWM1 DB0 PWM0 FRC 0 1 PWM1 PWM0 Status of PWM & FRC 4FRC 3FRC 0 0 1 1 0 1 0 1 9PWM 9PWM 12PWM 15PWM 53 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Set Gray Scale Mode & Register Consists of 2 bytes instruction. The first byte sets grayscale mode and the second byte updates the contents of gray scale register without issuing any other instruction. - Set Gray Scale Mode RS 0 RW 0 DB7 1 DB6 0 DB5 0 DB4 0 DB3 1 DB2 GM2 DB1 GM1 DB0 GM0 GM2 0 0 0 0 1 1 1 1 - GM1 0 0 1 1 0 0 1 1 GM0 0 1 0 1 0 1 0 1 Description In case of setting white mode and 1 / 2 rd st st nd th frame nd th In case of setting white mode and 3 / 4 frame In case of setting light gray mode and 1 / 2 rd frame frame In case of setting light gray mode and 3 / 4 frame In case of setting dark gray mode and 1 / 2 rd st nd th In case of setting dark gray mode and 3 / 4 frame In case of setting black mode and 1 / 2 rd st nd th frame In case of setting black mode and 3 / 4 frame Set Gray Scale Register RS 0 0 GA3, GB3, GC3, GD3 0 0 : 1 1 1 1 1 1 1 RW 0 0 DB7 GB3 GD3 DB6 GB2 GD2 GA1, GB1, GC1, GD1 0 0 : 0 1 1 0 0 1 1 DB5 GB1 GD1 GA0, GB0, GC0, GD0 0 1 : 1 0 1 0 1 0 1 DB4 GB0 GD0 DB3 GA3 GC3 DB2 GA2 GC2 DB1 GA1 GC1 DB0 GA0 GC0 GA2, GB2, GC2, GD2 0 0 : 0 0 0 1 1 1 1 Pulse width (9PWM) 0/9 1/9 : 9/9 0/9 0/9 0/9 0/9 0/9 0/9 Pulse width (12PWM) 0/12 1/12 : 9/12 10/12 11/12 12/12 0/12 0/12 0/12 Pulse width (15PWM) 0/15 1/15 : 9/15 10/15 11/15 12/15 13/15 14/15 15/15 GA3=WA3,LA3,DA3,BA3 GA2=WA2,LA2,DA2,BA2 GA1=WA1,LA1,DA1,BA1 GA0=WA0,LA0,DA0,BA0 GB3=WB3,LB3,DB3,BB3 GA2=WB2,LB2,DB2,BB2 GA1=WB1,LB1,DB1,BB1 GA0=WB0,LB0,DB0,BB0 GC3=WC3,LC3,DC3,BC3 GA2=WC2,LC2,DC2,BC2 GA1=WC1,LC1,DC1,BC1 GA0=WC0,LC0,DC0,BC0 GD3=WD3,LD3,DD3,BD3 GA2=WD2,LD2,DD2,BD2 GA1=WD1,LD1,DD1,BD1 GA0=WD0,LD0,DD0,BD0 54 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Referential Instruction Set-up Flow: Initializing with the built-in Power Supply Circuits User System Setup by External Pins Start of Initialization Power ON (VDD-VSS) Keeping the RESETB Pin = "L" Waiting for Stabilizing the Power RESETB Pin = "H" User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator ON] [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Gray-scale Select] User LCD Power Setup by Internal Instructions [Voltage Converter ON] Waiting for 50% rising of VOUT User LCD Power Setup by Internal Instructions [Voltage Regulator ON] Waiting for 1ms User LCD Power Setup by Internal Instructions [Voltage Follower ON] Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 33. Initializing with the Built-in Power Supply Circuits 55 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Referential Instruction Set-up Flow: Initializing without the built-in Power Supply Circuits User System Setup by External Pins Start of Initialization Power ON (VDD-VSS) Keeping the RESETB Pin = "L" Waiting for Stabilizing the Power RESETB Pin = "H" Set Power Save User Application Setup by Internal Instructions [Display Duty Select] [ADC Select] [SHL Select] [COM0 Register Select] User LCD Power Setup by Internal Instructions [Oscillator ON] Regulator or Follower Register Select [Gray-scale Select] [Power Control] Release Power Save Waiting for Stabilizing the LCD Power Levels End of Initialization Figure 34. Initializing without the Built-in Power Supply Circuits 56 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Referential Instruction Set-up Flow: Data Displaying End of Initialization Display Data RAM Addressing by Instruction [Initial Display Line] [Set Page Address] [Set Column Address] Write Display Data by Instruction [Display Data Write] Turn Display ON / OFF Instruction [Display ON / OFF] End of Data Display Figure 35. Data Displaying Referential Instruction Set-up Flow: Power OFF Optional Status Set Power Save by Instruction Power OFF (VDD-VSS) End of Power OFF Figure 36. Power OFF 57 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Referential Instruction Set-up Flow: Partial Duty Changing Start of Partial changing Set Display OFF by Internal [Display ON / OFF] Set Sleep Mode by Internal Instruction [Power Save Mode] Set Partial Duty by Internal Instructions [Partial Display Duty Ratio Select] [Initial Display Line Register] [COM0 Register Select] User LCD Power Setup by Internal Instructions [DC-DC Step-up Register Select] [Regulator Resistor Select] [Electronic Volume Register Select] [LCD Bias Register Select] [Power Control] [Gray-scale Select] Waiting for Discharging the LCD Power Levels Release Power Save Waiting for Stabilizing the LCD Power Levels Write Display Data & Display ON by Internal Instruction [Display Data Write] [Display ON / OFF] End of Partial Changing Figure 37. Partial Duty Changing 58 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS Table 18. Absolute Maximum Ratings Parameter Supply voltage range Symbol VDD V0, VOUT V1, V2, V3, V4 External reference voltage Input voltage range Operating temperature range Storage temperature range VEXT VIN TOPR TSTR Rating - 0.3 ~ + 7.0 - 0.3 ~ +17.0 - 0.3 ~ V0 + 0.3 +0.3 ~ VDD - 0.3 ~ VDD + 0.3 - 40 ~ + 85 - 55 ~ + 125 V C C (VSS = 0V) Unit V V V NOTES: 1. VDD, V0, VOUT, V1 to V4 and VEXT are based on VSS = 0V. 2. Voltages V0 V1 V2 V3 V4 VSS must always be satisfied.(VLCD = V0 - VSS) 3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently. It is desirable to use this LSI under electrical characteristic conditions during general operation. Otherwise, this LSI may malfunction or reduced LSI reliability may result. 59 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X DC CHARACTERISTICS Table 19. DC Characteristics (VSS = 0V, VDD = 1.8 to 3.3V, Ta = -40 to 85C) Item Operating voltage (1) Operating voltage (2) Input voltage Output voltage High Low High Low Symbol VDD V0 VIH VIL VOH VOL IIL IOZ RON IOH = -0.5mA IOL = 0.5mA VIN = VDD or VSS VIN = VDD or VSS Ta = 25C, V0 = 8V Ta = 25C 1/128 Duty, 9 PWM REXT = 620k ( *11) x3/x4 Voltage converter Input voltage VCI 5 x3 / x4 / x5 VOUT voltage conversion (no-load ) 95 99 % VOUT 2.4 3.0 V Condition Min. 1.8 4.0 0.8VDD VSS 0.8VDD VSS - 1.0 - 3.0 Typ. 2.0 Max. 3.3 15.0 VDD 0.2VDD VDD 0.2VDD + 1.0 + 3.0 3.0 A A k (*3) (*5) SEGn COMn (*6) (*7) (*11) V (*4) Unit V V V Pin used VDD (*1) V0 (*2) (*3) Input leakage current Output leakage current LCD driver ON resistance Operating frequency fFR 70 85 100 Hz 2.4 - 3.3 V VCI Voltage converter output voltage Voltage regulator operating voltage Voltage follower operating voltage Reference voltage VOUT V0 VREF Ta = 25C 5.4 4.0 2.04 2.10 15.0 11.0 2.16 V V V VOUT V0 (*8) (*9) 60 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Dynamic Current Consumption when The Internal Power Supply is ON Table 20. Dynamic Current 2 (Internal Power) (VDD = 2.5V, Ta = 25C) Item Symbol Condition Vci=2.5V, V0 - Vss =9.004V, x5 boosting, duty = 1/81, normal mode (Display Off) Dynamic current consumption Vci=2.5V, V0 - Vss = 9.004V, x5 boosting, duty = 1/81, normal mode (Display On , Checker Pattern) Vci=2.5V, V0 - Vss = 10.0V, x5 boosting, duty = 1/81,on LCD module (Display On , Checker Pattern) Min. Typ. Max. Unit Pin used - 60 - (*10) IDD - 120 - (*10) 400 Current Consumption during Power Save Mode Table 21. Power Save Mode Current (VDD = 2.5V, Ta = 25C) Item Sleep mode current Symbol IDDS1 Condition During sleep Min. Typ. Max. 2 Unit Pin used (*10) 61 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Table 22. The Relationship between Oscillation Frequency and Frame Frequency Duty ratio 1/N Item fCL Fosc On-chip oscillator circuit is fFR x N fFR x PWM x 2 x N used (fOSC: oscillation frequency, fCL: display clock frequency, fFR: frame frequency, N = 16 to 129) [* Remark Solves] *1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage assurance during access from the MPU. *2. In case of external power supply is applied. *3. CSB, RS, DB0 to DB7, E_RD, RW_WR, RESETB, PS1, PS0, INTRS and REF *4. DB0 to DB7 *5. Applies when the DB0 to DB7 pins are in high i mpedance. *6. Resistance value when -0.1[mA] is applied during the ON status of the output pin SEGn or COMn. RON [k] = V[V] / 0.1[mA] (V : voltage change when -0.1[mA] is applied in the ON status.) *7. See Table 23 for the relationship between oscillation frequency and frame frequency. *8. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range. *9. On-chip reference voltage source of the voltage regulator circuit to adjust V0. *10. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU. The current consumption, when the built-in power supply circuit is ON. The current flowing through voltage regulation resistors(Rb and Ra) is not included. It does not include the current of the LCD panel capacity, wiring capacity, etc. Other conditions are 1/12 bias, 3 FRC, 9 PWM, Frame inversion, Frame freq. = 85HZ, BL=(9,9,9,0), DG=(6,6,6,0), LG=(3,3,3,0), WH=(0,0,0,0). *11. Applies when PWM method is used. When both PWM and FRC method are used, frame frequency should be increased up to more than 130Hz. So, oscillator resistor value between OSC1 and VDD pin should be reduced. 62 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD AC CHARACTERISTICS Read / Write Characteristics (8080-series MPU) RS tA S 8 0 t CY80 tP W L /RD, /WR CSB DB0 to DB7 ( Write ) tACC80 DB0 to DB7 ( Read ) tO D 8 0 0.9V D D 0.1V D D t DS80 tD H 8 0 tP W H t AH80 Figure 38. Read / Write Characteristics (8080-series MPU) Item Address setup time Address hold time System cycle time for write System cycle time for read Pulse width low Pulse width high Data setup time Data hold time Read access time Output disable time /WR /RD DB0 to DB7 Signal RS Symbol tAS80 tAH80 tCY80 tCY80 tPWL tPWH tDS80 tDH80 tACC80 tOD80 CL = 100 pF Condition (VDD = 1.8V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 150 330 60 60 40 10 15 10 50 ns ns ns ns ns Item Address setup time Address hold time System cycle time for write System cycle time for read Pulse width low Pulse width high Data setup time Data hold time Read access time Output disable time Signal RS Symbol tAS80 tAH80 tCY80 tCY80 Condition (VDD = 2.7V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 100 166 40 40 30 5 50 ns ns ns ns ns /WR /RD DB0 to DB7 tPWL tPWH tDS80 tDH80 tACC80 tOD80 CL = 100 pF 15 10 NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (tCY80 - tPWLW - tPWHW ) for write, (tr + tf) < (tCY80 - tPWLR - tPWHR ) for read 63 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Read / Write Characteristics (6800-series Microprocessor) RS, R/W tAS68 tCY68 tEWL CSB 0 .9 V D D 0 .1 V D D tE W L E DB0 to DB7 ( Write ) tA C C 6 8 DB0 to DB7 ( Read ) tO D 6 8 0.1V DD 0.9VDD tE W H tDS68 tDH68 tEWH tA H 6 8 Figure39. Read / Write Characteristics (6800-series Microprocessor) Item Address setup time Address hold time System cycle time for write System cycle time for read Enable width high Enable width low Data setup time Data hold time Read access time Output disable time E_RD (E) DB0 to DB7 Signal RS RW Symbol tAS68 tAH68 tCY68 tCY68 tEWH tEWL tDS68 tDH68 tACC68 tOD68 CL = 100 pF Condition (VDD = 1.8V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 150 330 60 60 40 10 15 10 50 ns ns ns ns ns Item Address setup time Address hold time System cycle time for write System cycle time for read Enable width high Enable width low Data setup time Data hold time Read access time Output disable time Signal RS RW Symbol tAS68 tAH68 tCY68 tCY68 Condition (VDD = 2.7V, Ta = -40 ~ +85C) Min. Max. Unit 0 0 100 166 40 40 30 5 50 ns ns ns ns ns E_RD (E) DB0 to DB7 tEWH tEWL tDS68 tDH68 tACC68 tOD68 CL = 100 pF 15 10 NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. (tr + tf) < (t CY68 - tEWHW - tEWLW ) for write, (tr + tf) < (t CY68 - tEWHR - tEWLR ) for read 64 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD Serial Interface Characteristics tCSS CSB tASS RS tCYS DB6 (SCLK) 0.9VDD 0.1VDD tWLS tDSS DB7 (SID) tCHS tAHS tWHS tDHS Figure 40. Serial Interface Characteristics (VDD = 1.8V, Ta = -40 ~ +85C) Min. Max. Unit 111 60 60 60 60 60 60 60 1/2 * tCYS ns Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CSB setup time CSB hold time Signal DB6 (SCLK) RS DB7 (SID) CSB Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS Condition ns ns ns Item Serial clock cycle SCLK high pulse width SCLK low pulse width Address setup time Address hold time Data setup time Data hold time CSB setup time CSB hold time Signal DB6 (SCLK) RS DB7 (SID) CSB Symbol tCYS tWHS tWLS tASS tAHS tDSS tDHS tCSS tCHS Condition (VDD = 2.7V, Ta = -40 ~ +85C) Min. Max. Unit 58.8 30 30 30 30 30 30 30 1/2 * tCYS ns ns ns ns NOTE: *1. The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. 65 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X Reset Input Timing tRW RESETB tR Internal status During reset Reset complete Figure 41. Reset Input Timing (VDD = 1.8 ~ 3.3V, Ta = -40 ~ +85C) Item Reset low pulse width Reset time Signal RESETB Symbol tRW tR Condition Min. 1000 Max. 1000 Unit ns ns 66 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD REFERENCE APPLICATIONS MICROPROCESSOR INTERFACE In Case of Interfacing with 6800-series (PS0 = "H", PS1 = "H") 6800-series MPU C SB RS E RW DB0 to DB7 RESETB VD D VD D C SB RS S6B0729 E_RD RW_WR DB0 to DB7 RESETB PS0 PS1 Figure 42. Interfacing with 6800-series (PS0 = "H", C68 = "H") In Case of Interfacing with 8080-series (PS0 = "H", PS1 = "L") C SB 8080-series MPU RS /RD /WR DB0 to DB7 RESETB VD D VSS C SB RS E_RD RW_WR DB0 to DB7 RESETB PS0 PS1 S6B0729 Figure 43. Interfacing with 8080-series (PS0 = "H", C68 = "L") 67 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD S6B0729X In Case of 4-pin SPI mode (PS0 = "L" , PS1 = "H" ) C SB RS C SB RS DB7(SID) MPU SID SCLK RESETB OPEN V SS VDD S6B0729 DB6(SCLK) RESETB DB0 to DB5 PS0 PS1 Figure 44. Serial Interface (PS0 = "L", PS1 = "H") In Case of 3-pin SPI mode (PS0 = "L" , PS1 = "L" ) C SB SID SCLK C SB DB7(SID) DB6(SCLK) RESETB S6B0729 MPU RESETB OPEN V SS V SS DB0 to DB5 PS0 PS1 Figure 45. Serial Interface (PS0 = "L", PS1 = "L") 68 S6B0729X 102 SEG / 81 COM DRIVER & CONTROLLER FOR STN LCD CONNECTIONS BETWEEN S6B0729 AND LCD PANEL Single Chip Configuration (1/81 Duty Configurations) COMS1 COM79 : COM40 S6B0729 (Bottom View) ........... COM39 : COM0 COMS0 COM 39 : COM 0 COMS0 S6B0729 (Top View) ............ COMS1 COM 79 : COM 40 SEG101 SEG0 SEG0 SEG101 (R) (R) 80 x 102 pixels (R) 80 x 102 pixels (R) Figure 46. SHL = 0, ADC = 1 Figure 47. SHL = 0, ADC = 0 (R) (R) 80 x 102 pixels (R) 80 x 102 pixels (R) SEG0 COMS COM0 : COM39 ........... SEG101 COM 40 : COM 79 COMS SEG101 COM79 : COM 40 COMS1 ........... SEG0 COMS0 COM 0 : COM39 S6B0729 (Bottom View) S6B0729 (Top View) Figure 48. SHL = 1, ADC = 0 Figure49. SHL = 1, ADC = 1 69 |
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