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| Under development CMOS 8-Bit Microcontroller TMP86FP24 TMP86FP24F The TMP86FP24 is a Flash type MCU which includes 48 K bytes Flash memory. It is a pin compatible with a mask ROM product of the TMP86CP24. Writing the program to built-in Flash memory, the TMP86FP24 operates as the same way as the TMP86CP24. The TMP86FP24 has a 2 K bytes BOOT ROM (masked ROM) for programming to Flash memory. Product No. TMP86FP24F Flash Memory 48 K 8 bits BOOT ROM 2K 8 bits RAM 2K 8 bits Package P-LQFP80-1212-0.50A P-LQFP80-1212-0.50A TMP86FP24F 000707EBP1 For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance / Handling Precautions. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document are subject to the foreign exchange and foreign trade laws. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. The information contained herein is subject to change without notice. 86FP24-1 2003-04-15 Under development Pin Assignments (Top View) P-LQFP80-1212-0.50A TMP86FP24 V3 V2 V1 C1 C0 WAKE VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 Note: The mask ROM product (TMP86CP24) doesn't have a BOOT function in P23 pin. (STOP/INT5) (BOOT) (INT0) (INT1) (INT2) (TC2) P20 P23 P00 P01 P02 P03 P04 (RXD/SI1) P05 (TXD/SO1) P06 (SCK1) P07 AVDD VAREF RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (SO2) P10 (SI2) P11 ( SCK2 ) P12 ( PWM5 / PDO5 /TC5) P13 (INT3/TC3) P14 (TC1) P15 P30 P31 P32 P33 P34 P35 P36 P37 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P97 (SEG8) P96 (SEG9) P95 (SEG10) P94 (SEG11) P93 (SEG12) P92 (SEG13) P91 (SEG14) P90 (SEG15) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P47 (SEG16) P46 (SEG17) P45 (SEG18) P44 (SEG19) P43 (SEG20) P42 (SEG21) P41 (SEG22) P40 (SEG23/STOP4) P53 P52 P51 ( DVO ) P50 ( PPG ) P67 (AIN7/STOP3) P66 (AIN6/STOP2) P65 (AIN5/STOP1) P64 (AIN4/STOP0) P63 (AIN3) P62 (AIN2) P61 (AIN1) P60 (AIN0) 86FP24-2 2003-04-15 Under development Block Diagram I/O Port (Segment output) Common outputs COM3 to COM0 Segment outputs SEG7 to SEG0 P97 (SEG8) P47 (SEG16) to to P90 (SEG15) P40 (SEG23) TMP86FP24 I/O Port P37 to P30 Power supply VDD VSS LCD driver circuit C0 C1 V1 V2 V3 RESET TEST P9 P4 P3 LCD power supply Address/data bus LCD voltage booster circuit TLCS-870/C CPU System control circuit Standby control circuit (Key-on wake-up) Timing generator Data memory (RAM) Program memory (Flash) BOOT ROM (mask ROM) Reset input test pin Interrupt controller Resonator connecting pins Time base timer XIN XOUT High frequency Clock generator Low frequency 16-bit timer/counter TC1 TC2 8-bit timer/counter TC3 TC5 HSIO UART SIO2 SIO1 Watchdog timer Address/data bus P2 P6 P1 P0 P5 10-bit AD converter P23 to P20 AVDD VAREF Analog reference pins P67 (AIN7) P15 to P10 to P60 (AIN0) I/O ports P07 to P00 P53 to P50 I/O ports 86FP24-3 2003-04-15 Under development Pin Funtions The TMP86FP24 has MCU mode and serial PROM mode. (1)MCU mode TMP86FP24 In the MCU mode, the TMP86FP24 is a pin compatible with the TMP86CP24 (Make sure to fix the TEST pin to low level). (2)Serial PROM mode In the Serial PROM mode, programming to Flash memory is available by executing BOOT ROM. For details, refer to "2.1 Serial PROM mode". 86FP24-4 2003-04-15 Under development 1.1 FLASH Memory Outline TMP86FP24 1.1.1 The TMP86FP24 incorporates 49152 bytes of FLASH memory (address 4000H to FFFFH). The writing to FLASH is controlled by FLASH control register (EEPCR), FLASH status register (EEPSR) and FLASH write emulate time control register (EEPEVA). To write data to the FLASH , execute the Serial PROM mode. For details about the Serial PROM mode, refer to "2.1 Serial PROM mode". The FLASH memory of the TMP86FP24 features: The FLASH memory is constructed of 384 pages FLASH and one page size is 128 bytes (384 pages 128 bytes 49512 bytes). The TMP86FP24 incorporates a 128-byte temporary data buffer. The data written to FLASH is temporarily stored in this data buffer. After 128 bytes data have been written to the temporary data buffer, the writing to FLASH automatically starts by page writing (The 128 bytes data are written to specified page of FLASH simultaneously). At the same time, page-by-page erasing occurs automatically. So, it is unnecessary to erase individual pages in advance. The FLASH control circuit incorporates an oscillator dedicated to the FLASH. So FLASH writing time is independent of the system clock frequency (fc). In addition, because an FLASH control circuit controls writing time for each FLASH cell, the writing time varies in each page (Typically 4 ms per page). Controlling the power for the FLASH control circuit (regulator and voltage step-up circuit) achieves low power consumption if the FLASH is not in use (Example. When the program is executed in RAM area). 1.1.2 Conditions for Accessing the FLASH Areas The conditions for accessing the FLASH areas vary depending on each operation mode. The following tables shows FLASH are access conditions. Table 1.1.1 FLASH Area Access Conditions Area MCU mode FLASH Memory 4000H to FFFFH Operation Mode (Note 1) Serial PROM mode (Note 2) Read/Fetch only Write/Read/Fetch supported Note1: "MCU mode" shows NORMAL1/2 and SLOW1/2 modes. Note2: "Serial PROM mode" shows the FLASH controlling mode. For details, refer to "2.1 Serial PROM mode". Note3: "Fetch" means reading operation of FLASH data as an instruction by CPU. 86FP24-5 2003-04-15 Under development 2.1 Serial PROM Mode Outline TMP86FP24 2.1.1 The TMP86FP24 has a 2 Kbytes BOOT-ROM for programming to FLASH memory. This BOOT-ROM is a mask ROM that contains a program to write the FLASH memory on-board. The BOOT-ROM is available in a serial PROM mode and it is controlled by BOOT pin (P23) and RESET pin, and is communicated via TXD (P06) and RXD (P05) pins. There are four operation modes in a serial PROM mode: FLASH writing mode, RAM loader mode, FLASH memory SUM output mode and Product discrimination code output mode. Operating area of serial PROM mode differs from that of MCU mode. The operating area of serial PROM mode shows in Table 2.1.1. Table 2.1.1 Operating Area of Serial PROM Mode Parameter Operating voltage High frequency (Note) Temperature Min 2.7 2 25 5 Max 3.6 16 Unit V MHz Note: Even though included in above operating area, part of frequency can not be supported in serial PROM mode. For details, refer to Table 2.1.4. 2.1.2 Memory Mapping The BOOT-ROM is mapped in address 3800H to 3FFFH. The Figure 2.1.1 shows a memory mapping. 0000H SFR RAM 083FH 1F80H DBR 1FFFH 3800H BOOT ROM 3FFFH 4000H FLASH memory FFFFH 49152 bytes 2048 bytes 128 bytes 003FH 0040H 64 bytes 2048 bytes Figure 2.1.1 Memory Address Maps 2.1.3 Serial PROM Mode Setting Serial PROM Mode Control Pins To execute on-board programming, start the TMP86FP24 in serial PROM mode. Setting of a serial PROM mode is shown in Table 2.1.2. Table 2.1.2 Serial PROM Mode Setting Pin TEST pin BOOT pin (P23) RESET pin Setting High 2.1.3.1 86FP24-22 2003-04-15 Under development Electrical Characteristics Absolute Maximum Ratings Parameter Supply voltage Input voltage Output voltage TMP86FP24 (VSS 0 V) Pins Rating 0.3 to 4.0 0.3 to VDD Except V3 pin V3 pin P0, P1, P20, P23, P3, P5, P6 Ports P0, P1, P2, P4, P6, P9, WAKE Ports P3, P5 Ports P0, P1, P20, P23, P3, P5, P6 Ports P0, P1, P2, P4, P6, P9, WAKE Ports P3, P5 Ports 0.3 to VDD -0.3 to 4.0 2 2 10 80 80 30 350 260 (10 s) 55 to 125 40 to 85 C mW mA 0.3 0.3 V Symbol VDD VIN VOUT1 VOUT2 IOUT1 IOUT2 IOUT3 IOUT1 Unit Output current (Per 1 pin) Output current (Total) Power dissipation [Topr Storage temperature Operating temperature 85C] IOUT2 IOUT3 PD Tsld Tstg Topr Soldering temperature (time) Note: The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is exceeded, a device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user. Thus, when designing products which include this device, ensure that no absolute maximum rating value will ever be exceeded. 86FP24-43 2003-04-15 Under development TMP86FP24 Recommended Operating Condition-1 Parameter Symbol Pins (VSS 0 V, Topr 40 to 85C) Condition Min 2.7 1.8 Max Unit fc fc 16 MHz 8 MHz NORMAL1, 2 mode IDLE0, 1, 2 mode NORMAL1, 2 mode IDLE0, 1, 2 mode SLOW1, 2 mode SLEEP0, 1, 2 mode STOP mode Supply voltage VDD 3.6 fs 32.768 kHz VIH1 Input high level VIH2 VIH3 VIL1 Input low level VIL2 VIL3 Clock frequency LCD reference voltage Capacity for LCD booster circuit fc fs V1 V2 CLCD XIN, XOUT XTIN, XTOUT Except hysteresis input Hysteresis input Except hysteresis input Hysteresis input 1.8 V VDD VDD VDD 0 0.70 0.75 0.80 VDD VDD VDD 1.0 30.0 0.8 1.6 0.1 0.30 0.25 0.20 MHz kHz V F VDD VDD VDD VDD VDD VDD VDD VDD (V3 (V3 2.7 V 2.7 V 2.7 V 2.7 V 1.8 to 3.6 V 2.7 to 3.6 V 1.8 to 3.6 V VDD) VDD) 8.0 16.0 34.0 1.2 2.4 0.47 Booster circuit is enable LCD booster circuit is enable Note: The recommended operating conditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. If the device is used under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified AC/DC values etc.), malfunction may occur. Thus, when designing products which include this device, ensure that the recommended operating conditions for the device are always adhered to. Recommended Operating Condition-2 (Serial PROM mode) Parameter Supply voltage (VSS 0 V, Topr 25C Min 2.7 5C) Max 3.6 Symbol VDD Pins 2 MHz fc Condition 16MHz Unit V Clock frequency fc XIN, XOUT VDD 2.7 to 3.6 V 2.0 16.0 MHz Note: The operating temperature area of serial PROM mode is 25C frequency of serial PROM mode is different from MCU mode. 5C and the operating area of high 86FP24-44 2003-04-15 Under development DC Characteristics Parameter Hysteresis voltage Input current TMP86FP24 (VSS 0 V, Topr Pins Hysteresis input TEST RESET 40 to 85C) Condition VDD VDD VDD VDD VDD 3.3 V 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 3.6 V, VIN 0V 3.6 V/0 V 3.6 V 3.6 V 0V 100 70 220 T.B.D. VDD VDD VDD VOUT VDD 3.6 V 3.6 V 3.6 V 3.4V / 0.2 V 3.6 V, lOH 3.6 V, IOL 0.6 mA 0.9 mA 6 V1 2 V1 3 V2 1/2 V2 3/2 00 01 10 11 00 01 10 11 Symbol VHS IIN1 IIN2 IIN4 RIN1 Min Typ. 0.4 Max 5 5 +5 Unit V A Sink-open drain, Tri-state VDD TEST pull-down RESET pull-Up Input resistance RIN2 RIN3 P21, P22 ports Programmable pull-down (P4, P9 ports) XOUT XTOUT Sink-open drain, Tri-state C-MOS, Tri-state 450 k High frequency feedback resister Low frequency feedback resister Output leakage current Output high voltage Output low voltage Output low current LCD output voltage (LCD booster is enable) RFB RFBT ILO VOH VOL IOL V2-3OUT V1-3OUT 1.2 M 14 10 3.2 0.4 V mA A Except XOUT, P3 and P5 VDD Ports P3, P5 ports V2 pin V3 pin V1 pin V3 pin VDD 3.6 V, VOL 1.0 V V3 VDD Reference supply pin: V1 SEG/COM pin: No-load V3 VDD Reference supply pin: V2 SEG/COM pin: No-load VDD fc 3.6 V V T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. T.B.D. A mA mV/ A CLCD 0.1 F LCD output current capacity (LCD booster is enable) Reference supply pin: ILCDV3 V3 pin V1 VDD fc 1V 3.6 V 16 MHz CLCD 0.1 F Reference supply pin: V2 2V Supply current in NORMAL1, 2 mode Supply current in IDLE0, 1, 2 mode Supply current in SLOW1 mode Supply current in SLEEP1 mode Supply current in SLEEP0 mode Supply current in STOP mode Fetch area Flash area VDD RAM area VIN fc fs Flash area RAM area VDD VIN fs 3.6 V 3.4 V/0.2 V 32.768 kHz 3.6 V 3.4 V/0.2 V 16 MHz 32.768 kHz MNP MNP MNP ATP MNP ATP IDD Fetch area MNP MNP MNP "1" "0" "1" "1" "0" "1" "0" MNP ATP MNP ATP MNP ATP MNP ATP VDD VIN 3.6 V 3.4 V/0.2 V Note 1: Typical values show those at Topr 25C, VDD 3.3 V. Note 2: Input current (IIN1, IIN2): The current through pull-up or pull-down resistor is not included. Note 3: IDD does not include IREF current. Note 4: The supply currents of SLOW 2 and SLEEP 2 modes are equivalent to IDLE0, 1, 2. 86FP24-45 2003-04-15 Under development TMP86FP24 Note 5: Current capacity indicates the drop in pin V3 output voltage per 1 A. Select an appropriate booster frequency setting in LCDCR 86FP24-46 2003-04-15 Under development AD Conversion Characteristics Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error TMP86FP24 40 to 85C) Typ. 1.0 VDD V 2.5 VSS VAREF T.B.D. T.B.D. 2 2 2 2 mA (VSS 0.0 V, 2.7 V Condition VDD 3.6 V, Topr Min AVDD Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Max AVDD Unit AVDD 0.0 V AVDD 0.0 V 2.7 V VAREF 3.6 V 2.7 V LSB (VSS Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error 0.0 V, 2.0 V Condition VDD 2.7 V, Topr Min AVDD 0.6 40 to 85C) Typ. Max AVDD VDD V Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Unit 2.0 VSS AVDD 0.0 V AVDD 0.0 V 2.0 V 2.0 V VAREF 2.0V T.B.D. VAREF T.B.D. 4 4 4 4 mA LSB (VSS Parameter Analog reference voltage Power supply voltage of analog control circuit Analog reference voltage range (Note 4) Analog input voltage Power supply current of analog reference voltage Non linearity error Zero point error Full scale error Total error 0.0 V, 1.8 V Condition VDD 2.0 V, Topr Min AVDD 0.1 10 to 85C) (Note 5) Typ. Max AVDD VDD V Symbol VAREF AVDD VAREF VAIN IREF VDD VSS VDD VSS VAREF Unit 1.8 VSS AVDD 0.0 V AVDD 0.0 V 1.8 V 1.8 V VAREF 1.8V T.B.D. VAREF T.B.D. 4 4 4 4 mA LSB Note 1: The total error includes all errors except a quantization error, and is defined as a maximum deviation from the ideal conversion line. Note 2: Conversion time is different in recommended value by power supply voltage. About conversion time, please refer to "2.12.2 Register Configuration". Note 3: Please use input voltage to AIN input Pin in limit of VAREF VSS. When voltage of range outside is input, conversion value becomes unsettled and gives affect to other channel conversion value. Note 4: Analog Reference Voltage Range: VAREF VAREF VSS. Note 5: When AD is used with VDD < 2.0 V, the guaranteed temperature range varies with the operating voltage. Note 6: When AD converter is not used, fix the AVDD pin on the VDD level. 86FP24-47 2003-04-15 Under development AC Characteristics Parameter (VSS 0 V, VDD 2.7 to 3.6 V, Topr Condition NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode High level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL For external clock operation (XIN input) fc 16 MHz For external clock operation (XTIN input) fs 32.768 kHz TMP86FP24 40 to 85C) Min 0.25 117.6 Symbol Typ. Max 4 Unit s 133.3 31.25 ns 15.26 s (VSS Parameter 0 V, VDD 1.8 to 3.6 V, Topr Condition 40 to 85C) Min 0.5 117.6 Symbol Typ. Max 4 Unit NORMAL1, 2 mode Machine cycle time tcy IDLE1, 2 mode SLOW1, 2 mode SLEEP1, 2 mode High level clock pulse width Low level clock pulse width High level clock pulse width Low level clock pulse width twcH twcL twcH twcL For external clock operation (XIN input) fc 8 MHz For external clock operation (XTIN input) fs 32.768 kHz s 133.3 62.5 ns 15.26 s 86FP24-48 2003-04-15 Under development UART Timing in Serial PROM Mode UART Timing-1 (VDD Parameter Time from the reception of a matching data until the output of an echo back Time from the reception of a Baud Rate Modification Data until the output of an echo back Time from the reception of an operation command until the output of an echo back Calculation time of checksum TMP86FP24 2.7 V to 3.6 V, fc 2 MHz to 16 MHz,Ta Symbol CMeb1 CMeb2 CMeb3 CKsm 25C) Required Minimum Time at fc 2 MHz at fc 16 MHz The Number of Clock (fc) Approx. 600 Approx. 700 Approx. 600 Approx. 2360000 300 s 350 s 300 s 1180 ms 37.5 s 43.7 s 37.5 s 147.5 ms UART Timing-2 (VDD Parameter 2.7 V to 3.6 V, fc 2 MHz to 16 MHz,Ta Symbol RXsup CMtr1 CMtr2 CMtr3 CMtr4 25C) Required Minimum Time at fc 2 MHz at fc 16 MHz 55 ms 14.3 ms 300 s 375 s 475 s 6.9 ms 1.8 ms 37.5 s 46.9 s 59.4 s The Number of Clock (fc) 110000 28500 600 750 950 Time from reset release until acceptance of start bit of RXD pin Time between a matching data and the next matching data Time from the echo back of matching data until the acceptance of baud rate modification data Time from the output of echo back of baud rate modification data until the acceptance of an operation command Time from the output of echo back of operation command until the acceptance of Password count storage addresses RXsup RESET pin (TMP86FP24) CMtr2 CMtr3 CMtr4 (5A) RXD pin (TMP86FP24) (5A) TXD pin (TMP86FP24) (28) (28) (30) (30) CMeb1 (5A) RXD pin (TMP86FP24) TXD pin (TMP86FP24) CMtr1 (5A) CMeb2 (5A) CMeb3 86FP24-49 2003-04-15 Under development Recommended Oscillating Conditions TMP86FP24 Note 1: An electrical shield by metal shield plate on the surface of IC package is recommended in order to protect the device from the high electric field stress applied from CRT (Cathodic Ray Tube) for continuous reliable operation. Note 2: The product numbers and specifications of the resonators by Murata Manufacturing Co., Ltd. are subject to change. For up-to-date information, please refer to the following http://www.murata.co.jp/search/index.html 86FP24-50 2003-04-15 |
Price & Availability of E03041586FP24SUMMARY
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