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| PRELIMINARY www.fairchildsemi.com FAN4272 Dual, Low Cost, +2.7V & +5V, Rail-to-Rail I/O Amplifier Features at 2.7V I I I I I I I I I General Description The FAN4272 is an ultra-low cost, low power, voltage feedback amplifier. At 5V, the FAN4272 uses only 160A of supply current per amplifier and is designed to operate from a supply range of 2.5V to 5.5V (1.25V to 2.75V). The input voltage range exceeds the negative and positive rails. The FAN4272 offers high bipolar performance at a low CMOS price. The FAN4272 offers superior dynamic performance with a 4.9MHz small signal bandwidth and 5.3V/s slew rate. The combination of low power, high bandwidth, and rail-to-rail performance make the FAN4272 well suited for battery-powered communication/computing systems. 136A supply current per amplifier 4.9MHz bandwidth Output swings to within 20mV of either rail Input voltage range exceeds the rail by >250mV 5.3V/s slew rate 16mA output current 26nV/Hz input voltage noise Directly replaces MAX4126, OPA2340, LMV822, and TLV2462 in single supply applications Available in SOIC-8 and MSOP-8 package options Applications I I I I I I I I I I Magnitude (1dB/div) Automotive applications Portable/battery-powered applications PCMCIA, USB Mobile communications, cellular phones, pagers Notebooks and PDA's Sensor Interface A/D buffer Active filters Signal conditioning Portable test instruments FAN4272 Packages SOIC Out1 -In1 +In1 -Vs 1 2 3 4 - + - 6 5 -In2 Output Voltage (0.27V/div) P + e r 8 7 +Vs Out2 +In2 8 +Vs Out2 -In2 +In2 7 6 5 m i l i 0.01 Large Signal Frequency Response Vs = 5V a n Vo = 4Vpp Vo = 2Vpp y r 10 Vo = 1Vpp 0.1 1 Frequency (MHz) Output Swing vs. Load 1.35 RL = 10k RL = 1k 0 RL = 75 RL = 100 RL = 200 RL = 75/100 MSOP Out1 -In1 +In1 -Vs 1 2 3 4 + -1.35 -2.0 0 2.0 + Input Voltage (0.4V/div) Preliminary September 2001 DATA SHEET FAN4272 FAN4272 Electrical Characteristics Parameters Case Temperature Frequency Domain Response -3dB bandwidth full power bandwidth gain bandwidth product Time Domain Response rise and fall time overshoot slew rate Distortion and Noise Response 2nd harmonic distortion 3rd harmonic distortion THD input voltage noise DC Performance input offset voltage average drift input bias current average drift power supply rejection ratio open loop gain quiescent current per channel Conditions (Vs = +2.7V, G = 2, RL = 10k to Vs/2, Rf = 5k; unless noted) TYP +25C Min & Max +25C MHz MHz MHz MHz ns % V/s dBc dBc % nV/Hz mV V/C nA pA/C dB dB A M pF V dB V V V mA V 1 UNITS NOTES G = +1, Vo = 0.02Vpp G = +2, Vo = 0.2Vpp G = +2, Vo = 2Vpp 1V step 1V step 1V step 1Vpp, 10kHz 1Vpp, 10kHz 1Vpp, 10kHz >10kHz 4.9 3.7 1.4 2.2 163 <1 5.3 -72 -72 0.03 26 0.5 4 90 32 83 90 136 12 2 -0.25 to 2.95 81 0.02 to 2.68 0.05 to 2.63 0.11 to 2.52 16 2.7 Pr Input Characteristics input resistance input capacitance input common mode voltage range common mode rejection ratio Output Characteristics output voltage swing output current power supply operating range el DC RL = 10k DC, Vcm = 0V to Vs RL = 10k to Vs/2 RL = 1k to Vs/2 RL = 200 to Vs/2 im Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. NOTES: in 1) For G = +1, Rf = 0. Absolute Maximum Ratings supply voltage 0 to +6V maximum junction temperature +175C storage temperature range -65C to +150C lead temperature (10 sec) +260C operating temperature range (recommended) -40C to +125C input voltage range +Vs + 0.5V, -Vs - 0.5V Package Thermal Resistance Package 8 lead SOIC 8 lead MSOP ar 2.5 to 5.5 JA 152C/W 206C/W y 2 Preliminary September 2001 FAN4272 DATA SHEET FAN4272 Electrical Characteristics Parameters Case Temperature Frequency Domain Response -3dB bandwidth full power bandwidth gain bandwidth product Time Domain Response rise and fall time overshoot slew rate Distortion and Noise Response 2nd harmonic distortion 3rd harmonic distortion THD input voltage noise DC Performance input offset voltage average drift input offset voltage input bias current average drift input offset current power supply rejection ratio open loop gain quiescent current per channel Input Characteristics input resistance input capacitance input common mode voltage range common mode rejection ratio Output Characteristics output voltage swing Conditions (Vs = +5V, G = 2, RL = 10k to Vs/2, Rf = 5k; unless noted) TYP +25C Min & Max +25C MHz MHz MHz MHz ns % V/s 1 UNITS NOTES G = +1, Vo = 0.02Vpp G = +2, Vo = 0.2Vpp G = +2, Vo = 2Vpp 1V step 1V step 1V step 2Vpp, 10kHz 2Vpp, 10kHz 2Vpp, 10kHz >10kHz 4.3 3.0 2.3 2.0 110 <1 9 -73 -75 0.03 27 <0.25 8 <0.7 90 40 60 80 160 2 2 450 (-40C to +125C) (-40C to +125C) DC RL = 10k DC, Vcm = 0V to Vs RL RL RL RL = = = = output current power supply operating range Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. NOTES: 1) For G = +1, Rf = 0. 2) 100% tested at +25C. P e r m i l 10k to Vs/2 10k to Vs/2 (-40C to +125C) 1k to Vs/2 200 to Vs/2 i 12 2 -0.25 to 5.25 85 a n 50 40 235 58 y r mV V/C mV nA pA/C nA dB dB A M pF V dB V V V V mA V 2 2 2 2 2 2 dBc dBc % nV/Hz 0.04 to 4.96 0.08 to 4.92 0.2 to 4.8 0.07 to 4.9 0.14 to 4.67 30 5.0 2.5 to 5.5 Preliminary September 2001 3 DATA SHEET FAN4272 FAN4272 Performance Characteristics (Vs = +2.7, G = 2, RL = 10k to Vs/2, Rf = 5k; unless noted) Non-Inverting Freq. Response Vs = +5V Normalized Magnitude (1dB/div) Vo = 0.2Vpp G=2 Rf = 5k G=1 Rf = 0 Inverting Frequency Response Vs = +5V Normalized Magnitude (1dB/div) Vo = 0.2Vpp G = -2 Rf = 5k G = -1 Rf = 5k G = 10 Rf = 5k G=5 Rf = 5k Normalized Magnitude (1dB/div) Vo = 0.2Vpp Normalized Magnitude (1dB/div) Pr 0.01 0.01 G = -10 Rf = 5k G = -5 Rf = 5k 0.1 1 10 0.01 0.1 1 10 Non-Inverting Freq. Response Vs = +2.7V G=1 Rf = 0 el G=2 Rf = 5k G = 10 Rf = 5k G=5 Rf = 5k Frequency (MHz) Frequency (MHz) Inverting Frequency Response Vs = +2.7V Rf = 5k G = -2 G = -1 0.1 im 1 10 CL = 50pF Rs = 0 G = -10 Frequency (MHz) Frequency Response vs. CL Vo = 0.05V CL = 100pF Rs = 100 Magnitude (1dB/div) Magnitude (1dB/div) in 0.01 0.01 140 120 |Gain| RL = 10k G = -5 0.1 1 10 Frequency (MHz) Frequency Response vs. RL CL = 20pF Rs = 0 CL = 10pF Rs = 0 + 5k 5k Rs CL RL RL = 200 ar RL = 1k RL = 50 RL = 10k 0.01 0.1 1 10 0.1 1 Frequency (MHz) Large Signal Frequency Response Vs = 5V Frequency (MHz) y 10 Open Loop Gain & Phase vs. Frequency |Gain| No load Vs = 5V Open Loop Phase (deg) Open Loop Gain (dB) Magnitude (1dB/div) Vo = 1Vpp 100 80 60 40 20 0 -20 100 Phase RL = 10k Phase No load 0 -45 -90 -135 -180 101 102 103 104 105 106 107 108 Vo = 4Vpp Vo = 2Vpp 0.01 0.1 1 10 Frequency (MHz) Frequency (Hz) 4 Preliminary September 2001 FAN4272 DATA SHEET FAN4272 Performance Characteristics (Vs = +2.7V, G = 2, RL = 10k to Vs/2, Rf = 5k; unless noted) 2nd & 3rd Harmonic Distortion; Vs = +2.7V -20 Vo = 1Vpp 2nd Harmonic Distortion vs. Vo -20 -30 -30 Distortion (dBc) -50 -60 -70 -80 -90 0 20 40 60 2nd RL = 10k 3rd RL = 10k Distortion (dB) -40 2nd RL = 200 3rd RL = 1k 3rd RL = 200 -40 -50 50kHz -60 50kHz 100kHz -70 -80 -90 10kHz, 20kHz 10kHz 2nd RL = 1k 80 100 0.5 1 1.5 2 Frequency (kHz) 3rd Harmonic Distortion vs. Vo -20 -30 50kHz Output Amplitude (Vpp) CMRR 0 -10 -20 Distortion (dB) -40 -50 -60 -70 10kHz CMRR (dB) -30 -40 -50 -60 -70 -80 -90 100kHz 20kHz -80 -90 0.5 1 1.5 2 2.5 Output Amplitude (Vpp) PSRR 0 -10 -20 Output Voltage (0.27V/div) PSRR (dB) -30 -40 -50 -60 -70 P -80 -90 10 e r 100 1000 1.2V offset 0.6V offset No offset -0.6V offset -1.2V offset m i l 10000 100000 55 50 45 40 35 30 25 20 15 10 5 0 10 Output Swing vs. Load RL = 10k RL = 1k i a n 100 1000 10000 y r 2.5 100000 2.0 Frequency (Hz) 1.35 0 RL = 75 RL = 100 RL = 200 RL = 75/100 -1.35 -2.0 0 Frequency (Hz) Input Voltage (0.4V/div) Input Voltage Noise Pulse Resp. vs. Common Mode Voltage Output Voltage (0.5V/div) nV/Hz Time (1s/div) 0.1k 1k 10k 100k 1M Frequency (Hz) Preliminary September 2001 5 DATA SHEET FAN4272 General Description The FAN4272 is single supply, general purpose, voltage-feedback amplifier. The FAN4272 is fabricated on a complimentary bipolar process, features a rail-to-rail input and output, and is unity gain stable. The typical non-inverting circuit schematic is shown in Figure 1. +Vs extended time, device failure may occur. Overdrive Recovery Overdrive of an amplifier occurs when the output and/or input ranges are exceeded. The recovery time varies based on whether the input or output is overdriven and by how much the ranges are exceeded. The FAN4272 will typically recover in less than 50ns from an overdrive condition. Figure 3 shows the G=5 Pr In Rg + Input Voltage (0.5V/div) 6.8F Output Input KM4270 - el + Rf + 0.01F Out Figure 1: Typical Non-inverting Configuration im Vo Time (10s/div) FAN4272 in an overdriven condition. Figure 3: Overdrive Recovery Driving Capacitive Loads The Frequency Response vs. CL plot, illustrates the response of the FAN4272. A small series resistance (Rs) at the output of the amplifier, illustrated in Figure 4, will improve stability and settling performance. Rs values in the Frequency Response vs. CL plot were chosen to achieve maximum bandwidth with less than 2dB of peaking. For maximum flatness, use a larger Rs. As the plot indicates, the FAN4272 can easily drive a 50pF capacitive load without a series resistance. Input Common Mode Voltage The common mode input range extends to 250mV below ground and to 250mV above Vs, in single supply operation. Exceeding these values will not cause phase reversal. However, if the input voltage exceeds the rails by more than 0.5V, the input ESD devices will begin to conduct. The output will stay at the rail during this overdrive condition. If the absolute maximum input voltage (700mV beyond either rail) is exceeded, externally limit the input current to 5mA as shown in in Rg + ar Rs Rf y CL RL Vin 10k KM4270 Figure 2. Figure 2: Circuit for Input Current Protection Power Dissipation The maximum internal power dissipation allowed is directly related to the maximum junction temperature. If the maximum junction temperature exceeds 150C, some performance degradation will occur. It the maximum junction temperature exceeds 175C for an Figure 4: Typical Topology for driving a capacitive load Driving a capacitive load introduces phase-lag into the output signal, which reduces phase margin in the amplifier. The unity gain follower is the most sensitive configuration. In a unity gain follower configuration, the FAN4272 requires a 510 series resistor to drive a 100pF load. 6 Preliminary September 2001 FAN4272 DATA SHEET Figure 5 and Figure 6. Layout Considerations General layout and supply bypassing play major roles in high frequency performance. Fairchild has evaluation boards to use as a guide for high frequency layout and as aid in device testing and characterization. Follow the steps below as a basis for high frequency layout: * Include 6.8F and 0.01F ceramic capacitors * Place the 6.8F capacitor within 0.75 inches of the power pin * Place the 0.01F capacitor within 0.1 inches of the power pin * Remove the ground plane under and around the part, especially near the input and output pins to reduce parasitic capacitance * Minimize all trace lengths to reduce series inductances Refer to the evaluation board layouts shown in Figure 6 for more information. Evaluation Board Information The following evaluation boards are available to aid in the testing and layout of this device: Eval Board KEB006 KEB010 Description Dual Channel, Dual Supply, 8 lead SOIC Dual Channel, Dual Supply, 8 lead MSOP Products Figure 5: Evaluation Board Schematic Evaluation board schematics and layouts are shown in P Preliminary September 2001 e r m i l FAN4272MA FAN4272M i a n y r 7 DATA SHEET FAN4272 FAN4272 Evaluation Board Layout Pr el Figure 6a: KEB006 (top side) im in Figure 6b: KEB006 (bottom side) ar y Figure 6c: KEB010 (top side) Figure 6d: KEB010 (bottom side) 8 Preliminary September 2001 FAN4272 DATA SHEET FAN4272 Package Dimensions SOIC-8 D e ZD C L 7 SYMBOL A1 B C D E e H h L A ZD A2 L MIN MAX 0.10 0.25 0.36 0.46 0.19 0.25 4.80 4.98 3.81 3.99 1.27 BSC 5.80 6.20 0.25 0.50 0.41 1.27 1.52 1.72 8 0 0.53 ref 1.37 1.57 SOIC C L E H Pin No. 1 B DETAIL-A h x 45 NOTE: DETAIL-A A A1 A2 C e S 02 t1 MSOP E/2 2X -H- t2 Gauge Plane E1 3 7 -B- 2 E3 E4 1 2 2 4 6 ccc A B C aaa A bbb M A B C P 2 3 4 5 6 7 NOTE: 1 All dimensions are in millimeters (angle in degrees), unless otherwise specified. Datums - B - and - C - to be determined at datum plane - H - . Dimensions "D" and "E1" are to be determined at datum - H - . Dimensions "D2" and "E2" are for top package and dimensions "D" and "E1" are for bottom package. Cross sections A - A to be determined at 0.13 to 0.25mm from the leadtip. Dimension "D" and "D2" does not include mold flash, protrusion or gate burrs. Dimension "E1" and "E2" does not include interlead flash or protrusion. e r D2 A2 -C- A b -A- A1 D m i l 0.25mm 03 b c c1 b1 Section A - A 5 i L L1 R1 R a n 01 1. All dimensions are in millimeters. 2. Lead coplanarity should be 0 to 0.10mm (.004") max. 3. Package surface finishing: (2.1) Top: matte (charmilles #18~30). (2.2) All sides: matte (charmilles #18~30). (2.3) Bottom: smooth or matte (charmilles #18~30). 4. All dimensions excluding mold flashes and end flash from the package body shall not exceed o.152mm (.006) per side(d). Detail A Scale 40:1 Detail A E2 A A E1 E 3 4 SYMBOL MIN A 1.10 A1 0.10 A2 0.86 D 3.00 D2 2.95 E 4.90 E1 3.00 E2 2.95 E3 0.51 E4 0.51 R 0.15 R1 0.15 t1 0.31 t2 0.41 b 0.33 b1 0.30 c 0.18 c1 0.15 01 3.0 02 12.0 03 12.0 L 0.55 L1 0.95 BSC aaa 0.10 bbb 0.08 ccc 0.25 e 0.65 BSC S 0.525 BSC y r MSOP-8 MAX - 0.05 0.08 0.10 0.10 0.15 0.10 0.10 0.13 0.13 +0.15/-0.06 +0.15/-0.06 0.08 0.08 +0.07/-0.08 0.05 0.05 +0.03/-0.02 3.0 3.0 3.0 0.15 - - - - - - Preliminary September 2001 9 DATA SHEET FAN4272 Ordering Information Model FAN4272 Part Number FAN4272M FAN4272MX FAN4272MA FAN4272MAX Package SOIC-8 SOIC-8 MSOP-8 MSOP-8 Container Rail Reel Rail Reel Pack Qty 95 2500 50 4000 Temperature range for all parts: -40C to +125C. Pr el im in ar y DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICES TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com (c) 2001 Fairchild Semiconductor Corporation |
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