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FAN5098
Two Phase Interleaved Synchronous Buck Converter for AMD Hammer
Features
* Programmable output from 800mV to 1.550V in 25mV steps using an integrated 5-bit DAC * Two interleaved synchronous phases for maximum performance * 100nsec response time * Built-in current sharing between phases * Remote sense * Programmable Active Droop (Voltage Positioning) * Programmable frequency from 200KHz to 2MHz * Adaptive delay gate switching * Integrated high-current gate drivers * Integrated Power Good, OV, UV, Enable/Soft Start functions * Drives N-channel MOSFETs * Operation optimized for 12V operation * High efficiency mode (E*) at light load * Overcurrent protection using MOSFET sensing * 24 pin TSSOP package
Description
The FAN5098 is a synchronous multi-phase DC-DC controller IC which provides a highly accurate, programmable output voltage for the AMD Hammer processor. Two interleaved synchronous buck regulator phases with built-in current sharing operate 180 out of phase to provide the fast transient response needed to satisfy high current applications while minimizing external components. The FAN5098 features remote voltage sensing and Programmable Active Droop for 100nsec converter transient response with minimum output capacitance. It has integrated high-current gate drivers, with adaptive delay gate switching, eliminating the need for external drive devices. The FAN5098 uses a 5-bit D/A converter to program the output voltage from 800mV to 1.550V in 25mV steps with an accuracy of 1%. The FAN5098 uses a high level of integration to deliver load currents in excess of 40A from a 12V source with minimal external circuitry. The FAN5098 also offers integrated functions including Power Good, Output Enable/Soft Start, under-voltage lockout, over-voltage protection, and adjustable current limiting with independent current sense on each phase. It is available in a 24 pin TSSOP package.
Preliminary Specification
Applications
* Power supply for Athlon(R) and Hammer(R) * VRM for Hammer * Programmable step-down power supply
Block Diagram
Bypass 6 23 +12V 18 5V Reg UVL O +12V+5V 13 +12V
OSC
14
+ -
Digital Control
15 +12V 17 16 +12V+5V VO +12V
+
GNDA
Current Limit
+ + +
12 11
Digital Control
10 +12V 8 9
5-Bit DAC
1 23 4 5 VID0 VID2 VID4 VID1 VID3 24
Power Good
19 PWRGD 21 7 22 ENABLE/SS 20 ILIM
DROOP/E* GNDA
Athlon and Hammer are registered trademarks of AMD. Programmable Active Droop is a trademark of Fairchild Semiconductor.
PRELIMINARY SPECIFICATION describes products that are not in full production at the time of printing. Specifications are based on design goals and limited characterization. In the process of final production release, specifications may change. Contact Fairchild Semiconductor for current information.
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Pin Assignments
VID0 VID1 VID2 VID3 VID4 BYPASS AGND LDRVB PGNDB SWB HDRVB BOOTB 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VFB RT ENABLE/SS DROOP/E* ILIM PWRGD VCC LDRVA PGNDA SWA HDRVA BOOTA
FAN5098
Preliminary Specification
Pin Definitions
Pin Number 1-5 Pin Name VID0-4 Pin Function Description Voltage Identification Code Inputs. These open collector/TTL compatible inputs will program the output voltage over the ranges specified in Table 1. 250K pull-up resistors to 2.5V are internal to the controller. 5V Rail. Bypass this pin with a 0.1F ceramic capacitor to AGND. Analog Ground. Return path for low power analog circuitry. This pin should be connected to a low impedance system ground plane to minimize ground loops. Low Side FET Driver for B. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should optimally be <0.5". Power Ground B. Return pin for high currents flowing in low-side MOSFET. Connect directly to low-side MOSFET source. High side driver source and low side driver drain switching node B. Gate drive return for high side MOSFET, and negative input for low-side MOSFET current sense. High Side FET Driver B. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should optimally be <0.5". Bootstrap B. Input supply for high-side MOSFET. Bootstrap A. Input supply for high-side MOSFET. High Side FET Driver A. Connect this pin to the gate of an N-channel MOSFET. The trace from this pin to the MOSFET gate should optimally be <0.5". High side driver source and low side driver drain switching node A. Gate drive return for high side MOSFET, and negative input for low-side MOSFET current sense. Power Ground A. Return pin for high currents flowing in low-side MOSFET. Connect directly to low-side MOSFET source. Low Side FET Driver for A. Connect this pin to the gate of an N-channel MOSFET for synchronous operation. The trace from this pin to the MOSFET gate should optimally be <0.5". VCC. Internal IC supply. Connect to system 12V supply, and decouple with a 10 resistor and a 0.1F ceramic capacitor. Power Good Flag. An open collector output that will be logic LOW if the output voltage is less than 350mV less than the nominal output voltage setpoint. Power Good is prevented from going low until the output voltage is out of spec for 500sec.
6 7 8
BYPASS AGND LDRVB
9 10
PGNDB SWB
11 12 13 14 15
HDRVB BOOTB BOOTA HDRVA SWA
16 17
PGNDA LDRVA
18 19
VCC PWRGD
2
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Pin Number 20 21
Pin Name ILIM DROOP/E*
Pin Function Description Current Limit. A resistor from this pin to ground sets the over current trip level. Droop Control/Energy Star Mode Control. A resistor from this pin to ground sets the amount of droop by controlling the gain of the current sense amplifier. When this pin is pulled high to BYPASS, the phase A drivers are turned off for Energy-star operation. Output Enable/Softstart. A logic LOW on this pin will disable the output. An 10A internal current source allows for open collector control. This pin also doubles as soft start. Frequency Set. A resistor from this pin to ground sets the switching frequency. Voltage Feedback. Connect to the desired regulation point at the output of the converter.
22
ENABLE/SS
23 24
RT VFB
Preliminary Specification
Absolute Maximum Ratings
Parameter Supply Voltage VCC Supply Voltages BOOTA, BOOTB Voltage Identification Code Inputs, VID0-VID4 VFB, ENABLE/SS, PWRGD, DROOP/E* SWA, SWB PGNDA, PGNDB to AGND Gate Drive Current, peak pulse Junction Temperature, TJ Storage Temperature Lead Soldering Temperature, 10 seconds Power Dissipation, PD Thermal Resistance Junction-to-Case, JC -55 -65 300 950 13 -5 -0.5 3 150 150 Min. Typ. Max. 15 22 6 6 15 0.5 Unit V V V V V V A C C C mW C/W
Recommended Operating Conditions
Parameter Output Driver Supply, BOOT Input Logic HIGH Input Logic LOW Ambient Operating Temperature 0 Conditions Min. 16 2.4 0.8 70 Typ. Max. 17 Units V V V C
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FAN5098
Electrical Specifications
(VCC = 12V,VOUT = 1.400V, and TA = +25C using circuit in Figure 2, unless otherwise noted.) The * denotes specifications which apply over the full operating temperature range. Parameter Output Voltage Output Current Internal Reference Voltage Initial Voltage Setpoint Output Temperature Drift Line Regulation Droop3 Programmable Droop Range Total Output Variation, Steady State1 Total Output Variation, Transient2 Response Time Gate Drive On-Resistance Upper Drive Low Voltage Upper Drive High Voltage Lower Drive Low Voltage Lower Drive High Voltage Output Driver Rise & Fall Time Current Mismatch Output Overvoltage Detect Efficiency Oscillator Frequency Oscillator Range Maximum Duty Cycle Minimum LDRV on-time Input LOW current, VID pins Soft Start Current Enable Threshold BYPASS Voltage BYPASS Capacitor PWRGD Threshold PWRGD Output Voltage PWRGD Delay 12V UVLO UVLO Hysteresis 12V Supply Current Over Temperature Shutdown Over Temperature Hysteresis 4 HDRV and LDRV Open Logic LOW, VVID - VPWRGD Isink = 4mA High Low * 8.5 500 9.5 0.5 5 150 25 10.5 * ON OFF 0 IBYPASS 1mA 0.8 4.75 100 333 350 367 0.4 5 5.25 V nF mV V sec V V mA C C
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Conditions See Table 1 *
Min. 0.800 0 1.393
Typ. 40 1.400 1.425 +5 +130
Max. 1.550 1.407 1.439
Units V A V V mV V
ILOAD = 5A TA = 0 to 70C VCC = 11.4V to 12.6V ILOAD = 3A to Imax ILOAD = 3A to Imax ILOAD = 3A to Imax Vout = 10mV VHDRV-VSW at Isink = 10A VBOOT-VHDRV at Isource = 10A Isink = 10A VCC-VLDRV at Isource = 10A See Figure 3 RDS,on (A) = RDS,on (B) * ILOAD = Imax ILOAD = 3A (E*-mode) RT = 41.2K RT = 125K to 12.5 K RT = 125K RT = 12.5K VVID = 0.4V * * * *
1.411
Preliminary Specification
-90 -10 1.350 1.350
-100
-110 0 1.450 1.450
mV %Vout V V nsec V V V V nsec %
100 1.0 0.2 0.5 0.2 0.5 20 5 2.1 85 70 450 200 90 330 50 10 1.7 600 750 2000 2.3
V % KHz KHz % nsec A A V
FAN5098
Notes: 1. Steady State Voltage Regulation includes Initial Voltage Setpoint, Output Ripple and Output Temperature Drift and is measured at the converter's VFB sense point. 2. As measured at the converter's VFB sense point. For motherboard applications, the PCB layout should exhibit no more than 0.5m trace resistance between the converter's output capacitors and the CPU. Remote sensing should be used for optimal performance. 3. Using the VFB pin for remote sensing of the converter's output at the load, the converter will be in compliance with AMD specification of +50, -50mV.
Table 1. Output Voltage Programming Codes
VID4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: 1. 0 = VID pin is tied to GND. 1 = VID pin is open.
VID3 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
VID2 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
VID1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
VID0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
VOUT to CPU OFF 0.800V 0.825V 0.850V 0.875V 0.900V 0.925V 0.950V 0.975V 1.000V 1.025V 1.050V 1.075V 1.100V 1.125V 1.150V 1.175V 1.200V 1.225V 1.250V 1.275V 1.300V 1.325V 1.350V 1.375V 1.400V 1.425V 1.450V 1.475V 1.500V 1.525V 1.550V
Preliminary Specification
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Typical Operating Characteristics
(VCC = 12V, and TA = +25C using circuit in Figure 2, unless otherwise noted.)
EFFICIENCY VS. OUTPUT CURRENT
Preliminary Specification
90 85 80 75 70 65 60 55 50 45 40 0
EFFICIENCY (%)
E-*
2-Slice
10
20
30
40
50
OUTPUT CURRENT (A)
TRANSIENT RESPONSE, 0.5A TO 50A TRANSIENT RESPONSE, 50A to 0.5A
VOUT (50mV / DIV)
V OUT (50mV / div)
1.440V 1.400V 1.330V
1.440V 1.400V 1.330V
TIME (20s/DIVISION)
TIME (20s/DIVISION)
HIGH-SIDE GATE DRIVES, NORMAL OPERATION
HIGH-SIDE GATE DRIVES, E*-MODE
10V/DIVISION
10V/DIVISION
TIME (500ns/DIVISION)
TIME (500ns/DIVISION)
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Typical Operating Characteristics (Continued)
OUTPUT RIPPLE VOLTAGE GATE DRIVE RISE TIME
10mV/DIVISION
5V/DIVISION
Preliminary Specification
TIME (1s/DIVISION)
TIME (50ns/DIVISION)
GATE DRIVE FALL TIME
ADAPTIVE GATE DELAY
5V/DIVISION
10V/DIVISION
5V/DIVISION
TIME (50ns/DIVISION) TIME (10ns/DIVISION)
CURRENT SHARING BETWEEN INDUCTORS
POWER GOOD DURING DYNAMIC VOLTAGE ADJUSTMENT
5A/DIVISION
TIME (500ns/DIVISION)
5V/DIVISION
50mV/DIVISION
TIME (200s/DIVISION)
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FAN5098
Typical Operating Characteristics (Continued)
Droop vs. RDroop (RT = 25K) 180 160 140 Droop (mV)
VOUT (V) 1.501 1.500 1.499 1.498 1.497 1.496 1.495 1.494 VOUT TEMPERATURE VARIATION
120 100 80 60 40 20
Preliminary Specification
0 0 5 10 15 20 25 30 35 40 45 50 RDroop (K)
0
25
70
100
TEMPERATURE (C)
Application Circuit
L1 (Optional) +12V CIN R6 Q1 L2 +12V +12V
C2 VID4 VID3 VID2 VID1 VID0 12 3 456 78 9 10 11 12
R7 Q2 C4
D3 +12V
C5
D2 D1 +5V VO COUT
U1 FAN5098
+12V 24 23 22 21 20 19 18 17 16 15 14 13 ENABLE/SS C1 R4 R3 R2 R9 Q3 R10 Q4 PWRGD R1 R5 +12V C3 L3
Figure 1. Application Circuit for 31A AMD Hammer Desktop Application (500 KHz each phase)
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FAN5098
Table 2. FAN5098 Application Bill of Materials for Figure 1
Reference C1-4 C5 CIN COUT D1-3 L1 L2-3 Q1, Q3 Q2, Q4 R1 R2 R3 R4 R5 R6-7, R9-10 U1 Manufacturer Part # Panasonic ECU-V1H104ZFX Any Rubycon 16MBZ1500M Rubycon 6.3MBZ2200M Fairchild MBR0540 Any Coiltronics DR127-IR0 Fairchild FDD6690A Fairchild FDD6680S Any Any Any Any Any Any Fairchild FAN5098M Quantity 4 1 2 6 3 Optional 2 2 2 1 1 1 1 1 4 1 Description 100nF, 50V Capacitor 1F, 25V Capacitor 1500F, 16V Electrolytic 2200F, 6.3V Electrolytic 500mA, 40V Schottky Diode 1.3H, 5A Inductor 1H, 16A Inductor N-Channel MOSFET N-Channel MOSFET with Integrated Schottky 10K 43.2K 2.0K 24.9K 10 4.7 DC/DC Controller DCR ~ 20m See Note 1. DCR ~ 2.5m RDS(ON) = 16m @ VGS = 4.5V See Note 2. RDS(ON) = 11m See Note 2. IRMS = 5.4A @ 65C ESR 13m Requirements/Comments
Preliminary Specification
Notes: 1. Inductor L1 is recommended to isolate the 12V input supply from noise generated by the MOSFET switching, and to comply with AMD dI/dt requirements. L1 may be omitted if desired. 2. For a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8. *Output capacitance requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details. Pin 24 must be used to remote sense the voltage at the processor to achieve the specified performance.
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FAN5098
L1 (Optional) +12V CIN R7 +12V R6
+12V
Q2 Q1 R8 Q3 L2
C2 VID4 VID3 VID2 VID1 VID0 1 2 3456 78 9 10 11 12 +12V D3 D2 C5
C4
R9 Q4 D1 +5V VO +12V R10 Q6 R11 Q5 L3 COUT
Preliminary Specification
U1 FAN5098
24 23 22 21 20 19 18 17 16 15 14 13 ENABLE/SS C1 R3 R4 R2 R12
Q7 PWRGD R1 +5V +12V C3 R5 R13 Q8
Figure 2. Application Circuit for 42A AMD Hammer Desktop Application
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FAN5098
Table 3. FAN5098 Application Bill of Materials for Figure 2
Reference C1-4 C5 CIN COUT D1-3 L1 L2-3 Q1-2, Q5-6 Q304, Q7-8 R1 R2 R3 R4 R5 R6-13 U1 Manufacturer Part # Quantity Panasonic ECU-V1H104ZFX Any Rubycon 16MBZ1500M Rubycon 6.3MBZ2200M Fairchild MBR0540 Any Coiltronics HC1-1R0 Fairchild FDD6690A Fairchild FDD6680S Any Any Any Any Any Any Fairchild FAN5098M 4 1 2 7 3 Optional 2 4 4 1 1 1 1 1 8 1 Description 100nF, 50V Capacitor 1F, 25V Capacitor 1500F, 16V Electrolytic 2200F, 6.3V Electrolytic 0.5A, 40V Schottky Diode 1.3H, 6A Inductor 1H, 28A Inductor N-Channel MOSFET N-Channel MOSFET with Integrated Schottky 10K 150K 15K 68.1K 10 4.7 DC/DC Controller DCR ~ 15m See Note 1. DCR ~ 1.4m RDS(ON) = 16m @ VGS = 4.5V. See Note 2. RDS(ON) = 11m. See Note 2. IRMS = 5.4A @ 65C ESR 13m Requirements/Comments
Preliminary Specification
Notes: 1. Inductor L1 is recommended to isolate the 12V input supply from noise generated by the MOSFET switching, and to comply with AMD dI/dt requirements. L1 may be omitted if desired. 2. For a spreadsheet on MOSFET selections, refer to Applications Bulletin AB-8. *Output capacitance requirements depend critically on layout and processor type. Consult Application Bulletin AB-14 for details. Pin 24 must be used to remote sense the voltage at the processor to achieve the specified performance.
Test Parameters
tR 90% 10% tDT 2V 2V 90% 2V 10% tDT 2V tF HIDRV
LODRV
Figure 3. Output Drive Timing Diagram
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FAN5098
Application Information Operation
The FAN5098 Controller
The FAN5098 is a programmable synchronous multi-phase DC-DC controller IC. When designed around the appropriate external components, the FAN5098 can be configured to deliver more than 40A of output current, as appropriate for the AMD Hammer. The FAN5098 functions as a fixed frequency PWM step down regulator, with a high efficiency mode (E*) at light load.
output pins for each phase. These outputs control the external power MOSFETs.
Response Time
The FAN5098 utilizes leading-edge, not trailing-edge control. Conventional trailing-edge control turns on the high-side MOSFET at a clock signal, and then turns it off when the error amplifier output voltage is equal to the ramp voltage. As a result, the response time of a trailing-edge converter can be as long as the off-time of the high-side driver, nearly an entire switching period. The FAN5098's leading-edge control turns the high-side MOSFET on when the error amplifier output voltage is equal to the ramp voltage, and turns it off at the clock signal. As a result, when a transient occurs, the FAN5098 responds immediately by turning on the high-side MOSFET. Response time is set by the internal propagation delays, typically 100nsec. In worse case, the response time is set by the minimum on-time of the low-side MOSFET, 300nsec.
Main Control Loop
Preliminary Specification
Refer to the FAN5098 Block Diagram on page 1. The FAN5098 consists of two interleaved synchronous buck converters, implemented with summing-mode control. Each phase has its own current feedback, and there is a common voltage feedback. The two buck converters controlled by the FAN5098 are interleaved, that is, they run 180 out of phase with each other. This minimizes the RMS input ripple current, minimizing the number of input capacitors required. It also doubles the effective switching frequency, improving transient response. The FAN5098 implements "summing mode control", which is different from both classical voltage-mode and currentmode control. It provides superior performance to either by allowing a large converter bandwidth over a wide range of output loads and external components. No external compensation is required. The control loop of the regulator contains two main sections: the analog control block and the digital control block. The analog section consists of signal conditioning amplifiers feeding into a comparator which provides the input to the digital control block. The signal conditioning section accepts inputs from a current sensor and a voltage sensor, with the voltage sensor being common to both phases, and the current sensor separate for each. The voltage sensor amplifies the difference between the VFB signal and the reference voltage from the DAC and presents the output to each of the two comparators. The current control path for each phase takes the difference between its PGND and SW pins when the lowside MOSFET is on, reproducing the voltage across the MOSFET and thus the input current; it presents the resulting signal to the same input of its summing amplifier, adding its signal to the voltage amplifier's with a certain gain. These two signals are thus summed together. This sum is then presented to a comparator looking at the oscillator ramp, which provides the main PWM control signal to the digital control block. The oscillator ramps are 180 out of phase with each other, so that the two phases are on alternately. The digital control block takes the analog comparator input to provide the appropriate pulses to the HDRV and LDRV 12
Remote Voltage Sense
The FAN5098 has true remote voltage sense capability, eliminating errors due to trace resistance. To utilize remote sense, the VFB and AGND pins should be connected as a Kelvin trace pair to the point of regulation, such as the processor pins. The converter will maintain the voltage in regulation at that point. Care is required in layout of these grounds; see the layout guidelines in this datasheet.
High Current Output Drivers
The FAN5098 contains four high current output drivers that utilize MOSFETs in a push-pull configuration. The drivers for the high-side MOSFETs use the BOOT pin for input power and the SW pin for return. The drivers for the low-side MOSFETs use the VCC pin for input power and the PGND pin for return. Typically, the BOOT pin will use a charge pump as shown in Figure 1. Note that the BOOT and VCC pins are separated from the chip's internal power and ground, BYPASS and AGND, for switching noise immunity.
Adaptive Delay Gate Drive
The FAN5098 embodies an advanced design that ensures minimum MOSFET transition times while eliminating shoot-through current. It senses the state of the MOSFETs and adjusts the gate drive adaptively to ensure that they are never on simultaneously. When the high-side MOSFET turns off, the voltage on its source begins to fall. When the voltage there reaches approximately 2.5V, the low-side MOSFETs gate drive is applied with approximately 50nsec delay. When the low-side MOSFET turns off, the voltage at the LDRV pin is sensed. When it drops below approximately 2V, the highside MOSFET's gate drive is applied.
Maximum Duty Cycle
In order to ensure that the current-sensing and chargepumping work, the FAN5098 guarantees that the low-side MOSFET will be on a certain portion of each period. For low
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frequencies, this occurs as a maximum duty cycle of approximately 90%. Thus at 250KHz, with a period of 4sec, the low-side will be on at least 4sec * 10% = 400nsec. At higher frequencies, this time might fall so low as to be ineffective. The FAN5098 guarantees a minimum low-side on-time of approximately 330nsec, regardless of what duty cycle this corresponds to.
As an example, consider the typical characteristic of the DC-DC converter circuit with two FDP6670AL low-side MOSFETs (RDS = 6.5m maximum at 25C * 1.2 at 75C = 7.8m each, or 3.9m total) in each phase, RT = 42.1K (600KHz oscillator) and a 50K RS. The converter exhibits a normal load regulation characteristic until the voltage across the MOSFETs exceeds the internal short circuit threshold of 50K/(3.9m * 41.2K * 6.66) = 47A. [Note that this current limit level can be as high as 50K/(3.5m * 41.2K * 6.66) = 52A, if the MOSFETs have typical RDS,on rather than maximum, and are at 25C.] At this point, the internal comparator trips and signals the controller to leave on the low-side MOSFETs and keep off the high-side MOSFETs. The inductor current decreases, and power is not applied again until the inductor current reaches 0A and the converter attempts to re-softstart.
Current Sensing
The FAN5098 has two independent current sensors, one for each phase. Current sensing is accomplished by measuring the source-to-drain voltage of the low-side MOSFET during its on-time. Each phase has its own power ground pin, to permit the phases to be placed in different locations without affecting measurement accuracy. For best results, it is important to connect the PGND and SW pins for each phase as a Kelvin trace pair directly to the source and drain, respectively, of the appropriate low-side MOSFET. Care is required in the layout of these grounds; see the layout guidelines in this datasheet.
Preliminary Specification
Light Load Efficiency
At light load, the FAN5098 uses a number of techniques to improve efficiency. Because a synchronous buck converter is two quadrant, able to both source and sink current, during light load the inductor current will flow away from the output and towards the input during a portion of the switching cycle. This reverse current flow is detected by the FAN5098 as a positive voltage appearing on the low-side MOSFET during its on-time. When reverse current flow is detected, the low-side MOSFET is turned off for the rest of the cycle, and the current instead flows through the body diode of the high-side MOSFET, returning the power to the source. This technique substantially enhances light load efficiency.
Current Sharing
The two independent current sensors of the FAN5098 operate with their independent current control loops to guarantee that the two phases each deliver half of the total output current. The only mismatch between the two phases occurs if there is a mismatch between the RDS,on of the low-side MOSFETs.
Short Circuit Current Characteristics
The FAN5098 short circuit current characteristic includes a function that protects the DC-DC converter from damage in the event of a short circuit. The short circuit limit is set with the RS resistor, as given by the formula R S ( ) = I SC * R DS, on * RT * 6.66 with ISC the desired current limit, RT the oscillator resistor and RDS,on one phase's low-side MOSFET's on resistance. Remember to make the RS large enough to include the effects of initial tolerance and temperature variation on the MOSFETs' RDS,on. Important Note! The oscillator frequency must be selected before selecting the current limit resistor, because the value of RT is used in the calculation of RS. When an overcurrent is detected, the high-side MOSFETs are turned off, and the low-side MOSFETs are turned on, and they remain in this state until the measured current through the low-side MOSFET has returned to zero amps. After reaching zero, the FAN5098 re-soft-starts, ensuring that it can also safely turn on into a short. A limitation on the current sense circuit is that ISC * RDS,on must be less that 375mV. To ensure correct operation, use ISC * RDS,on 300mV; between 300mV and 375mV, there will be some non-linearity in the short-circuit current not accounted for in the equation.
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E*-mode
In addition, further enhancement in efficiency can be obtained by putting the FAN5098 into E*-mode. When the Droop pin is pulled to the 5V BYPASS voltage, the "A" phase of the FAN5098 is completely turned off, reducing in half the amount of gate charge power being consumed. E*-mode can be implemented with the circuit shown in Figure 4.
BYPASS
10K 1K HI = E*mode on 10K 2N2222 RDROOP 2N2907 FAN5098 pin 21
Figure 4. Implementing E*-mode Control
Note that the charge pump for the HIDRVs should be based on the "B" phase of the FAN5098, since the "A" phase is off in E*-mode.
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FAN5098
Internal Voltage Reference
The reference included in the FAN5098 is a precision bandgap voltage reference. Its internal resistors are precisely trimmed to provide a near zero temperature coefficient (TC). Based on the reference is the output from an integrated 5-bit DAC. The DAC monitors the 5 voltage identification pins, VID0-4, and scales the reference voltage from 800mV to 1.550V in 25mV steps.
Oscillator
The FAN5098 oscillator section runs at a frequency determined by a resistor from the RT pin to ground according to the formula 25 * 10 9 RT ( ) = --------------------f ( Hz ) The oscillator generates two internal sawtooth ramps, each at one-half the oscillator frequency, and running 180 out of phase with each other. These ramps cause the turn-on time of the two phases to be phased apart. The oscillator frequency of the FAN5098 can be programmed from 200KHz to 2MHz with each phase running at 100KHz to 1MHz, respectively. Selection of a frequency will depend on various system performance criteria, with higher frequency resulting in smaller components but lower efficiency.
BYPASS Reference
The internal logic of the FAN5098 runs on 5V. To permit the IC to run with 12V only, it produces 5V internally with a linear regulator, whose output is present on the BYPASS pin. This pin should be bypassed with a 100nF capacitor for noise suppression. The BYPASS pin should not have any external load attached to it.
Preliminary Specification
Dynamic Voltage Adjustment
The FAN5098 can have its output voltage dynamically adjusted to accommodate low power modes. The designer must ensure that the transitions on the VID lines all occur simultaneously (within less than 500nsec) to avoid false codes generating undesired output voltages. The Power Good flag tracks the VID codes, but has a 500sec delay transitioning from high to low; this is long enough to ensure that there will not be any glitches during dynamic voltage adjustment.
Programmable Active DroopTM
The FAN5098 features Programmable Active DroopTM: as the output current increases, the output voltage drops proportionately an amount that can be programmed with an external resistor. This feature is offered in order to allow maximum headroom for transient response of the converter. The current is sensed losslessly by measuring the voltage across the low-side MOSFET during its on time. Consult the section on current sensing for details. The droop is adjusted by the droop resistor changing the gain of the current loop. Note that this method makes the droop dependent on the temperature and initial tolerance of the MOSFET, and the droop must be calculated taking account of these tolerances. Given a maximum output current, the amount of droop can be programmed with a resistor to ground on the droop pin, according to the formula V Droop * RT R Droop ( ) = -----------------------------------I max * R DS, on with VDroop the desired droop voltage, RT the oscillator resistor, Imax the output current at which the droop is desired, and RDS, on the on-state resistance of one phase's low-side MOSFET. Important Note! The oscillator frequency must be selected before selecting the droop resistor, because the value of RT is used in the calculation of RDroop.
Power Good (PWRGD)
The FAN5098 Power Good function is designed in accordance with the Hammer DC-DC converter specifications and provides a continuous voltage monitor on the VFB pin. The circuit compares the VFB signal to the VREF voltage and outputs an active-low interrupt signal to the CPU should the power supply voltage be less than 350mV less than nominal setpoint. The output is guaranteed open-collector high otherwise. The Power Good flag provides no control functions to the FAN5098.
Output Enable/Soft Start (ENABLE/SS)
The FAN5098 will accept an open collector/TTL signal for controlling the output voltage. The low state disables the output voltage. When disabled, the PWRGD output is in the low state. Even if an enable is not required in the circuit, this pin should have attached a capacitor (typically 100nF) to softstart the switching. A softstart capacitor may be approximately chosen by the formula:
t * 10A C = --------------------1 + V out
Higher Current Converters
Active droop makes it possible to parallel multiple FAN5098s for even higher output current requirements. Please refer to Application Bulletin AB-XX for details.
However, C must be 100nF.
Over-Voltage Protection
The FAN5098 constantly monitors the output voltage for protection against over-voltage conditions. If the voltage at the VFB pin exceeds 2.2V, an over-voltage condition is
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assumed and the FAN5098 latches on the external low-side MOSFET and latches off the high-side MOSFET. The DC-DC converter returns to normal operation only after VCC has been recycled.
Over Temperature Protection
If the FAN5098 die temperature exceeds approximately 150C, the IC shuts itself off. It remains off until the temperature has dropped approximately 25C, at which time it resumes normal operation.
The gate resistor also limits the power dissipation inside the IC, which could otherwise be a limiting factor on the switching frequency. It may thus carry significant power, especially at higher frequencies. As an example, consider the gate resistors used for the low-side MOSFETs (Q2 and Q4) in Figure 1. The FDB7045L has a maximum gate charge of 70nC at 5V, and an input capacitance of 5.4nF. The total energy used in powering the gate during one cycle is the energy needed to get it up to 5V, plus the energy to get it up to 12V:
2 1 1 E = QV + -- C * V 2 = 70nC * 5V + -- 5.4nF * ( 12V - 5V ) 2 2 = 482nJ
Component Selection
MOSFET Selection
This application requires N-channel Enhancement Mode Field Effect Transistors. Desired characteristics are as follows: * * * * * Low Drain-Source On-Resistance, RDS,ON < 10m (lower is better); Power package with low Thermal Resistance; Drain-Source voltage rating > 15V; Low gate charge, especially for higher frequency operation.
Preliminary Specification
This power is dissipated every cycle, and is divided between the internal resistance of the FAN5098 gate driver and the gate resistor. Thus, E * f * R gate P Rgate = ------------------------------------------------ = 482nJ * 300KHz * ( R gate + R internal ) 4.7 -------------------------------- = 131mW 4.7 + 0.5 and each gate resistor thus requires a 1/4W resistor to ensure worst case power dissipation.
For the low-side MOSFET, the on-resistance (RDS,ON) is the primary parameter for selection. Because of the small duty cycle of the high-side, the on-resistance determines the power dissipation in the low-side MOSFET and therefore significantly affects the efficiency of the DC-DC converter. For high current applications, it may be necessary to use two MOSFETs in parallel for the low-side for each phase. For the high-side MOSFET, the gate charge is as important as the on-resistance, especially with a 12V input and with higher switching frequencies. This is because the speed of the transition greatly affects the power dissipation. It may be a good trade-off to select a MOSFET with a somewhat higher RDS,on, if by so doing a much smaller gate charge is available. For high current applications, it may be necessary to use two MOSFETs in parallel for the high-side for each phase. At the FAN5098's highest operating frequencies, it may be necessary to limit the total gate charge of both the high-side and low-side MOSFETs together, to avert excess power dissipation in the IC. For details and a spreadsheet on MOSFET selection, refer to Applications Bulletin AB-8.
Inductor Selection
Choosing the value of the inductor is a tradeoff between allowable ripple voltage and required transient response. A smaller inductor produces greater ripple while producing better transient response. In any case, the minimum inductance is determined by the allowable ripple. The first order equation (close approximation) for minimum inductance for a two-phase converter is: V in - 2 * V out V out ESR L min = ---------------------------------- * ---------- * ----------------V in V ripple f where: Vin = Input Power Supply Vout = Output Voltage f = DC/DC converter switching frequency ESR = Equivalent series resistance of all output capacitors in parallel Vripple = Maximum peak to peak output ripple voltage budget. One other limitation on the minimum size of the inductor is caused by the current feedback loop stability criterion. The inductor must be greater than: L 3 * 10
- 10
Gate Resistors
Use of a gate resistor on every MOSFET is mandatory. The gate resistor prevents high-frequency oscillations caused by the trace inductance ringing with the MOSFET gate capacitance. The gate resistors should be located physically as close to the MOSFET gate as possible.
* R DS, on * R Droop * ( V in - 2V o )
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FAN5098
where L is the inductance in Henries, RDS,on is the on-state resistance of one phase's low-side MOSFET, RDroop is the value of the droop resistor in Ohms, Vin is either 5V or 12V, and Vo is the output voltage. For most applications, this formula will not present any limitation on the selection of the inductor value. A typical value for the inductor is 1.3H at an oscillator frequency of 600KHz (300KHz each phase) and 220nH at an oscillator frequency of 2MHz (1MHz each phase). For other frequencies, use the interpolating formula 930,000 L ( nH ) -------------------- - 240 f ( KHz )
For higher frequency applications, particularly those running the FAN5098 oscillator at >1MHz, Oscon or ceramic capacitors may be considered. They have much smaller ESR than comparable electrolytics, but also much smaller capacitance. The output capacitance should also include a number of small value ceramic capacitors placed as close as possible to the processor; 0.1F and 0.01F are recommended values.
Input Filter
The DC-DC converter design may include an input inductor between the system main supply and the converter input as shown in Figure 5. This inductor serves to isolate the main supply from the noise in the switching portion of the DC-DC converter, and to limit the inrush current into the input capacitors during power up. A value of 1.3H is recommended. It is necessary to have some low ESR capacitors at the input to the converter. These capacitors deliver current when the high side MOSFET switches on. Because of the interleaving, the number of such capacitors required is greatly reduced from that required for a single-phase buck converter. Figure 5 shows 3 x 1000F, but the exact number required will vary with the output voltage and current, according to the formula I out I rms = -------- 2DC - 4DC 2 2 for the two phase FAN5098, where DC is the duty cycle, DC = Vout / Vin. Capacitor ripple current rating is a function of temperature, and so the manufacturer should be contacted to find out the ripple current rating at the expected operational temperature. For details on the design of an input filter, refer to Applications Bulletin AB-16.
1.3H +12V Vin 1000F, 16V Electrolytic
Preliminary Specification
Schottky Diode Selection
The application circuit of Figure 1 shows a Schottky diode, D1 (D2 respectively), one in each phase. They are used as free-wheeling diodes to ensure that the body-diodes in the low-side MOSFETs do not conduct when the upper MOSFET is turning off and the lower MOSFETs are turning on. It is undesirable for this diode to conduct because its high forward voltage drop and long reverse recovery time degrades efficiency, and so the Schottky provides a shunt path for the current. Since this time duration is extremely short, being minimized by the adaptive gate delay, the selection criterion for the diode is that the forward voltage of the Schottky at the output current should be less than the forward voltage of the MOSFET's body diode. Power capability is not a criterion for this device, as its dissipation is very small.
Output Filter Capacitors
The output bulk capacitors of a converter help determine its output ripple voltage and its transient response. It has already been seen in the section on selecting an inductor that the ESR helps set the minimum inductance. For most converters, the number of capacitors required is determined by the transient response and the output ripple voltage, and these are determined by the ESR and not the capacitance value. That is, in order to achieve the necessary ESR to meet the transient and ripple requirements, the capacitance value required is already very large. The most commonly used choice for output bulk capacitors is aluminum electrolytics, because of their low cost and low ESR. The only type of aluminum capacitor used should be those that have an ESR rated at 100kHz. Consult Application Bulletin AB-14 for detailed information on output capacitor selection.
Figure 5. Input Filter
Design Considerations and Component Selection
Additional information on design and component selection may be found in Fairchild's Application Note 59.
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PCB Layout Guidelines
* Placement of the MOSFETs relative to the FAN5098 is critical. Place the MOSFETs such that the trace length of the HIDRV and LODRV pins of the FAN5098 to the FET gates is minimized. A long lead length on these pins will cause high amounts of ringing due to the inductance of the trace and the gate capacitance of the FET. This noise radiates throughout the board, and, because it is switching at such a high voltage and frequency, it is very difficult to suppress. * In general, all of the noisy switching lines should be kept away from the quiet analog section of the FAN5098. That is, traces that connect to pins 8-17 (LODRV, HIDRV, PGND and BOOT) should be kept far away from the traces that connect to pins 1 through 7, and pins 18-24. * Place the 0.1F decoupling capacitors as close to the FAN5098 pins as possible. Extra lead length on these reduces their ability to suppress noise. * Each power and ground pin should have its own via to the appropriate plane. This helps provide isolation between pins. * Place the MOSFETs, inductor, and Schottky of a given phase as close together as possible for the same reasons as in the first bullet above. Place the input bulk capacitors as close to the drains of the high side MOSFETs as possible. In addition, placement of a 0.1F decoupling cap right on the drain of each high side MOSFET helps to suppress some of the high frequency switching noise on the input of the DC-DC converter. * Place the output bulk capacitors as close to the CPU as possible to optimize their ability to supply instantaneous current to the load in the event of a current transient. Additional space between the output capacitors and the CPU will allow the parasitic resistance of the board traces to degrade the DC-DC converter's performance under severe load transient conditions, causing higher voltage deviation. For more detailed information regarding capacitor placement, refer to Application Bulletin AB-5. * A PC Board Layout Checklist is available from Fairchild Applications. Ask for Application Bulletin AB-11.
PC Motherboard Sample Layout and Gerber File
A reference design for motherboard implementation of the FAN5098 along with the PCAD layout Gerber file and silk screen can be obtained through your local Fairchild representative.
FAN5098 Evaluation Board
Fairchild provides an evaluation board to verify the system level performance of the FAN5098. It serves as a guide to performance expectations when using the supplied external components and PCB layout. Please contact your local Fairchild representative for an evaluation board.
Additional Information
For additional information contact your local Fairchild representative.
Preliminary Specification
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Mechanical Dimensions - 24 Lead TSSOP
Symbol A A1 B C D E e H Inches Min. -- .002 .007 .004 .303 Max. .047 .006 .012 .008 .316 Millimeters Min. -- 0.05 0.19 0.09 7.70 Max. 1.20 0.15 0.30 0.20 7.90 Notes: Notes 1. Dimensioning and tolerancing per ANSI Y14.5M-1982. 2. "D" and "E" do not include mold flash. Mold flash or protrusions shall not exceed .006 inch (0.15mm). 3. "L" is the length of terminal for soldering to a substrate. 4. Terminal numbers are shown for reference only. 5. Symbol "N" is the maximum number of terminals. 2 2
Preliminary Specification
L N ccc
.169 .177 .026 BSC .252 BSC .018 .030 24 0 -- 8 .004
4.30 4.50 0.65 BSC 6.40 BSC 0.45 0.75 24 0 -- 8 0.10
3 5
D
E
H
A B e
A1 SEATING PLANE -C- LEAD COPLANARITY ccc C L
C
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Ordering Information
Product Number FAN5098MTC Description AMD Hammer Controller Package 24 pin TSSOP
Preliminary Specification
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 3/8/02 0.0m 005 Stock#DS30005098 2002 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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