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| HM-6504 March 1997 4096 x 1 CMOS RAM Description The HM-6504 is a 4096 x 1 static CMOS RAM fabricated using self-aligned silicon gate technology. The device utilizes synchronous circuitry to achieve high performance and low power operation. On-chip latches are provided for addresses, data input and data output allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded memory arrays. Gated inputs allow lower operating current and also eliminate the need for pull up or pull down resistors. The HM-6504 is a fully static RAM and may be maintained in any state for an indefinite period of time. Data retention supply voltage and supply current are guaranteed over temperature. Features * Low Power Standby . . . . . . . . . . . . . . . . . . . 125W Max * Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max * Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min * TTL Compatible Input/Output * Three-State Output * Standard JEDEC Pinout * Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max * 18 Lead Package for High Density * On-Chip Address Register * Gated Inputs - No Pull Up or Pull Down Resistors Required Ordering Information 120ns HM1-6504S-9 24501BVA 810240IVA 200ns HM3-6504B-9 HM1-6504B-9 8102403VA 300ns HM3-6504-9 HM1-6504-9 8102405VA HM4-6504-9 TEMP. RANGE -40oC to +85oC -40oC to +85oC -40oC to+85oC PDIP CERDIP JAN # SMD # CLCC PACKAGE PKG. NO. E18.3 F18.3 F18.3 F18.3 J18.B Pinouts HM-6504 (PDIP, CERDIP) TOP VIEW A0 A1 A2 A3 A4 A5 Q W GND 1 2 3 4 5 6 7 8 9 18 VCC 17 A6 16 A7 15 A8 14 A9 13 A10 12 A11 11 D 10 E VCC 18 PIN A E W D Q DESCRIPTION Address Input Chip Enable Write Enable Data Input Data Output A2 A3 A4 A5 Q 3 4 5 6 7 HM-6504 (CLCC) TOP VIEW A1 A0 A6 17 16 A7 15 A8 14 A9 13 A10 12 A11 8 W 9 GND 10 E 11 D 2 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 File Number 2994.1 6-126 HM-6504 Functional Diagram LSB A8 A7 A6 A0 A1 A2 A LATCHED ADDRESS REGISTER L 6 GATED ROW DECODER G 64 G D Q A GATED COLUMN DECODER AND DATA I/O D Q Q A 64 x 64 MATRIX 64 A 6 D D Q LATCH L LATCH L W LATCH L 6 A L LATCHED ADDRESS REGISTER 6 A E D L Q LATCH LSB A11 A5 A4 A3 A9 A10 NOTES: 13. All lines active high-positive logic. 14. Three-state Buffers: A high output active. 15. Control and Data Latches: L low Q = D and Q latches on rising edge of L. 16. Address Latches: Latch on falling edge of E. 17. Gated Decoders: Gate on rising edge of G. 6-127 HM-6504 Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Information Thermal Resistance (Typical) JA JC CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W PDIP Package . . . . . . . . . . . . . . . . . . . 75oC/W N/A CLCC Package . . . . . . . . . . . . . . . . . . 90oC/W 33oC/W Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300oC Die Characteristics Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6910 Gates CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V Operating Temperature Range HM-6504S-9, HM-6504B-9, HM-6504-9 . . . . . . . .-40oC to +85oC HM-6504B-8, HM-6504-8 . . . . . . . . . . . . . . . . . .-55oC to +125oC DC Electrical Specifications SYMBOL ICCSB VCC = 5V 10%; TA = -40oC to +85oC (HM-6504B-9, HM-6504-9) TA = -55oC to +125oC (HM-6504B-8, HM-6504-8) MIN HM-6504-9 HM-6504-8 MAX 25 50 7 UNITS A A mA A A V A A V V V V V VI = VCC or GND, VCC = 5.5V VO = VCC or GND, VCC = 5.5V VCC = 4.5V VCC = 5.5V IO = 2.0mA, VCC = 4.5V IO = -1.0mA, VCC = 4.5V IO = -100A, VCC = 4.5V TEST CONDITIONS IO = 0mA, E = VCC -0.3V, VCC = 5.5V E = 1MHz, IO = 0mA, VI = GND, VCC = 5.5V IO = 0mA, VCC = 2.0V, E = VCC PARAMETER Standby Supply Current ICCOP Operating Supply Current (Note 1) Data Retention Supply Current HM-6504-9 HM-6504-8 ICCDR 2.0 -1.0 -1.0 -0.3 VCC -2.0 2.4 VCC -0.4 15 25 +1.0 +1.0 0.8 VCC +0.3 0.4 - VCCDR II IOZ VIL VIH VOL VOH1 VOH2 Data Retention Supply Voltage Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Output High Voltage (Note 2) TA = +25oC PARAMETER Input Capacitance (Note 2) Output Capacitance (Note 2) Capacitance SYMBOL CI CO NOTES: MAX 8 10 UNITS pF pF TEST CONDITIONS f = 1MHz, All measurements are referenced to device GND 1. Typical derating 5mA/MHz increase in ICCOP. 2. Tested at initial design and after major design changes. 6-128 HM-6504 AC Electrical Specifications VCC = 5V 10%; TA = -40oC to +85oC (HM-6504S-9, HM-6504B-9, HM-6504-9) TA = -55oC to +125oC (HM-6504B-8, HM-6504-8) HM-6504S SYMBOL (1) (2) (3) HM-6504B MIN 5 MAX 200 220 - HM-6504 MIN 5 MAX 300 320 UNITS ns ns ns TEST CONDITIONS (Notes 1, 3) (Notes 1, 3, 4) (Notes 2, 3) PARAMETER Chip Enable Access Time Address Access Time Chip Enable Output Enable Time Chip Enable Output Disable Time Chip Enable Pulse Negative Width Chip Enable Pulse Positive Width Address Setup Time Address Hold Time Write Enable Pulse Width Write Enable Pulse Setup Time Early Write Pulse Setup Time Write Enable Read Mode Setup Time Early Write Pulse Hold Time Data Setup Time Early Write Data Setup Time Data Hold Time Early Write Data Hold Time Read or Write Cycle Time MIN 5 MAX 120 120 - TELQV TAVQV TELQX (4) TEHQZ - 50 - 80 - 100 ns (Notes 2, 3) (5) TELEH 120 - 200 - 300 - ns (Notes 1, 3) (6) TEHEL 50 - 90 - 120 - ns (Notes 1, 3) (7) (8) (9) (10) TAVEL TELAX TWLWH TWLEH 0 40 20 70 - 20 50 60 150 - 20 50 80 200 - ns ns ns ns (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (11) TWLEL 0 - 0 - 0 - ns (Notes 1, 3) (12) TWHEL 0 - 0 - 0 - ns (Notes 1, 3) (13) (14) (15) (16) (17) (18) TELWH TDVWL TDVEL TWLDX TELDX TELEL 40 0 0 25 25 170 - 60 0 0 60 60 290 - 80 0 0 80 80 420 - ns ns ns ns ns ns (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) (Notes 1, 3) NOTES: 1. Input pulse levels: 0.8V to VCC - 2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate equivalent, CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF. 2. Tested at initial design and after major design changes. 3. VCC = 4.5V and 5.5V. 4. TAVQV = TELQV + TAVEL. 6-129 HM-6504 Timing Waveforms (7) TAVEL A (6) TEHEL E (1) TELQV (3) TELQX (8) TELAX (7) TAVEL NEXT ADD TELEH (5) TELEL (18) TEHEL (6) ADD VALID (4) TEHQZ VALID DATA OUTPUT HIGH Z Q HIGH Z HIGH W TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 11. READ CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L E H W X H H H H X H A X V X X X X V OUTPUT Q Z Z X V V Z Z Memory Disabled Cycle Begins, Addresses are Latched Output Enabled Output Valid Read Accomplished Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION The address information is latched in the on-chip registers on the falling edge of E (T = 0). Minimum address set-up and hold time requirements must be met. After the required hold time, the addresses may change state without affecting device operation. During time (T = 1) the output becomes enabled but the data is not valid until during time (T = 2). W must remain high for the read cycle. After the output data has been read, E may return high (T = 3). This will disable the output buffer and all input and ready the RAM for the next memory cycle (T = 4). 6-130 HM-6504 Timing Waveforms (Continued) (7) TAVEL A (6) TEHEL E (11) TWLEL W (15) TDVEL D HIGH-Z 0 TIME REFERENCE -1 0 1 2 3 4 (17) TELDX (15) TDVEL NEXT DATA HIGH-Z (13) TELWH (11) TWLEL (8) TELAX (7) TAVEL NEXT ADD (18) TELEL (5) TELEH ADD VALID (6) TEHEL DATA VALID FIGURE 12. EARLY WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 H L E H W X L X X X L A X V X X X V D X V X X X V OUTPUT Q Z Z Z Z Z Z Memory Disabled Cycle Begins, Addresses are Latched Write in Progress Internally Write Completed Prepare for Next Cycle (Same as - 1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION The early write cycle is the only cycle where the output is guaranteed not to become active. On the falling edge of E (T = 0), the addresses, the write signal, and the data input are latched in on-chip registers. The logic value of W at the time E falls, determines the state of the output buffer for that cycle. Since W is low when E falls, the output buffer is latched into the high impedance state and will remain in that state until E returns high (T = 2). For this cycle, the data input is latched by E going low; therefore, data set-up and hold times should be referenced to E. When E (T = 2) returns to the high state, the output buffer and all inputs are disabled and all signals are unlatched. The device is now ready for the next cycle. 6-131 HM-6504 Timing Waveforms (Continued) (7) TAVEL (8) TELAX (7) TAVEL NEXT ADD (18) TELEL (5) TELEH E (6) TEHEL (9) TWLWH W (14) TDVWL D (3) TELQX Q HIGH Z DATA VALID (4) TEHQZ (16) TWLDX (10) TWLEH (6) TEHEL A ADD VALID HIGH Z TIME REFERENCE -1 0 1 2 3 4 5 FIGURE 13. LATE WRITE CYCLE TRUTH TABLE INPUTS TIME REFERENCE -1 0 1 2 3 4 5 H L L H H X H E H W X H A X V X X X X V D X X V X X X X OUTPUTS Q Z Z X X X Z Z Memory Disabled Cycle Begins, Addresses are Latched Write Begins, Data is Latched Write In Progress Internally Write Completed Prepare for Next Cycle (Same as -1) Cycle Ends, Next Cycle Begins (Same as 0) FUNCTION The late write cycle is a cross between the early write cycle and the read-modify-write cycle. Recall that in the early write, the output is guaranteed to remain high impedance, and in the read-modify-write the output is guaranteed valid at access time. The late write is between these two cases. With this cycle the output may become active, and may become valid data, or may remain active but undefined. Valid data is written into the RAM if data setup, data hold, write setup and write pulse widths are observed. 6-132 HM-6504 Test Load Circuit DUT (NOTE 1) CL IOH + - 1.5V IOL EQUIVALENT CIRCUIT NOTE: 1. Test head capacitance includes stray and jig capacitance. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 6-133 |
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