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INTEGRATED CIRCUITS
GTLPH16612 18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
Product data File under Integrated Ciruits ICL03 2001 Sep 28
Philips Semiconductors
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
FEATURES
* 18-bit bidirectional bus interface * Translates between GTLP logic levels (B ports) and LVTTL/TTL * Edge rate control circuitry on the Bn outputs rising/falling edges to * 5 V I/O tolerant on the LVTTL side * No bus current loading when LVTTL output is tied to 5 V bus * 3-State buffers * Output capability: +64 mA/-32 mA on the LVTTL side; +40 mA on * LVTTL input levels on control pins * Power-up reset * Power-up 3-State * Positive edge triggered clock inputs * Latch-up protection exceeds 500 mA per JESD78 * ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 750 V (Bn I/O exceeds 1000 V) CDM per JESD22-C101 the GTLP side minimize system noise in a multipoint backplane environment logic levels (A ports)
DESCRIPTION
The GTLPH16612 is a high-performance BiCMOS product designed for VCC operation at 3.3V with I/O compatibility up to 5 V. The GTLPH16612 is unique in that pin 50 is a no connect and this device can be used as a replacement device in sockets where pin 50 is 3.3/5 V VCC or 3.3 V BIAS VCC. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CPAB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the Low-to-High transition of CPAB. When OEAB is Low, the outputs are active. When OEAB is High, the outputs are in the high-impedance state. The clocks can be controlled with the clock-enable inputs (CEBA/CEAB). Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA.
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN CI/O CI/O ICCZ PARAMETER Propagation delay An to Bn or Bn to An Input capacitance (Control pins) An I/O pin capacitance Bn I/O pin capacitance Total supply current CL = 50 pF VI = 0 V or VCC VI/O = 0 V or VCC VI/O = 0 V or 1.5 V Outputs disabled CONDITIONS Tamb = 25 C TYPICAL UNIT 3.3 V 1.9 4 9 5.3 12 ns pF pF pF mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP 56-Pin Plastic TSSOP TEMPERATURE RANGE -40 to +85 C -40 to +85 C ORDER CODE GTLPH16612DL GTLPH16612DGG DWG NUMBER SOT371-1 SOT364-1
NOTE: 1. Standard packing quantities and other packaging data is available at www.philipslogic.com/support/packages.
2001 Sep 28
2
853-2285 27174
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
PIN CONFIGURATION
OEAB LEAB A0 GND A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND A12 A13 A14 VCC A15 A16 GND A17 OEBA LEBA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CEAB CPAB B0 GND B1 B2 NC B3 B4 B5 GND B6 B7 B8 B9 B10 B11 GND B12 B13 B14 VREF B15 B16 GND B17 CPBA CEBA
PIN DESCRIPTION
PIN NUMBER 1, 27 29, 56 2, 28 55, 30 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 4, 11, 18, 25, 32, 39, 46, 53 7, 22 35 50 SYMBOL OEAB/OEBA CEBA/CEAB LEAB/LEBA CPAB/CPBA NAME AND FUNCTION A-to-B/ B-to-A Output enable input (active Low) B-to-A/A-to-B clock enable A-to-B/B-to-A Latch enable input A-to-B/B-to-A Clock input (active rising edge) Data inputs/outputs (A side)
A0-A17
B0-B17
Data inputs/outputs (B side)
GND VCC VREF NC
Ground (0V) Positive supply voltage GTLP reference voltage No connect
SW00486
2001 Sep 28
3
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
FUNCTION TABLE
INPUTS CEAB X L L X X L L H X= H= L= = Z= = OEAB H L L L L L L L LEAB X L L H H L L L CPAB X X X H L X A X L H L H X X X OUTPUT B Z L H L H BO BO BO Trans arent Transparent Clocked storage of A data MODE Isolation
Latched storage of A data Clock inhibit
Don't care High voltage level Low voltage level Low to High High impedance "off " state A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, CPBA, and CEBA. The condition when OEAB and OEBA are both low at the same time is not recommended. = Output level before the indicated steady-state input conditions were established. = Output level before the indicated steady-state input conditions were established, provided that CPAB was Low before LEAB went Low.
LOGIC SYMBOL (Positive Logic)
VREF 35
OEAB
1
CEAB
56
CPAB
55
LEAB
2
LEBA
28
CPBA
30
CEBA
29
OEBA
27 CE
A0
3
1D C1 CLK CE 1D C1 CLK
54
B0
To 17 other channels
SW00894
2001 Sep 28
4
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VO OUT IO OL IOH Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 DC output diode current DC output voltage3 Current into any output in the LOW state Current into any output in the HIGH state Storage temperature range VI < 0 V A port B port VO < 0 V; A port Output in Off or High state; A port Output in Off or High state; B port A port B port A port CONDITIONS RATING -0.5 to +4.6 -50 -0.5 to +7.0 -0.5 to +4.6 -50 -0.5 to +7.0 -0.5 to +4.6 128 80 -64 -65 to +150 UNIT V mA V mA V V mA mA mA C
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 C. 3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS1, 2
SYMBOL VCC VTT VREF VI VIH VIL IOH IOL t/v t/VCC Tamb PARAMETER DC supply voltage Termination voltage GTL reference voltage Input voltage HIGH-level HIGH level input voltage LOW-level LOW level input voltage HIGH-level output current LOW-level output current Input transition rise or fall rate Power-up rate Operating free-air temperature range GTL GTLP GTL GTLP B port Except B port B port Except B port B port Except A port A port B port, GTL B port, GTLP A port Outputs enabled TEST CONDITIONS 3.3V RANGE LIMITS MIN 3.0 1.14 1.35 0.74 0.9 0 0 VREF+50mV 2.0 -- -- -- -- -- -- -- 20 -40 TYP 3.3 1.2 1.5 0.8 1 VTT VCC -- -- -- -- -- -- -- -- -- -- -- MAX 3.6 1.26 1.65 0.87 1.10 Note 3 5.5 -- -- VREF-50mV 0.8 -32 32 40 64 10 -- +85 UNIT V V V V V V mA mA mA mA ns/V s/V C
NOTES: 1. Normal connection sequence is GND first; VCC, I/O, control inputs, VTT and VREF (any order) last. 2. VREF can be adjusted to optimize noise margins, but normally is two-thirds VTT. 3. VTT and RTT can be adjusted to accommodate backplane impedances if the DC recommended IOL ratings are not exceeded and the absolute max VI rating is not exceeded.
2001 Sep 28
5
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
DC ELECTRICAL CHARACTERISTICS (3.3 V "0.3 V RANGE)
LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40 to +85 C MIN VIK VO OH Input clamp voltage High-level High level output voltage VCC = 3.0 V; IIK = -18 mA VCC = 3.0 to 3.6 V; IOH = -100 A VCC = 3.0 V; IOH = -32 mA VCC = 3.0 V; IOL = 100 A VCC = 3.0 V; IOL = 16 mA VOL Low-level output voltage VCC = 3.0 V; IOL = 32 mA VCC = 3.0 V; IOL = 64 mA VCC = 3.0 V; IOL = 40 mA VCC = 3.6 V; VI = VCC or GND VCC = 0 or 3.6 V; VI = 5.5 V II Input leakage current VCC = 3.6 V; VI = 5.5 V VCC = 3.6 V; VI = VCC VCC = 3.6 V; VI = 0 V VCC = 3.6 V; VI = VTT or GND IOFF IHOLD O IEX IPU/PD ICCH ICCL ICCZ5 ICCH ICCL ICC CIN CI/O CI/O Additional supply current per input pin2 Control pins capacitance An I/O pin capacitance Bn I/O pin capacitance B-Port B Port Outputs low VCC = 3 V to 3.6 V; One input at VCC-0.6 V, Other inputs at VCC or GND VI = 0 V or VCC VI/O = 0 V or VCC VI/O = 0 V or 1.5 V -- -- -- -- -- 7.0 0.04 4 9.0 5.3 12.0 0.2 -- -- 7.36 mA pF pF pF VCC = 3.6 V Output off current Bus Hold current A outputs current, Current into an output in the High state when VO > VCC Power up/down 3-State output current3 A-Port A Port Outputs low Disabled Outputs high VI = GND or VCC; IO = 0 -- -- -- 10.5 6.0 9.7 18.5 11.5 17.5 mA VCC = 0 V; VI or VO = 0 to 4.5 V VCC = 3 V; VI = 0.8 V VCC = 3 V; VI = 2.0 V VO = 5.5 V; VCC = 3.0 V A port B port I/O Data pins4 ort A port B port Control pins -- -- -- -- -- -- 75 -75 -- -- -- 0.1 0.1 0.5 0.1 -- 0.1 130 -140 10 1.0 5.0 A port -- -- -- -- 0.3 0.4 0.4 0.1 0.5 0.55 0.5 1 10 20 10 -5 5 100 -- -- 125 100 9.0 A A A A A A V A A port -- VCC-0.2 2.0 -- -- TYP1 -0.85 VCC 2.3 0.07 0.25 MAX -1.2 -- V -- 0.2 0.4 V V UNIT
VCC 1.2 V; VO = 0.5 V to VCC; VI = GND or VCC OE = Don't care Outputs high
NOTES: 1. All typical values are at VCC = 3.3 V and Tamb = 25 C. 2. This is the increase in supply current for each LVTTL input at the specified voltage level other than VCC or GND 3. This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 msec. From VCC = 1.2 V to VCC = 3.3 V 0.3 V a transition time of 100 sec is permitted. This parameter is valid for Tamb = 25 C only. 4. Unused pins at VCC or GND. 5. ICCZ is measured with outputs pulled up to VCC or pulled down to ground. 6. The maximum Bn I/O pin capacitance is based on simulation data.
2001 Sep 28
6
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
AC CHARACTERISTICS (A PORT)
GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; Tamb = -40 to +85 C. GTLP GTLPH16612 An Port VCC = 3.3 V 0.3 V VREF = 1.0 V SYMBOL Fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPHZ tPZL tPLZ Bn to An Bn to An LEBA to An LEBA to An CPBA to An CPBA to An OEBA to An OEBA to An OEBA to An OEBA to An 2 2 3 3 1 1 5 5 6 6 PARAMETER WAVEFORM MIN 250 1.5 2.6 1.6 2.0 1.1 1.8 1.5 1.4 1.5 1.0 TYP1 290 2.6 4.3 3.0 3.0 2.7 3.0 4.3 3.6 3.8 2.6 MAX -- 5.5 6.5 4.9 4.5 4.9 4.6 6.2 4.8 6.2 5.5 MHz ns ns ns ns ns ns ns ns ns ns UNIT
NOTE: 1. Typical values are at VCC = 3.3 V, Tamb = +25 C.
AC CHARACTERISTICS (B PORT)
GND = 0 V; tr = tf = 2.5 ns; CL = 30 pF; RL = 25 ; Tamb = -40 to +85 C. GTLP GTLPH16612 Bn Port VCC = 3.3 V 0.3 V VREF = 1.0 V SYMBOL Fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL trise tfall An to Bn An to Bn LEAB to Bn LEAB to Bn CPAB to Bn CPAB to Bn OEAB to Bn OEAB to Bn Transition time B outputs 20% to 80% Transition time B outputs 20% to 80% 2 2 3 3 1 1 7 7 PARAMETER WAVEFORM MIN 250 1.8 1.0 1.9 1.9 2.7 2.2 1.4 1.5 -- -- TYP1 270 4.8 3.9 4.6 4.5 5.1 4.9 4.2 5.0 3.1 4.6 MAX -- 9.0 8.2 8.4 8.0 8.7 8.6 8.3 9.5 -- -- MHz ns ns ns ns ns ns ns ns ns ns UNIT
NOTE: 1. Typical values are at VCC = 3.3 V, Tamb = +25 C.
2001 Sep 28
7
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
AC SETUP REQUIREMENTS (3.3 V 0.3 V RANGE)
GTLPH16612
A Port: GND = 0 V; Input tr = tf = 2.5 ns; CL = 50 pF; RL = 500 ; Tamb = -40 to +85 C; VREF = 0.8 V or 1.0 V. B Port: GND = 0 V; Input tr = tf = 2.5 ns; CL = 30 pF; RL = 25 ; VREF = 0.8 V or 1.0 V. LIMITS SYMBOL DESCRIPTION PARAMETER WAVEFORM MIN tw(H) tw(H or L) ts(H or L) ts(H) ts(L) ts(H or L) ts(H or L) ts(L) ts(L) th(H or L) th(H or L) th(H or L) th(H or L) th(H) th(H) Pulse duration Pulse duration Setup time Setup time Setup time Setup time Setup time Setup time Setup time Hold time Hold time Hold time Hold time Hold time Hold time LEAB or LEBA CPAB or CPBA An before CPAB rising edge Bn before CPBA rising edge Bn before CPBA rising edge An before LEAB falling edge Bn before LEBA falling edge CEAB before CPAB rising edge CEBA before CPBA rising edge An after CPAB rising edge Bn after CPBA rising edge An after LEAB falling edge Bn after LEBA falling edge CEAB after CPAB rising edge CEBA after CPBA rising edge 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 1.0 2.5 2.0 2.5 3.1 0.5 2.5 0 0 0 0 0.5 0 1.1 1.1 VCC = 3.3 V 0.3 V TYP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MAX -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns UNIT
2001 Sep 28
8
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
AC WAVEFORMS
VM = 1.5 V at VCC w 3.0 V. VM = 1.5 V for A ports and control pins; VM = 1.0 V for B ports in GTLP mode. VX = VOL + 0.3 V at VCC w 3.0 V. VY = VOH - 0.3 V at VCC w 3.0 V.
1/fMAX 3.0 V or VCC, whichever is less OEBA VM VM 3.0 V or VCC, whichever is less
CPBA or CPAB
VM
VM
0V tW(L) tPHL An or Bn VM tW(H) tPLH VM VOL VOH An or Bn
tPZH
tPHZ VOH VM VY
SW00181
SW00223
Waveform 1. Propagation delay, clock input to output, clock pulse width, and maximum clock frequency
3.0 V or VCC, whichever is less 0V tPLH tPHL VOH
Waveform 5. 3-State output enable time to high level and output disable time from high level
OEBA VM VM 3.0 V or VCC, whichever is less
An or Bn
VM
VM
tPZL
tPLZ
An or Bn An or Bn VM VM VOL
VM
VX VOL
SW00176
SW00224
Waveform 2. Propagation delay, transparent mode
Waveform 6. 3-State output enable time to low level and output disable time from low level
OEAB VM VM 3.0 V or VCC, whichever is less
LEAB or LEBA
VM
VM
VM
3.0 V or VCC, whichever is less
0V tW(H) tPHL VOH An or Bn VM VM VOL Bn VM VM VOL tPLH tPLH tPHL
SW00177
SW00495
Waveform 3.
Propagation delay, enable to output, and enable pulse width
Waveform 7.
Output enable time on open collector output with pull-up
An or Bn CEAB or CEBA VM VM
VM
VM
3.0 V or VCC, whichever is less 0V
CPAB or CPBA, LEAB or LEBA
2001 Sep 28
EEE EEEE EEE EEE EEEE EEE EEE EEEE EEE
tS(H) th(H) tS(L) th(L) VM VM
3.0 V or VCC, whichever is less 0V SW00222
Waveform 4. Data setup and hold times
9
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
TEST CIRCUIT
VCC 6.0 V or VCC x 2
Open
VIN D.U.T. RT CL RL = 500 VOUT RL = 500
90% NEGATIVE PULSE VM 10% tTHL (tF) tTLH (tR) 90%
tW VM 10%
90%
VIN
GND
PULSE GENERATOR
0V tTLH (tR) tTHL (tF) VIN VM 10% tW 0V
90%
Test Circuit for A Outputs
1.2 V 25 FROM OUTPUT UNDER TEST CL = 30 pF (INCLUDES PROBE AND JIG CAPACITANCE) TEST POINT
POSITIVE PULSE 10%
VM
Input Waveforms
Load Circuit for B Outputs
SWITCH POSITION
TEST tPLZ/tPZL tPLH/tPHL tPHZ/tPZH SWITCH 6V Open GND
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance: See AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators. GTLP FAMILY Amplitude
INPUT PULSE REQUIREMENTS Rep. Rate tW tR tF
3.0 V or VCC whichever is less
v10 MHz 500 ns v2.5 ns v2.5 ns
SW00255
2001 Sep 28
10
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
2001 Sep 28
11
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
2001 Sep 28
12
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
NOTES
2001 Sep 28
13
Philips Semiconductors
Product data
18-bit GTLP to LVTTL/TTL bidirectional universal translator (3-State)
GTLPH16612
Data sheet status
Data sheet status [1] Objective data Preliminary data Product status [2] Development Qualification Definitions This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Product data
Production
[1] Please consult the most recently issued data sheet before initiating or completing a design. [2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
(c) Koninklijke Philips Electronics N.V. 2001 All rights reserved. Printed in U.S.A. Date of release: 09-01
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Document order number:
9397 750 08911
Philips Semiconductors
2001 Sep 28 14

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